source: firmware/FTU/ram/FTU_dual_port_ram_readme.txt@ 11933

Last change on this file since 11933 was 273, checked in by qweitzel, 14 years ago
new structure for FTU firmware, not yet finished
File size: 2.3 KB
Line 
1The following files were generated for 'FTU_dual_port_ram' in directory
2/ihp/home01/qweitzel/CT3-FACT/fact_repos.svn/FPGA/FTU/ram/
3
4FTU_dual_port_ram.asy:
5 Graphical symbol information file. Used by the ISE tools and some
6 third party tools to create a symbol representing the core.
7
8FTU_dual_port_ram.gise:
9 ISE Project Navigator support file. This is a generated file and should
10 not be edited directly.
11
12FTU_dual_port_ram.ise:
13 ISE Project Navigator support file. This is a generated file and should
14 not be edited directly.
15
16FTU_dual_port_ram.ngc:
17 Binary Xilinx implementation netlist file containing the information
18 required to implement the module in a Xilinx (R) FPGA.
19
20FTU_dual_port_ram.sym:
21 Please see the core data sheet.
22
23FTU_dual_port_ram.v:
24 Verilog wrapper file provided to support functional simulation.
25 This file contains simulation model customization data that is
26 passed to a parameterized simulation model for the core.
27
28FTU_dual_port_ram.veo:
29 VEO template file containing code that can be used as a model for
30 instantiating a CORE Generator module in a Verilog design.
31
32FTU_dual_port_ram.vhd:
33 VHDL wrapper file provided to support functional simulation. This
34 file contains simulation model customization data that is passed to
35 a parameterized simulation model for the core.
36
37FTU_dual_port_ram.vho:
38 VHO template file containing code that can be used as a model for
39 instantiating a CORE Generator module in a VHDL design.
40
41FTU_dual_port_ram.xco:
42 CORE Generator input file containing the parameters used to
43 regenerate a core.
44
45FTU_dual_port_ram.xise:
46 ISE Project Navigator support file. This is a generated file and should
47 not be edited directly.
48
49FTU_dual_port_ram_readme.txt:
50 Text file indicating the files generated and how they are used.
51
52FTU_dual_port_ram_flist.txt:
53 Text file listing all of the output files produced when a customized
54 core was generated in the CORE Generator.
55
56FTU_dual_port_ram_xmdf.tcl:
57 ISE Project Navigator interface file. ISE uses this file to determine
58 how the files output by CORE Generator for the core can be integrated
59 into your ISE project.
60
61blk_mem_gen_ds512.pdf:
62 Please see the core data sheet.
63
64
65Please see the Xilinx CORE Generator online help for further details on
66generated files and how to use them.
67
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