| 1 | The following files were generated for 'FTU_dual_port_ram64' in directory
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| 2 | /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTU/ram64/
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| 3 |
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| 4 | FTU_dual_port_ram64.asy:
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| 5 | Graphical symbol information file. Used by the ISE tools and some
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| 6 | third party tools to create a symbol representing the core.
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| 7 |
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| 8 | FTU_dual_port_ram64.gise:
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| 9 | ISE Project Navigator support file. This is a generated file and should
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| 10 | not be edited directly.
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| 11 |
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| 12 | FTU_dual_port_ram64.ise:
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| 13 | ISE Project Navigator support file. This is a generated file and should
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| 14 | not be edited directly.
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| 15 |
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| 16 | FTU_dual_port_ram64.ngc:
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| 17 | Binary Xilinx implementation netlist file containing the information
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| 18 | required to implement the module in a Xilinx (R) FPGA.
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| 19 |
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| 20 | FTU_dual_port_ram64.sym:
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| 21 | Please see the core data sheet.
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| 22 |
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| 23 | FTU_dual_port_ram64.v:
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| 24 | Verilog wrapper file provided to support functional simulation.
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| 25 | This file contains simulation model customization data that is
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| 26 | passed to a parameterized simulation model for the core.
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| 27 |
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| 28 | FTU_dual_port_ram64.veo:
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| 29 | VEO template file containing code that can be used as a model for
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| 30 | instantiating a CORE Generator module in a Verilog design.
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| 31 |
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| 32 | FTU_dual_port_ram64.vhd:
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| 33 | VHDL wrapper file provided to support functional simulation. This
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| 34 | file contains simulation model customization data that is passed to
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| 35 | a parameterized simulation model for the core.
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| 36 |
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| 37 | FTU_dual_port_ram64.vho:
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| 38 | VHO template file containing code that can be used as a model for
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| 39 | instantiating a CORE Generator module in a VHDL design.
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| 40 |
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| 41 | FTU_dual_port_ram64.xco:
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| 42 | CORE Generator input file containing the parameters used to
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| 43 | regenerate a core.
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| 44 |
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| 45 | FTU_dual_port_ram64.xise:
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| 46 | ISE Project Navigator support file. This is a generated file and should
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| 47 | not be edited directly.
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| 48 |
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| 49 | FTU_dual_port_ram64_readme.txt:
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| 50 | Text file indicating the files generated and how they are used.
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| 51 |
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| 52 | FTU_dual_port_ram64_flist.txt:
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| 53 | Text file listing all of the output files produced when a customized
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| 54 | core was generated in the CORE Generator.
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| 55 |
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| 56 | FTU_dual_port_ram64_xmdf.tcl:
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| 57 | ISE Project Navigator interface file. ISE uses this file to determine
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| 58 | how the files output by CORE Generator for the core can be integrated
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| 59 | into your ISE project.
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| 60 |
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| 61 | blk_mem_gen_ds512.pdf:
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| 62 | Please see the core data sheet.
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| 63 |
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| 64 |
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| 65 | Please see the Xilinx CORE Generator online help for further details on
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| 66 | generated files and how to use them.
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| 67 |
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