source: firmware/FTU/rs485/FTU_rs485_control.vhd@ 10009

Last change on this file since 10009 was 10009, checked in by weitzel, 15 years ago
DNA identifier added and RS485 debugged
File size: 44.4 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: top level entity of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_control is
36 port(
37 main_clk : IN std_logic;
38 brd_add : IN std_logic_vector(5 downto 0);
39 rx_d : IN std_logic;
40 rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending
41 DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending
42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending
43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending
44 ping_pong_ready : IN std_logic; -- ping pong successful
45 rate_array_rs485 : IN rate_array_type;
46 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
47 dac_array_rs485_in : IN dac_array_type;
48 enable_array_rs485_in : IN enable_array_type;
49 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
50 dna : IN STD_LOGIC_VECTOR(63 downto 0);
51 rx_en : OUT std_logic;
52 tx_d : OUT std_logic;
53 tx_en : OUT std_logic;
54 new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485
55 new_enables : OUT std_logic := '0'; -- new enables arrived via RS485
56 new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485
57 read_rates : OUT std_logic := '0'; -- FTM wants to read rates
58 read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs
59 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern
60 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value
61 ping_pong : OUT std_logic := '0'; -- ping pong command from FTM
62 dac_array_rs485_out : OUT dac_array_type;
63 enable_array_rs485_out : OUT enable_array_type;
64 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
65 );
66end FTU_rs485_control;
67
68architecture Behavioral of FTU_rs485_control is
69
70 signal tx_start_sig : std_logic := '0';
71 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
72 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
73
74 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface
75 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface
76 signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
77
78 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver
79 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver
80
81 signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
82 signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
83 signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
84 signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter
85 signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
86 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
87 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter
89
90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames
91
92 component FTU_rs485_receiver
93 port(
94 rec_clk : in std_logic;
95 --rx_busy : in std_logic;
96 rec_din : in std_logic_vector(7 downto 0);
97 rec_den : in std_logic;
98 rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
99 rec_valid : out std_logic
100 );
101 end component;
102
103 component FTU_rs485_interpreter
104 port(
105 clk : IN std_logic;
106 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
107 block_valid : IN std_logic;
108 brd_add : IN std_logic_vector(5 downto 0);
109 int_new_DACs : OUT std_logic;
110 int_new_enables : OUT std_logic;
111 int_new_prescaling : OUT std_logic;
112 int_read_rates : OUT std_logic;
113 int_read_DACs : OUT std_logic;
114 int_read_enables : OUT std_logic;
115 int_read_prescaling : OUT std_logic;
116 int_ping_pong : OUT std_logic;
117 dac_array_rs485_out : OUT dac_array_type;
118 enable_array_rs485_out : OUT enable_array_type;
119 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
120 );
121 end component;
122
123 component FTU_rs485_interface
124 port(
125 clk : IN std_logic;
126 -- RS485
127 rx_d : IN std_logic;
128 rx_en : OUT std_logic;
129 tx_d : OUT std_logic;
130 tx_en : OUT std_logic;
131 -- FPGA
132 rx_data : OUT std_logic_vector (7 DOWNTO 0);
133 rx_busy : OUT std_logic := '0';
134 rx_valid : OUT std_logic := '0';
135 tx_data : IN std_logic_vector (7 DOWNTO 0);
136 tx_busy : OUT std_logic := '0';
137 tx_start : IN std_logic
138 );
139 end component;
140
141 type FTU_rs485_control_StateType is (RECEIVE,
142 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
143 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT,
144 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
145 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT);
146 signal FTU_rs485_control_State : FTU_rs485_control_StateType;
147
148begin
149
150 Inst_FTU_rs485_receiver : FTU_rs485_receiver
151 port map(
152 rec_clk => main_clk,
153 --rx_busy =>,
154 rec_din => rx_data_sig,
155 rec_den => rx_valid_sig,
156 rec_dout => data_block_sig,
157 rec_valid => block_valid_sig
158 );
159
160 Inst_FTU_rs485_interpreter : FTU_rs485_interpreter
161 port map(
162 clk => main_clk,
163 data_block => data_block_sig,
164 block_valid => block_valid_sig,
165 brd_add => brd_add,
166 int_new_DACs => int_new_DACs_sig,
167 int_new_enables => int_new_enables_sig,
168 int_new_prescaling => int_new_prescaling_sig,
169 int_read_rates => int_read_rates_sig,
170 int_read_DACs => int_read_DACs_sig,
171 int_read_enables => int_read_enables_sig,
172 int_read_prescaling => int_read_prescaling_sig,
173 int_ping_pong => int_ping_pong_sig,
174 dac_array_rs485_out => dac_array_rs485_out,
175 enable_array_rs485_out => enable_array_rs485_out,
176 prescaling_rs485_out => prescaling_rs485_out
177 );
178
179 Inst_FTU_rs485_interface : FTU_rs485_interface
180 port map(
181 clk => main_clk,
182 -- RS485
183 rx_d => rx_d,
184 rx_en => rx_en,
185 tx_d => tx_d,
186 tx_en => tx_en,
187 -- FPGA
188 rx_data => rx_data_sig,
189 rx_busy => rx_busy_sig,
190 rx_valid => rx_valid_sig,
191 tx_data => tx_data_sig,
192 tx_busy => tx_busy_sig,
193 tx_start => tx_start_sig
194 );
195
196 --FTU RS485 control finite state machine
197
198 FTU_rs485_control_FSM: process (main_clk)
199 begin
200 if Rising_edge(main_clk) then
201 case FTU_rs485_control_State is
202
203 when RECEIVE => -- default state, receiver on, no transmission
204 tx_start_sig <= '0';
205 if (int_new_DACs_sig = '1') then
206 new_DACs <= '1';
207 new_enables <= '0';
208 new_prescaling <= '0';
209 read_rates <= '0';
210 read_DACs <= '0';
211 read_enables <= '0';
212 read_prescaling <= '0';
213 ping_pong <= '0';
214 FTU_rs485_control_State <= SET_DAC_WAIT;
215 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then
216 new_DACs <= '0';
217 new_enables <= '1';
218 new_prescaling <= '0';
219 read_rates <= '0';
220 read_DACs <= '0';
221 read_enables <= '0';
222 read_prescaling <= '0';
223 ping_pong <= '0';
224 FTU_rs485_control_State <= SET_ENABLE_WAIT;
225 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then
226 new_DACs <= '0';
227 new_enables <= '0';
228 new_prescaling <= '1';
229 read_rates <= '0';
230 read_DACs <= '0';
231 read_enables <= '0';
232 read_prescaling <= '0';
233 ping_pong <= '0';
234 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
235 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
236 int_read_rates_sig = '1') then
237 new_DACs <= '0';
238 new_enables <= '0';
239 new_prescaling <= '0';
240 read_rates <= '1';
241 read_DACs <= '0';
242 read_enables <= '0';
243 read_prescaling <= '0';
244 ping_pong <= '0';
245 FTU_rs485_control_State <= READ_RATES_WAIT;
246 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
247 int_read_rates_sig = '0' and int_read_DACs_sig = '1') then
248 new_DACs <= '0';
249 new_enables <= '0';
250 new_prescaling <= '0';
251 read_rates <= '0';
252 read_DACs <= '1';
253 read_enables <= '0';
254 read_prescaling <= '0';
255 ping_pong <= '0';
256 FTU_rs485_control_State <= READ_DAC_WAIT;
257 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
258 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then
259 new_DACs <= '0';
260 new_enables <= '0';
261 new_prescaling <= '0';
262 read_rates <= '0';
263 read_DACs <= '0';
264 read_enables <= '1';
265 read_prescaling <= '0';
266 ping_pong <= '0';
267 FTU_rs485_control_State <= READ_ENABLE_WAIT;
268 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
269 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then
270 new_DACs <= '0';
271 new_enables <= '0';
272 new_prescaling <= '0';
273 read_rates <= '0';
274 read_DACs <= '0';
275 read_enables <= '0';
276 read_prescaling <= '1';
277 ping_pong <= '0';
278 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
279 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
280 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and
281 int_ping_pong_sig = '1') then
282 new_DACs <= '0';
283 new_enables <= '0';
284 new_prescaling <= '0';
285 read_rates <= '0';
286 read_DACs <= '0';
287 read_enables <= '0';
288 read_prescaling <= '0';
289 ping_pong <= '1';
290 FTU_rs485_control_State <= PING_PONG_WAIT;
291 else
292 new_DACs <= '0';
293 new_enables <= '0';
294 new_prescaling <= '0';
295 read_rates <= '0';
296 read_DACs <= '0';
297 read_enables <= '0';
298 read_prescaling <= '0';
299 ping_pong <= '0';
300 FTU_rs485_control_State <= RECEIVE;
301 end if;
302
303 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM
304 if (DACs_ready = '1') then
305 new_DACs <= '0';
306 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
307 else
308 new_DACs <= '1';
309 FTU_rs485_control_State <= SET_DAC_WAIT;
310 end if;
311
312 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
313 if (enables_ready = '1') then
314 new_enables <= '0';
315 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
316 else
317 new_enables <= '1';
318 FTU_rs485_control_State <= SET_ENABLE_WAIT;
319 end if;
320
321 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
322 if (prescaling_ready = '1') then
323 new_prescaling <= '0';
324 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
325 else
326 new_prescaling <= '1';
327 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
328 end if;
329
330 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM
331 if (rates_ready = '1') then
332 read_rates <= '0';
333 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
334 else
335 read_rates <= '1';
336 FTU_rs485_control_State <= READ_RATES_WAIT;
337 end if;
338
339 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM
340 if (DACs_ready = '1') then
341 read_DACs <= '0';
342 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
343 else
344 read_DACs <= '1';
345 FTU_rs485_control_State <= READ_DAC_WAIT;
346 end if;
347
348 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
349 if (enables_ready = '1') then
350 read_enables <= '0';
351 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
352 else
353 read_enables <= '1';
354 FTU_rs485_control_State <= READ_ENABLE_WAIT;
355 end if;
356
357 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
358 if (prescaling_ready = '1') then
359 read_prescaling <= '0';
360 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
361 else
362 read_prescaling <= '1';
363 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
364 end if;
365
366 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM
367 if (ping_pong_ready = '1') then
368 ping_pong <= '0';
369 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
370 else
371 ping_pong <= '1';
372 FTU_rs485_control_State <= PING_PONG_WAIT;
373 end if;
374
375 when SET_DAC_TRANSMIT =>
376 if tx_busy_sig = '0' then
377 if txcnt = 0 then -- start delimiter
378 txcnt <= txcnt + 1;
379 tx_data_sig <= RS485_START_DELIM;
380 tx_start_sig <= '1';
381 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
382 elsif txcnt = 1 then -- FTM address
383 txcnt <= txcnt + 1;
384 tx_data_sig <= FTM_ADDRESS;
385 tx_start_sig <= '1';
386 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
387 elsif txcnt = 2 then -- board address
388 txcnt <= txcnt + 1;
389 tx_data_sig <= "00" & brd_add;
390 tx_start_sig <= '1';
391 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
392 elsif txcnt = 3 then -- mirrored command
393 txcnt <= txcnt + 1;
394 tx_data_sig <= "00000000";
395 tx_start_sig <= '1';
396 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
397 elsif txcnt = 4 then -- data: DAC A low
398 txcnt <= txcnt + 1;
399 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
400 tx_start_sig <= '1';
401 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
402 elsif txcnt = 5 then -- data: DAC A high
403 txcnt <= txcnt + 1;
404 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
405 tx_start_sig <= '1';
406 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
407 elsif txcnt = 6 then -- data: DAC B low
408 txcnt <= txcnt + 1;
409 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
410 tx_start_sig <= '1';
411 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
412 elsif txcnt = 7 then -- data: DAC B high
413 txcnt <= txcnt + 1;
414 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
415 tx_start_sig <= '1';
416 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
417 elsif txcnt = 8 then -- data: DAC C low
418 txcnt <= txcnt + 1;
419 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
420 tx_start_sig <= '1';
421 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
422 elsif txcnt = 9 then -- data: DAC C high
423 txcnt <= txcnt + 1;
424 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
425 tx_start_sig <= '1';
426 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
427 elsif txcnt = 10 then -- data: DAC D low
428 txcnt <= txcnt + 1;
429 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
430 tx_start_sig <= '1';
431 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
432 elsif txcnt = 11 then -- data: DAC D high
433 txcnt <= txcnt + 1;
434 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
435 tx_start_sig <= '1';
436 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
437 elsif txcnt = 12 then -- data: DAC E low
438 txcnt <= txcnt + 1;
439 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
440 tx_start_sig <= '1';
441 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
442 elsif txcnt = 13 then -- data: DAC E high
443 txcnt <= txcnt + 1;
444 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
445 tx_start_sig <= '1';
446 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
447 elsif txcnt < 15 then -- data: not used
448 txcnt <= txcnt + 1;
449 tx_data_sig <= "00000000";
450 tx_start_sig <= '1';
451 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
452 elsif txcnt = 15 then -- check sum
453 txcnt <= txcnt + 1;
454 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
455 tx_start_sig <= '1';
456 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
457 else -- transmission finished
458 txcnt <= 0;
459 FTU_rs485_control_State <= RECEIVE;
460 end if;
461 else
462 tx_start_sig <= '0';
463 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
464 end if;
465
466 when SET_ENABLE_TRANSMIT =>
467 if tx_busy_sig = '0' then
468 if txcnt = 0 then -- start delimiter
469 txcnt <= txcnt + 1;
470 tx_data_sig <= RS485_START_DELIM;
471 tx_start_sig <= '1';
472 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
473 elsif txcnt = 1 then -- FTM address
474 txcnt <= txcnt + 1;
475 tx_data_sig <= FTM_ADDRESS;
476 tx_start_sig <= '1';
477 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
478 elsif txcnt = 2 then -- board address
479 txcnt <= txcnt + 1;
480 tx_data_sig <= "00" & brd_add;
481 tx_start_sig <= '1';
482 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
483 elsif txcnt = 3 then -- mirrored command
484 txcnt <= txcnt + 1;
485 tx_data_sig <= "00000011";
486 tx_start_sig <= '1';
487 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
488 elsif txcnt = 4 then -- data: enable pattern A7-0
489 txcnt <= txcnt + 1;
490 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
491 tx_start_sig <= '1';
492 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
493 elsif txcnt = 5 then -- data: enable pattern A8
494 txcnt <= txcnt + 1;
495 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
496 tx_start_sig <= '1';
497 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
498 elsif txcnt = 6 then -- data: enable pattern B7-0
499 txcnt <= txcnt + 1;
500 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
501 tx_start_sig <= '1';
502 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
503 elsif txcnt = 7 then -- data: enable pattern B8
504 txcnt <= txcnt + 1;
505 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
506 tx_start_sig <= '1';
507 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
508 elsif txcnt = 8 then -- data: enable pattern C7-0
509 txcnt <= txcnt + 1;
510 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
511 tx_start_sig <= '1';
512 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
513 elsif txcnt = 9 then -- data: enable pattern C8
514 txcnt <= txcnt + 1;
515 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
516 tx_start_sig <= '1';
517 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
518 elsif txcnt = 10 then -- data: enable pattern D7-0
519 txcnt <= txcnt + 1;
520 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
521 tx_start_sig <= '1';
522 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
523 elsif txcnt = 11 then -- data: enable pattern D8
524 txcnt <= txcnt + 1;
525 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
526 tx_start_sig <= '1';
527 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
528 elsif txcnt < 15 then -- data: not used
529 txcnt <= txcnt + 1;
530 tx_data_sig <= "00000000";
531 tx_start_sig <= '1';
532 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
533 elsif txcnt = 15 then -- check sum
534 txcnt <= txcnt + 1;
535 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
536 tx_start_sig <= '1';
537 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
538 else -- transmission finished
539 txcnt <= 0;
540 FTU_rs485_control_State <= RECEIVE;
541 end if;
542 else
543 tx_start_sig <= '0';
544 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
545 end if;
546
547 when SET_PRESCALING_TRANSMIT =>
548 if tx_busy_sig = '0' then
549 if txcnt = 0 then -- start delimiter
550 txcnt <= txcnt + 1;
551 tx_data_sig <= RS485_START_DELIM;
552 tx_start_sig <= '1';
553 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
554 elsif txcnt = 1 then -- FTM address
555 txcnt <= txcnt + 1;
556 tx_data_sig <= FTM_ADDRESS;
557 tx_start_sig <= '1';
558 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
559 elsif txcnt = 2 then -- board address
560 txcnt <= txcnt + 1;
561 tx_data_sig <= "00" & brd_add;
562 tx_start_sig <= '1';
563 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
564 elsif txcnt = 3 then -- mirrored command
565 txcnt <= txcnt + 1;
566 tx_data_sig <= "00000110";
567 tx_start_sig <= '1';
568 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
569 elsif txcnt = 4 then -- data: prescaling
570 txcnt <= txcnt + 1;
571 tx_data_sig <= prescaling_rs485_in;
572 tx_start_sig <= '1';
573 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
574 elsif txcnt < 15 then -- data: not used
575 txcnt <= txcnt + 1;
576 tx_data_sig <= "00000000";
577 tx_start_sig <= '1';
578 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
579 elsif txcnt = 15 then -- check sum
580 txcnt <= txcnt + 1;
581 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
582 tx_start_sig <= '1';
583 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
584 else -- transmission finished
585 txcnt <= 0;
586 FTU_rs485_control_State <= RECEIVE;
587 end if;
588 else
589 tx_start_sig <= '0';
590 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
591 end if;
592
593 when READ_RATES_TRANSMIT =>
594 if tx_busy_sig = '0' then
595 if txcnt = 0 then -- start delimiter
596 txcnt <= txcnt + 1;
597 tx_data_sig <= RS485_START_DELIM;
598 tx_start_sig <= '1';
599 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
600 elsif txcnt = 1 then -- FTM address
601 txcnt <= txcnt + 1;
602 tx_data_sig <= FTM_ADDRESS;
603 tx_start_sig <= '1';
604 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
605 elsif txcnt = 2 then -- board address
606 txcnt <= txcnt + 1;
607 tx_data_sig <= "00" & brd_add;
608 tx_start_sig <= '1';
609 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
610 elsif txcnt = 3 then -- mirrored command
611 txcnt <= txcnt + 1;
612 tx_data_sig <= "00000010";
613 tx_start_sig <= '1';
614 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
615 elsif txcnt = 4 then -- data: counter A low
616 txcnt <= txcnt + 1;
617 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(7 downto 0);
618 tx_start_sig <= '1';
619 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
620 elsif txcnt = 5 then -- data: counter A high
621 txcnt <= txcnt + 1;
622 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(15 downto 8);
623 tx_start_sig <= '1';
624 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
625 elsif txcnt = 6 then -- data: counter B low
626 txcnt <= txcnt + 1;
627 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(7 downto 0);
628 tx_start_sig <= '1';
629 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
630 elsif txcnt = 7 then -- data: counter B high
631 txcnt <= txcnt + 1;
632 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(15 downto 8);
633 tx_start_sig <= '1';
634 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
635 elsif txcnt = 8 then -- data: counter C low
636 txcnt <= txcnt + 1;
637 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(7 downto 0);
638 tx_start_sig <= '1';
639 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
640 elsif txcnt = 9 then -- data: counter C high
641 txcnt <= txcnt + 1;
642 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(15 downto 8);
643 tx_start_sig <= '1';
644 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
645 elsif txcnt = 10 then -- data: counter D low
646 txcnt <= txcnt + 1;
647 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(7 downto 0);
648 tx_start_sig <= '1';
649 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
650 elsif txcnt = 11 then -- data: counter D high
651 txcnt <= txcnt + 1;
652 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(15 downto 8);
653 tx_start_sig <= '1';
654 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
655 elsif txcnt = 12 then -- data: trigger counter low
656 txcnt <= txcnt + 1;
657 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(7 downto 0);
658 tx_start_sig <= '1';
659 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
660 elsif txcnt = 13 then -- data: trigger counter high
661 txcnt <= txcnt + 1;
662 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(15 downto 8);
663 tx_start_sig <= '1';
664 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
665 elsif txcnt = 14 then -- data: overflow register
666 txcnt <= txcnt + 1;
667 tx_data_sig <= overflow_array_rs485_in;
668 tx_start_sig <= '1';
669 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
670 elsif txcnt = 15 then -- check sum
671 txcnt <= txcnt + 1;
672 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
673 tx_start_sig <= '1';
674 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
675 else -- transmission finished
676 txcnt <= 0;
677 FTU_rs485_control_State <= RECEIVE;
678 end if;
679 else
680 tx_start_sig <= '0';
681 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
682 end if;
683
684 when READ_DAC_TRANSMIT =>
685 if tx_busy_sig = '0' then
686 if txcnt = 0 then -- start delimiter
687 txcnt <= txcnt + 1;
688 tx_data_sig <= RS485_START_DELIM;
689 tx_start_sig <= '1';
690 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
691 elsif txcnt = 1 then -- FTM address
692 txcnt <= txcnt + 1;
693 tx_data_sig <= FTM_ADDRESS;
694 tx_start_sig <= '1';
695 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
696 elsif txcnt = 2 then -- board address
697 txcnt <= txcnt + 1;
698 tx_data_sig <= "00" & brd_add;
699 tx_start_sig <= '1';
700 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
701 elsif txcnt = 3 then -- mirrored command
702 txcnt <= txcnt + 1;
703 tx_data_sig <= "00000001";
704 tx_start_sig <= '1';
705 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
706 elsif txcnt = 4 then -- data: DAC A low
707 txcnt <= txcnt + 1;
708 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
709 tx_start_sig <= '1';
710 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
711 elsif txcnt = 5 then -- data: DAC A high
712 txcnt <= txcnt + 1;
713 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
714 tx_start_sig <= '1';
715 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
716 elsif txcnt = 6 then -- data: DAC B low
717 txcnt <= txcnt + 1;
718 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
719 tx_start_sig <= '1';
720 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
721 elsif txcnt = 7 then -- data: DAC B high
722 txcnt <= txcnt + 1;
723 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
724 tx_start_sig <= '1';
725 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
726 elsif txcnt = 8 then -- data: DAC C low
727 txcnt <= txcnt + 1;
728 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
729 tx_start_sig <= '1';
730 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
731 elsif txcnt = 9 then -- data: DAC C high
732 txcnt <= txcnt + 1;
733 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
734 tx_start_sig <= '1';
735 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
736 elsif txcnt = 10 then -- data: DAC D low
737 txcnt <= txcnt + 1;
738 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
739 tx_start_sig <= '1';
740 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
741 elsif txcnt = 11 then -- data: DAC D high
742 txcnt <= txcnt + 1;
743 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
744 tx_start_sig <= '1';
745 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
746 elsif txcnt = 12 then -- data: DAC E low
747 txcnt <= txcnt + 1;
748 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
749 tx_start_sig <= '1';
750 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
751 elsif txcnt = 13 then -- data: DAC E high
752 txcnt <= txcnt + 1;
753 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
754 tx_start_sig <= '1';
755 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
756 elsif txcnt < 15 then -- data: not used
757 txcnt <= txcnt + 1;
758 tx_data_sig <= "00000000";
759 tx_start_sig <= '1';
760 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
761 elsif txcnt = 15 then -- check sum
762 txcnt <= txcnt + 1;
763 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
764 tx_start_sig <= '1';
765 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
766 else -- transmission finished
767 txcnt <= 0;
768 FTU_rs485_control_State <= RECEIVE;
769 end if;
770 else
771 tx_start_sig <= '0';
772 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
773 end if;
774
775 when READ_ENABLE_TRANSMIT =>
776 if tx_busy_sig = '0' then
777 if txcnt = 0 then -- start delimiter
778 txcnt <= txcnt + 1;
779 tx_data_sig <= RS485_START_DELIM;
780 tx_start_sig <= '1';
781 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
782 elsif txcnt = 1 then -- FTM address
783 txcnt <= txcnt + 1;
784 tx_data_sig <= FTM_ADDRESS;
785 tx_start_sig <= '1';
786 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
787 elsif txcnt = 2 then -- board address
788 txcnt <= txcnt + 1;
789 tx_data_sig <= "00" & brd_add;
790 tx_start_sig <= '1';
791 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
792 elsif txcnt = 3 then -- mirrored command
793 txcnt <= txcnt + 1;
794 tx_data_sig <= "00000100";
795 tx_start_sig <= '1';
796 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
797 elsif txcnt = 4 then -- data: enable pattern A7-0
798 txcnt <= txcnt + 1;
799 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
800 tx_start_sig <= '1';
801 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
802 elsif txcnt = 5 then -- data: enable pattern A8
803 txcnt <= txcnt + 1;
804 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
805 tx_start_sig <= '1';
806 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
807 elsif txcnt = 6 then -- data: enable pattern B7-0
808 txcnt <= txcnt + 1;
809 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
810 tx_start_sig <= '1';
811 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
812 elsif txcnt = 7 then -- data: enable pattern B8
813 txcnt <= txcnt + 1;
814 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
815 tx_start_sig <= '1';
816 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
817 elsif txcnt = 8 then -- data: enable pattern C7-0
818 txcnt <= txcnt + 1;
819 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
820 tx_start_sig <= '1';
821 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
822 elsif txcnt = 9 then -- data: enable pattern C8
823 txcnt <= txcnt + 1;
824 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
825 tx_start_sig <= '1';
826 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
827 elsif txcnt = 10 then -- data: enable pattern D7-0
828 txcnt <= txcnt + 1;
829 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
830 tx_start_sig <= '1';
831 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
832 elsif txcnt = 11 then -- data: enable pattern D8
833 txcnt <= txcnt + 1;
834 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
835 tx_start_sig <= '1';
836 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
837 elsif txcnt < 15 then -- data: not used
838 txcnt <= txcnt + 1;
839 tx_data_sig <= "00000000";
840 tx_start_sig <= '1';
841 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
842 elsif txcnt = 15 then -- check sum
843 txcnt <= txcnt + 1;
844 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
845 tx_start_sig <= '1';
846 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
847 else -- transmission finished
848 txcnt <= 0;
849 FTU_rs485_control_State <= RECEIVE;
850 end if;
851 else
852 tx_start_sig <= '0';
853 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
854 end if;
855
856 when READ_PRESCALING_TRANSMIT =>
857 if tx_busy_sig = '0' then
858 if txcnt = 0 then -- start delimiter
859 txcnt <= txcnt + 1;
860 tx_data_sig <= RS485_START_DELIM;
861 tx_start_sig <= '1';
862 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
863 elsif txcnt = 1 then -- FTM address
864 txcnt <= txcnt + 1;
865 tx_data_sig <= FTM_ADDRESS;
866 tx_start_sig <= '1';
867 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
868 elsif txcnt = 2 then -- board address
869 txcnt <= txcnt + 1;
870 tx_data_sig <= "00" & brd_add;
871 tx_start_sig <= '1';
872 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
873 elsif txcnt = 3 then -- mirrored command
874 txcnt <= txcnt + 1;
875 tx_data_sig <= "00000111";
876 tx_start_sig <= '1';
877 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
878 elsif txcnt = 4 then -- data: prescaling
879 txcnt <= txcnt + 1;
880 tx_data_sig <= prescaling_rs485_in;
881 tx_start_sig <= '1';
882 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
883 elsif txcnt = 5 then -- data: overflow register
884 txcnt <= txcnt + 1;
885 tx_data_sig <= overflow_array_rs485_in;
886 tx_start_sig <= '1';
887 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
888 elsif txcnt < 15 then -- data: not used
889 txcnt <= txcnt + 1;
890 tx_data_sig <= "00000000";
891 tx_start_sig <= '1';
892 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
893 elsif txcnt = 15 then -- check sum
894 txcnt <= txcnt + 1;
895 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
896 tx_start_sig <= '1';
897 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
898 else -- transmission finished
899 txcnt <= 0;
900 FTU_rs485_control_State <= RECEIVE;
901 end if;
902 else
903 tx_start_sig <= '0';
904 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
905 end if;
906
907 when PING_PONG_TRANSMIT =>
908 if tx_busy_sig = '0' then
909 if txcnt = 0 then -- start delimiter
910 txcnt <= txcnt + 1;
911 tx_data_sig <= RS485_START_DELIM;
912 tx_start_sig <= '1';
913 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
914 elsif txcnt = 1 then -- FTM address
915 txcnt <= txcnt + 1;
916 tx_data_sig <= FTM_ADDRESS;
917 tx_start_sig <= '1';
918 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
919 elsif txcnt = 2 then -- board address
920 txcnt <= txcnt + 1;
921 tx_data_sig <= "00" & brd_add;
922 tx_start_sig <= '1';
923 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
924 elsif txcnt = 3 then -- mirrored command
925 txcnt <= txcnt + 1;
926 tx_data_sig <= "00000101";
927 tx_start_sig <= '1';
928 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
929 elsif txcnt = 4 then -- data: device DNA
930 txcnt <= txcnt + 1;
931 tx_data_sig <= dna(7 downto 0);
932 tx_start_sig <= '1';
933 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
934 elsif txcnt = 5 then -- data: device DNA
935 txcnt <= txcnt + 1;
936 tx_data_sig <= dna(15 downto 8);
937 tx_start_sig <= '1';
938 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
939 elsif txcnt = 6 then -- data: device DNA
940 txcnt <= txcnt + 1;
941 tx_data_sig <= dna(23 downto 16);
942 tx_start_sig <= '1';
943 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
944 elsif txcnt = 7 then -- data: device DNA
945 txcnt <= txcnt + 1;
946 tx_data_sig <= dna(31 downto 24);
947 tx_start_sig <= '1';
948 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
949 elsif txcnt = 8 then -- data: device DNA
950 txcnt <= txcnt + 1;
951 tx_data_sig <= dna(39 downto 32);
952 tx_start_sig <= '1';
953 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
954 elsif txcnt = 9 then -- data: device DNA
955 txcnt <= txcnt + 1;
956 tx_data_sig <= dna(47 downto 40);
957 tx_start_sig <= '1';
958 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
959 elsif txcnt = 10 then -- data: device DNA
960 txcnt <= txcnt + 1;
961 tx_data_sig <= dna(55 downto 48);
962 tx_start_sig <= '1';
963 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
964 elsif txcnt = 11 then -- data: device DNA
965 txcnt <= txcnt + 1;
966 tx_data_sig <= dna(63 downto 56);
967 tx_start_sig <= '1';
968 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
969 elsif txcnt < 15 then -- data: not used
970 txcnt <= txcnt + 1;
971 tx_data_sig <= "00000000";
972 tx_start_sig <= '1';
973 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
974 elsif txcnt = 15 then -- check sum
975 txcnt <= txcnt + 1;
976 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
977 tx_start_sig <= '1';
978 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
979 else -- transmission finished
980 txcnt <= 0;
981 FTU_rs485_control_State <= RECEIVE;
982 end if;
983 else
984 tx_start_sig <= '0';
985 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
986 end if;
987
988 end case;
989 end if;
990 end process FTU_rs485_control_FSM;
991
992end Behavioral;
993
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