source: firmware/FTU/rs485/FTU_rs485_control.vhd@ 15410

Last change on this file since 15410 was 10238, checked in by weitzel, 15 years ago
change in FTU rs485 module; FTUs answer now one BAUD period later
File size: 63.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: top level entity of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_control is
36 port(
37 main_clk : IN std_logic;
38 brd_add : IN std_logic_vector(5 downto 0);
39 rx_d : IN std_logic;
40 rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending
41 DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending
42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending
43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending
44 ping_pong_ready : IN std_logic; -- ping pong successful
45 rate_array_rs485 : IN rate_array_type;
46 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
47 dac_array_rs485_in : IN dac_array_type;
48 enable_array_rs485_in : IN enable_array_type;
49 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
50 dna : IN STD_LOGIC_VECTOR(63 downto 0);
51 rx_en : OUT std_logic;
52 tx_d : OUT std_logic;
53 tx_en : OUT std_logic;
54 new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485
55 new_enables : OUT std_logic := '0'; -- new enables arrived via RS485
56 new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485
57 read_rates : OUT std_logic := '0'; -- FTM wants to read rates
58 read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs
59 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern
60 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value
61 ping_pong : OUT std_logic := '0'; -- ping pong command from FTM
62 dac_array_rs485_out : OUT dac_array_type;
63 enable_array_rs485_out : OUT enable_array_type;
64 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
65 );
66end FTU_rs485_control;
67
68architecture Behavioral of FTU_rs485_control is
69
70 signal tx_start_sig : std_logic := '0';
71 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
72 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
73
74 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface
75 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface
76 signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
77
78 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver
79 signal start_interpreter_sig : std_logic := '0';
80 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver
81
82 signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
83 signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
84 signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
85 signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter
86 signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
87 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
88 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
89 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter
90
91 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 28 1-byte frames
92
93 signal reset_crc_sig : std_logic := '0';
94 signal crc_enable_sig : std_logic := '0';
95 signal crc_input_sig : std_logic_vector(RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
96 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0');
97 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0');
98 signal crc_error_cnt_sig : integer range 0 to 255 := 0;
99
100 component ucrc_par
101 generic(
102 POLYNOMIAL : std_logic_vector;
103 INIT_VALUE : std_logic_vector;
104 DATA_WIDTH : integer range 2 to 256;
105 SYNC_RESET : integer range 0 to 1
106 );
107 port(
108 clk_i : in std_logic;
109 rst_i : in std_logic;
110 clken_i : in std_logic;
111 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
112 match_o : out std_logic;
113 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
114 );
115 end component;
116
117 component FTU_rs485_receiver
118 port(
119 rec_clk : in std_logic;
120 -- rx_busy : in std_logic;
121 rec_din : in std_logic_vector(7 downto 0);
122 rec_den : in std_logic;
123 rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
124 rec_valid : out std_logic
125 );
126 end component;
127
128 component FTU_rs485_interpreter
129 port(
130 clk : IN std_logic;
131 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
132 block_valid : IN std_logic;
133 brd_add : IN std_logic_vector(5 downto 0);
134 crc_error_cnt : OUT integer range 0 to 255;
135 int_new_DACs : OUT std_logic;
136 int_new_enables : OUT std_logic;
137 int_new_prescaling : OUT std_logic;
138 int_read_rates : OUT std_logic;
139 int_read_DACs : OUT std_logic;
140 int_read_enables : OUT std_logic;
141 int_read_prescaling : OUT std_logic;
142 int_ping_pong : OUT std_logic;
143 dac_array_rs485_out : OUT dac_array_type;
144 enable_array_rs485_out : OUT enable_array_type;
145 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
146 );
147 end component;
148
149 component FTU_rs485_interface
150 port(
151 clk : IN std_logic;
152 -- RS485
153 rx_d : IN std_logic;
154 rx_en : OUT std_logic;
155 tx_d : OUT std_logic;
156 tx_en : OUT std_logic;
157 -- FPGA
158 rx_data : OUT std_logic_vector (7 DOWNTO 0);
159 rx_busy : OUT std_logic := '0';
160 rx_valid : OUT std_logic := '0';
161 tx_data : IN std_logic_vector (7 DOWNTO 0);
162 tx_busy : OUT std_logic := '0';
163 tx_start : IN std_logic
164 );
165 end component;
166
167 type FTU_rs485_control_StateType is (INIT, RECEIVE,
168 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
169 READ_RATES_WAIT_2, READ_DAC_WAIT_2, READ_ENABLE_WAIT_2, READ_PRESCALING_WAIT_2,
170 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT,
171 SET_DAC_WAIT_2, SET_ENABLE_WAIT_2, SET_PRESCALING_WAIT_2, PING_PONG_WAIT_2,
172 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
173 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT);
174 signal FTU_rs485_control_State : FTU_rs485_control_StateType;
175
176begin
177
178 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
179 start_interpreter_sig <= block_valid_sig and (not rx_busy_sig); -- avoid answering to early to FTM
180
181 Inst_ucrc_par : ucrc_par
182 generic map(
183 POLYNOMIAL => CRC_POLYNOMIAL,
184 INIT_VALUE => CRC_INIT_VALUE,
185 DATA_WIDTH => 216,
186 SYNC_RESET => 1
187 )
188 port map(
189 clk_i => main_clk,
190 rst_i => reset_crc_sig,
191 clken_i => crc_enable_sig,
192 data_i => crc_input_sig,
193 match_o => open,
194 crc_o => crc_sig_inv
195 );
196
197 Inst_FTU_rs485_receiver : FTU_rs485_receiver
198 port map(
199 rec_clk => main_clk,
200 -- rx_busy => rx_busy_sig,
201 rec_din => rx_data_sig,
202 rec_den => rx_valid_sig,
203 rec_dout => data_block_sig,
204 rec_valid => block_valid_sig
205 );
206
207 Inst_FTU_rs485_interpreter : FTU_rs485_interpreter
208 port map(
209 clk => main_clk,
210 data_block => data_block_sig,
211 block_valid => start_interpreter_sig,
212 brd_add => brd_add,
213 crc_error_cnt => crc_error_cnt_sig,
214 int_new_DACs => int_new_DACs_sig,
215 int_new_enables => int_new_enables_sig,
216 int_new_prescaling => int_new_prescaling_sig,
217 int_read_rates => int_read_rates_sig,
218 int_read_DACs => int_read_DACs_sig,
219 int_read_enables => int_read_enables_sig,
220 int_read_prescaling => int_read_prescaling_sig,
221 int_ping_pong => int_ping_pong_sig,
222 dac_array_rs485_out => dac_array_rs485_out,
223 enable_array_rs485_out => enable_array_rs485_out,
224 prescaling_rs485_out => prescaling_rs485_out
225 );
226
227 Inst_FTU_rs485_interface : FTU_rs485_interface
228 port map(
229 clk => main_clk,
230 -- RS485
231 rx_d => rx_d,
232 rx_en => rx_en,
233 tx_d => tx_d,
234 tx_en => tx_en,
235 -- FPGA
236 rx_data => rx_data_sig,
237 rx_busy => rx_busy_sig,
238 rx_valid => rx_valid_sig,
239 tx_data => tx_data_sig,
240 tx_busy => tx_busy_sig,
241 tx_start => tx_start_sig
242 );
243
244 --FTU RS485 control finite state machine
245
246 FTU_rs485_control_FSM: process (main_clk)
247 begin
248 if Rising_edge(main_clk) then
249 case FTU_rs485_control_State is
250
251 when INIT => -- reset CRC register
252 reset_crc_sig <= '1';
253 FTU_rs485_control_State <= RECEIVE;
254
255 when RECEIVE => -- default state, receiver on, no transmission
256 reset_crc_sig <= '0';
257 crc_enable_sig <= '0';
258 tx_start_sig <= '0';
259 if (int_new_DACs_sig = '1') then
260 new_DACs <= '1';
261 new_enables <= '0';
262 new_prescaling <= '0';
263 read_rates <= '0';
264 read_DACs <= '0';
265 read_enables <= '0';
266 read_prescaling <= '0';
267 ping_pong <= '0';
268 FTU_rs485_control_State <= SET_DAC_WAIT;
269 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then
270 new_DACs <= '0';
271 new_enables <= '1';
272 new_prescaling <= '0';
273 read_rates <= '0';
274 read_DACs <= '0';
275 read_enables <= '0';
276 read_prescaling <= '0';
277 ping_pong <= '0';
278 FTU_rs485_control_State <= SET_ENABLE_WAIT;
279 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then
280 new_DACs <= '0';
281 new_enables <= '0';
282 new_prescaling <= '1';
283 read_rates <= '0';
284 read_DACs <= '0';
285 read_enables <= '0';
286 read_prescaling <= '0';
287 ping_pong <= '0';
288 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
289 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
290 int_read_rates_sig = '1') then
291 new_DACs <= '0';
292 new_enables <= '0';
293 new_prescaling <= '0';
294 read_rates <= '1';
295 read_DACs <= '0';
296 read_enables <= '0';
297 read_prescaling <= '0';
298 ping_pong <= '0';
299 FTU_rs485_control_State <= READ_RATES_WAIT;
300 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
301 int_read_rates_sig = '0' and int_read_DACs_sig = '1') then
302 new_DACs <= '0';
303 new_enables <= '0';
304 new_prescaling <= '0';
305 read_rates <= '0';
306 read_DACs <= '1';
307 read_enables <= '0';
308 read_prescaling <= '0';
309 ping_pong <= '0';
310 FTU_rs485_control_State <= READ_DAC_WAIT;
311 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
312 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then
313 new_DACs <= '0';
314 new_enables <= '0';
315 new_prescaling <= '0';
316 read_rates <= '0';
317 read_DACs <= '0';
318 read_enables <= '1';
319 read_prescaling <= '0';
320 ping_pong <= '0';
321 FTU_rs485_control_State <= READ_ENABLE_WAIT;
322 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
323 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then
324 new_DACs <= '0';
325 new_enables <= '0';
326 new_prescaling <= '0';
327 read_rates <= '0';
328 read_DACs <= '0';
329 read_enables <= '0';
330 read_prescaling <= '1';
331 ping_pong <= '0';
332 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
333 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
334 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and
335 int_ping_pong_sig = '1') then
336 new_DACs <= '0';
337 new_enables <= '0';
338 new_prescaling <= '0';
339 read_rates <= '0';
340 read_DACs <= '0';
341 read_enables <= '0';
342 read_prescaling <= '0';
343 ping_pong <= '1';
344 FTU_rs485_control_State <= PING_PONG_WAIT;
345 else
346 new_DACs <= '0';
347 new_enables <= '0';
348 new_prescaling <= '0';
349 read_rates <= '0';
350 read_DACs <= '0';
351 read_enables <= '0';
352 read_prescaling <= '0';
353 ping_pong <= '0';
354 FTU_rs485_control_State <= RECEIVE;
355 end if;
356
357 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM
358 if (DACs_ready = '1') then
359 new_DACs <= '0';
360 crc_enable_sig <= '1';
361 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
362 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
363 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
364 & "00000000"
365 & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0)
366 & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0)
367 & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0)
368 & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0)
369 & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000000"
370 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
371 FTU_rs485_control_State <= SET_DAC_WAIT_2;
372 else
373 new_DACs <= '1';
374 FTU_rs485_control_State <= SET_DAC_WAIT;
375 end if;
376
377 when SET_DAC_WAIT_2 => -- wait one cycle for CRC calculation
378 crc_enable_sig <= '0';
379 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
380
381 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
382 if (enables_ready = '1') then
383 new_enables <= '0';
384 crc_enable_sig <= '1';
385 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
386 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
387 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
388 & "00000000" & "00000000" & "00000000"
389 & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0)
390 & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0)
391 & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0)
392 & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000011"
393 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
394 FTU_rs485_control_State <= SET_ENABLE_WAIT_2;
395 else
396 new_enables <= '1';
397 FTU_rs485_control_State <= SET_ENABLE_WAIT;
398 end if;
399
400 when SET_ENABLE_WAIT_2 => -- wait one cycle for CRC calculation
401 crc_enable_sig <= '0';
402 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
403
404 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
405 if (prescaling_ready = '1') then
406 new_prescaling <= '0';
407 crc_enable_sig <= '1';
408 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
409 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
410 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
411 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
412 & "00000000" & "00000000" & "00000000" & "00000000"
413 & overflow_array_rs485_in & prescaling_rs485_in & "00000110"
414 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
415 FTU_rs485_control_State <= SET_PRESCALING_WAIT_2;
416 else
417 new_prescaling <= '1';
418 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
419 end if;
420
421 when SET_PRESCALING_WAIT_2 => -- wait one cycle for CRC calculation
422 crc_enable_sig <= '0';
423 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
424
425 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM
426 if (rates_ready = '1') then
427 read_rates <= '0';
428 crc_enable_sig <= '1';
429 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
430 & overflow_array_rs485_in
431 & conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16)
432 & conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0)
433 & conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16)
434 & conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0)
435 & conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16)
436 & conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0)
437 & conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16)
438 & conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0)
439 & conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16)
440 & conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0) & "00000010"
441 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
442 FTU_rs485_control_State <= READ_RATES_WAIT_2;
443 else
444 read_rates <= '1';
445 FTU_rs485_control_State <= READ_RATES_WAIT;
446 end if;
447
448 when READ_RATES_WAIT_2 => -- wait one cycle for CRC calculation
449 crc_enable_sig <= '0';
450 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
451
452 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM
453 if (DACs_ready = '1') then
454 read_DACs <= '0';
455 crc_enable_sig <= '1';
456 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
457 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
458 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
459 & "00000000"
460 & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0)
461 & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0)
462 & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0)
463 & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0)
464 & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000001"
465 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
466 FTU_rs485_control_State <= READ_DAC_WAIT_2;
467 else
468 read_DACs <= '1';
469 FTU_rs485_control_State <= READ_DAC_WAIT;
470 end if;
471
472 when READ_DAC_WAIT_2 => -- wait one cycle for CRC calculation
473 crc_enable_sig <= '0';
474 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
475
476 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
477 if (enables_ready = '1') then
478 read_enables <= '0';
479 crc_enable_sig <= '1';
480 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
481 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
482 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
483 & "00000000" & "00000000" & "00000000"
484 & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0)
485 & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0)
486 & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0)
487 & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000100"
488 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
489 FTU_rs485_control_State <= READ_ENABLE_WAIT_2;
490 else
491 read_enables <= '1';
492 FTU_rs485_control_State <= READ_ENABLE_WAIT;
493 end if;
494
495 when READ_ENABLE_WAIT_2 => -- wait one cycle for CRC calculation
496 crc_enable_sig <= '0';
497 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
498
499 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
500 if (prescaling_ready = '1') then
501 read_prescaling <= '0';
502 crc_enable_sig <= '1';
503 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
504 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
505 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
506 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
507 & "00000000" & "00000000" & "00000000" & "00000000"
508 & overflow_array_rs485_in & prescaling_rs485_in & "00000111"
509 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
510 FTU_rs485_control_State <= READ_PRESCALING_WAIT_2;
511 else
512 read_prescaling <= '1';
513 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
514 end if;
515
516 when READ_PRESCALING_WAIT_2 => -- wait one cycle for CRC calculation
517 crc_enable_sig <= '0';
518 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
519
520 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM
521 if (ping_pong_ready = '1') then
522 ping_pong <= '0';
523 crc_enable_sig <= '1';
524 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
525 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
526 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
527 & "00000000" & "00000000" & "00000000"
528 & dna(63 downto 0) & "00000101"
529 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
530 FTU_rs485_control_State <= PING_PONG_WAIT_2;
531 else
532 ping_pong <= '1';
533 FTU_rs485_control_State <= PING_PONG_WAIT;
534 end if;
535
536 when PING_PONG_WAIT_2 => -- wait one cycle for CRC calculation
537 crc_enable_sig <= '0';
538 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
539
540 when SET_DAC_TRANSMIT =>
541 if tx_busy_sig = '0' then
542 if txcnt = 0 then -- start delimiter
543 txcnt <= txcnt + 1;
544 tx_data_sig <= RS485_START_DELIM;
545 tx_start_sig <= '1';
546 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
547 elsif txcnt = 1 then -- FTM address
548 txcnt <= txcnt + 1;
549 tx_data_sig <= FTM_ADDRESS;
550 tx_start_sig <= '1';
551 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
552 elsif txcnt = 2 then -- board address
553 txcnt <= txcnt + 1;
554 tx_data_sig <= "00" & brd_add;
555 tx_start_sig <= '1';
556 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
557 elsif txcnt = 3 then -- firmware ID
558 txcnt <= txcnt + 1;
559 tx_data_sig <= FIRMWARE_ID;
560 tx_start_sig <= '1';
561 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
562 elsif txcnt = 4 then -- mirrored command
563 txcnt <= txcnt + 1;
564 tx_data_sig <= "00000000";
565 tx_start_sig <= '1';
566 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
567 elsif txcnt = 5 then -- data: DAC A low
568 txcnt <= txcnt + 1;
569 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
570 tx_start_sig <= '1';
571 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
572 elsif txcnt = 6 then -- data: DAC A high
573 txcnt <= txcnt + 1;
574 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
575 tx_start_sig <= '1';
576 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
577 elsif txcnt = 7 then -- data: DAC B low
578 txcnt <= txcnt + 1;
579 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
580 tx_start_sig <= '1';
581 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
582 elsif txcnt = 8 then -- data: DAC B high
583 txcnt <= txcnt + 1;
584 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
585 tx_start_sig <= '1';
586 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
587 elsif txcnt = 9 then -- data: DAC C low
588 txcnt <= txcnt + 1;
589 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
590 tx_start_sig <= '1';
591 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
592 elsif txcnt = 10 then -- data: DAC C high
593 txcnt <= txcnt + 1;
594 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
595 tx_start_sig <= '1';
596 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
597 elsif txcnt = 11 then -- data: DAC D low
598 txcnt <= txcnt + 1;
599 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
600 tx_start_sig <= '1';
601 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
602 elsif txcnt = 12 then -- data: DAC D high
603 txcnt <= txcnt + 1;
604 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
605 tx_start_sig <= '1';
606 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
607 elsif txcnt = 13 then -- data: DAC E low
608 txcnt <= txcnt + 1;
609 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
610 tx_start_sig <= '1';
611 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
612 elsif txcnt = 14 then -- data: DAC E high
613 txcnt <= txcnt + 1;
614 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
615 tx_start_sig <= '1';
616 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
617 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
618 txcnt <= txcnt + 1;
619 tx_data_sig <= "00000000";
620 tx_start_sig <= '1';
621 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
622 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
623 txcnt <= txcnt + 1;
624 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
625 tx_start_sig <= '1';
626 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
627 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
628 txcnt <= txcnt + 1;
629 tx_data_sig <= crc_sig;
630 tx_start_sig <= '1';
631 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
632 else -- transmission finished
633 txcnt <= 0;
634 reset_crc_sig <= '1';
635 FTU_rs485_control_State <= RECEIVE;
636 end if;
637 else
638 tx_start_sig <= '0';
639 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
640 end if;
641
642 when SET_ENABLE_TRANSMIT =>
643 if tx_busy_sig = '0' then
644 if txcnt = 0 then -- start delimiter
645 txcnt <= txcnt + 1;
646 tx_data_sig <= RS485_START_DELIM;
647 tx_start_sig <= '1';
648 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
649 elsif txcnt = 1 then -- FTM address
650 txcnt <= txcnt + 1;
651 tx_data_sig <= FTM_ADDRESS;
652 tx_start_sig <= '1';
653 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
654 elsif txcnt = 2 then -- board address
655 txcnt <= txcnt + 1;
656 tx_data_sig <= "00" & brd_add;
657 tx_start_sig <= '1';
658 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
659 elsif txcnt = 3 then -- firmware ID
660 txcnt <= txcnt + 1;
661 tx_data_sig <= FIRMWARE_ID;
662 tx_start_sig <= '1';
663 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
664 elsif txcnt = 4 then -- mirrored command
665 txcnt <= txcnt + 1;
666 tx_data_sig <= "00000011";
667 tx_start_sig <= '1';
668 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
669 elsif txcnt = 5 then -- data: enable pattern A7-0
670 txcnt <= txcnt + 1;
671 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
672 tx_start_sig <= '1';
673 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
674 elsif txcnt = 6 then -- data: enable pattern A8
675 txcnt <= txcnt + 1;
676 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
677 tx_start_sig <= '1';
678 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
679 elsif txcnt = 7 then -- data: enable pattern B7-0
680 txcnt <= txcnt + 1;
681 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
682 tx_start_sig <= '1';
683 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
684 elsif txcnt = 8 then -- data: enable pattern B8
685 txcnt <= txcnt + 1;
686 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
687 tx_start_sig <= '1';
688 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
689 elsif txcnt = 9 then -- data: enable pattern C7-0
690 txcnt <= txcnt + 1;
691 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
692 tx_start_sig <= '1';
693 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
694 elsif txcnt = 10 then -- data: enable pattern C8
695 txcnt <= txcnt + 1;
696 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
697 tx_start_sig <= '1';
698 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
699 elsif txcnt = 11 then -- data: enable pattern D7-0
700 txcnt <= txcnt + 1;
701 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
702 tx_start_sig <= '1';
703 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
704 elsif txcnt = 12 then -- data: enable pattern D8
705 txcnt <= txcnt + 1;
706 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
707 tx_start_sig <= '1';
708 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
709 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
710 txcnt <= txcnt + 1;
711 tx_data_sig <= "00000000";
712 tx_start_sig <= '1';
713 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
714 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
715 txcnt <= txcnt + 1;
716 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
717 tx_start_sig <= '1';
718 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
719 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
720 txcnt <= txcnt + 1;
721 tx_data_sig <= crc_sig;
722 tx_start_sig <= '1';
723 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
724 else -- transmission finished
725 txcnt <= 0;
726 reset_crc_sig <= '1';
727 FTU_rs485_control_State <= RECEIVE;
728 end if;
729 else
730 tx_start_sig <= '0';
731 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
732 end if;
733
734 when SET_PRESCALING_TRANSMIT =>
735 if tx_busy_sig = '0' then
736 if txcnt = 0 then -- start delimiter
737 txcnt <= txcnt + 1;
738 tx_data_sig <= RS485_START_DELIM;
739 tx_start_sig <= '1';
740 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
741 elsif txcnt = 1 then -- FTM address
742 txcnt <= txcnt + 1;
743 tx_data_sig <= FTM_ADDRESS;
744 tx_start_sig <= '1';
745 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
746 elsif txcnt = 2 then -- board address
747 txcnt <= txcnt + 1;
748 tx_data_sig <= "00" & brd_add;
749 tx_start_sig <= '1';
750 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
751 elsif txcnt = 3 then -- firmware ID
752 txcnt <= txcnt + 1;
753 tx_data_sig <= FIRMWARE_ID;
754 tx_start_sig <= '1';
755 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
756 elsif txcnt = 4 then -- mirrored command
757 txcnt <= txcnt + 1;
758 tx_data_sig <= "00000110";
759 tx_start_sig <= '1';
760 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
761 elsif txcnt = 5 then -- data: prescaling
762 txcnt <= txcnt + 1;
763 tx_data_sig <= prescaling_rs485_in;
764 tx_start_sig <= '1';
765 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
766 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
767 txcnt <= txcnt + 1;
768 tx_data_sig <= "00000000";
769 tx_start_sig <= '1';
770 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
771 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
772 txcnt <= txcnt + 1;
773 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
774 tx_start_sig <= '1';
775 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
776 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
777 txcnt <= txcnt + 1;
778 tx_data_sig <= crc_sig;
779 tx_start_sig <= '1';
780 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
781 else -- transmission finished
782 txcnt <= 0;
783 reset_crc_sig <= '1';
784 FTU_rs485_control_State <= RECEIVE;
785 end if;
786 else
787 tx_start_sig <= '0';
788 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
789 end if;
790
791 when READ_RATES_TRANSMIT =>
792 if tx_busy_sig = '0' then
793 if txcnt = 0 then -- start delimiter
794 txcnt <= txcnt + 1;
795 tx_data_sig <= RS485_START_DELIM;
796 tx_start_sig <= '1';
797 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
798 elsif txcnt = 1 then -- FTM address
799 txcnt <= txcnt + 1;
800 tx_data_sig <= FTM_ADDRESS;
801 tx_start_sig <= '1';
802 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
803 elsif txcnt = 2 then -- board address
804 txcnt <= txcnt + 1;
805 tx_data_sig <= "00" & brd_add;
806 tx_start_sig <= '1';
807 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
808 elsif txcnt = 3 then -- firmware ID
809 txcnt <= txcnt + 1;
810 tx_data_sig <= FIRMWARE_ID;
811 tx_start_sig <= '1';
812 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
813 elsif txcnt = 4 then -- mirrored command
814 txcnt <= txcnt + 1;
815 tx_data_sig <= "00000010";
816 tx_start_sig <= '1';
817 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
818 elsif txcnt = 5 then -- data: counter A 7...0
819 txcnt <= txcnt + 1;
820 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0);
821 tx_start_sig <= '1';
822 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
823 elsif txcnt = 6 then -- data: counter A 15...8
824 txcnt <= txcnt + 1;
825 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8);
826 tx_start_sig <= '1';
827 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
828 elsif txcnt = 7 then -- data: counter A 23...16
829 txcnt <= txcnt + 1;
830 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16);
831 tx_start_sig <= '1';
832 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
833 elsif txcnt = 8 then -- data: counter A 31...24
834 txcnt <= txcnt + 1;
835 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24);
836 tx_start_sig <= '1';
837 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
838 elsif txcnt = 9 then -- data: counter B 7...0
839 txcnt <= txcnt + 1;
840 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0);
841 tx_start_sig <= '1';
842 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
843 elsif txcnt = 10 then -- data: counter B 15...8
844 txcnt <= txcnt + 1;
845 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8);
846 tx_start_sig <= '1';
847 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
848 elsif txcnt = 11 then -- data: counter B 23...16
849 txcnt <= txcnt + 1;
850 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16);
851 tx_start_sig <= '1';
852 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
853 elsif txcnt = 12 then -- data: counter B 31...24
854 txcnt <= txcnt + 1;
855 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24);
856 tx_start_sig <= '1';
857 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
858 elsif txcnt = 13 then -- data: counter C 7...0
859 txcnt <= txcnt + 1;
860 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0);
861 tx_start_sig <= '1';
862 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
863 elsif txcnt = 14 then -- data: counter C 15...8
864 txcnt <= txcnt + 1;
865 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8);
866 tx_start_sig <= '1';
867 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
868 elsif txcnt = 15 then -- data: counter C 23...16
869 txcnt <= txcnt + 1;
870 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16);
871 tx_start_sig <= '1';
872 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
873 elsif txcnt = 16 then -- data: counter C 31...24
874 txcnt <= txcnt + 1;
875 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24);
876 tx_start_sig <= '1';
877 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
878 elsif txcnt = 17 then -- data: counter D 7...0
879 txcnt <= txcnt + 1;
880 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0);
881 tx_start_sig <= '1';
882 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
883 elsif txcnt = 18 then -- data: counter D 15...8
884 txcnt <= txcnt + 1;
885 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8);
886 tx_start_sig <= '1';
887 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
888 elsif txcnt = 19 then -- data: counter D 23...16
889 txcnt <= txcnt + 1;
890 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16);
891 tx_start_sig <= '1';
892 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
893 elsif txcnt = 20 then -- data: counter D 31...24
894 txcnt <= txcnt + 1;
895 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24);
896 tx_start_sig <= '1';
897 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
898 elsif txcnt = 21 then -- data: trigger counter 7...0
899 txcnt <= txcnt + 1;
900 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0);
901 tx_start_sig <= '1';
902 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
903 elsif txcnt = 22 then -- data: trigger counter 15...8
904 txcnt <= txcnt + 1;
905 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8);
906 tx_start_sig <= '1';
907 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
908 elsif txcnt = 23 then -- data: trigger counter 23...16
909 txcnt <= txcnt + 1;
910 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16);
911 tx_start_sig <= '1';
912 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
913 elsif txcnt = 24 then -- data: trigger counter 31...24
914 txcnt <= txcnt + 1;
915 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24);
916 tx_start_sig <= '1';
917 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
918 elsif txcnt = 25 then -- data: overflow register
919 txcnt <= txcnt + 1;
920 tx_data_sig <= overflow_array_rs485_in;
921 tx_start_sig <= '1';
922 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
923 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
924 txcnt <= txcnt + 1;
925 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
926 tx_start_sig <= '1';
927 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
928 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
929 txcnt <= txcnt + 1;
930 tx_data_sig <= crc_sig;
931 tx_start_sig <= '1';
932 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
933 else -- transmission finished
934 txcnt <= 0;
935 reset_crc_sig <= '1';
936 FTU_rs485_control_State <= RECEIVE;
937 end if;
938 else
939 tx_start_sig <= '0';
940 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
941 end if;
942
943 when READ_DAC_TRANSMIT =>
944 if tx_busy_sig = '0' then
945 if txcnt = 0 then -- start delimiter
946 txcnt <= txcnt + 1;
947 tx_data_sig <= RS485_START_DELIM;
948 tx_start_sig <= '1';
949 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
950 elsif txcnt = 1 then -- FTM address
951 txcnt <= txcnt + 1;
952 tx_data_sig <= FTM_ADDRESS;
953 tx_start_sig <= '1';
954 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
955 elsif txcnt = 2 then -- board address
956 txcnt <= txcnt + 1;
957 tx_data_sig <= "00" & brd_add;
958 tx_start_sig <= '1';
959 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
960 elsif txcnt = 3 then -- firmware ID
961 txcnt <= txcnt + 1;
962 tx_data_sig <= FIRMWARE_ID;
963 tx_start_sig <= '1';
964 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
965 elsif txcnt = 4 then -- mirrored command
966 txcnt <= txcnt + 1;
967 tx_data_sig <= "00000001";
968 tx_start_sig <= '1';
969 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
970 elsif txcnt = 5 then -- data: DAC A low
971 txcnt <= txcnt + 1;
972 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
973 tx_start_sig <= '1';
974 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
975 elsif txcnt = 6 then -- data: DAC A high
976 txcnt <= txcnt + 1;
977 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
978 tx_start_sig <= '1';
979 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
980 elsif txcnt = 7 then -- data: DAC B low
981 txcnt <= txcnt + 1;
982 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
983 tx_start_sig <= '1';
984 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
985 elsif txcnt = 8 then -- data: DAC B high
986 txcnt <= txcnt + 1;
987 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
988 tx_start_sig <= '1';
989 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
990 elsif txcnt = 9 then -- data: DAC C low
991 txcnt <= txcnt + 1;
992 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
993 tx_start_sig <= '1';
994 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
995 elsif txcnt = 10 then -- data: DAC C high
996 txcnt <= txcnt + 1;
997 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
998 tx_start_sig <= '1';
999 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1000 elsif txcnt = 11 then -- data: DAC D low
1001 txcnt <= txcnt + 1;
1002 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
1003 tx_start_sig <= '1';
1004 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1005 elsif txcnt = 12 then -- data: DAC D high
1006 txcnt <= txcnt + 1;
1007 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
1008 tx_start_sig <= '1';
1009 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1010 elsif txcnt = 13 then -- data: DAC E low
1011 txcnt <= txcnt + 1;
1012 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
1013 tx_start_sig <= '1';
1014 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1015 elsif txcnt = 14 then -- data: DAC E high
1016 txcnt <= txcnt + 1;
1017 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
1018 tx_start_sig <= '1';
1019 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1020 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1021 txcnt <= txcnt + 1;
1022 tx_data_sig <= "00000000";
1023 tx_start_sig <= '1';
1024 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1025 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1026 txcnt <= txcnt + 1;
1027 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1028 tx_start_sig <= '1';
1029 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1030 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1031 txcnt <= txcnt + 1;
1032 tx_data_sig <= crc_sig;
1033 tx_start_sig <= '1';
1034 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1035 else -- transmission finished
1036 txcnt <= 0;
1037 reset_crc_sig <= '1';
1038 FTU_rs485_control_State <= RECEIVE;
1039 end if;
1040 else
1041 tx_start_sig <= '0';
1042 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
1043 end if;
1044
1045 when READ_ENABLE_TRANSMIT =>
1046 if tx_busy_sig = '0' then
1047 if txcnt = 0 then -- start delimiter
1048 txcnt <= txcnt + 1;
1049 tx_data_sig <= RS485_START_DELIM;
1050 tx_start_sig <= '1';
1051 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1052 elsif txcnt = 1 then -- FTM address
1053 txcnt <= txcnt + 1;
1054 tx_data_sig <= FTM_ADDRESS;
1055 tx_start_sig <= '1';
1056 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1057 elsif txcnt = 2 then -- board address
1058 txcnt <= txcnt + 1;
1059 tx_data_sig <= "00" & brd_add;
1060 tx_start_sig <= '1';
1061 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1062 elsif txcnt = 3 then -- firmware ID
1063 txcnt <= txcnt + 1;
1064 tx_data_sig <= FIRMWARE_ID;
1065 tx_start_sig <= '1';
1066 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1067 elsif txcnt = 4 then -- mirrored command
1068 txcnt <= txcnt + 1;
1069 tx_data_sig <= "00000100";
1070 tx_start_sig <= '1';
1071 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1072 elsif txcnt = 5 then -- data: enable pattern A7-0
1073 txcnt <= txcnt + 1;
1074 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
1075 tx_start_sig <= '1';
1076 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1077 elsif txcnt = 6 then -- data: enable pattern A8
1078 txcnt <= txcnt + 1;
1079 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
1080 tx_start_sig <= '1';
1081 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1082 elsif txcnt = 7 then -- data: enable pattern B7-0
1083 txcnt <= txcnt + 1;
1084 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
1085 tx_start_sig <= '1';
1086 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1087 elsif txcnt = 8 then -- data: enable pattern B8
1088 txcnt <= txcnt + 1;
1089 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
1090 tx_start_sig <= '1';
1091 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1092 elsif txcnt = 9 then -- data: enable pattern C7-0
1093 txcnt <= txcnt + 1;
1094 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
1095 tx_start_sig <= '1';
1096 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1097 elsif txcnt = 10 then -- data: enable pattern C8
1098 txcnt <= txcnt + 1;
1099 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
1100 tx_start_sig <= '1';
1101 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1102 elsif txcnt = 11 then -- data: enable pattern D7-0
1103 txcnt <= txcnt + 1;
1104 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
1105 tx_start_sig <= '1';
1106 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1107 elsif txcnt = 12 then -- data: enable pattern D8
1108 txcnt <= txcnt + 1;
1109 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
1110 tx_start_sig <= '1';
1111 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1112 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1113 txcnt <= txcnt + 1;
1114 tx_data_sig <= "00000000";
1115 tx_start_sig <= '1';
1116 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1117 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1118 txcnt <= txcnt + 1;
1119 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1120 tx_start_sig <= '1';
1121 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1122 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1123 txcnt <= txcnt + 1;
1124 tx_data_sig <= crc_sig;
1125 tx_start_sig <= '1';
1126 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1127 else -- transmission finished
1128 txcnt <= 0;
1129 reset_crc_sig <= '1';
1130 FTU_rs485_control_State <= RECEIVE;
1131 end if;
1132 else
1133 tx_start_sig <= '0';
1134 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
1135 end if;
1136
1137 when READ_PRESCALING_TRANSMIT =>
1138 if tx_busy_sig = '0' then
1139 if txcnt = 0 then -- start delimiter
1140 txcnt <= txcnt + 1;
1141 tx_data_sig <= RS485_START_DELIM;
1142 tx_start_sig <= '1';
1143 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1144 elsif txcnt = 1 then -- FTM address
1145 txcnt <= txcnt + 1;
1146 tx_data_sig <= FTM_ADDRESS;
1147 tx_start_sig <= '1';
1148 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1149 elsif txcnt = 2 then -- board address
1150 txcnt <= txcnt + 1;
1151 tx_data_sig <= "00" & brd_add;
1152 tx_start_sig <= '1';
1153 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1154 elsif txcnt = 3 then -- firmware ID
1155 txcnt <= txcnt + 1;
1156 tx_data_sig <= FIRMWARE_ID;
1157 tx_start_sig <= '1';
1158 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1159 elsif txcnt = 4 then -- mirrored command
1160 txcnt <= txcnt + 1;
1161 tx_data_sig <= "00000111";
1162 tx_start_sig <= '1';
1163 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1164 elsif txcnt = 5 then -- data: prescaling
1165 txcnt <= txcnt + 1;
1166 tx_data_sig <= prescaling_rs485_in;
1167 tx_start_sig <= '1';
1168 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1169 elsif txcnt = 6 then -- data: overflow register
1170 txcnt <= txcnt + 1;
1171 tx_data_sig <= overflow_array_rs485_in;
1172 tx_start_sig <= '1';
1173 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1174 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1175 txcnt <= txcnt + 1;
1176 tx_data_sig <= "00000000";
1177 tx_start_sig <= '1';
1178 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1179 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1180 txcnt <= txcnt + 1;
1181 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1182 tx_start_sig <= '1';
1183 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1184 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1185 txcnt <= txcnt + 1;
1186 tx_data_sig <= crc_sig;
1187 tx_start_sig <= '1';
1188 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1189 else -- transmission finished
1190 txcnt <= 0;
1191 reset_crc_sig <= '1';
1192 FTU_rs485_control_State <= RECEIVE;
1193 end if;
1194 else
1195 tx_start_sig <= '0';
1196 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
1197 end if;
1198
1199 when PING_PONG_TRANSMIT =>
1200 crc_enable_sig <= '0';
1201 if tx_busy_sig = '0' then
1202 if txcnt = 0 then -- start delimiter
1203 txcnt <= txcnt + 1;
1204 tx_data_sig <= RS485_START_DELIM;
1205 tx_start_sig <= '1';
1206 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1207 elsif txcnt = 1 then -- FTM address
1208 txcnt <= txcnt + 1;
1209 tx_data_sig <= FTM_ADDRESS;
1210 tx_start_sig <= '1';
1211 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1212 elsif txcnt = 2 then -- board address
1213 txcnt <= txcnt + 1;
1214 tx_data_sig <= "00" & brd_add;
1215 tx_start_sig <= '1';
1216 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1217 elsif txcnt = 3 then -- firmware ID
1218 txcnt <= txcnt + 1;
1219 tx_data_sig <= FIRMWARE_ID;
1220 tx_start_sig <= '1';
1221 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1222 elsif txcnt = 4 then -- mirrored command
1223 txcnt <= txcnt + 1;
1224 tx_data_sig <= "00000101";
1225 tx_start_sig <= '1';
1226 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1227 elsif txcnt = 5 then -- data: device DNA
1228 txcnt <= txcnt + 1;
1229 tx_data_sig <= dna(7 downto 0);
1230 tx_start_sig <= '1';
1231 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1232 elsif txcnt = 6 then -- data: device DNA
1233 txcnt <= txcnt + 1;
1234 tx_data_sig <= dna(15 downto 8);
1235 tx_start_sig <= '1';
1236 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1237 elsif txcnt = 7 then -- data: device DNA
1238 txcnt <= txcnt + 1;
1239 tx_data_sig <= dna(23 downto 16);
1240 tx_start_sig <= '1';
1241 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1242 elsif txcnt = 8 then -- data: device DNA
1243 txcnt <= txcnt + 1;
1244 tx_data_sig <= dna(31 downto 24);
1245 tx_start_sig <= '1';
1246 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1247 elsif txcnt = 9 then -- data: device DNA
1248 txcnt <= txcnt + 1;
1249 tx_data_sig <= dna(39 downto 32);
1250 tx_start_sig <= '1';
1251 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1252 elsif txcnt = 10 then -- data: device DNA
1253 txcnt <= txcnt + 1;
1254 tx_data_sig <= dna(47 downto 40);
1255 tx_start_sig <= '1';
1256 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1257 elsif txcnt = 11 then -- data: device DNA
1258 txcnt <= txcnt + 1;
1259 tx_data_sig <= dna(55 downto 48);
1260 tx_start_sig <= '1';
1261 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1262 elsif txcnt = 12 then -- data: device DNA
1263 txcnt <= txcnt + 1;
1264 tx_data_sig <= dna(63 downto 56);
1265 tx_start_sig <= '1';
1266 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1267 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used
1268 txcnt <= txcnt + 1;
1269 tx_data_sig <= "00000000";
1270 tx_start_sig <= '1';
1271 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1272 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter
1273 txcnt <= txcnt + 1;
1274 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
1275 tx_start_sig <= '1';
1276 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1277 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum
1278 txcnt <= txcnt + 1;
1279 tx_data_sig <= crc_sig;
1280 tx_start_sig <= '1';
1281 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1282 else -- transmission finished
1283 txcnt <= 0;
1284 reset_crc_sig <= '1';
1285 FTU_rs485_control_State <= RECEIVE;
1286 end if;
1287 else
1288 tx_start_sig <= '0';
1289 FTU_rs485_control_State <= PING_PONG_TRANSMIT;
1290 end if;
1291
1292 end case;
1293 end if;
1294 end process FTU_rs485_control_FSM;
1295
1296end Behavioral;
1297
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