source: firmware/FTU/rs485/FTU_rs485_control.vhd@ 9928

Last change on this file since 9928 was 9928, checked in by weitzel, 16 years ago
first version of RS485 interface added to FTU firmware; not yet connected to main control state machine
File size: 39.1 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: top level entity of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_control is
36 port(
37 main_clk : IN std_logic;
38 brd_add : IN std_logic_vector(5 downto 0);
39 rx_d : IN std_logic;
40 rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending
41 DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending
42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending
43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending
44 rate_array_rs485 : IN rate_array_type;
45 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
46 dac_array_rs485_in : IN dac_array_type;
47 enable_array_rs485_in : IN enable_array_type;
48 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
49 rx_en : OUT std_logic;
50 tx_d : OUT std_logic;
51 tx_en : OUT std_logic;
52 new_DACs : OUT std_logic; -- new DACs arrived via RS485
53 new_enables : OUT std_logic; -- new enables arrived via RS485
54 new_prescaling : OUT std_logic; -- new prescaling arrived via RS485
55 read_rates : OUT std_logic; -- FTM wants to read rates
56 read_DACs : OUT std_logic; -- FTM wants to read DACs
57 read_enables : OUT std_logic; -- FTM wants to read enable pattern
58 read_prescaling : OUT std_logic; -- FTM wants to read prescaling value
59 --rs485_error : OUT std_logic; -- to be discussed!
60 dac_array_rs485_out : OUT dac_array_type;
61 enable_array_rs485_out : OUT enable_array_type;
62 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
63 );
64end FTU_rs485_control;
65
66architecture Behavioral of FTU_rs485_control is
67
68 signal tx_start_sig : std_logic := '0';
69 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
70 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
71
72 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface
73 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface
74 signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
75
76 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver
77 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver
78
79 signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
80 signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
81 signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
82 signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter
83 signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
84 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
85 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
86
87 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames
88
89 component FTU_rs485_receiver
90 port(
91 rec_clk : in std_logic;
92 --rx_busy : in std_logic;
93 rec_din : in std_logic_vector(7 downto 0);
94 rec_den : in std_logic;
95 rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
96 rec_valid : out std_logic
97 );
98 end component;
99
100 component FTU_rs485_interpreter
101 port(
102 clk : IN std_logic;
103 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
104 block_valid : IN std_logic;
105 brd_add : IN std_logic_vector(5 downto 0);
106 int_new_DACs : OUT std_logic;
107 int_new_enables : OUT std_logic;
108 int_new_prescaling : OUT std_logic;
109 int_read_rates : OUT std_logic;
110 int_read_DACs : OUT std_logic;
111 int_read_enables : OUT std_logic;
112 int_read_prescaling : OUT std_logic;
113 dac_array_rs485_out : OUT dac_array_type;
114 enable_array_rs485_out : OUT enable_array_type;
115 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
116 );
117 end component;
118
119 component FTU_rs485_interface
120 port(
121 clk : IN std_logic;
122 -- RS485
123 rx_d : IN std_logic;
124 rx_en : OUT std_logic;
125 tx_d : OUT std_logic;
126 tx_en : OUT std_logic;
127 -- FPGA
128 rx_data : OUT std_logic_vector (7 DOWNTO 0);
129 rx_busy : OUT std_logic := '0';
130 rx_valid : OUT std_logic := '0';
131 tx_data : IN std_logic_vector (7 DOWNTO 0);
132 tx_busy : OUT std_logic := '0';
133 tx_start : IN std_logic
134 );
135 end component;
136
137 type FTU_rs485_control_StateType is (RECEIVE,
138 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
139 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT,
140 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
141 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT);
142 signal FTU_rs485_control_State : FTU_rs485_control_StateType;
143
144begin
145
146 Inst_FTU_rs485_receiver : FTU_rs485_receiver
147 port map(
148 rec_clk => main_clk,
149 --rx_busy =>,
150 rec_din => rx_data_sig,
151 rec_den => rx_valid_sig,
152 rec_dout => data_block_sig,
153 rec_valid => block_valid_sig
154 );
155
156 Inst_FTU_rs485_interpreter : FTU_rs485_interpreter
157 port map(
158 clk => main_clk,
159 data_block => data_block_sig,
160 block_valid => block_valid_sig,
161 brd_add => brd_add,
162 int_new_DACs => int_new_DACs_sig,
163 int_new_enables => int_new_enables_sig,
164 int_new_prescaling => int_new_prescaling_sig,
165 int_read_rates => int_read_rates_sig,
166 int_read_DACs => int_read_DACs_sig,
167 int_read_enables => int_read_enables_sig,
168 int_read_prescaling => int_read_prescaling_sig,
169 dac_array_rs485_out => dac_array_rs485_out,
170 enable_array_rs485_out => enable_array_rs485_out,
171 prescaling_rs485_out => prescaling_rs485_out
172 );
173
174 Inst_FTU_rs485_interface : FTU_rs485_interface
175 port map(
176 clk => main_clk,
177 -- RS485
178 rx_d => rx_d,
179 rx_en => rx_en,
180 tx_d => tx_d,
181 tx_en => tx_en,
182 -- FPGA
183 rx_data => rx_data_sig,
184 rx_busy => rx_busy_sig,
185 rx_valid => rx_valid_sig,
186 tx_data => tx_data_sig,
187 tx_busy => tx_busy_sig,
188 tx_start => tx_start_sig
189 );
190
191 --FTU RS485 control finite state machine
192
193 FTU_rs485_control_FSM: process (main_clk)
194 begin
195 if Rising_edge(main_clk) then
196 case FTU_rs485_control_State is
197
198 when RECEIVE => -- default state, receiver on, no transmission
199 tx_start_sig <= '0';
200 if (int_new_DACs_sig = '1') then
201 new_DACs <= '1';
202 new_enables <= '0';
203 new_prescaling <= '0';
204 read_rates <= '0';
205 read_DACs <= '0';
206 read_enables <= '0';
207 read_prescaling <= '0';
208 FTU_rs485_control_State <= SET_DAC_WAIT;
209 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then
210 new_DACs <= '0';
211 new_enables <= '1';
212 new_prescaling <= '0';
213 read_rates <= '0';
214 read_DACs <= '0';
215 read_enables <= '0';
216 read_prescaling <= '0';
217 FTU_rs485_control_State <= SET_ENABLE_WAIT;
218 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then
219 new_DACs <= '0';
220 new_enables <= '0';
221 new_prescaling <= '1';
222 read_rates <= '0';
223 read_DACs <= '0';
224 read_enables <= '0';
225 read_prescaling <= '0';
226 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
227 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
228 int_read_rates_sig = '1') then
229 new_DACs <= '0';
230 new_enables <= '0';
231 new_prescaling <= '0';
232 read_rates <= '1';
233 read_DACs <= '0';
234 read_enables <= '0';
235 read_prescaling <= '0';
236 FTU_rs485_control_State <= READ_RATES_WAIT;
237 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
238 int_read_rates_sig = '0' and int_read_DACs_sig = '1') then
239 new_DACs <= '0';
240 new_enables <= '0';
241 new_prescaling <= '0';
242 read_rates <= '0';
243 read_DACs <= '1';
244 read_enables <= '0';
245 read_prescaling <= '0';
246 FTU_rs485_control_State <= READ_DAC_WAIT;
247 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
248 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then
249 new_DACs <= '0';
250 new_enables <= '0';
251 new_prescaling <= '0';
252 read_rates <= '0';
253 read_DACs <= '0';
254 read_enables <= '1';
255 read_prescaling <= '0';
256 FTU_rs485_control_State <= READ_ENABLE_WAIT;
257 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
258 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then
259 new_DACs <= '0';
260 new_enables <= '0';
261 new_prescaling <= '0';
262 read_rates <= '0';
263 read_DACs <= '0';
264 read_enables <= '0';
265 read_prescaling <= '1';
266 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
267 else
268 new_DACs <= '0';
269 new_enables <= '0';
270 new_prescaling <= '0';
271 read_rates <= '0';
272 read_DACs <= '0';
273 read_enables <= '0';
274 read_prescaling <= '0';
275 FTU_rs485_control_State <= RECEIVE;
276 end if;
277
278 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM
279 if (DACs_ready = '1') then
280 new_DACs <= '0';
281 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
282 else
283 new_DACs <= '1';
284 FTU_rs485_control_State <= SET_DAC_WAIT;
285 end if;
286
287 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
288 if (enables_ready = '1') then
289 new_enables <= '0';
290 FTU_rs485_control_State <= RECEIVE;
291 else
292 new_enables <= '1';
293 FTU_rs485_control_State <= SET_ENABLE_WAIT;
294 end if;
295
296 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
297 if (prescaling_ready = '1') then
298 new_prescaling <= '0';
299 FTU_rs485_control_State <= RECEIVE;
300 else
301 new_prescaling <= '1';
302 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
303 end if;
304
305 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM
306 if (rates_ready = '1') then
307 read_rates <= '0';
308 FTU_rs485_control_State <= RECEIVE;
309 else
310 read_rates <= '1';
311 FTU_rs485_control_State <= READ_RATES_WAIT;
312 end if;
313
314 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM
315 if (DACs_ready = '1') then
316 read_DACs <= '0';
317 FTU_rs485_control_State <= RECEIVE;
318 else
319 read_DACs <= '1';
320 FTU_rs485_control_State <= READ_DAC_WAIT;
321 end if;
322
323 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
324 if (enables_ready = '1') then
325 read_enables <= '0';
326 FTU_rs485_control_State <= RECEIVE;
327 else
328 read_enables <= '1';
329 FTU_rs485_control_State <= READ_ENABLE_WAIT;
330 end if;
331
332 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
333 if (prescaling_ready = '1') then
334 read_prescaling <= '0';
335 FTU_rs485_control_State <= RECEIVE;
336 else
337 read_prescaling <= '1';
338 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
339 end if;
340
341 when SET_DAC_TRANSMIT =>
342 if tx_busy_sig = '0' then
343 if txcnt = 0 then -- start delimiter
344 txcnt <= txcnt + 1;
345 tx_data_sig <= RS485_START_DELIM;
346 tx_start_sig <= '1';
347 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
348 elsif txcnt = 1 then -- FTM address
349 txcnt <= txcnt + 1;
350 tx_data_sig <= FTM_ADDRESS;
351 tx_start_sig <= '1';
352 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
353 elsif txcnt = 2 then -- board address
354 txcnt <= txcnt + 1;
355 tx_data_sig <= "00" & brd_add;
356 tx_start_sig <= '1';
357 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
358 elsif txcnt = 3 then -- mirrored command
359 txcnt <= txcnt + 1;
360 tx_data_sig <= "00000000";
361 tx_start_sig <= '1';
362 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
363 elsif txcnt = 4 then -- data: DAC A low
364 txcnt <= txcnt + 1;
365 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
366 tx_start_sig <= '1';
367 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
368 elsif txcnt = 5 then -- data: DAC A high
369 txcnt <= txcnt + 1;
370 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
371 tx_start_sig <= '1';
372 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
373 elsif txcnt = 6 then -- data: DAC B low
374 txcnt <= txcnt + 1;
375 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
376 tx_start_sig <= '1';
377 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
378 elsif txcnt = 7 then -- data: DAC B high
379 txcnt <= txcnt + 1;
380 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
381 tx_start_sig <= '1';
382 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
383 elsif txcnt = 8 then -- data: DAC C low
384 txcnt <= txcnt + 1;
385 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
386 tx_start_sig <= '1';
387 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
388 elsif txcnt = 9 then -- data: DAC C high
389 txcnt <= txcnt + 1;
390 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
391 tx_start_sig <= '1';
392 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
393 elsif txcnt = 10 then -- data: DAC D low
394 txcnt <= txcnt + 1;
395 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
396 tx_start_sig <= '1';
397 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
398 elsif txcnt = 11 then -- data: DAC D high
399 txcnt <= txcnt + 1;
400 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
401 tx_start_sig <= '1';
402 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
403 elsif txcnt = 12 then -- data: DAC E low
404 txcnt <= txcnt + 1;
405 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
406 tx_start_sig <= '1';
407 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
408 elsif txcnt = 13 then -- data: DAC E high
409 txcnt <= txcnt + 1;
410 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
411 tx_start_sig <= '1';
412 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
413 elsif txcnt < 15 then -- data: not used
414 txcnt <= txcnt + 1;
415 tx_data_sig <= "00000000";
416 tx_start_sig <= '1';
417 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
418 elsif txcnt = 15 then -- check sum
419 txcnt <= txcnt + 1;
420 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
421 tx_start_sig <= '1';
422 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
423 else -- transmission finished
424 txcnt <= 0;
425 FTU_rs485_control_State <= RECEIVE;
426 end if;
427 else
428 tx_start_sig <= '0';
429 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
430 end if;
431
432 when SET_ENABLE_TRANSMIT =>
433 if tx_busy_sig = '0' then
434 if txcnt = 0 then -- start delimiter
435 txcnt <= txcnt + 1;
436 tx_data_sig <= RS485_START_DELIM;
437 tx_start_sig <= '1';
438 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
439 elsif txcnt = 1 then -- FTM address
440 txcnt <= txcnt + 1;
441 tx_data_sig <= FTM_ADDRESS;
442 tx_start_sig <= '1';
443 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
444 elsif txcnt = 2 then -- board address
445 txcnt <= txcnt + 1;
446 tx_data_sig <= "00" & brd_add;
447 tx_start_sig <= '1';
448 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
449 elsif txcnt = 3 then -- mirrored command
450 txcnt <= txcnt + 1;
451 tx_data_sig <= "00000011";
452 tx_start_sig <= '1';
453 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
454 elsif txcnt = 4 then -- data: enable pattern A7-0
455 txcnt <= txcnt + 1;
456 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
457 tx_start_sig <= '1';
458 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
459 elsif txcnt = 5 then -- data: enable pattern A8
460 txcnt <= txcnt + 1;
461 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
462 tx_start_sig <= '1';
463 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
464 elsif txcnt = 6 then -- data: enable pattern B7-0
465 txcnt <= txcnt + 1;
466 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
467 tx_start_sig <= '1';
468 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
469 elsif txcnt = 7 then -- data: enable pattern B8
470 txcnt <= txcnt + 1;
471 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
472 tx_start_sig <= '1';
473 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
474 elsif txcnt = 8 then -- data: enable pattern C7-0
475 txcnt <= txcnt + 1;
476 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
477 tx_start_sig <= '1';
478 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
479 elsif txcnt = 9 then -- data: enable pattern C8
480 txcnt <= txcnt + 1;
481 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
482 tx_start_sig <= '1';
483 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
484 elsif txcnt = 10 then -- data: enable pattern D7-0
485 txcnt <= txcnt + 1;
486 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
487 tx_start_sig <= '1';
488 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
489 elsif txcnt = 11 then -- data: enable pattern D8
490 txcnt <= txcnt + 1;
491 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
492 tx_start_sig <= '1';
493 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
494 elsif txcnt < 15 then -- data: not used
495 txcnt <= txcnt + 1;
496 tx_data_sig <= "00000000";
497 tx_start_sig <= '1';
498 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
499 elsif txcnt = 15 then -- check sum
500 txcnt <= txcnt + 1;
501 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
502 tx_start_sig <= '1';
503 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
504 else -- transmission finished
505 txcnt <= 0;
506 FTU_rs485_control_State <= RECEIVE;
507 end if;
508 else
509 tx_start_sig <= '0';
510 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
511 end if;
512
513 when SET_PRESCALING_TRANSMIT =>
514 if tx_busy_sig = '0' then
515 if txcnt = 0 then -- start delimiter
516 txcnt <= txcnt + 1;
517 tx_data_sig <= RS485_START_DELIM;
518 tx_start_sig <= '1';
519 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
520 elsif txcnt = 1 then -- FTM address
521 txcnt <= txcnt + 1;
522 tx_data_sig <= FTM_ADDRESS;
523 tx_start_sig <= '1';
524 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
525 elsif txcnt = 2 then -- board address
526 txcnt <= txcnt + 1;
527 tx_data_sig <= "00" & brd_add;
528 tx_start_sig <= '1';
529 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
530 elsif txcnt = 3 then -- mirrored command
531 txcnt <= txcnt + 1;
532 tx_data_sig <= "00000110";
533 tx_start_sig <= '1';
534 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
535 elsif txcnt = 4 then -- data: prescaling
536 txcnt <= txcnt + 1;
537 tx_data_sig <= prescaling_rs485_in;
538 tx_start_sig <= '1';
539 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
540 elsif txcnt < 15 then -- data: not used
541 txcnt <= txcnt + 1;
542 tx_data_sig <= "00000000";
543 tx_start_sig <= '1';
544 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
545 elsif txcnt = 15 then -- check sum
546 txcnt <= txcnt + 1;
547 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
548 tx_start_sig <= '1';
549 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
550 else -- transmission finished
551 txcnt <= 0;
552 FTU_rs485_control_State <= RECEIVE;
553 end if;
554 else
555 tx_start_sig <= '0';
556 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
557 end if;
558
559 when READ_RATES_TRANSMIT =>
560 if tx_busy_sig = '0' then
561 if txcnt = 0 then -- start delimiter
562 txcnt <= txcnt + 1;
563 tx_data_sig <= RS485_START_DELIM;
564 tx_start_sig <= '1';
565 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
566 elsif txcnt = 1 then -- FTM address
567 txcnt <= txcnt + 1;
568 tx_data_sig <= FTM_ADDRESS;
569 tx_start_sig <= '1';
570 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
571 elsif txcnt = 2 then -- board address
572 txcnt <= txcnt + 1;
573 tx_data_sig <= "00" & brd_add;
574 tx_start_sig <= '1';
575 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
576 elsif txcnt = 3 then -- mirrored command
577 txcnt <= txcnt + 1;
578 tx_data_sig <= "00000010";
579 tx_start_sig <= '1';
580 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
581 elsif txcnt = 4 then -- data: counter A low
582 txcnt <= txcnt + 1;
583 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(7 downto 0);
584 tx_start_sig <= '1';
585 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
586 elsif txcnt = 5 then -- data: counter A high
587 txcnt <= txcnt + 1;
588 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(15 downto 8);
589 tx_start_sig <= '1';
590 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
591 elsif txcnt = 6 then -- data: counter B low
592 txcnt <= txcnt + 1;
593 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(7 downto 0);
594 tx_start_sig <= '1';
595 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
596 elsif txcnt = 7 then -- data: counter B high
597 txcnt <= txcnt + 1;
598 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(15 downto 8);
599 tx_start_sig <= '1';
600 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
601 elsif txcnt = 8 then -- data: counter C low
602 txcnt <= txcnt + 1;
603 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(7 downto 0);
604 tx_start_sig <= '1';
605 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
606 elsif txcnt = 9 then -- data: counter C high
607 txcnt <= txcnt + 1;
608 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(15 downto 8);
609 tx_start_sig <= '1';
610 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
611 elsif txcnt = 10 then -- data: counter D low
612 txcnt <= txcnt + 1;
613 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(7 downto 0);
614 tx_start_sig <= '1';
615 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
616 elsif txcnt = 11 then -- data: counter D high
617 txcnt <= txcnt + 1;
618 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(15 downto 8);
619 tx_start_sig <= '1';
620 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
621 elsif txcnt = 12 then -- data: trigger counter low
622 txcnt <= txcnt + 1;
623 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(7 downto 0);
624 tx_start_sig <= '1';
625 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
626 elsif txcnt = 13 then -- data: trigger counter high
627 txcnt <= txcnt + 1;
628 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(15 downto 8);
629 tx_start_sig <= '1';
630 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
631 elsif txcnt = 14 then -- data: overflow register
632 txcnt <= txcnt + 1;
633 tx_data_sig <= overflow_array_rs485_in;
634 tx_start_sig <= '1';
635 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
636 elsif txcnt = 15 then -- check sum
637 txcnt <= txcnt + 1;
638 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
639 tx_start_sig <= '1';
640 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
641 else -- transmission finished
642 txcnt <= 0;
643 FTU_rs485_control_State <= RECEIVE;
644 end if;
645 else
646 tx_start_sig <= '0';
647 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
648 end if;
649
650 when READ_DAC_TRANSMIT =>
651 if tx_busy_sig = '0' then
652 if txcnt = 0 then -- start delimiter
653 txcnt <= txcnt + 1;
654 tx_data_sig <= RS485_START_DELIM;
655 tx_start_sig <= '1';
656 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
657 elsif txcnt = 1 then -- FTM address
658 txcnt <= txcnt + 1;
659 tx_data_sig <= FTM_ADDRESS;
660 tx_start_sig <= '1';
661 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
662 elsif txcnt = 2 then -- board address
663 txcnt <= txcnt + 1;
664 tx_data_sig <= "00" & brd_add;
665 tx_start_sig <= '1';
666 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
667 elsif txcnt = 3 then -- mirrored command
668 txcnt <= txcnt + 1;
669 tx_data_sig <= "00000001";
670 tx_start_sig <= '1';
671 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
672 elsif txcnt = 4 then -- data: DAC A low
673 txcnt <= txcnt + 1;
674 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
675 tx_start_sig <= '1';
676 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
677 elsif txcnt = 5 then -- data: DAC A high
678 txcnt <= txcnt + 1;
679 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
680 tx_start_sig <= '1';
681 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
682 elsif txcnt = 6 then -- data: DAC B low
683 txcnt <= txcnt + 1;
684 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
685 tx_start_sig <= '1';
686 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
687 elsif txcnt = 7 then -- data: DAC B high
688 txcnt <= txcnt + 1;
689 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
690 tx_start_sig <= '1';
691 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
692 elsif txcnt = 8 then -- data: DAC C low
693 txcnt <= txcnt + 1;
694 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
695 tx_start_sig <= '1';
696 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
697 elsif txcnt = 9 then -- data: DAC C high
698 txcnt <= txcnt + 1;
699 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
700 tx_start_sig <= '1';
701 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
702 elsif txcnt = 10 then -- data: DAC D low
703 txcnt <= txcnt + 1;
704 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
705 tx_start_sig <= '1';
706 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
707 elsif txcnt = 11 then -- data: DAC D high
708 txcnt <= txcnt + 1;
709 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
710 tx_start_sig <= '1';
711 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
712 elsif txcnt = 12 then -- data: DAC E low
713 txcnt <= txcnt + 1;
714 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
715 tx_start_sig <= '1';
716 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
717 elsif txcnt = 13 then -- data: DAC E high
718 txcnt <= txcnt + 1;
719 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
720 tx_start_sig <= '1';
721 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
722 elsif txcnt < 15 then -- data: not used
723 txcnt <= txcnt + 1;
724 tx_data_sig <= "00000000";
725 tx_start_sig <= '1';
726 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
727 elsif txcnt = 15 then -- check sum
728 txcnt <= txcnt + 1;
729 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
730 tx_start_sig <= '1';
731 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
732 else -- transmission finished
733 txcnt <= 0;
734 FTU_rs485_control_State <= RECEIVE;
735 end if;
736 else
737 tx_start_sig <= '0';
738 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
739 end if;
740
741 when READ_ENABLE_TRANSMIT =>
742 if tx_busy_sig = '0' then
743 if txcnt = 0 then -- start delimiter
744 txcnt <= txcnt + 1;
745 tx_data_sig <= RS485_START_DELIM;
746 tx_start_sig <= '1';
747 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
748 elsif txcnt = 1 then -- FTM address
749 txcnt <= txcnt + 1;
750 tx_data_sig <= FTM_ADDRESS;
751 tx_start_sig <= '1';
752 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
753 elsif txcnt = 2 then -- board address
754 txcnt <= txcnt + 1;
755 tx_data_sig <= "00" & brd_add;
756 tx_start_sig <= '1';
757 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
758 elsif txcnt = 3 then -- mirrored command
759 txcnt <= txcnt + 1;
760 tx_data_sig <= "00000100";
761 tx_start_sig <= '1';
762 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
763 elsif txcnt = 4 then -- data: enable pattern A7-0
764 txcnt <= txcnt + 1;
765 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
766 tx_start_sig <= '1';
767 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
768 elsif txcnt = 5 then -- data: enable pattern A8
769 txcnt <= txcnt + 1;
770 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
771 tx_start_sig <= '1';
772 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
773 elsif txcnt = 6 then -- data: enable pattern B7-0
774 txcnt <= txcnt + 1;
775 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
776 tx_start_sig <= '1';
777 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
778 elsif txcnt = 7 then -- data: enable pattern B8
779 txcnt <= txcnt + 1;
780 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
781 tx_start_sig <= '1';
782 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
783 elsif txcnt = 8 then -- data: enable pattern C7-0
784 txcnt <= txcnt + 1;
785 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
786 tx_start_sig <= '1';
787 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
788 elsif txcnt = 9 then -- data: enable pattern C8
789 txcnt <= txcnt + 1;
790 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
791 tx_start_sig <= '1';
792 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
793 elsif txcnt = 10 then -- data: enable pattern D7-0
794 txcnt <= txcnt + 1;
795 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
796 tx_start_sig <= '1';
797 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
798 elsif txcnt = 11 then -- data: enable pattern D8
799 txcnt <= txcnt + 1;
800 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
801 tx_start_sig <= '1';
802 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
803 elsif txcnt < 15 then -- data: not used
804 txcnt <= txcnt + 1;
805 tx_data_sig <= "00000000";
806 tx_start_sig <= '1';
807 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
808 elsif txcnt = 15 then -- check sum
809 txcnt <= txcnt + 1;
810 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
811 tx_start_sig <= '1';
812 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
813 else -- transmission finished
814 txcnt <= 0;
815 FTU_rs485_control_State <= RECEIVE;
816 end if;
817 else
818 tx_start_sig <= '0';
819 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
820 end if;
821
822 when READ_PRESCALING_TRANSMIT =>
823 if tx_busy_sig = '0' then
824 if txcnt = 0 then -- start delimiter
825 txcnt <= txcnt + 1;
826 tx_data_sig <= RS485_START_DELIM;
827 tx_start_sig <= '1';
828 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
829 elsif txcnt = 1 then -- FTM address
830 txcnt <= txcnt + 1;
831 tx_data_sig <= FTM_ADDRESS;
832 tx_start_sig <= '1';
833 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
834 elsif txcnt = 2 then -- board address
835 txcnt <= txcnt + 1;
836 tx_data_sig <= "00" & brd_add;
837 tx_start_sig <= '1';
838 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
839 elsif txcnt = 3 then -- mirrored command
840 txcnt <= txcnt + 1;
841 tx_data_sig <= "00000111";
842 tx_start_sig <= '1';
843 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
844 elsif txcnt = 4 then -- data: prescaling
845 txcnt <= txcnt + 1;
846 tx_data_sig <= prescaling_rs485_in;
847 tx_start_sig <= '1';
848 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
849 elsif txcnt = 5 then -- data: overflow register
850 txcnt <= txcnt + 1;
851 tx_data_sig <= overflow_array_rs485_in;
852 tx_start_sig <= '1';
853 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
854 elsif txcnt < 15 then -- data: not used
855 txcnt <= txcnt + 1;
856 tx_data_sig <= "00000000";
857 tx_start_sig <= '1';
858 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
859 elsif txcnt = 15 then -- check sum
860 txcnt <= txcnt + 1;
861 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
862 tx_start_sig <= '1';
863 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
864 else -- transmission finished
865 txcnt <= 0;
866 FTU_rs485_control_State <= RECEIVE;
867 end if;
868 else
869 tx_start_sig <= '0';
870 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
871 end if;
872
873 end case;
874 end if;
875 end process FTU_rs485_control_FSM;
876
877end Behavioral;
878
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