source: firmware/FTU/rs485/FTU_rs485_control.vhd@ 9939

Last change on this file since 9939 was 9939, checked in by weitzel, 16 years ago
FTU RS485 interface is now connected to main control
File size: 39.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: top level entity of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_control is
36 port(
37 main_clk : IN std_logic;
38 brd_add : IN std_logic_vector(5 downto 0);
39 rx_d : IN std_logic;
40 rates_ready : IN std_logic; -- rate_array_rs485 has now valid rates for sending
41 DACs_ready : IN std_logic; -- dac_array_rs485_in is ok for sending
42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending
43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending
44 rate_array_rs485 : IN rate_array_type;
45 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
46 dac_array_rs485_in : IN dac_array_type;
47 enable_array_rs485_in : IN enable_array_type;
48 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
49 rx_en : OUT std_logic;
50 tx_d : OUT std_logic;
51 tx_en : OUT std_logic;
52 new_DACs : OUT std_logic := '0'; -- new DACs arrived via RS485
53 new_enables : OUT std_logic := '0'; -- new enables arrived via RS485
54 new_prescaling : OUT std_logic := '0'; -- new prescaling arrived via RS485
55 read_rates : OUT std_logic := '0'; -- FTM wants to read rates
56 read_DACs : OUT std_logic := '0'; -- FTM wants to read DACs
57 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern
58 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value
59 dac_array_rs485_out : OUT dac_array_type;
60 enable_array_rs485_out : OUT enable_array_type;
61 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
62 );
63end FTU_rs485_control;
64
65architecture Behavioral of FTU_rs485_control is
66
67 signal tx_start_sig : std_logic := '0';
68 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
69 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
70
71 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface
72 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface
73 signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
74
75 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver
76 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTU_rs485_receiver
77
78 signal int_new_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
79 signal int_new_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
80 signal int_new_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
81 signal int_read_rates_sig : std_logic; -- initialized in FTU_rs485_interpreter
82 signal int_read_DACs_sig : std_logic; -- initialized in FTU_rs485_interpreter
83 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter
84 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter
85
86 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames
87
88 component FTU_rs485_receiver
89 port(
90 rec_clk : in std_logic;
91 --rx_busy : in std_logic;
92 rec_din : in std_logic_vector(7 downto 0);
93 rec_den : in std_logic;
94 rec_dout : out std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
95 rec_valid : out std_logic
96 );
97 end component;
98
99 component FTU_rs485_interpreter
100 port(
101 clk : IN std_logic;
102 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
103 block_valid : IN std_logic;
104 brd_add : IN std_logic_vector(5 downto 0);
105 int_new_DACs : OUT std_logic;
106 int_new_enables : OUT std_logic;
107 int_new_prescaling : OUT std_logic;
108 int_read_rates : OUT std_logic;
109 int_read_DACs : OUT std_logic;
110 int_read_enables : OUT std_logic;
111 int_read_prescaling : OUT std_logic;
112 dac_array_rs485_out : OUT dac_array_type;
113 enable_array_rs485_out : OUT enable_array_type;
114 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
115 );
116 end component;
117
118 component FTU_rs485_interface
119 port(
120 clk : IN std_logic;
121 -- RS485
122 rx_d : IN std_logic;
123 rx_en : OUT std_logic;
124 tx_d : OUT std_logic;
125 tx_en : OUT std_logic;
126 -- FPGA
127 rx_data : OUT std_logic_vector (7 DOWNTO 0);
128 rx_busy : OUT std_logic := '0';
129 rx_valid : OUT std_logic := '0';
130 tx_data : IN std_logic_vector (7 DOWNTO 0);
131 tx_busy : OUT std_logic := '0';
132 tx_start : IN std_logic
133 );
134 end component;
135
136 type FTU_rs485_control_StateType is (RECEIVE,
137 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
138 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT,
139 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
140 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT);
141 signal FTU_rs485_control_State : FTU_rs485_control_StateType;
142
143begin
144
145 Inst_FTU_rs485_receiver : FTU_rs485_receiver
146 port map(
147 rec_clk => main_clk,
148 --rx_busy =>,
149 rec_din => rx_data_sig,
150 rec_den => rx_valid_sig,
151 rec_dout => data_block_sig,
152 rec_valid => block_valid_sig
153 );
154
155 Inst_FTU_rs485_interpreter : FTU_rs485_interpreter
156 port map(
157 clk => main_clk,
158 data_block => data_block_sig,
159 block_valid => block_valid_sig,
160 brd_add => brd_add,
161 int_new_DACs => int_new_DACs_sig,
162 int_new_enables => int_new_enables_sig,
163 int_new_prescaling => int_new_prescaling_sig,
164 int_read_rates => int_read_rates_sig,
165 int_read_DACs => int_read_DACs_sig,
166 int_read_enables => int_read_enables_sig,
167 int_read_prescaling => int_read_prescaling_sig,
168 dac_array_rs485_out => dac_array_rs485_out,
169 enable_array_rs485_out => enable_array_rs485_out,
170 prescaling_rs485_out => prescaling_rs485_out
171 );
172
173 Inst_FTU_rs485_interface : FTU_rs485_interface
174 port map(
175 clk => main_clk,
176 -- RS485
177 rx_d => rx_d,
178 rx_en => rx_en,
179 tx_d => tx_d,
180 tx_en => tx_en,
181 -- FPGA
182 rx_data => rx_data_sig,
183 rx_busy => rx_busy_sig,
184 rx_valid => rx_valid_sig,
185 tx_data => tx_data_sig,
186 tx_busy => tx_busy_sig,
187 tx_start => tx_start_sig
188 );
189
190 --FTU RS485 control finite state machine
191
192 FTU_rs485_control_FSM: process (main_clk)
193 begin
194 if Rising_edge(main_clk) then
195 case FTU_rs485_control_State is
196
197 when RECEIVE => -- default state, receiver on, no transmission
198 tx_start_sig <= '0';
199 if (int_new_DACs_sig = '1') then
200 new_DACs <= '1';
201 new_enables <= '0';
202 new_prescaling <= '0';
203 read_rates <= '0';
204 read_DACs <= '0';
205 read_enables <= '0';
206 read_prescaling <= '0';
207 FTU_rs485_control_State <= SET_DAC_WAIT;
208 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then
209 new_DACs <= '0';
210 new_enables <= '1';
211 new_prescaling <= '0';
212 read_rates <= '0';
213 read_DACs <= '0';
214 read_enables <= '0';
215 read_prescaling <= '0';
216 FTU_rs485_control_State <= SET_ENABLE_WAIT;
217 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then
218 new_DACs <= '0';
219 new_enables <= '0';
220 new_prescaling <= '1';
221 read_rates <= '0';
222 read_DACs <= '0';
223 read_enables <= '0';
224 read_prescaling <= '0';
225 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
226 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
227 int_read_rates_sig = '1') then
228 new_DACs <= '0';
229 new_enables <= '0';
230 new_prescaling <= '0';
231 read_rates <= '1';
232 read_DACs <= '0';
233 read_enables <= '0';
234 read_prescaling <= '0';
235 FTU_rs485_control_State <= READ_RATES_WAIT;
236 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
237 int_read_rates_sig = '0' and int_read_DACs_sig = '1') then
238 new_DACs <= '0';
239 new_enables <= '0';
240 new_prescaling <= '0';
241 read_rates <= '0';
242 read_DACs <= '1';
243 read_enables <= '0';
244 read_prescaling <= '0';
245 FTU_rs485_control_State <= READ_DAC_WAIT;
246 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
247 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '1') then
248 new_DACs <= '0';
249 new_enables <= '0';
250 new_prescaling <= '0';
251 read_rates <= '0';
252 read_DACs <= '0';
253 read_enables <= '1';
254 read_prescaling <= '0';
255 FTU_rs485_control_State <= READ_ENABLE_WAIT;
256 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and
257 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '1') then
258 new_DACs <= '0';
259 new_enables <= '0';
260 new_prescaling <= '0';
261 read_rates <= '0';
262 read_DACs <= '0';
263 read_enables <= '0';
264 read_prescaling <= '1';
265 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
266 else
267 new_DACs <= '0';
268 new_enables <= '0';
269 new_prescaling <= '0';
270 read_rates <= '0';
271 read_DACs <= '0';
272 read_enables <= '0';
273 read_prescaling <= '0';
274 FTU_rs485_control_State <= RECEIVE;
275 end if;
276
277 when SET_DAC_WAIT=> -- wait until FTU control says "done" and then answer to FTM
278 if (DACs_ready = '1') then
279 new_DACs <= '0';
280 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
281 else
282 new_DACs <= '1';
283 FTU_rs485_control_State <= SET_DAC_WAIT;
284 end if;
285
286 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
287 if (enables_ready = '1') then
288 new_enables <= '0';
289 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
290 else
291 new_enables <= '1';
292 FTU_rs485_control_State <= SET_ENABLE_WAIT;
293 end if;
294
295 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
296 if (prescaling_ready = '1') then
297 new_prescaling <= '0';
298 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
299 else
300 new_prescaling <= '1';
301 FTU_rs485_control_State <= SET_PRESCALING_WAIT;
302 end if;
303
304 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM
305 if (rates_ready = '1') then
306 read_rates <= '0';
307 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
308 else
309 read_rates <= '1';
310 FTU_rs485_control_State <= READ_RATES_WAIT;
311 end if;
312
313 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM
314 if (DACs_ready = '1') then
315 read_DACs <= '0';
316 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
317 else
318 read_DACs <= '1';
319 FTU_rs485_control_State <= READ_DAC_WAIT;
320 end if;
321
322 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM
323 if (enables_ready = '1') then
324 read_enables <= '0';
325 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
326 else
327 read_enables <= '1';
328 FTU_rs485_control_State <= READ_ENABLE_WAIT;
329 end if;
330
331 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM
332 if (prescaling_ready = '1') then
333 read_prescaling <= '0';
334 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
335 else
336 read_prescaling <= '1';
337 FTU_rs485_control_State <= READ_PRESCALING_WAIT;
338 end if;
339
340 when SET_DAC_TRANSMIT =>
341 if tx_busy_sig = '0' then
342 if txcnt = 0 then -- start delimiter
343 txcnt <= txcnt + 1;
344 tx_data_sig <= RS485_START_DELIM;
345 tx_start_sig <= '1';
346 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
347 elsif txcnt = 1 then -- FTM address
348 txcnt <= txcnt + 1;
349 tx_data_sig <= FTM_ADDRESS;
350 tx_start_sig <= '1';
351 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
352 elsif txcnt = 2 then -- board address
353 txcnt <= txcnt + 1;
354 tx_data_sig <= "00" & brd_add;
355 tx_start_sig <= '1';
356 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
357 elsif txcnt = 3 then -- mirrored command
358 txcnt <= txcnt + 1;
359 tx_data_sig <= "00000000";
360 tx_start_sig <= '1';
361 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
362 elsif txcnt = 4 then -- data: DAC A low
363 txcnt <= txcnt + 1;
364 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
365 tx_start_sig <= '1';
366 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
367 elsif txcnt = 5 then -- data: DAC A high
368 txcnt <= txcnt + 1;
369 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
370 tx_start_sig <= '1';
371 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
372 elsif txcnt = 6 then -- data: DAC B low
373 txcnt <= txcnt + 1;
374 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
375 tx_start_sig <= '1';
376 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
377 elsif txcnt = 7 then -- data: DAC B high
378 txcnt <= txcnt + 1;
379 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
380 tx_start_sig <= '1';
381 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
382 elsif txcnt = 8 then -- data: DAC C low
383 txcnt <= txcnt + 1;
384 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
385 tx_start_sig <= '1';
386 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
387 elsif txcnt = 9 then -- data: DAC C high
388 txcnt <= txcnt + 1;
389 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
390 tx_start_sig <= '1';
391 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
392 elsif txcnt = 10 then -- data: DAC D low
393 txcnt <= txcnt + 1;
394 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
395 tx_start_sig <= '1';
396 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
397 elsif txcnt = 11 then -- data: DAC D high
398 txcnt <= txcnt + 1;
399 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
400 tx_start_sig <= '1';
401 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
402 elsif txcnt = 12 then -- data: DAC E low
403 txcnt <= txcnt + 1;
404 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
405 tx_start_sig <= '1';
406 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
407 elsif txcnt = 13 then -- data: DAC E high
408 txcnt <= txcnt + 1;
409 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
410 tx_start_sig <= '1';
411 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
412 elsif txcnt < 15 then -- data: not used
413 txcnt <= txcnt + 1;
414 tx_data_sig <= "00000000";
415 tx_start_sig <= '1';
416 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
417 elsif txcnt = 15 then -- check sum
418 txcnt <= txcnt + 1;
419 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
420 tx_start_sig <= '1';
421 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
422 else -- transmission finished
423 txcnt <= 0;
424 FTU_rs485_control_State <= RECEIVE;
425 end if;
426 else
427 tx_start_sig <= '0';
428 FTU_rs485_control_State <= SET_DAC_TRANSMIT;
429 end if;
430
431 when SET_ENABLE_TRANSMIT =>
432 if tx_busy_sig = '0' then
433 if txcnt = 0 then -- start delimiter
434 txcnt <= txcnt + 1;
435 tx_data_sig <= RS485_START_DELIM;
436 tx_start_sig <= '1';
437 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
438 elsif txcnt = 1 then -- FTM address
439 txcnt <= txcnt + 1;
440 tx_data_sig <= FTM_ADDRESS;
441 tx_start_sig <= '1';
442 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
443 elsif txcnt = 2 then -- board address
444 txcnt <= txcnt + 1;
445 tx_data_sig <= "00" & brd_add;
446 tx_start_sig <= '1';
447 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
448 elsif txcnt = 3 then -- mirrored command
449 txcnt <= txcnt + 1;
450 tx_data_sig <= "00000011";
451 tx_start_sig <= '1';
452 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
453 elsif txcnt = 4 then -- data: enable pattern A7-0
454 txcnt <= txcnt + 1;
455 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
456 tx_start_sig <= '1';
457 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
458 elsif txcnt = 5 then -- data: enable pattern A8
459 txcnt <= txcnt + 1;
460 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
461 tx_start_sig <= '1';
462 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
463 elsif txcnt = 6 then -- data: enable pattern B7-0
464 txcnt <= txcnt + 1;
465 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
466 tx_start_sig <= '1';
467 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
468 elsif txcnt = 7 then -- data: enable pattern B8
469 txcnt <= txcnt + 1;
470 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
471 tx_start_sig <= '1';
472 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
473 elsif txcnt = 8 then -- data: enable pattern C7-0
474 txcnt <= txcnt + 1;
475 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
476 tx_start_sig <= '1';
477 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
478 elsif txcnt = 9 then -- data: enable pattern C8
479 txcnt <= txcnt + 1;
480 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
481 tx_start_sig <= '1';
482 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
483 elsif txcnt = 10 then -- data: enable pattern D7-0
484 txcnt <= txcnt + 1;
485 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
486 tx_start_sig <= '1';
487 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
488 elsif txcnt = 11 then -- data: enable pattern D8
489 txcnt <= txcnt + 1;
490 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
491 tx_start_sig <= '1';
492 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
493 elsif txcnt < 15 then -- data: not used
494 txcnt <= txcnt + 1;
495 tx_data_sig <= "00000000";
496 tx_start_sig <= '1';
497 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
498 elsif txcnt = 15 then -- check sum
499 txcnt <= txcnt + 1;
500 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
501 tx_start_sig <= '1';
502 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
503 else -- transmission finished
504 txcnt <= 0;
505 FTU_rs485_control_State <= RECEIVE;
506 end if;
507 else
508 tx_start_sig <= '0';
509 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
510 end if;
511
512 when SET_PRESCALING_TRANSMIT =>
513 if tx_busy_sig = '0' then
514 if txcnt = 0 then -- start delimiter
515 txcnt <= txcnt + 1;
516 tx_data_sig <= RS485_START_DELIM;
517 tx_start_sig <= '1';
518 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
519 elsif txcnt = 1 then -- FTM address
520 txcnt <= txcnt + 1;
521 tx_data_sig <= FTM_ADDRESS;
522 tx_start_sig <= '1';
523 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
524 elsif txcnt = 2 then -- board address
525 txcnt <= txcnt + 1;
526 tx_data_sig <= "00" & brd_add;
527 tx_start_sig <= '1';
528 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
529 elsif txcnt = 3 then -- mirrored command
530 txcnt <= txcnt + 1;
531 tx_data_sig <= "00000110";
532 tx_start_sig <= '1';
533 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
534 elsif txcnt = 4 then -- data: prescaling
535 txcnt <= txcnt + 1;
536 tx_data_sig <= prescaling_rs485_in;
537 tx_start_sig <= '1';
538 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
539 elsif txcnt < 15 then -- data: not used
540 txcnt <= txcnt + 1;
541 tx_data_sig <= "00000000";
542 tx_start_sig <= '1';
543 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
544 elsif txcnt = 15 then -- check sum
545 txcnt <= txcnt + 1;
546 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
547 tx_start_sig <= '1';
548 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
549 else -- transmission finished
550 txcnt <= 0;
551 FTU_rs485_control_State <= RECEIVE;
552 end if;
553 else
554 tx_start_sig <= '0';
555 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
556 end if;
557
558 when READ_RATES_TRANSMIT =>
559 if tx_busy_sig = '0' then
560 if txcnt = 0 then -- start delimiter
561 txcnt <= txcnt + 1;
562 tx_data_sig <= RS485_START_DELIM;
563 tx_start_sig <= '1';
564 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
565 elsif txcnt = 1 then -- FTM address
566 txcnt <= txcnt + 1;
567 tx_data_sig <= FTM_ADDRESS;
568 tx_start_sig <= '1';
569 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
570 elsif txcnt = 2 then -- board address
571 txcnt <= txcnt + 1;
572 tx_data_sig <= "00" & brd_add;
573 tx_start_sig <= '1';
574 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
575 elsif txcnt = 3 then -- mirrored command
576 txcnt <= txcnt + 1;
577 tx_data_sig <= "00000010";
578 tx_start_sig <= '1';
579 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
580 elsif txcnt = 4 then -- data: counter A low
581 txcnt <= txcnt + 1;
582 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(7 downto 0);
583 tx_start_sig <= '1';
584 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
585 elsif txcnt = 5 then -- data: counter A high
586 txcnt <= txcnt + 1;
587 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(15 downto 8);
588 tx_start_sig <= '1';
589 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
590 elsif txcnt = 6 then -- data: counter B low
591 txcnt <= txcnt + 1;
592 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(7 downto 0);
593 tx_start_sig <= '1';
594 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
595 elsif txcnt = 7 then -- data: counter B high
596 txcnt <= txcnt + 1;
597 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(15 downto 8);
598 tx_start_sig <= '1';
599 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
600 elsif txcnt = 8 then -- data: counter C low
601 txcnt <= txcnt + 1;
602 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(7 downto 0);
603 tx_start_sig <= '1';
604 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
605 elsif txcnt = 9 then -- data: counter C high
606 txcnt <= txcnt + 1;
607 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(15 downto 8);
608 tx_start_sig <= '1';
609 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
610 elsif txcnt = 10 then -- data: counter D low
611 txcnt <= txcnt + 1;
612 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(7 downto 0);
613 tx_start_sig <= '1';
614 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
615 elsif txcnt = 11 then -- data: counter D high
616 txcnt <= txcnt + 1;
617 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(15 downto 8);
618 tx_start_sig <= '1';
619 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
620 elsif txcnt = 12 then -- data: trigger counter low
621 txcnt <= txcnt + 1;
622 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(7 downto 0);
623 tx_start_sig <= '1';
624 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
625 elsif txcnt = 13 then -- data: trigger counter high
626 txcnt <= txcnt + 1;
627 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(15 downto 8);
628 tx_start_sig <= '1';
629 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
630 elsif txcnt = 14 then -- data: overflow register
631 txcnt <= txcnt + 1;
632 tx_data_sig <= overflow_array_rs485_in;
633 tx_start_sig <= '1';
634 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
635 elsif txcnt = 15 then -- check sum
636 txcnt <= txcnt + 1;
637 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
638 tx_start_sig <= '1';
639 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
640 else -- transmission finished
641 txcnt <= 0;
642 FTU_rs485_control_State <= RECEIVE;
643 end if;
644 else
645 tx_start_sig <= '0';
646 FTU_rs485_control_State <= READ_RATES_TRANSMIT;
647 end if;
648
649 when READ_DAC_TRANSMIT =>
650 if tx_busy_sig = '0' then
651 if txcnt = 0 then -- start delimiter
652 txcnt <= txcnt + 1;
653 tx_data_sig <= RS485_START_DELIM;
654 tx_start_sig <= '1';
655 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
656 elsif txcnt = 1 then -- FTM address
657 txcnt <= txcnt + 1;
658 tx_data_sig <= FTM_ADDRESS;
659 tx_start_sig <= '1';
660 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
661 elsif txcnt = 2 then -- board address
662 txcnt <= txcnt + 1;
663 tx_data_sig <= "00" & brd_add;
664 tx_start_sig <= '1';
665 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
666 elsif txcnt = 3 then -- mirrored command
667 txcnt <= txcnt + 1;
668 tx_data_sig <= "00000001";
669 tx_start_sig <= '1';
670 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
671 elsif txcnt = 4 then -- data: DAC A low
672 txcnt <= txcnt + 1;
673 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0);
674 tx_start_sig <= '1';
675 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
676 elsif txcnt = 5 then -- data: DAC A high
677 txcnt <= txcnt + 1;
678 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8);
679 tx_start_sig <= '1';
680 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
681 elsif txcnt = 6 then -- data: DAC B low
682 txcnt <= txcnt + 1;
683 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0);
684 tx_start_sig <= '1';
685 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
686 elsif txcnt = 7 then -- data: DAC B high
687 txcnt <= txcnt + 1;
688 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8);
689 tx_start_sig <= '1';
690 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
691 elsif txcnt = 8 then -- data: DAC C low
692 txcnt <= txcnt + 1;
693 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0);
694 tx_start_sig <= '1';
695 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
696 elsif txcnt = 9 then -- data: DAC C high
697 txcnt <= txcnt + 1;
698 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8);
699 tx_start_sig <= '1';
700 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
701 elsif txcnt = 10 then -- data: DAC D low
702 txcnt <= txcnt + 1;
703 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0);
704 tx_start_sig <= '1';
705 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
706 elsif txcnt = 11 then -- data: DAC D high
707 txcnt <= txcnt + 1;
708 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8);
709 tx_start_sig <= '1';
710 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
711 elsif txcnt = 12 then -- data: DAC E low
712 txcnt <= txcnt + 1;
713 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0);
714 tx_start_sig <= '1';
715 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
716 elsif txcnt = 13 then -- data: DAC E high
717 txcnt <= txcnt + 1;
718 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8);
719 tx_start_sig <= '1';
720 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
721 elsif txcnt < 15 then -- data: not used
722 txcnt <= txcnt + 1;
723 tx_data_sig <= "00000000";
724 tx_start_sig <= '1';
725 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
726 elsif txcnt = 15 then -- check sum
727 txcnt <= txcnt + 1;
728 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
729 tx_start_sig <= '1';
730 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
731 else -- transmission finished
732 txcnt <= 0;
733 FTU_rs485_control_State <= RECEIVE;
734 end if;
735 else
736 tx_start_sig <= '0';
737 FTU_rs485_control_State <= READ_DAC_TRANSMIT;
738 end if;
739
740 when READ_ENABLE_TRANSMIT =>
741 if tx_busy_sig = '0' then
742 if txcnt = 0 then -- start delimiter
743 txcnt <= txcnt + 1;
744 tx_data_sig <= RS485_START_DELIM;
745 tx_start_sig <= '1';
746 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
747 elsif txcnt = 1 then -- FTM address
748 txcnt <= txcnt + 1;
749 tx_data_sig <= FTM_ADDRESS;
750 tx_start_sig <= '1';
751 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
752 elsif txcnt = 2 then -- board address
753 txcnt <= txcnt + 1;
754 tx_data_sig <= "00" & brd_add;
755 tx_start_sig <= '1';
756 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
757 elsif txcnt = 3 then -- mirrored command
758 txcnt <= txcnt + 1;
759 tx_data_sig <= "00000100";
760 tx_start_sig <= '1';
761 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
762 elsif txcnt = 4 then -- data: enable pattern A7-0
763 txcnt <= txcnt + 1;
764 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0);
765 tx_start_sig <= '1';
766 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
767 elsif txcnt = 5 then -- data: enable pattern A8
768 txcnt <= txcnt + 1;
769 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8);
770 tx_start_sig <= '1';
771 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
772 elsif txcnt = 6 then -- data: enable pattern B7-0
773 txcnt <= txcnt + 1;
774 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0);
775 tx_start_sig <= '1';
776 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
777 elsif txcnt = 7 then -- data: enable pattern B8
778 txcnt <= txcnt + 1;
779 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8);
780 tx_start_sig <= '1';
781 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
782 elsif txcnt = 8 then -- data: enable pattern C7-0
783 txcnt <= txcnt + 1;
784 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0);
785 tx_start_sig <= '1';
786 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
787 elsif txcnt = 9 then -- data: enable pattern C8
788 txcnt <= txcnt + 1;
789 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8);
790 tx_start_sig <= '1';
791 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
792 elsif txcnt = 10 then -- data: enable pattern D7-0
793 txcnt <= txcnt + 1;
794 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0);
795 tx_start_sig <= '1';
796 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
797 elsif txcnt = 11 then -- data: enable pattern D8
798 txcnt <= txcnt + 1;
799 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8);
800 tx_start_sig <= '1';
801 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
802 elsif txcnt < 15 then -- data: not used
803 txcnt <= txcnt + 1;
804 tx_data_sig <= "00000000";
805 tx_start_sig <= '1';
806 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
807 elsif txcnt = 15 then -- check sum
808 txcnt <= txcnt + 1;
809 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
810 tx_start_sig <= '1';
811 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
812 else -- transmission finished
813 txcnt <= 0;
814 FTU_rs485_control_State <= RECEIVE;
815 end if;
816 else
817 tx_start_sig <= '0';
818 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
819 end if;
820
821 when READ_PRESCALING_TRANSMIT =>
822 if tx_busy_sig = '0' then
823 if txcnt = 0 then -- start delimiter
824 txcnt <= txcnt + 1;
825 tx_data_sig <= RS485_START_DELIM;
826 tx_start_sig <= '1';
827 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
828 elsif txcnt = 1 then -- FTM address
829 txcnt <= txcnt + 1;
830 tx_data_sig <= FTM_ADDRESS;
831 tx_start_sig <= '1';
832 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
833 elsif txcnt = 2 then -- board address
834 txcnt <= txcnt + 1;
835 tx_data_sig <= "00" & brd_add;
836 tx_start_sig <= '1';
837 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
838 elsif txcnt = 3 then -- mirrored command
839 txcnt <= txcnt + 1;
840 tx_data_sig <= "00000111";
841 tx_start_sig <= '1';
842 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
843 elsif txcnt = 4 then -- data: prescaling
844 txcnt <= txcnt + 1;
845 tx_data_sig <= prescaling_rs485_in;
846 tx_start_sig <= '1';
847 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
848 elsif txcnt = 5 then -- data: overflow register
849 txcnt <= txcnt + 1;
850 tx_data_sig <= overflow_array_rs485_in;
851 tx_start_sig <= '1';
852 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
853 elsif txcnt < 15 then -- data: not used
854 txcnt <= txcnt + 1;
855 tx_data_sig <= "00000000";
856 tx_start_sig <= '1';
857 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
858 elsif txcnt = 15 then -- check sum
859 txcnt <= txcnt + 1;
860 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!
861 tx_start_sig <= '1';
862 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
863 else -- transmission finished
864 txcnt <= 0;
865 FTU_rs485_control_State <= RECEIVE;
866 end if;
867 else
868 tx_start_sig <= '0';
869 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
870 end if;
871
872 end case;
873 end if;
874 end process FTU_rs485_control_FSM;
875
876end Behavioral;
877
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