1 | --
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2 | -- VHDL Architecture FACT_FAD_lib.rs485_interface.beha
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3 | --
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4 | -- Created:
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5 | -- by - Benjamin Krumm.UNKNOWN (EEPC8)
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6 | -- at - 13:24:23 08.06.2010
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7 | --
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8 | -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
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9 | --
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10 | --
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11 | -- modified for FTU design by Q. Weitzel, 30 July 2010
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12 | --
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13 |
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14 | LIBRARY ieee;
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15 | USE ieee.std_logic_1164.all;
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16 | USE ieee.std_logic_arith.all;
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17 |
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18 | library ftu_definitions;
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19 | USE ftu_definitions.ftu_array_types.all;
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20 | USE ftu_definitions.ftu_constants.all;
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21 |
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22 | ENTITY FTU_rs485_interface IS
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23 | GENERIC(
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24 | CLOCK_FREQUENCY : integer := INT_CLK_FREQUENCY;
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25 | BAUD_RATE : integer := RS485_BAUD_RATE
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26 | );
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27 | PORT(
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28 | clk : IN std_logic;
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29 | -- RS485
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30 | rx_d : IN std_logic;
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31 | rx_en : OUT std_logic;
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32 | tx_d : OUT std_logic;
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33 | tx_en : OUT std_logic;
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34 | -- FPGA
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35 | rx_data : OUT std_logic_vector (7 DOWNTO 0);
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36 | --rx_busy : OUT std_logic := '0';
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37 | rx_valid : OUT std_logic := '0';
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38 | tx_data : IN std_logic_vector (7 DOWNTO 0);
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39 | tx_busy : OUT std_logic := '0';
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40 | tx_start : IN std_logic
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41 | );
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42 |
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43 | END FTU_rs485_interface;
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44 |
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45 | ARCHITECTURE beha OF FTU_rs485_interface IS
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46 |
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47 | signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable
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48 |
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49 | --transmit
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50 | signal tx_start_f : std_logic := '0';
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51 | signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bits
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52 | signal tx_bitcnt : integer range 0 to 11 := 11;
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53 | signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1);
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54 |
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55 | --receive
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56 | signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1');
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57 | signal rx_sr : std_logic_vector(7 downto 0) := (others => '0');
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58 | signal rx_bitcnt : integer range 0 to 11 := 11;
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59 | signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1);
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60 |
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61 | BEGIN
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62 |
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63 | -- Senden
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64 | tx_data_proc: process(clk)
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65 | begin
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66 | if rising_edge(clk) then
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67 | tx_start_f <= tx_start;
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68 | if (tx_start = '1' or tx_bitcnt < 11) then
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69 | flow_ctrl <= '1';
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70 | else
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71 | flow_ctrl <= '0';
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72 | end if;
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73 | if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts
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74 | tx_cnt <= 0; -- Zaehler initialisieren
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75 | tx_bitcnt <= 0;
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76 | tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los
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77 | else
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78 | if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then
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79 | tx_cnt <= tx_cnt + 1;
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80 | else -- naechstes Bit ausgeben
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81 | if (tx_bitcnt < 11) then
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82 | tx_cnt <= 0;
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83 | tx_bitcnt <= tx_bitcnt + 1;
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84 | tx_sr <= '1' & tx_sr(tx_sr'left downto 1);
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85 | end if;
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86 | end if;
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87 | end if;
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88 | end if;
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89 | end process;
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90 |
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91 | tx_en <= flow_ctrl;
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92 | tx_d <= tx_sr(0); -- LSB first
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93 | tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0';
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94 |
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95 | -- Empfangen
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96 | rx_data_proc: process(clk)
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97 | begin
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98 | if rising_edge(clk) then
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99 | rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d;
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100 | if (rx_bitcnt < 11) then -- Empfang laeuft
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101 | if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then
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102 | rx_cnt <= rx_cnt + 1;
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103 | else
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104 | rx_cnt <= 0;
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105 | rx_bitcnt <= rx_bitcnt + 1;
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106 | if (rx_bitcnt < 9) then
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107 | rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first
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108 | else
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109 | rx_valid <= '1';
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110 | end if;
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111 | end if;
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112 | else
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113 | if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit
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114 | rx_valid <= '0';
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115 | rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2;
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116 | rx_bitcnt <= 0;
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117 | end if;
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118 | end if;
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119 | end if;
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120 | end process;
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121 |
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122 | rx_en <= flow_ctrl;
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123 | rx_data <= rx_sr;
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124 | --rx_busy <= '1' when (rx_bitcnt < 11) else '0';
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125 |
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126 | END ARCHITECTURE beha;
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