source: firmware/FTU/rs485/FTU_rs485_interpreter.vhd@ 10047

Last change on this file since 10047 was 10047, checked in by weitzel, 14 years ago
timeout implemented for FTU RS485 communication; new version of FTU docu
File size: 9.1 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 09/13/2010
6-- Design Name:
7-- Module Name: FTU_rs485_interpreter - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: command interpreter of FTU RS485 module
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_rs485_interpreter is
36 port(
37 clk : IN std_logic;
38 data_block : IN std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);
39 block_valid : IN std_logic;
40 brd_add : IN std_logic_vector(5 downto 0);
41 int_new_DACs : OUT std_logic := '0';
42 int_new_enables : OUT std_logic := '0';
43 int_new_prescaling : OUT std_logic := '0';
44 int_read_rates : OUT std_logic := '0';
45 int_read_DACs : OUT std_logic := '0';
46 int_read_enables : OUT std_logic := '0';
47 int_read_prescaling : OUT std_logic := '0';
48 int_ping_pong : OUT std_logic := '0';
49 dac_array_rs485_out : OUT dac_array_type;
50 enable_array_rs485_out : OUT enable_array_type;
51 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
52 );
53end FTU_rs485_interpreter;
54
55architecture Behavioral of FTU_rs485_interpreter is
56
57 signal block_valid_sr : std_logic_vector(3 downto 0) := (others => '0');
58
59 signal dac_array_rs485_out_sig : dac_array_type := DEFAULT_DAC;
60 signal enable_array_rs485_out_sig : enable_array_type := DEFAULT_ENABLE;
61 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(DEFAULT_PRESCALING,8);
62
63 type FTU_rs485_interpreter_StateType is (WAIT_FOR_DATA, CHECK_HEADER, DECODE);
64 signal FTU_rs485_interpreter_State : FTU_rs485_interpreter_StateType;
65
66begin
67
68 FTU_rs485_interpreter_FSM: process (clk)
69 begin
70 if Rising_edge(clk) then
71 case FTU_rs485_interpreter_State is
72
73 when WAIT_FOR_DATA => -- default state, waiting for valid 16-byte block
74 block_valid_sr <= block_valid_sr(2 downto 0) & block_valid;
75 int_new_DACs <= '0';
76 int_new_enables <= '0';
77 int_new_prescaling <= '0';
78 int_read_rates <= '0';
79 int_read_DACs <= '0';
80 int_read_enables <= '0';
81 int_read_prescaling <= '0';
82 int_ping_pong <= '0';
83 if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal
84 FTU_rs485_interpreter_State <= CHECK_HEADER;
85 else
86 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
87 end if;
88
89 when CHECK_HEADER => -- check start delimiter and addresses
90 int_new_DACs <= '0';
91 int_new_enables <= '0';
92 int_new_prescaling <= '0';
93 int_read_rates <= '0';
94 int_read_DACs <= '0';
95 int_read_enables <= '0';
96 int_read_prescaling <= '0';
97 int_ping_pong <= '0';
98 if (data_block(7 downto 0) = RS485_START_DELIM) and
99 (data_block(15 downto 8) = ("00" & brd_add)) and
100 (data_block(23 downto 16) = FTM_ADDRESS) then
101 FTU_rs485_interpreter_State <= DECODE;
102 else
103 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
104 end if;
105
106 when DECODE => -- decode instruction
107 if(data_block(39 downto 32) = "00000000") then -- set DACs
108 int_new_DACs <= '1';
109 int_new_enables <= '0';
110 int_new_prescaling <= '0';
111 int_read_rates <= '0';
112 int_read_DACs <= '0';
113 int_read_enables <= '0';
114 int_read_prescaling <= '0';
115 int_ping_pong <= '0';
116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(51 downto 40))),
117 conv_integer(unsigned(data_block(67 downto 56))),
118 conv_integer(unsigned(data_block(83 downto 72))),
119 conv_integer(unsigned(data_block(99 downto 88))),
120 DEFAULT_DAC(4),
121 DEFAULT_DAC(5),
122 DEFAULT_DAC(6),
123 conv_integer(unsigned(data_block(115 downto 104)))
124 );
125 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
126 elsif (data_block(39 downto 32) = "00000001") then -- read DACs
127 int_new_DACs <= '0';
128 int_new_enables <= '0';
129 int_new_prescaling <= '0';
130 int_read_rates <= '0';
131 int_read_DACs <= '1';
132 int_read_enables <= '0';
133 int_read_prescaling <= '0';
134 int_ping_pong <= '0';
135 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
136 elsif (data_block(39 downto 32) = "00000010") then -- read rates
137 int_new_DACs <= '0';
138 int_new_enables <= '0';
139 int_new_prescaling <= '0';
140 int_read_rates <= '1';
141 int_read_DACs <= '0';
142 int_read_enables <= '0';
143 int_read_prescaling <= '0';
144 int_ping_pong <= '0';
145 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
146 elsif (data_block(39 downto 32) = "00000011") then -- set enables
147 int_new_DACs <= '0';
148 int_new_enables <= '1';
149 int_new_prescaling <= '0';
150 int_read_rates <= '0';
151 int_read_DACs <= '0';
152 int_read_enables <= '0';
153 int_read_prescaling <= '0';
154 int_ping_pong <= '0';
155 enable_array_rs485_out_sig <= (data_block(55 downto 40),
156 data_block(71 downto 56),
157 data_block(87 downto 72),
158 data_block(103 downto 88)
159 );
160 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
161 elsif (data_block(39 downto 32) = "00000100") then -- read enables
162 int_new_DACs <= '0';
163 int_new_enables <= '0';
164 int_new_prescaling <= '0';
165 int_read_rates <= '0';
166 int_read_DACs <= '0';
167 int_read_enables <= '1';
168 int_read_prescaling <= '0';
169 int_ping_pong <= '0';
170 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
171 elsif (data_block(39 downto 32) = "00000110") then -- set counter mode
172 int_new_DACs <= '0';
173 int_new_enables <= '0';
174 int_new_prescaling <= '1';
175 int_read_rates <= '0';
176 int_read_DACs <= '0';
177 int_read_enables <= '0';
178 int_read_prescaling <= '0';
179 int_ping_pong <= '0';
180 prescaling_rs485_out_sig <= data_block(47 downto 40);
181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
182 elsif (data_block(39 downto 32) = "00000111") then -- read counter mode
183 int_new_DACs <= '0';
184 int_new_enables <= '0';
185 int_new_prescaling <= '0';
186 int_read_rates <= '0';
187 int_read_DACs <= '0';
188 int_read_enables <= '0';
189 int_read_prescaling <= '1';
190 int_ping_pong <= '0';
191 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
192 elsif (data_block(39 downto 32) = "00000101") then -- ping pong
193 int_new_DACs <= '0';
194 int_new_enables <= '0';
195 int_new_prescaling <= '0';
196 int_read_rates <= '0';
197 int_read_DACs <= '0';
198 int_read_enables <= '0';
199 int_read_prescaling <= '0';
200 int_ping_pong <= '1';
201 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
202 else
203 int_new_DACs <= '0';
204 int_new_enables <= '0';
205 int_new_prescaling <= '0';
206 int_read_rates <= '0';
207 int_read_DACs <= '0';
208 int_read_enables <= '0';
209 int_read_prescaling <= '0';
210 int_ping_pong <= '0';
211 FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
212 end if;
213
214 end case;
215 end if;
216 end process FTU_rs485_interpreter_FSM;
217
218 dac_array_rs485_out <= dac_array_rs485_out_sig;
219 enable_array_rs485_out <= enable_array_rs485_out_sig;
220 prescaling_rs485_out <= prescaling_rs485_out_sig;
221
222end Behavioral;
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