source: firmware/FTU/rs485/FTU_rs485_receiver.vhd@ 18066

Last change on this file since 18066 was 10238, checked in by weitzel, 14 years ago
change in FTU rs485 module; FTUs answer now one BAUD period later
File size: 2.1 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.rs485_receiver.beha
3--
4-- Created:
5-- by - Benjamin Krumm.UNKNOWN (EEPC8)
6-- at - 12:16:57 11.06.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9--
10--
11-- modified for FTU design by Q. Weitzel, 13 September 2010
12-- timeout added, Q. Weitzel, 26 October 2010
13--
14
15LIBRARY ieee;
16USE ieee.std_logic_1164.all;
17USE ieee.std_logic_arith.all;
18
19library ftu_definitions;
20USE ftu_definitions.ftu_constants.all;
21
22ENTITY FTU_rs485_receiver IS
23 generic(
24 RX_BYTES : integer := RS485_BLOCK_WIDTH / 8; -- no. of bytes to receive
25 RX_WIDTH : integer := RS485_BLOCK_WIDTH
26 );
27 port(
28 rec_clk : in std_logic;
29 -- rx_busy : in std_logic;
30 rec_din : in std_logic_vector(7 downto 0);
31 rec_den : in std_logic;
32 rec_dout : out std_logic_vector(RX_WIDTH - 1 downto 0) := (others => '0');
33 rec_valid : out std_logic := '0'
34 );
35END ENTITY FTU_rs485_receiver;
36
37ARCHITECTURE beha OF FTU_rs485_receiver IS
38
39 signal rxcnt : integer range 0 to RX_BYTES := 0;
40 signal rxsr : std_logic_vector(3 downto 0) := (others => '0');
41 signal timeout_cnt : integer range 0 to RS485_TIMEOUT + 1 := 0;
42
43BEGIN
44
45 rx_data_proc : process(rec_clk)
46 begin
47 if rising_edge(rec_clk) then
48 rxsr <= rxsr(2 downto 0) & rec_den;
49 if (timeout_cnt = RS485_TIMEOUT) then
50 rec_dout <= (others => '0');
51 rxcnt <= 0;
52 rec_valid <= '0';
53 else
54 if (rxsr(3 downto 2) = "01") then -- identify rising edge
55 rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din;
56 rxcnt <= rxcnt + 1;
57 if (rxcnt < RX_BYTES - 1) then
58 rec_valid <= '0';
59 else
60 rxcnt <= 0;
61 rec_valid <= '1';
62 end if;
63 end if;
64 end if;
65 end if;
66 end process rx_data_proc;
67
68 rx_timeout_proc : process(rec_clk)
69 begin
70 if rising_edge(rec_clk) then
71 if (rxcnt > 0) then
72 timeout_cnt <= timeout_cnt + 1;
73 else
74 timeout_cnt <= 0;
75 end if;
76 end if;
77 end process rx_timeout_proc;
78
79END ARCHITECTURE beha;
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