1 | --
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2 | -- VHDL Architecture FACT_FAD_lib.rs485_receiver.beha
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3 | --
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4 | -- Created:
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5 | -- by - Benjamin Krumm.UNKNOWN (EEPC8)
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6 | -- at - 12:16:57 11.06.2010
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7 | --
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8 | -- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
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9 | --
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10 | --
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11 | -- modified for FTU design by Q. Weitzel, 13 September 2010
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12 | -- timeout added, Q. Weitzel, 26 October 2010
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13 | --
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14 |
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15 | LIBRARY ieee;
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16 | USE ieee.std_logic_1164.all;
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17 | USE ieee.std_logic_arith.all;
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18 |
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19 | library ftu_definitions;
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20 | USE ftu_definitions.ftu_constants.all;
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21 |
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22 | ENTITY FTU_rs485_receiver IS
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23 | generic(
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24 | RX_BYTES : integer := RS485_BLOCK_WIDTH / 8; -- no. of bytes to receive
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25 | RX_WIDTH : integer := RS485_BLOCK_WIDTH
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26 | );
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27 | port(
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28 | rec_clk : in std_logic;
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29 | -- rx_busy : in std_logic;
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30 | rec_din : in std_logic_vector(7 downto 0);
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31 | rec_den : in std_logic;
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32 | rec_dout : out std_logic_vector(RX_WIDTH - 1 downto 0) := (others => '0');
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33 | rec_valid : out std_logic := '0'
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34 | );
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35 | END ENTITY FTU_rs485_receiver;
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36 |
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37 | ARCHITECTURE beha OF FTU_rs485_receiver IS
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38 |
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39 | signal rxcnt : integer range 0 to RX_BYTES := 0;
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40 | signal rxsr : std_logic_vector(3 downto 0) := (others => '0');
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41 | signal timeout_cnt : integer range 0 to RS485_TIMEOUT + 1 := 0;
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42 |
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43 | BEGIN
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44 |
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45 | rx_data_proc : process(rec_clk)
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46 | begin
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47 | if rising_edge(rec_clk) then
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48 | rxsr <= rxsr(2 downto 0) & rec_den;
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49 | if (timeout_cnt = RS485_TIMEOUT) then
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50 | rec_dout <= (others => '0');
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51 | rxcnt <= 0;
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52 | rec_valid <= '0';
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53 | else
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54 | if (rxsr(3 downto 2) = "01") then -- identify rising edge
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55 | rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din;
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56 | rxcnt <= rxcnt + 1;
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57 | if (rxcnt < RX_BYTES - 1) then
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58 | rec_valid <= '0';
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59 | else
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60 | rxcnt <= 0;
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61 | rec_valid <= '1';
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62 | end if;
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63 | end if;
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64 | end if;
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65 | end if;
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66 | end process rx_data_proc;
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67 |
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68 | rx_timeout_proc : process(rec_clk)
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69 | begin
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70 | if rising_edge(rec_clk) then
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71 | if (rxcnt > 0) then
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72 | timeout_cnt <= timeout_cnt + 1;
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73 | else
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74 | timeout_cnt <= 0;
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75 | end if;
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76 | end if;
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77 | end process rx_timeout_proc;
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78 |
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79 | END ARCHITECTURE beha;
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