source: firmware/FTU/rs485/FTU_rs485_receiver.vhd @ 9928

Last change on this file since 9928 was 9928, checked in by weitzel, 10 years ago
first version of RS485 interface added to FTU firmware; not yet connected to main control state machine
File size: 1.6 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.rs485_receiver.beha
3--
4-- Created:
5--          by - Benjamin Krumm.UNKNOWN (EEPC8)
6--          at - 12:16:57 11.06.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
9--
10--
11-- modified for FTU design by Q. Weitzel, 13 September 2010
12--
13
14LIBRARY ieee;
15USE ieee.std_logic_1164.all;
16USE ieee.std_logic_arith.all;
17
18library ftu_definitions;
19USE ftu_definitions.ftu_constants.all;
20
21ENTITY FTU_rs485_receiver IS
22  generic(
23    RX_BYTES  : integer := RS485_BLOCK_WIDTH / 8; -- no. of bytes to receive
24    RX_WIDTH  : integer := RS485_BLOCK_WIDTH
25  );
26  port(
27    rec_clk   : in  std_logic;
28    --rx_busy   : in  std_logic;
29    rec_din   : in  std_logic_vector(7 downto 0);
30    rec_den   : in  std_logic;
31    rec_dout  : out std_logic_vector(RX_WIDTH - 1 downto 0) := (others => '0');
32    rec_valid : out std_logic := '0'
33  );
34END ENTITY FTU_rs485_receiver;
35
36ARCHITECTURE beha OF FTU_rs485_receiver IS
37 
38  signal rxcnt : integer range 0 to RX_BYTES := 0;
39  signal rxsr : std_logic_vector(3 downto 0) := (others => '0');
40 
41BEGIN
42 
43  rx_data_proc: process (rec_clk)
44  begin
45    if rising_edge(rec_clk) then
46      rxsr <= rxsr(2 downto 0) & rec_den;
47      if (rxsr(3 downto 2) = "01") then -- identify rising edge
48        rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din;
49        rxcnt <= rxcnt + 1;
50        if (rxcnt < RX_BYTES - 1) then
51          rec_valid <= '0';
52        else
53          rxcnt <= 0;
54          rec_valid <= '1';
55        end if;
56      end if;
57    end if; 
58  end process rx_data_proc;
59   
60END ARCHITECTURE beha;
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