source: firmware/FTU/test_firmware/FTU_test1/FTU_test1_tb.vhd@ 18558

Last change on this file since 18558 was 235, checked in by qweitzel, 14 years ago
small fix in TB of FTU_tes1
File size: 6.2 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 05/04/2010
6-- Design Name:
7-- Module Name: /home/qweitzel/FPGA/FACT/FTU/test_firmware/FTU_test1_tb.vhd
8-- Project Name: FTU_test1_sim01
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for test1 entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_test1
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33entity FTU_test1_tb is
34end FTU_test1_tb;
35
36architecture behavior of FTU_test1_tb is
37
38 -- Component Declaration for the Unit Under Test (UUT)
39
40 component FTU_test1
41 port(
42 -- global control
43 ext_clk : IN STD_LOGIC; -- external clock from FTU board
44 --reset : in STD_LOGIC; -- reset
45 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
46 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable address
47
48 -- rate counters LVDS inputs
49 -- use IBUFDS differential input buffer
50 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
51 patch_A_n : IN STD_LOGIC;
52 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
53 patch_B_n : IN STD_LOGIC;
54 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
55 patch_C_n : IN STD_LOGIC;
56 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
57 patch_D_n : IN STD_LOGIC;
58 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
59 trig_prim_n : IN STD_LOGIC;
60
61 -- DAC interface
62 -- miso : IN STD_LOGIC; -- master-in-slave-out
63 sck : OUT STD_LOGIC; -- serial clock to DAC
64 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
65 clr : OUT STD_LOGIC; -- clear signal to DAC
66 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
67
68 -- RS-485 interface to FTM
69 rx : IN STD_LOGIC; -- serial data from FTM
70 tx : OUT STD_LOGIC; -- serial data to FTM
71 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
72 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
73
74 -- analog buffer enable
75 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
76 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
78 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
79
80 -- testpoints
81 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
82 );
83 end component;
84
85 --Inputs
86 signal ext_clk : STD_LOGIC := '0';
87 --signal reset : STD_LOGIC := '0';
88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
89 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
90 signal patch_A_p : STD_LOGIC := '0';
91 signal patch_A_n : STD_LOGIC := '0';
92 signal patch_B_p : STD_LOGIC := '0';
93 signal patch_B_n : STD_LOGIC := '0';
94 signal patch_C_p : STD_LOGIC := '0';
95 signal patch_C_n : STD_LOGIC := '0';
96 signal patch_D_p : STD_LOGIC := '0';
97 signal patch_D_n : STD_LOGIC := '0';
98 signal trig_prim_p : STD_LOGIC := '0';
99 signal trig_prim_n : STD_LOGIC := '0';
100 -- signal miso : STD_LOGIC := '0';
101 signal rx : STD_LOGIC := '0';
102
103 --Outputs
104 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
105 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
106 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
107 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
108 signal clr : STD_LOGIC;
109 signal cs_ld : STD_LOGIC;
110 signal sck : STD_LOGIC;
111 signal mosi : STD_LOGIC;
112 signal tx : STD_LOGIC;
113 signal rx_en : STD_LOGIC;
114 signal tx_en : STD_LOGIC;
115 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
116
117 -- Clock period definitions
118 constant ext_clk_period : TIME := 20 ns;
119
120begin
121
122 -- Instantiate the Unit Under Test (UUT)
123 uut: FTU_test1
124 port map(
125 ext_clk => ext_clk,
126 --reset => reset,
127 brd_add => brd_add,
128 brd_id => brd_id,
129 patch_A_p => patch_A_p,
130 patch_A_n => patch_A_n,
131 patch_B_p => patch_B_p,
132 patch_B_n => patch_B_n,
133 patch_C_p => patch_C_p,
134 patch_C_n => patch_C_n,
135 patch_D_p => patch_D_p,
136 patch_D_n => patch_D_n,
137 trig_prim_p => trig_prim_p,
138 trig_prim_n => trig_prim_n,
139 -- miso => miso,
140 rx => rx,
141 rx_en => rx_en,
142 enables_A => enables_A,
143 enables_B => enables_B,
144 enables_C => enables_C,
145 enables_D => enables_D,
146 clr => clr,
147 cs_ld => cs_ld,
148 sck => sck,
149 mosi => mosi,
150 tx => tx,
151 tx_en => tx_en,
152 TP_A => TP_A
153 );
154
155 -- Clock process definitions
156 ext_clk_proc: process
157 begin
158 ext_clk <= '0';
159 wait for ext_clk_period/2;
160 ext_clk <= '1';
161 wait for ext_clk_period/2;
162 end process ext_clk_proc;
163
164 -- Stimulus process
165 stim_proc: process
166 begin
167 -- hold reset state for 100ms.
168 wait for 100ms;
169
170 wait for ext_clk_period*10;
171
172 -- insert stimulus here
173
174 wait;
175 end process stim_proc;
176
177end;
Note: See TracBrowser for help on using the repository browser.