| Line | |
|---|
| 1 | # Generated by Xilinx Architecture Wizard
|
|---|
| 2 | # --- UCF Template Only ---
|
|---|
| 3 | # Cut and paste these attributes into the project's UCF file, if desired
|
|---|
| 4 | INST DCM_SP_INST CLK_FEEDBACK = NONE;
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|---|
| 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
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| 6 | INST DCM_SP_INST CLKFX_DIVIDE = 20;
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| 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 2;
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| 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
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| 9 | INST DCM_SP_INST CLKIN_PERIOD = 20.000;
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| 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
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|---|
| 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
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| 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
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| 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
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|---|
| 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
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|---|
| 15 | INST DCM_SP_INST FACTORY_JF = C080;
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|---|
| 16 | INST DCM_SP_INST PHASE_SHIFT = 0;
|
|---|
| 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE;
|
|---|
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