source: firmware/FTU/test_firmware/FTU_test6/FTU_test6.vhd@ 18558

Last change on this file since 18558 was 9621, checked in by weitzel, 14 years ago
FTU_test6 added (RS485 receiver)
File size: 9.2 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 07/30/2010
6-- Design Name:
7-- Module Name: FTU_test6 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTU board, set enables via RS485
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library ftu_definitions_test6;
25USE ftu_definitions_test6.ftu_array_types.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32
33entity FTU_test6 is
34 port(
35 -- global control
36 ext_clk : IN STD_LOGIC; -- external clock from FTU board
37 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
38 brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
39
40 -- rate counters LVDS inputs
41 -- use IBUFDS differential input buffer
42 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
43 patch_A_n : IN STD_LOGIC;
44 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
45 patch_B_n : IN STD_LOGIC;
46 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
47 patch_C_n : IN STD_LOGIC;
48 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
49 patch_D_n : IN STD_LOGIC;
50 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
51 trig_prim_n : IN STD_LOGIC;
52
53 -- DAC interface
54 sck : OUT STD_LOGIC; -- serial clock to DAC
55 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
56 clr : OUT STD_LOGIC; -- clear signal to DAC
57 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
58
59 -- RS-485 interface to FTM
60 rx : IN STD_LOGIC; -- serial data from FTM
61 tx : OUT STD_LOGIC; -- serial data to FTM
62 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
63 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
64
65 -- analog buffer enable
66 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70
71 -- testpoints
72 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
73 );
74end FTU_test6;
75
76
77architecture Behavioral of FTU_test6 is
78
79 component FTU_test6_dcm
80 port(
81 CLKIN_IN : IN STD_LOGIC;
82 RST_IN : IN STD_LOGIC;
83 CLKFX_OUT : OUT STD_LOGIC;
84 CLKIN_IBUFG_OUT : OUT STD_LOGIC;
85 LOCKED_OUT : OUT STD_LOGIC
86 );
87 end component;
88
89 component FTU_test6_rs485_interface
90 GENERIC(
91 CLOCK_FREQUENCY : integer := 50000000; -- Hertz
92 BAUD_RATE : integer := 250000 -- bits / sec
93 );
94 PORT(
95 clk : IN std_logic;
96 -- RS485
97 rx_d : IN std_logic;
98 rx_en : OUT std_logic;
99 tx_d : OUT std_logic;
100 tx_en : OUT std_logic;
101 -- FPGA
102 rx_data : OUT std_logic_vector(7 DOWNTO 0);
103 rx_busy : OUT std_logic := '0';
104 rx_valid : OUT std_logic := '0';
105 tx_data : IN std_logic_vector(7 DOWNTO 0);
106 tx_busy : OUT std_logic := '0';
107 tx_start : IN std_logic
108 );
109 end component;
110
111 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
112 signal clk_50M_sig : STD_LOGIC;
113
114 signal enable_sig : enable_array_type := DEFAULT_ENABLE;
115
116 signal rx_en_sig : STD_LOGIC := '0';
117 signal tx_en_sig : STD_LOGIC := '0';
118 signal rx_sig : STD_LOGIC;
119 signal tx_sig : STD_LOGIC := 'X';
120 signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
121 signal rx_busy_sig : STD_LOGIC;
122 signal rx_valid_sig : STD_LOGIC;
123
124 type FTU_test6_StateType is (INIT, RUN1, RUN2, RUN3, RUN4);
125 signal FTU_test6_State, FTU_test6_NextState: FTU_test6_StateType;
126
127begin
128
129 Inst_FTU_test6_dcm : FTU_test6_dcm
130 port map(
131 CLKIN_IN => ext_clk,
132 RST_IN => reset_sig,
133 CLKFX_OUT => clk_50M_sig,
134 CLKIN_IBUFG_OUT => open,
135 LOCKED_OUT => open
136 );
137
138 Inst_FTU_test6_rs485_interface : FTU_test6_rs485_interface
139 generic map(
140 CLOCK_FREQUENCY => 50000000,
141 BAUD_RATE => 10000000 --simulation
142 --BAUD_RATE => 19600 --implement
143 )
144 port map(
145 clk => clk_50M_sig,
146 -- RS485
147 rx_d => rx_sig,
148 rx_en => rx_en_sig,
149 tx_d => tx_sig,
150 tx_en => tx_en_sig,
151 -- FPGA
152 rx_data => rx_data_sig,
153 rx_busy => rx_busy_sig,
154 rx_valid => rx_valid_sig,
155 tx_data => (others => '0'),
156 tx_busy => open,
157 tx_start => '0'
158 );
159
160 enables_A <= enable_sig(0)(8 downto 0);
161 enables_B <= enable_sig(1)(8 downto 0);
162 enables_C <= enable_sig(2)(8 downto 0);
163 enables_D <= enable_sig(3)(8 downto 0);
164
165 rx_en <= rx_en_sig;
166 tx_en <= tx_en_sig;
167 tx <= tx_sig;
168 rx_sig <= rx;
169
170 --FTU main state machine (two-process implementation)
171
172 FTU_test6_Registers: process (clk_50M_sig)
173 begin
174 if Rising_edge(clk_50M_sig) then
175 FTU_test6_State <= FTU_test6_NextState;
176 end if;
177 end process FTU_test6_Registers;
178
179 FTU_test6_C_logic: process (FTU_test6_State, rx_data_sig, rx_valid_sig)
180 begin
181 FTU_test6_NextState <= FTU_test6_State;
182 case FTU_test6_State is
183 when INIT =>
184 reset_sig <= '0';
185 enable_sig <= DEFAULT_ENABLE;
186 if (rx_data_sig = "00110001" and rx_valid_sig = '1') then
187 FTU_test6_NextState <= RUN1;
188 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
189 FTU_test6_NextState <= RUN2;
190 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
191 FTU_test6_NextState <= RUN3;
192 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
193 FTU_test6_NextState <= RUN4;
194 else
195 FTU_test6_NextState <= INIT;
196 end if;
197 when RUN1 =>
198 reset_sig <= '0';
199 enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111");
200 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
201 FTU_test6_NextState <= INIT;
202 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
203 FTU_test6_NextState <= RUN2;
204 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
205 FTU_test6_NextState <= RUN3;
206 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
207 FTU_test6_NextState <= RUN4;
208 else
209 FTU_test6_NextState <= RUN1;
210 end if;
211 when RUN2 =>
212 reset_sig <= '0';
213 enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111");
214 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
215 FTU_test6_NextState <= INIT;
216 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
217 FTU_test6_NextState <= RUN1;
218 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
219 FTU_test6_NextState <= RUN3;
220 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
221 FTU_test6_NextState <= RUN4;
222 else
223 FTU_test6_NextState <= RUN2;
224 end if;
225 when RUN3 =>
226 reset_sig <= '0';
227 enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111");
228 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
229 FTU_test6_NextState <= INIT;
230 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
231 FTU_test6_NextState <= RUN1;
232 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
233 FTU_test6_NextState <= RUN2;
234 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
235 FTU_test6_NextState <= RUN4;
236 else
237 FTU_test6_NextState <= RUN3;
238 end if;
239 when RUN4 =>
240 reset_sig <= '0';
241 enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000");
242 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
243 FTU_test6_NextState <= INIT;
244 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
245 FTU_test6_NextState <= RUN1;
246 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
247 FTU_test6_NextState <= RUN2;
248 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
249 FTU_test6_NextState <= RUN3;
250 else
251 FTU_test6_NextState <= RUN4;
252 end if;
253 end case;
254 end process FTU_test6_C_logic;
255
256end Behavioral;
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