source: firmware/FTU/test_firmware/FTU_test6_new/FTU_test6_new.vhd@ 17697

Last change on this file since 17697 was 10057, checked in by weitzel, 14 years ago
v3 of FTU docu and new version of FTU_test6 added
File size: 9.5 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 11/19/2010
6-- Design Name:
7-- Module Name: FTU_test6_new - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTU board, set enables via RS485, new version
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library ftu_definitions_test6_new;
25USE ftu_definitions_test6_new.ftu_array_types.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32entity FTU_test6_new is
33 port(
34 -- global control
35 ext_clk : IN STD_LOGIC; -- external clock from FTU board
36 --brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
37 --brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
38
39 -- rate counters LVDS inputs
40 -- use IBUFDS differential input buffer
41 --patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
42 --patch_A_n : IN STD_LOGIC;
43 --patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
44 --patch_B_n : IN STD_LOGIC;
45 --patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
46 --patch_C_n : IN STD_LOGIC;
47 --patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
48 --patch_D_n : IN STD_LOGIC;
49 --trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
50 --trig_prim_n : IN STD_LOGIC;
51
52 -- DAC interface
53 --sck : OUT STD_LOGIC; -- serial clock to DAC
54 --mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
55 --clr : OUT STD_LOGIC; -- clear signal to DAC
56 --cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
57
58 -- RS-485 interface to FTM
59 rx : IN STD_LOGIC; -- serial data from FTM
60 tx : OUT STD_LOGIC; -- serial data to FTM
61 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
62 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
63
64 -- analog buffer enable
65 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
66 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0) -- individual enables for analog inputs
69
70 -- testpoints
71 --TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
72 );
73end FTU_test6_new;
74
75
76architecture Behavioral of FTU_test6_new is
77
78 component FTU_test6_new_dcm
79 port(
80 CLKIN_IN : IN STD_LOGIC;
81 RST_IN : IN STD_LOGIC;
82 CLKFX_OUT : OUT STD_LOGIC;
83 CLKIN_IBUFG_OUT : OUT STD_LOGIC;
84 LOCKED_OUT : OUT STD_LOGIC
85 );
86 end component;
87
88 component FTU_test6_new_rs485_interface
89 GENERIC(
90 CLOCK_FREQUENCY : integer := 50000000; -- Hertz
91 BAUD_RATE : integer := 250000 -- bits / sec
92 );
93 PORT(
94 clk : IN std_logic;
95 -- RS485
96 rx_d : IN std_logic;
97 rx_en : OUT std_logic;
98 tx_d : OUT std_logic;
99 tx_en : OUT std_logic;
100 -- FPGA
101 rx_data : OUT std_logic_vector(7 DOWNTO 0);
102 --rx_busy : OUT std_logic := '0';
103 rx_valid : OUT std_logic := '0';
104 tx_data : IN std_logic_vector(7 DOWNTO 0);
105 tx_busy : OUT std_logic := '0';
106 tx_start : IN std_logic
107 );
108 end component;
109
110 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
111 signal clk_50M_sig : STD_LOGIC;
112
113 signal enable_sig : enable_array_type := DEFAULT_ENABLE;
114
115 signal rx_en_sig : STD_LOGIC := '0';
116 signal tx_en_sig : STD_LOGIC := '0';
117 signal rx_sig : STD_LOGIC;
118 signal tx_sig : STD_LOGIC := 'X';
119 signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
120 signal rx_busy_sig : STD_LOGIC;
121 signal rx_valid_sig : STD_LOGIC;
122
123 type FTU_test6_new_StateType is (INIT, RUN1, RUN2, RUN3, RUN4);
124 signal FTU_test6_new_State, FTU_test6_new_NextState: FTU_test6_new_StateType;
125
126begin
127
128 Inst_FTU_test6_new_dcm : FTU_test6_new_dcm
129 port map(
130 CLKIN_IN => ext_clk,
131 RST_IN => reset_sig,
132 CLKFX_OUT => clk_50M_sig,
133 CLKIN_IBUFG_OUT => open,
134 LOCKED_OUT => open
135 );
136
137 Inst_FTU_test6_new_rs485_interface : FTU_test6_new_rs485_interface
138 generic map(
139 CLOCK_FREQUENCY => 50000000,
140 --BAUD_RATE => 10000000 --simulation
141 BAUD_RATE => 250000 --implement
142 )
143 port map(
144 clk => clk_50M_sig,
145 -- RS485
146 rx_d => rx_sig,
147 rx_en => rx_en_sig,
148 tx_d => tx_sig,
149 tx_en => tx_en_sig,
150 -- FPGA
151 rx_data => rx_data_sig,
152 --rx_busy => rx_busy_sig,
153 rx_valid => rx_valid_sig,
154 tx_data => (others => '0'),
155 tx_busy => open,
156 tx_start => '0'
157 );
158
159 enables_A <= enable_sig(0)(8 downto 0);
160 enables_B <= enable_sig(1)(8 downto 0);
161 enables_C <= enable_sig(2)(8 downto 0);
162 enables_D <= enable_sig(3)(8 downto 0);
163
164 rx_en <= rx_en_sig;
165 tx_en <= tx_en_sig;
166 tx <= tx_sig;
167 rx_sig <= rx;
168
169 --FTU main state machine (two-process implementation)
170
171 FTU_test6_new_Registers: process (clk_50M_sig)
172 begin
173 if Rising_edge(clk_50M_sig) then
174 FTU_test6_new_State <= FTU_test6_new_NextState;
175 end if;
176 end process FTU_test6_new_Registers;
177
178 FTU_test6_new_C_logic: process (FTU_test6_new_State, rx_data_sig, rx_valid_sig)
179 begin
180 FTU_test6_new_NextState <= FTU_test6_new_State;
181 case FTU_test6_new_State is
182 when INIT =>
183 reset_sig <= '0';
184 enable_sig <= DEFAULT_ENABLE;
185 if (rx_data_sig = "00110001" and rx_valid_sig = '1') then
186 FTU_test6_new_NextState <= RUN1;
187 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
188 FTU_test6_new_NextState <= RUN2;
189 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
190 FTU_test6_new_NextState <= RUN3;
191 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
192 FTU_test6_new_NextState <= RUN4;
193 else
194 FTU_test6_new_NextState <= INIT;
195 end if;
196 when RUN1 =>
197 reset_sig <= '0';
198 enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111");
199 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
200 FTU_test6_new_NextState <= INIT;
201 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
202 FTU_test6_new_NextState <= RUN2;
203 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
204 FTU_test6_new_NextState <= RUN3;
205 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
206 FTU_test6_new_NextState <= RUN4;
207 else
208 FTU_test6_new_NextState <= RUN1;
209 end if;
210 when RUN2 =>
211 reset_sig <= '0';
212 enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111");
213 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
214 FTU_test6_new_NextState <= INIT;
215 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
216 FTU_test6_new_NextState <= RUN1;
217 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
218 FTU_test6_new_NextState <= RUN3;
219 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
220 FTU_test6_new_NextState <= RUN4;
221 else
222 FTU_test6_new_NextState <= RUN2;
223 end if;
224 when RUN3 =>
225 reset_sig <= '0';
226 enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111");
227 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
228 FTU_test6_new_NextState <= INIT;
229 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
230 FTU_test6_new_NextState <= RUN1;
231 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
232 FTU_test6_new_NextState <= RUN2;
233 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
234 FTU_test6_new_NextState <= RUN4;
235 else
236 FTU_test6_new_NextState <= RUN3;
237 end if;
238 when RUN4 =>
239 reset_sig <= '0';
240 enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000");
241 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
242 FTU_test6_new_NextState <= INIT;
243 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
244 FTU_test6_new_NextState <= RUN1;
245 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
246 FTU_test6_new_NextState <= RUN2;
247 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
248 FTU_test6_new_NextState <= RUN3;
249 else
250 FTU_test6_new_NextState <= RUN4;
251 end if;
252 end case;
253 end process FTU_test6_new_C_logic;
254
255end Behavioral;
Note: See TracBrowser for help on using the repository browser.