| 1 | ########################################################
|
|---|
| 2 | # FTU Board
|
|---|
| 3 | # FACT Trigger Unit
|
|---|
| 4 | #
|
|---|
| 5 | # Pin location constraints
|
|---|
| 6 | #
|
|---|
| 7 | # by Patrick Vogler, Quirin Weitzel
|
|---|
| 8 | # 02 July 2010
|
|---|
| 9 | ########################################################
|
|---|
| 10 |
|
|---|
| 11 |
|
|---|
| 12 | #Clock
|
|---|
| 13 | #######################################################
|
|---|
| 14 | NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk
|
|---|
| 15 |
|
|---|
| 16 |
|
|---|
| 17 | # RS-485 Interface
|
|---|
| 18 | #######################################################
|
|---|
| 19 | #NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver
|
|---|
| 20 | #NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter
|
|---|
| 21 | #NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM
|
|---|
| 22 | #NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM
|
|---|
| 23 |
|
|---|
| 24 |
|
|---|
| 25 | # Board ID - inputs
|
|---|
| 26 | # local board-ID "solder programmable"
|
|---|
| 27 | #######################################################
|
|---|
| 28 | #NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0
|
|---|
| 29 | #NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1
|
|---|
| 30 | #NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2
|
|---|
| 31 | #NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3
|
|---|
| 32 | #NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4
|
|---|
| 33 | #NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5
|
|---|
| 34 | #NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6
|
|---|
| 35 | #NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7
|
|---|
| 36 |
|
|---|
| 37 |
|
|---|
| 38 | # Board Addresses
|
|---|
| 39 | # geographical slot address
|
|---|
| 40 | #######################################################
|
|---|
| 41 | #NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0
|
|---|
| 42 | #NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1
|
|---|
| 43 | #NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2
|
|---|
| 44 | #NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3
|
|---|
| 45 | #NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4
|
|---|
| 46 | #NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5
|
|---|
| 47 |
|
|---|
| 48 |
|
|---|
| 49 | # DAC SPI Interface
|
|---|
| 50 | #######################################################
|
|---|
| 51 | NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in
|
|---|
| 52 | NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC
|
|---|
| 53 | NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC
|
|---|
| 54 | NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC
|
|---|
| 55 |
|
|---|
| 56 |
|
|---|
| 57 | # Testpoints
|
|---|
| 58 | ######################################################
|
|---|
| 59 | # on Connector J5
|
|---|
| 60 | #NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0
|
|---|
| 61 | #NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0
|
|---|
| 62 | #NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0
|
|---|
| 63 | #NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0
|
|---|
| 64 |
|
|---|
| 65 | # on Connector J6
|
|---|
| 66 | #NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0
|
|---|
| 67 | #NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0
|
|---|
| 68 | #NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0
|
|---|
| 69 | #NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0
|
|---|
| 70 |
|
|---|
| 71 | # on Connector J7
|
|---|
| 72 | #NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0
|
|---|
| 73 | #NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0
|
|---|
| 74 | #NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0
|
|---|
| 75 | #NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0
|
|---|
| 76 |
|
|---|
| 77 |
|
|---|
| 78 | # Rate counter LVDS Inputs
|
|---|
| 79 | ######################################################
|
|---|
| 80 | # logic signal from first trigger patch
|
|---|
| 81 | #NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P
|
|---|
| 82 | #NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N
|
|---|
| 83 |
|
|---|
| 84 | # logic signal from second trigger patch
|
|---|
| 85 | #NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P
|
|---|
| 86 | #NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N
|
|---|
| 87 |
|
|---|
| 88 | # logic signal from third trigger patch
|
|---|
| 89 | #NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P
|
|---|
| 90 | #NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N
|
|---|
| 91 |
|
|---|
| 92 | # logic signal from fourth trigger patch
|
|---|
| 93 | #NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P
|
|---|
| 94 | #NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N
|
|---|
| 95 |
|
|---|
| 96 | #The Trigger Primitive: logic signal from n-out-of-4 circuit
|
|---|
| 97 | #NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+
|
|---|
| 98 | #NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P-
|
|---|
| 99 |
|
|---|
| 100 |
|
|---|
| 101 | # Enables
|
|---|
| 102 | ######################################################
|
|---|
| 103 | # Patch 0
|
|---|
| 104 | NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0
|
|---|
| 105 | NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
|
|---|
| 106 | NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
|
|---|
| 107 | NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
|
|---|
| 108 | NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
|
|---|
| 109 | NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
|
|---|
| 110 | NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
|
|---|
| 111 | NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7
|
|---|
| 112 | NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8
|
|---|
| 113 |
|
|---|
| 114 | ## Patch 1
|
|---|
| 115 | NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
|
|---|
| 116 | NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
|
|---|
| 117 | NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
|
|---|
| 118 | NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
|
|---|
| 119 | NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
|
|---|
| 120 | NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
|
|---|
| 121 | NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
|
|---|
| 122 | NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
|
|---|
| 123 | NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
|
|---|
| 124 |
|
|---|
| 125 | # Patch 2
|
|---|
| 126 | NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
|
|---|
| 127 | NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
|
|---|
| 128 | NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
|
|---|
| 129 | NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
|
|---|
| 130 | NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
|
|---|
| 131 | NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
|
|---|
| 132 | NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
|
|---|
| 133 | NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
|
|---|
| 134 | NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
|
|---|
| 135 |
|
|---|
| 136 | # Patch 3
|
|---|
| 137 | NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 138 | NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 139 | NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 140 | NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 141 | NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 142 | NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 143 | NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 144 | NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
| 145 | NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
|
|---|
