source: firmware/MSR/src/ad7719_adc.c@ 16318

Last change on this file since 16318 was 10588, checked in by neise, 14 years ago
added MSR Firmware MSR is the little brother of FSC
File size: 4.6 KB
Line 
1//-----------------------------------------------------------------------------
2
3#include "ad7719_adc.h"
4#include "spi_master.h"
5
6//-----------------------------------------------------------------------------
7
8void ad7719_init(void)
9{
10
11 // ADC communiaction works like this:
12 // a write operation to the COM register takes place - telling the device what up next.
13 // a write or read operation to another register takes place
14 // COM register bits have the following meaning:
15 //
16 // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
17 // |#WEN |R/#W | zero| zero| A3 | A2 | A1 | A0 |
18 //
19 // #WEN (inversed write enable) must be zero inorder to clock more bits into the SPI interface.
20 // R/#W (read / not write) must be zero if the next operation will be a WRITE. one if the next is READ.
21 // A3-A0 denote the address of the next register.
22
23
24 CLR_BIT(PORTB,ADC_RST); // Reset ADC (active low)
25 SET_BIT(PORTB,ADC_RST); // Stop Reset ADC
26
27 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
28 spi_transfer_byte(FILTER_RD); // Next Operation is write to IOCON
29 SET_BIT(PORTB,SPI_AD_CS);
30
31_delay_us(50);
32
33 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
34 spi_transfer_byte(0); // Next Operation is write to IOCON
35 SET_BIT(PORTB,SPI_AD_CS);
36
37_delay_us(50);
38
39 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
40 spi_transfer_byte(IOCON_WR); // Next Operation is write to IOCON
41 SET_BIT(PORTB,SPI_AD_CS);
42
43 _delay_us(50);
44
45 CLR_BIT(PORTB,SPI_AD_CS);
46 spi_transfer_byte(IOCON_INIT_HIGH); // Write to IOCON1
47 SET_BIT(PORTB,SPI_AD_CS);
48_delay_us(50);
49 CLR_BIT(PORTB,SPI_AD_CS);
50 spi_transfer_byte(IOCON_INIT_LOWBYTE); // Write to IOCON2
51 SET_BIT(PORTB,SPI_AD_CS); // Set CS high
52
53_delay_us(50);
54
55 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
56 spi_transfer_byte(FILTER_WR); // Next Operation is write to FILTER Start SPI
57 SET_BIT(PORTB,SPI_AD_CS);
58
59_delay_us(50);
60 CLR_BIT(PORTB,SPI_AD_CS);
61
62 spi_transfer_byte(FILTER_INIT); // Write to FILTER
63 SET_BIT(PORTB,SPI_AD_CS); // Set CS high
64_delay_us(50);
65 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
66 spi_transfer_byte(AD1CON_WR); // Next Operation is write to AD1CON Start SPI
67 SET_BIT(PORTB,SPI_AD_CS);
68
69_delay_us(50);
70
71 CLR_BIT(PORTB,SPI_AD_CS);
72 spi_transfer_byte(AD1CON_INIT); // Write to AD1CON
73 SET_BIT(PORTB,SPI_AD_CS); // Set CS high
74
75_delay_us(50);
76
77 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
78 spi_transfer_byte(AD0CON_WR); // Next Operation is write to AD0CON Start SPI
79 SET_BIT(PORTB,SPI_AD_CS);
80
81_delay_us(50);
82
83 CLR_BIT(PORTB,SPI_AD_CS);
84 spi_transfer_byte(AD0CON_INIT); // Write to AD0CON
85 SET_BIT(PORTB,SPI_AD_CS); // Set CS high
86
87_delay_us(50);
88
89 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
90 spi_transfer_byte(MODE_WR); // Next Operation is write to MODE Start SPI
91 SET_BIT(PORTB,SPI_AD_CS);
92
93_delay_us(50);
94
95 CLR_BIT(PORTB,SPI_AD_CS);
96 spi_transfer_byte(MODE_CONT); // Write to MODE
97 SET_BIT(PORTB,SPI_AD_CS); // Set CS high
98
99_delay_us(50);
100
101 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
102 spi_transfer_byte(FILTER_RD); // Next Operation is write to IOCON
103 SET_BIT(PORTB,SPI_AD_CS);
104
105_delay_us(50);
106
107 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
108 spi_transfer_byte(0); // Next Operation is write to IOCON
109 SET_BIT(PORTB,SPI_AD_CS);
110
111_delay_us(50);
112
113
114}
115
116void startconv(U08 continuous)
117{
118 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
119 spi_transfer_byte(MODE_WR); // Next Operation is write to Mode Register
120 SET_BIT(PORTB,SPI_AD_CS);
121 CLR_BIT(PORTB,SPI_AD_CS);
122 if (continuous) spi_transfer_byte(MODE_SINGLE); // Start new A/D conversion
123 else spi_transfer_byte(MODE_CONT); // Start continous conversion mode
124 SET_BIT(PORTB,SPI_AD_CS);
125}
126
127void stopconv(void)
128{
129 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
130 spi_transfer_byte(MODE_WR); // Next Operation is write to Mode Register
131 SET_BIT(PORTB,SPI_AD_CS);
132 CLR_BIT(PORTB,SPI_AD_CS);
133 spi_transfer_byte(MODE_IDLE);
134 SET_BIT(PORTB,SPI_AD_CS);
135}
136
137
138U32 read_adc(void)
139{
140 CLR_BIT(PORTB,SPI_AD_CS); // Set CS low
141 spi_transfer_byte(AD0DAT_RD); // Next Operation is read from Main ADC Data Register
142 SET_BIT(PORTB,SPI_AD_CS);
143 _delay_us(50);
144
145 CLR_BIT(PORTB,SPI_AD_CS);
146 U32 value=0; // actually a 24bit value is returned
147 value |= spi_transfer_byte(0) ;
148 value =value<<8;
149 value |= spi_transfer_byte(0) ;
150 value =value<<8;
151 value |= spi_transfer_byte(0) ;
152 SET_BIT(PORTB,SPI_AD_CS); // Set CS high
153 return value;
154}
155
156
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