source: firmware/MSR/src/application.c@ 20115

Last change on this file since 20115 was 10588, checked in by neise, 13 years ago
added MSR Firmware MSR is the little brother of FSC
File size: 2.8 KB
Line 
1//-----------------------------------------------------------------------------
2
3#include "application.h"
4#include <avr/wdt.h>
5
6
7//-----------------------------------------------------------------------------
8
9volatile U08 app_reset_source;
10//-----------------------------------------------------------------------------
11
12void app_init(void)
13{
14 app_reset_source = MCUSR; // Save last reset source
15 MCUSR = 0x00; // Clear reset source for next reset cycle
16
17
18 // Dangerous here: I still do not know much about the watchdog.
19 // This code is still from Udo Juerss.
20
21 // The watchdog timer is disabled by default ("startup.asm")
22 #ifdef USE_WATCHDOG
23 WDTCSR = WDTOE | (1 << WDE); // Enable watchdog reset (~16ms)
24 #endif
25
26 // define PORTS
27 // USART
28 DDRD &= ~(1<<PD0); // PD0 = RXD is input
29 DDRD |= 1<<PD1; // PD1 = TXD is output
30
31
32 // SPARE OUT/-INPUTS
33 // I set (nearly) all spare pins as inputs, so they are high-Z ... that's safe I guess.
34 DDRA &= ~(1<<PA5);
35 DDRA &= ~(1<<PA6);
36 DDRA &= ~(1<<PC4);
37 DDRA &= ~(1<<PC5);
38 DDRA &= ~(1<<PC6);
39 DDRA &= ~(1<<PC7);
40 // But this pin, is the heartbeat pin...
41 DDRA |= (1<<PA4);
42
43
44 // the pull ups should be off by default :-)
45
46 // ATmega internal ADC input
47 DDRA &= ~(1<<PA7);
48
49 // MUXER ADDRESS OUTs
50 DDRA |= 0x0F; // SA-pins -> output
51 DDRC |= 0x0F; // SB-pins -> output
52
53 // SPI
54 // set all CS's: output
55
56 DDRB |= (1 << SPI_E_CS);
57 DDRB |= (1 << SPI_AD_CS);
58
59 // set all Chips selects HIGH
60 PORTB |= (1 << SPI_E_CS);
61 PORTB |= (1 << SPI_AD_CS);
62
63
64
65 // set MOSI and SCK: output & // set MISO: input
66 SPI_DDR |= (1 << SPI_MOSI);
67 SPI_DDR |= (1 << SPI_SCLK);
68 SPI_DDR &= ~(1 << SPI_MISO);
69
70 // set MOSI, SCK: HIGH. MISO leave alone.
71 SPI_PRT |= (1 << SPI_MOSI);
72 SPI_PRT |= (1 << SPI_SCLK);
73 //SPI_PRT |= (1 << SPI_MISO);
74
75 // ADC
76 DDRD &= ~(1<<PD2); // PD2 is AD_READY input
77 DDRB |= 1<<PB1; // PB1 is AD_RESET output
78
79 // ACCELEROMETER
80 DDRB &= ~(1<<PB0); // PB0 is ACC_READY input (existiert nichtmehr, umgelegt)
81
82 //MAX6662 <--- not assembled
83 // DDRB &= ~(1<<PB0); // PB0 is over temperature alert input
84 // DDRB &= ~(1<<PB1); // PB1 is general temperature altert input
85}
86
87
88
89//-----------------------------------------------------------------------------
90
91void app_set_watchdog_prescaler(tWDT_PRESCALE wdt_prescale) // Set watchdog prescale
92{
93 U08 sreg_backup = SREG; // Copy status register to variable
94 U08 wdtcsr_value = WDE + wdt_prescale; // Set new prescale value to variable
95
96 cli(); // Disable interrups
97 wdt_reset(); // Reset watchdog
98
99 WDTCR |= (1 << WDTOE) | (1 << WDE); // Unlock register access, 4 cycles to store new value
100 WDTCR = wdtcsr_value; // Set new watchdog prescaler
101 SREG = sreg_backup; // Restore status register
102}
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