source: firmware/MSR/src/spi_master.c@ 16318

Last change on this file since 16318 was 10588, checked in by neise, 14 years ago
added MSR Firmware MSR is the little brother of FSC
File size: 6.6 KB
Line 
1//-----------------------------------------------------------------------------
2#include "spi_master.h"
3
4//-----------------------------------------------------------------------------
5volatile U08 spi_clock_index;
6volatile U08 spi_cpol;
7volatile U08 spi_cpha;
8volatile U08 spi_dord;
9volatile BOOL spi_ss_active_high;
10volatile U08 spi_read_buffer[SPI_READ_BUFFER_SIZE];
11volatile U08 spi_write_buffer[SPI_WRITE_BUFFER_SIZE];
12
13volatile U08 SPI_DEVICE_SS[2]={SPI_E_CS ,SPI_AD_CS};
14volatile BOOL SPI_DEVICE_ACTIVE_HIGH[2]={false ,false};
15//-----------------------------------------------------------------------------
16
17
18
19
20void spi_init(void)
21{
22 // there are a total of 4 devices on the SPI bus:
23 // 1.) Ethernet Modul WIZ812MJ
24 // 2.) AD7719 24bit ADC
25 // 3.) LIS3LV accelerometer
26 // 4.) MAX6662 temp sensor <---- not assembled!
27
28 // We check if they all can live with the same SPI settings:
29 // 1.) Ethernet modul:
30 // supports spi mode=0 or mode=3 --> eighther cpol=cpha=0 or cpol=cpha=1
31 // THAT IS NOT TRUE!!!!
32 // only mode 0 !!!!!!!!!!!!!!!!!!!!!!!!!!!1
33 // MSB first
34 // SCLK time 70ns minimum --> 14.2MHz maximum
35 //
36 // 2.) AD7719
37 // supports mode=3 --> cpol=cpha=1
38 // MSB first
39 // SCLK time 200ns minimum --> 5MHz maximum
40 //
41 // 3.) LIS3LV
42 // SPI CLK idles high --> cpol=1
43 // data valid at rising edge. --> cpha=1 as well
44 // ==> mode 3 is supported only.
45 // MSB first, but take take at multi byte transfers. LSbyte first
46 // SCLK time - is not mentioned in the datasheet
47 //
48 // 4.) MAX6662 Tempsensor
49 // since it is not assembled, this information is not necessary.
50
51 // fastes SPI CLK frequency can be --> F_CPU/2 = 4MHz
52 // slowest can be --> F_CPU/128 = 62.5KHz
53
54 // Lets try with the fastest!
55 spi_clock_index = 0; // Set Clockindex for lowest clock speed (F_CPU / 128)
56
57 spi_dord = 0; // Data Order MSB first dord = 0 --> good for all devices
58 spi_cpol = 1; spi_cpha = 1; // SPI mode=3 --> good for all devices
59 spi_setup(); // Setup SPI bits and clock speed
60
61}
62//-----------------------------------------------------------------------------
63void spi_setup(void)
64{
65 // Disable SPI, clear all flags
66 SPCR = 0;
67
68 // Set/Clear bits DORD, CPOL and CPHA in SPI Control Register
69 spi_dord & 0x01 ? (SPCR |= (1 << DORD)) : (SPCR &= ~(1 << DORD));
70 spi_cpol & 0x01 ? (SPCR |= (1 << CPOL)) : (SPCR &= ~(1 << CPOL));
71 spi_cpha & 0x01 ? (SPCR |= (1 << CPHA)) : (SPCR &= ~(1 << CPHA));
72
73 switch (spi_clock_index)
74 {
75 case 0:{ // F_CPU / 128
76 SPCR |= (1 << SPR1) | (1 << SPR0);
77 SPSR &= ~(1 <<SPI2X);
78 }
79 break;
80
81 case 1:{ // F_CPU / 64
82 SPCR |= (1 << SPR1);
83 SPSR &= ~(1 << SPI2X);
84 }
85 break;
86
87 case 2:{ // F_CPU / 32
88 SPCR |= (1 << SPR1);
89 SPSR |= (1 << SPI2X);
90 }
91 break;
92
93 case 3:{ // F_CPU / 16
94 SPCR |= (1 << SPR0);
95 SPSR &= ~(1 << SPI2X);
96 }
97 break;
98
99 case 4:{ // F_CPU / 8
100 SPCR |= (1 << SPR0);
101 SPSR |= (1 << SPI2X);
102 }
103 break;
104
105 case 5: // F_CPU / 4
106 SPSR &= ~(1 << SPI2X);
107 break;
108
109 case 6: // F_CPU / 2
110 SPSR |= (1 << SPI2X);
111 break;
112
113 default:{ // F_CPU / 128
114 SPCR |= (1 << SPR1) | (1 << SPR0);
115 SPSR &= ~(1 << SPI2X);
116 }
117 }
118
119 // Enable SPI in Master Mode
120 SPCR |= (1 << SPE) | (1 << MSTR);
121}
122
123//-----------------------------------------------------------------------------
124
125void spi_set_clock_index(U08 clock_index)
126{
127 if (clock_index > SPI_MAX_CLOCK_INDEX)
128 {
129 clock_index = SPI_MAX_CLOCK_INDEX;
130 }
131
132 spi_clock_index = clock_index;
133
134 spi_setup(); // Setup SPI bits and clock speed
135}
136//-----------------------------------------------------------------------------
137
138void spi_set_dord(U08 dord)
139{
140 if (dord > 1)
141 {
142 dord = 1;
143 }
144
145 spi_dord = dord;
146
147 spi_setup(); // Setup SPI bits and clock speed
148}
149//-----------------------------------------------------------------------------
150
151void spi_set_cpol(U08 cpol)
152{
153 if (cpol > 1)
154 {
155 cpol = 1;
156 }
157
158 spi_cpol = cpol;
159
160 spi_setup(); // Setup SPI bits and clock speed
161}
162//-----------------------------------------------------------------------------
163
164void spi_set_cpha(U08 cpha)
165{
166 if (cpha > 1)
167 {
168 cpha = 1;
169 }
170
171 spi_cpha = cpha;
172
173 spi_setup(); // Setup SPI bits and clock speed
174}
175
176//-----------------------------------------------------------------------------
177
178void spi_transfer(U08 bytes, U08 device)
179{
180
181 U08 n;
182 // Transfer requested bytes
183 for (n = 0; n < bytes; n++)
184 {
185 // Check for active slave select level
186 if (SPI_DEVICE_ACTIVE_HIGH[device])
187 {
188 if (device == 0) {
189 PORTB |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
190 } else {
191 PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
192 }
193 }
194 else
195 {
196 if (device == 0) {
197 PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
198 } else {
199 PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
200 }
201 }
202
203
204 spi_read_buffer[n] = spi_transfer_byte(spi_write_buffer[n]);
205
206
207 // Check for inactive slave select level
208 if (SPI_DEVICE_ACTIVE_HIGH[device])
209 {
210 if (device == 0) {
211 PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
212 } else {
213 PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
214 }
215 }
216 else
217 {
218 if (device == 0) {
219 PORTB |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
220 } else {
221 PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
222 }
223 }
224
225 }
226}
227//-----------------------------------------------------------------------------
228
229U08 spi_transfer_byte(U08 data)
230{
231 // Start SPI Transfer
232 if (!(SPCR & (1<<MSTR)) )
233 SPCR |= 1<<MSTR;
234 SPDR = data;
235
236 // Wait for transfer completed
237 while (!(SPSR & (1 << SPIF)))
238 {
239 }
240
241 // Return result of transfer
242 return SPDR;
243}
244
245//-----------------------------------------------------------------------------
246void spi_transfer_string(U08 length, U08* addr, U08 device)
247{
248
249 U08 n;
250
251 // I assume the CS line is in "not enable"-state;
252 if ( device == 0 ){
253 TGL_BIT(PORTB, SPI_DEVICE_SS[device]); // I toggle the line
254 } else {
255 TGL_BIT(PORTD, SPI_DEVICE_SS[device]); // I toggle the line
256 }
257 // now the line is in "enable"-state
258
259
260 // Transfer requested bytes
261 for (n = 0; n < length; n++)
262 {
263 spi_transfer_byte(addr[n]);
264 }
265
266 if ( device == 0 ){
267 TGL_BIT(PORTB, SPI_DEVICE_SS[device]); // I toggle the line
268 } else {
269 TGL_BIT(PORTD, SPI_DEVICE_SS[device]); // I toggle the line
270 }
271
272}
273//-----------------------------------------------------------------------------
Note: See TracBrowser for help on using the repository browser.