| 1 | /*-----------------------------------------------------------------------------
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| 2 | bcan.h -- Interface to Basic CAN Controller Chip PCA82C200
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| 3 |
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| 4 | Copyright (c) 1994 JANZ Computer AG
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| 5 | All Rights Reserved
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| 6 |
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| 7 | Created 94/10/11 by Soenke Hansen
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| 8 | Version 1.18 of 00/03/30
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| 9 |
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| 10 | Prototypes for functions in bcan.c.
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| 11 | Macros for descriptor word, CAN identifiers, RTR bits, and data length codes.
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| 12 | Defintions of register addresses and values for the Basic CAN controller.
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| 13 |
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| 14 | -----------------------------------------------------------------------------*/
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| 15 |
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| 16 | #ifndef bcan_DEFINED
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| 17 | #define bcan_DEFINED
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| 18 |
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| 19 | #ifdef __cplusplus
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| 20 | extern "C" {
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| 21 | #endif
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| 22 |
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| 23 | #include "defs.h"
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| 24 | #include "msg.h"
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| 25 |
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| 26 | /*-------- COBs CAN Communication Objects ----------------------------------*/
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| 27 |
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| 28 | /* COBs (CAN Communication Objects) consists of the following data:
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| 29 | WORD_t desc;
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| 30 | BYTE_t data[8];
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| 31 | The format of the descriptor word follows that of the PCA82C200 controller:
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| 32 | desc >> 5 is the 11-bit identifier
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| 33 | desc & 0x0010 is set iff the RTR bit is set
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| 34 | desc & 0x000f is the data length code DLC
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| 35 | There are at most 8 data bytes in data[] (DLC <= 8).
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| 36 | */
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| 37 |
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| 38 | /* RTR bit in COB descriptor */
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| 39 | #define COBD_RTR 0x0010
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| 40 |
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| 41 | /* Get RTR bit from COB descriptor */
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| 42 | #define cobd_get_rtr(desc) ((desc) & COBD_RTR)
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| 43 |
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| 44 | /* Get data length code from COB descriptor */
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| 45 | #define cobd_get_dlc(desc) ((desc) & 0x000f)
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| 46 |
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| 47 | /* Get real data length */
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| 48 | #define cobd_get_len(desc) (((desc) & COBD_RTR) ? 0 : \
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| 49 | (((desc) & 0x08) ? 8 : (desc) & 0x07))
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| 50 |
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| 51 | /* Get id and RTR bit from COB descriptor */
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| 52 | #define cobd_get_id_rtr(desc) ((desc) & 0xfff0)
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| 53 |
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| 54 | /* Get RTR bit and data length code from COB descriptor */
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| 55 | #define cobd_get_rtr_dlc(desc) ((desc) & 0x001f)
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| 56 |
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| 57 | /* Get identifier from COB descriptor */
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| 58 | #define cobd_get_id(desc) ((desc) >> 5) /* numerical value of id */
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| 59 |
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| 60 | /* Shift identifier for oring into COB descriptor */
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| 61 | #define cobd_id_to_desc(id) ((id) << 5)
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| 62 |
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| 63 | /* Set COB descriptor from Id, and data length code, with or without RTR */
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| 64 | #define cobd_set(id, dlc) (((id) << 5) | (0x000f & (WORD_t)(dlc)))
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| 65 | #define cobd_setrtr(id, dlc) (((id) << 5) | COBD_RTR | (0x000f & (WORD_t)(dlc)))
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| 66 |
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| 67 |
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| 68 | /*-------- Definitions of registers ----------------------------------------*/
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| 69 |
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| 70 | /*
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| 71 | * 82C200 and SJA1000 in BasicCAN Mode
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| 72 | */
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| 73 |
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| 74 | /* PCA82C200 Address Allocation */
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| 75 | #define BCAN_CR 0 /* control register */
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| 76 | #define BCAN_CMR 1 /* command register */
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| 77 | #define BCAN_SR 2 /* status register */
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| 78 | #define BCAN_IR 3 /* interrupt register */
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| 79 | #define BCAN_AC 4 /* acceptance code register */
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| 80 | #define BCAN_AM 5 /* acceptance mask register */
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| 81 | #define BCAN_BT0 6 /* bus timing register 0 */
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| 82 | #define BCAN_BT1 7 /* bus timing register 1 */
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| 83 | #define BCAN_OCR 8 /* output control register */
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| 84 | #define BCAN_TDESC1 10 /* first descriptor transmit buffer */
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| 85 | #define BCAN_TDESC2 11 /* second descriptor transmit buffer */
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| 86 | #define BCAN_TDATA 12 /* start data transmit buffer */
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| 87 | #define BCAN_RDESC1 20 /* first descriptor receive buffer */
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| 88 | #define BCAN_RDESC2 21 /* second descriptor receive buffer */
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| 89 | #define BCAN_RDATA 22 /* start data receive buffer */
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| 90 | #define BCAN_CDR 31 /* clock divider */
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| 91 |
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| 92 |
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| 93 | /* Control Register Bits */
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| 94 | #define BCAN_CR_OIE 0x10 /* Overrun Interrupt Enable */
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| 95 | #define BCAN_CR_EIE 0x08 /* Error Interrupt Enable */
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| 96 | #define BCAN_CR_TIE 0x04 /* Transmit Interrupt Enable */
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| 97 | #define BCAN_CR_RIE 0x02 /* Receive Interrupt Enable */
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| 98 | #define BCAN_CR_RR 0x01 /* Reset Request */
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| 99 |
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| 100 | /* Command Register Bits */
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| 101 | #define BCAN_CMR_GTS 0x10 /* Goto Sleep */
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| 102 | #define BCAN_CMR_COS 0x08 /* Clear Overrun Status */
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| 103 | #define BCAN_CMR_RRB 0x04 /* Release Receive Buffer */
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| 104 | #define BCAN_CMR_AT 0x02 /* Abort Transmission */
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| 105 | #define BCAN_CMR_TR 0x01 /* Transmission Request */
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| 106 |
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| 107 | /* Status Register Bits */
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| 108 | #define BCAN_SR_BS 0x80 /* Bus Status */
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| 109 | #define BCAN_SR_ES 0x40 /* Error Status */
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| 110 | #define BCAN_SR_TS 0x20 /* Transmit Status */
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| 111 | #define BCAN_SR_RS 0x10 /* Receive Status */
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| 112 | #define BCAN_SR_TCS 0x08 /* Transmission Complete Status */
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| 113 | #define BCAN_SR_TBS 0x04 /* Transmit Buffer Status */
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| 114 | #define BCAN_SR_DO 0x02 /* Data Overrun */
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| 115 | #define BCAN_SR_RBS 0x01 /* Receive Buffer Status */
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| 116 |
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| 117 | /* Interrupt Register Bits */
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| 118 | #define BCAN_IR_WUI 0x10 /* Wake-Up Interrupt */
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| 119 | #define BCAN_IR_OI 0x08 /* Overrun Interrupt */
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| 120 | #define BCAN_IR_EI 0x04 /* Error Interrupt */
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| 121 | #define BCAN_IR_TI 0x02 /* Transmit Interrupt */
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| 122 | #define BCAN_IR_RI 0x01 /* Receive Interrupt */
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| 123 |
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| 124 |
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| 125 | /*
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| 126 | * JSA1000 in PeliCAN mode
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| 127 | */
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| 128 |
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| 129 | /* PeliCAN mode address allocation */
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| 130 | #define PCAN_MODR 0 /* Mode register (rw) */
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| 131 | #define PCAN_CMR 1 /* Command register (wo) */
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| 132 | #define PCAN_SR 2 /* Status register (ro) */
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| 133 | #define PCAN_IR 3 /* Interrupt register (ro) */
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| 134 | #define PCAN_IER 4 /* Interrupt enable register (rw) */
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| 135 | #define PCAN_BTR0 6 /* Bus timing register 0 (ro, rw) */
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| 136 | #define PCAN_BTR1 7 /* Bus timing register 1 (ro, rw) */
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| 137 | #define PCAN_OCR 8 /* Output control register 1 (ro, rw) */
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| 138 | #define PCAN_TESTR 9 /* Test register */
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| 139 | #define PCAN_ALCR 11 /* Arbitration lost capture reg (ro) */
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| 140 | #define PCAN_ECCR 12 /* Error code capture register (ro) */
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| 141 | #define PCAN_EWLR 13 /* Error warning limit register (ro, rw) */
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| 142 | #define PCAN_RXERR 14 /* Rx error counter register (ro, rw) */
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| 143 | #define PCAN_TXERR 15 /* Tx error counter register (ro, rw) */
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| 144 | #define PCAN_ACR0 16 /* acceptance code register 0 (-, rw) */
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| 145 | #define PCAN_ACR1 17 /* acceptance code register 1 (-, rw) */
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| 146 | #define PCAN_ACR2 18 /* acceptance code register 2 (-, rw) */
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| 147 | #define PCAN_ACR3 19 /* acceptance code register 3 (-, rw) */
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| 148 | #define PCAN_AMR0 20 /* acceptance mask register 0 (-, rw) */
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| 149 | #define PCAN_AMR1 21 /* acceptance mask register 1 (-, rw) */
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| 150 | #define PCAN_AMR2 22 /* acceptance mask register 2 (-, rw) */
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| 151 | #define PCAN_AMR3 23 /* acceptance mask register 3 (-, rw) */
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| 152 | #define PCAN_RXFI 16 /* Rx Frame info SFF, EFF (ro, -) */
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| 153 | #define PCAN_RXID1 17 /* Rx Identifier 1 SFF, EFF (ro, -) */
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| 154 | #define PCAN_RXID2 18 /* Rx Identifier 2 SFF, EFF (ro, -) */
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| 155 | #define PCAN_RXID3 19 /* Rx Identifier 3 EFF (ro, -) */
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| 156 | #define PCAN_RXID4 20 /* Rx Identifier 4 EFF (ro, -) */
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| 157 | #define PCAN_RXSFFD 19 /* Rx standard frame data (ro, -) */
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| 158 | #define PCAN_RXEFFD 21 /* Rx extended frame data (ro, -) */
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| 159 | #define PCAN_TXFI 16 /* Tx Frame info SFF, EFF (wo, -) */
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| 160 | #define PCAN_TXID1 17 /* Tx Identifier 1 SFF, EFF (wo, -) */
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| 161 | #define PCAN_TXID2 18 /* Tx Identifier 2 SFF, EFF (wo, -) */
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| 162 | #define PCAN_TXID3 19 /* Tx Identifier 3 EFF (wo, -) */
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| 163 | #define PCAN_TXID4 20 /* Tx Identifier 4 EFF (wo, -) */
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| 164 | #define PCAN_TXSFFD 19 /* Tx standard frame data (wo, -) */
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| 165 | #define PCAN_TXEFFD 21 /* Tx extended frame data (wo, -) */
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| 166 | #define PCAN_RXMCR 29 /* Rx message counter register (ro) */
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| 167 | #define PCAN_RXBSAR 30 /* Rx buffer start address register (ro, rw) */
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| 168 | #define PCAN_CDR 31 /* Clock divider register ('rw', rw)*/
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| 169 |
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| 170 | #define PCAN_RXFI_RAM 96 /* RAM mirror of RXFI */
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| 171 | #define PCAN_TXFI_RAM 96 /* RAM mirror of TXFI */
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| 172 | #define PCAN_TXID1_RAM 97 /* RAM mirror Tx Identifier 1 SFF, EFF */
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| 173 | #define PCAN_TXID2_RAM 98 /* RAM mirror Tx Identifier 2 SFF, EFF */
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| 174 | #define PCAN_TXID3_RAM 99 /* RAM mirror Tx Identifier 3 EFF */
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| 175 | #define PCAN_TXID4_RAM 100 /* RAM mirror Tx Identifier 4 EFF */
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| 176 | #define PCAN_TXSFFD_RAM 99 /* RAM mirror Tx standard frame data */
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| 177 | #define PCAN_TXEFFD_RAM 101 /* RAM mirror Tx extended frame data */
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| 178 |
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| 179 |
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| 180 | /* Mode Register Bits */
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| 181 | #define PCAN_MODR_SM (1<<4) /* Sleep mode */
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| 182 | #define PCAN_MODR_AFM (1<<3) /* Acceptance filter mode */
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| 183 | #define PCAN_MODR_STM (1<<2) /* Self test mode */
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| 184 | #define PCAN_MODR_LOM (1<<1) /* Listen only mode */
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| 185 | #define PCAN_MODR_RM (1<<0) /* Reset mode */
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| 186 |
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| 187 | /* Command Register Bits */
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| 188 | #define PCAN_CMR_SRR (1<<4) /* Self reception request */
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| 189 | #define PCAN_CMR_CDO (1<<3) /* Clear data overrun */
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| 190 | #define PCAN_CMR_RRB (1<<2) /* Release receive buffer */
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| 191 | #define PCAN_CMR_AT (1<<1) /* Abort transmission */
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| 192 | #define PCAN_CMR_TR (1<<0) /* Transmission request */
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| 193 |
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| 194 | /* Status Register Bits */
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| 195 | #define PCAN_SR_BS (1<<7) /* Bus status */
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| 196 | #define PCAN_SR_ES (1<<6) /* Error status */
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| 197 | #define PCAN_SR_TS (1<<5) /* Transmit status */
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| 198 | #define PCAN_SR_RS (1<<4) /* Receive status */
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| 199 | #define PCAN_SR_TCS (1<<3) /* Transmission complete status */
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| 200 | #define PCAN_SR_TBS (1<<2) /* Transmit buffer status */
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| 201 | #define PCAN_SR_DOS (1<<1) /* Data overrun status */
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| 202 | #define PCAN_SR_RBS (1<<0) /* Receive buffer status */
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| 203 |
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| 204 | /* Interrupt Register Bits */
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| 205 | #define PCAN_IR_BEI (1<<7) /* Bus-eror interrupt */
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| 206 | #define PCAN_IR_ALI (1<<6) /* Arbitration lost interrupt */
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| 207 | #define PCAN_IR_EPI (1<<5) /* Error-passive interrupt */
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| 208 | #define PCAN_IR_WUI (1<<4) /* Wake-up interrupt */
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| 209 | #define PCAN_IR_DOI (1<<3) /* Data-overrun interrupt */
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| 210 | #define PCAN_IR_EI (1<<2) /* Error interrupt */
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| 211 | #define PCAN_IR_TI (1<<1) /* Transmit interrupt */
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| 212 | #define PCAN_IR_RI (1<<0) /* Receive interrupt */
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| 213 |
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| 214 | /* Interrupt enable register bits */
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| 215 | #define PCAN_IER_BEIE (1<<7) /* Bus-eror interrupt enable */
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| 216 | #define PCAN_IER_ALIE (1<<6) /* Arbitration lost interrupt enable */
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| 217 | #define PCAN_IER_EPIE (1<<5) /* Error-passive interrupt enable */
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| 218 | #define PCAN_IER_WUIE (1<<4) /* Wake-up interrupt enable */
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| 219 | #define PCAN_IER_DOIE (1<<3) /* Data-overrun interrupt enable */
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| 220 | #define PCAN_IER_EIE (1<<2) /* Error warning interrupt enable */
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| 221 | #define PCAN_IER_TIE (1<<1) /* Transmit interrupt enable */
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| 222 | #define PCAN_IER_RIE (1<<0) /* Receive interrupt enable */
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| 223 |
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| 224 | /* Clock divider register bits */
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| 225 | #define PCAN_CDR_PCAN (1<<7) /* Enable PCAN mode */
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| 226 | #define PCAN_CDR_CBP (1<<6) /* Enable Rx input comparator bypass */
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| 227 | #define PCAN_CDR_RXINTEN (1<<5) /* Enable RXINT output at TX1 */
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| 228 | #define PCAN_CDR_CLKOFF (1<<3) /* Disable clock output */
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| 229 |
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| 230 | /* Bit definitions for Rx/Tx Frame info */
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| 231 | #define PCAN_FINFO_FF (1<<7) /* Frame format bit */
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| 232 | #define PCAN_FINFO_EFF (1<<7) /* Extended frame indication */
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| 233 | #define PCAN_FINFO_RTR (1<<6) /* RTR frame bit */
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| 234 | #define PCAN_FINFO_DLC_MASK (0x0f) /* Data length code mask */
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| 235 |
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| 236 |
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| 237 |
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| 238 | /*
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| 239 | * BasicCAN, PeliCAN common definitions.
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| 240 | */
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| 241 |
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| 242 | /* Values of acceptance code/mask registers */
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| 243 | #define ACM_ALL word_from_bytes(0x00,0xff) /* accept all ids */
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| 244 |
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| 245 | /* Values of output control register */
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| 246 | #define OCR_PUSHPULL 0xfa /* push/pull */
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| 247 |
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| 248 | /* Admissable bus timing values (BTR1=msb, BTR0=lsb) */
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| 249 | #ifdef OSC_16MHZ /* if using a 16 MHz oscillator */
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| 250 | #define BTR_1MB 0x2300 /* 1 MBaud */
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| 251 | #if 0
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| 252 | #define BTR_1MB 0x1400 /* 1 MBaud */ /* The better value */
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| 253 | #endif
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| 254 | #define BTR_800KB 0x2500 /* 800 KBaud */
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| 255 | #define BTR_500KB 0x1c00 /* 500 KBaud */
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| 256 | #define BTR_250KB 0x1c01 /* 250 KBaud */
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| 257 | #define BTR_125KB 0x1c03 /* 125 KBaud */
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| 258 | #define BTR_100KB 0x34c7 /* 100 KBaud */
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| 259 | #define BTR_62_5KB 0xbac7 /* 62.5 KBaud */
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| 260 | #define BTR_50KB 0x34cf /* 50 KBaud */
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| 261 | #define BTR_20KB 0x7fcf /* 20 KBaud */
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| 262 | #define BTR_10KB 0x7fdf /* 10 KBaud */
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| 263 | #endif
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| 264 |
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| 265 | /* Admissable values in clock divider register */
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| 266 | #ifdef OSC_16MHZ /* if using a 16 MHz oscillator */
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| 267 | #define CDR_16MHZ 0x07 /* 16 MHz output */
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| 268 | #define CDR_8MHZ 0x00 /* 8 MHz output (division by 2) */
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| 269 | #define CDR_4MHZ 0x01 /* 4 MHz output (division by 4) */
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| 270 | #define CDR_2MHZ 0x03 /* 2 MHz output (division by 8) */
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| 271 | #endif
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| 272 |
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| 273 | /*-------- Gloal variables in bcan.c ---------------------------------------*/
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| 274 |
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| 275 | /* Indicates that we are using SJA1000 in pelican mode */
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| 276 | extern short pcan_mode;
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| 277 |
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| 278 | /* ----------------------- BulkBuffer-Stuff --------------------------*/
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| 279 | /* must be greater than length of biggest message type!!! */
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| 280 | #define BULK_LEFT_FREE 14
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| 281 |
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| 282 | #define DEFAULT_MAX_BULK_BUF_BYTE_COUNT MSGLEN
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| 283 | /* we need a minimum size of bulk buffer to generate messages */
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| 284 | /* of a certain format (not bounde, but allocated buffer!) */
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| 285 | /* to satisfy the message-handling inside the asm isr */
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| 286 | #define DEFAULT_MIN_BULK_BUF_BYTE_COUNT 20
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| 287 | #define DEFAULT_BULK_PREALLOC_COUNT 20
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| 288 |
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| 289 | /* Timer value for elapsed (e.g.) ms to determine */
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| 290 | /* if it is time to send current BulkBuffer. Will */
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| 291 | /* be maintained in timer.c */
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| 292 | extern LWORD_t bulkBufTim;
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| 293 |
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| 294 | void configBulkBuffer(unsigned short, unsigned char, unsigned char);
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| 295 |
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| 296 | /* ----------------------- SniffBuffer-Stuff --------------------------*/
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| 297 | /* must be greater than length of biggest message type!!! */
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| 298 | #define SNIFF_LEFT_FREE 26
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| 299 |
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| 300 | #define DEFAULT_MAX_SNIFF_BUF_BYTE_COUNT MSGLEN
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| 301 | /* we need a minimum size of sniff buffer to generate messages */
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| 302 | /* of a certain format (not bounde, but allocated buffer!) */
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| 303 | /* to satisfy the message-handling inside the asm isr */
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| 304 | #define DEFAULT_MIN_SNIFF_BUF_BYTE_COUNT 20
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| 305 | #define DEFAULT_SNIFF_PREALLOC_COUNT 20
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| 306 |
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| 307 | /* Timer value for elapsed (e.g.) ms to determine */
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| 308 | /* if it is time to send current SniffBuffer. Will */
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| 309 | /* be maintained in timer.c */
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| 310 | extern LWORD_t sniffBufTim;
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| 311 |
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| 312 | void configSniffBuffer(unsigned short, unsigned char, unsigned char);
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| 313 | void configSniffBufferEcho(unsigned short);
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| 314 | /* valid values for echo2sniff, configured by configSniffBufferEcho: */
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| 315 | #define SNIFF_ECHO_FROM_CANLOOK (1 << 0)
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| 316 | #define SNIFF_ECHO_FROM_PLAINQ (1 << 1)
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| 317 | #define SNIFF_ECHO_FROM_FASTQ (1 << 2)
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| 318 | #define SNIFF_RX_FROM_CAN (1 << 3)
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| 319 |
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| 320 |
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| 321 | /* message-commands inside sniff-message */
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| 322 | #define SNIFF_MS_ECHO_FROM_PLAIN_STD 3
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| 323 | #define SNIFF_MS_ECHO_FROM_PLAIN_XTD 4 /* not yet used */
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| 324 | #define SNIFF_MS_ECHO_FROM_FAST_STD 5
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| 325 | #define SNIFF_MS_ECHO_FROM_FAST_XTD 6
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| 326 | #define SNIFF_MS_ECHO_FROM_CANLOOK_STD 7
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| 327 | #define SNIFF_MS_ECHO_FROM_CANLOOK_XTD 8
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| 328 | #define SNIFF_MS_CAN_RX_STD 9
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| 329 | #define SNIFF_MS_CAN_RX_XTD 10
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| 330 | #define SNIFF_MS_MSG_LOST 0x80
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| 331 | #define SNIFF_MS_UNKNOWN 0xff
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| 332 |
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| 333 |
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| 334 | /* -----------------------Busload-Statistic-Stuff --------------------------*/
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| 335 | #define BUS_LOAD_STAT_SEND_TO_HOST (1 << 0)
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| 336 | #define BUS_LOAD_STAT_INTEGR_TIME_ELAPSED (1 << 1)
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| 337 | #define BUS_LOAD_STAT_ENABLED (1 << 7)
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| 338 |
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| 339 | #define BUS_LOAD_REQUEST_ALL 0
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| 340 | #define BUS_LOAD_REQUEST_STD 1
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| 341 | #define BUS_LOAD_REQUEST_XTD 2
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| 342 | #define BUS_LOAD_REQUEST_RX 3
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| 343 | #define BUS_LOAD_REQUEST_TX 4
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| 344 |
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| 345 | void resetBusLoad(void);
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| 346 | void configBusLoad(WORD_t, BYTE_t);
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| 347 | void sendBusLoadToHost(void);
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| 348 | void busLoadUpdate(void);
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| 349 | void checkBusLoadStatistic(void);
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| 350 |
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| 351 | void resetBusLoadSniff(void);
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| 352 | void configBusLoadSniff(WORD_t, BYTE_t);
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| 353 | void sendBusLoadToHostSniff(void);
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| 354 | void busLoadUpdateSniff(void);
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| 355 | void checkBusLoadStatisticSniff(void);
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| 356 |
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| 357 | /*-------- Functions in bcan.c ---------------------------------------------*/
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| 358 |
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| 359 | /* Switch to bus-on state */
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| 360 | extern void buson_bcan(void);
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| 361 |
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| 362 | /* Reset: Switch to bus-off state */
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| 363 | extern void busoff_bcan(void);
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| 364 |
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| 365 | /* Set bus timing registers (assumed state: bus-off) */
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| 366 | extern void write_btr_bcan(WORD_t);
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| 367 |
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| 368 | /* Set error waring limit */
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| 369 | void write_ewl_bcan( BYTE_t ewl);
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| 370 |
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| 371 | /* Control bus-error reporting */
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| 372 | void switch_berr_bcan( BYTE_t state);
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| 373 |
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| 374 | /* provide access to berrs_to_go outside bcan.c */
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| 375 | BYTE_t getBerrsToGo(void);
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| 376 |
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| 377 | /* Control listen only mode */
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| 378 | void switch_lom_bcan( BYTE_t state);
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| 379 |
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| 380 | /* Control self test mode */
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| 381 | void switch_stm_bcan( BYTE_t state);
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| 382 |
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| 383 | /* Set hardware acceptance filter */
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| 384 | extern void write_acm_bcan(WORD_t);
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| 385 |
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| 386 | /* Set extended hardware acceptance filter */
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| 387 | void write_ext_acm_bcan(int mode, LWORD_t ac, LWORD_t am);
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| 388 |
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| 389 | /* Abort current transmission */
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| 390 | extern void sendabort_bcan(void);
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| 391 |
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| 392 | /* Flush the transmit queue. */
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| 393 | extern void flush_tx_bcan(void);
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| 394 |
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| 395 | /* Initialize the BCAN controller. The controller is left in the bus-off
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| 396 | state. To start communication buson_bcan() must be called.
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| 397 | All interrupt sources are accepted. All messages pass the acceptance
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| 398 | filter. The bus timing and the clock divider registers are initialized
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| 399 | with the parameters to the function. */
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| 400 | extern void init_bcan(WORD_t, WORD_t, WORD_t, WORD_t);
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| 401 |
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| 402 | /* Service of BCAN message pool -- to be called cyclically */
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| 403 | extern void serv_bcan(void);
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| 404 |
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| 405 | /* Interrupt service for PCA82C200. */
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| 406 | extern void isr_bcan(void);
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| 407 | #ifdef ASSHACK
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| 408 | extern void a_isr_bcan(void);
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| 409 | extern void a_isr_bcan_end(void);
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| 410 | #endif
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| 411 |
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| 412 |
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| 413 | /* Request to send a CAN message: Fill the transmit buffer of the
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| 414 | CAN chip and issue a transmit request.
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| 415 | Return values: 1 okay, transmit request accepted by controller
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| 416 | 0 remote request successful
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| 417 | -1 transmit request failed (no buffer, no mem)
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| 418 | */
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| 419 | extern int sendreq_bcan(
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| 420 | int, /* transmit request specifier */
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| 421 | WORD_t, /* request id */
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| 422 | WORD_t, /* descriptor (id, rtr, dlc) */
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| 423 | BYTE_t * /* data bytes */
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| 424 | );
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| 425 |
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| 426 | #ifdef __cplusplus
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| 427 | }
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| 428 | #endif
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| 429 |
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| 430 | #endif /* !bcan_DEFINED */
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