| 1 | /*-----------------------------------------------------------------------------
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| 2 | dpm.h -- Linux driver of DPM interface to VMOD
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| 3 |
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| 4 | Copyright (c) 1996 JANZ Computer AG
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| 5 | All Rights Reserved
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| 6 |
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| 7 | Created 96/01/23 by Stefan Althoefer
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| 8 |
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| 9 | Version 1.12 of 96/09/27
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| 10 |
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| 11 | This file is for both, the "dpm" and the "dpmw" driver.
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| 12 | The only difference, besides the names of the driver functions, are the in
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| 13 | the INKERNEL structures. But these are not visible to the user.
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| 14 |
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| 15 | -----------------------------------------------------------------------------*/
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| 16 |
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| 17 | #ifndef __INCdpmh
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| 18 | #define __INCdpmh
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| 19 |
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| 20 | #ifdef __cplusplus
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| 21 | extern "C" {
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| 22 | #endif
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| 23 |
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| 24 | #include "defs.h"
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| 25 | #include "vmod.h"
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| 26 |
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| 27 | /* Max. Count of Devices for the dpm driver. */
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| 28 | /*#define DPM_MAJOR_NUMBER 57 */
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| 29 | #define MAX_BOARDS 16 /* max. # of boards supported */
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| 30 | #define MAX_MODUL_BOARDS 4 /* max. # of modules supported */
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| 31 | /* with one board */
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| 32 | #define MAX_DPM_DEV (MAX_BOARDS * MAX_MODUL_BOARDS)
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| 33 |
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| 34 | #define FAST_QUEUE '\0' /* flag for fast queue */
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| 35 | #define PLAIN_QUEUE '\1' /* flag for normal queue */
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| 36 |
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| 37 | /* Data type of messages */
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| 38 | #define MSGLEN 252 /* Maximum length of a message */
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| 39 | #define MSGHDLEN 4 /* Length of message head */
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| 40 |
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| 41 | #define ICAN2 1
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| 42 | #define ICAN3 2
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| 43 |
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| 44 | /* -*-Struct-*-
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| 45 | *
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| 46 | * Message - local message buffer for standard host interface
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| 47 | *
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| 48 | * This structure stores a message to be send to or received from
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| 49 | * a VMOD-ICAN module via the standard host interface.
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| 50 | *
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| 51 | * <cmd> is a 8 bit command specifier. Refer to the VMOD-ICAN manual
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| 52 | * to find out which services are provided by the different <cmd>
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| 53 | * specifiers. The data length to be transfered is stored in <len>, thereby
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| 54 | * <len> specifies how many bytes of the vector <data> are valid. The data
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| 55 | * have to be interpreted by means of <cmd>.
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| 56 | *
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| 57 | * At most MSGLEN bytes can be stored in a message. MSGLEN is 252 bytes
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| 58 | * for all current VMOD-ICAN modules.
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| 59 | */
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| 60 | typedef struct {
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| 61 | BYTE_t cmd; /* Message specifier */
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| 62 | BYTE_t gap1;
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| 63 | WORD_t len; /* Message length (<= MSGLEN) */
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| 64 | BYTE_t data[MSGLEN]; /* Data array of Message */
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| 65 | } Message;
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| 66 |
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| 67 |
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| 68 | /* -*-Struct-*-
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| 69 | *
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| 70 | * FastMessage - local message buffer for fast host interface
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| 71 | *
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| 72 | * This structure stores a CANbus message to be send to or received from
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| 73 | * a VMOD-ICAN modules fast interface.
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| 74 | *
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| 75 | * <cmd> is a 8 bit service multiplexor. Currently only <cmd>='0' is used.
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| 76 | *
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| 77 | * Through <data> the actual CANbus message is transfered if <cmd> equals '0'.
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| 78 | * The first two bytes store the message descriptor, that contains the
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| 79 | * ID, RTR-flag and CANbus data length code (DLC), the remaining bytes store
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| 80 | * the CANbus data bytes.
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| 81 | *
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| 82 | * .CS
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| 83 | * data[0] = ID/8;
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| 84 | * data[1] = 32(ID%8) + 16RTR + DLC
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| 85 | * data[2] = CAN BYTE 1
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| 86 | * data[:] = :
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| 87 | * data[9] = CAN BYTE 8
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| 88 | * data[10] = unused
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| 89 | * data[:] = :
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| 90 | * data[13] = unused
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| 91 | * .CE
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| 92 | *
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| 93 | */
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| 94 | typedef struct {
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| 95 | BYTE_t unused;
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| 96 | BYTE_t cmd; /* Service specifier */
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| 97 | BYTE_t data[14]; /* Data array */
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| 98 | } FastMessage;
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| 99 |
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| 100 |
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| 101 |
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| 102 | /*** DPM: Special Driver Functions (Driver management) *********************/
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| 103 | #ifdef nodef
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| 104 |
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| 105 | /* Create the dpm driver. */
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| 106 | extern STATUS dpmDrv(void);
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| 107 |
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| 108 | /* Remove the dpm driver from the system. */
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| 109 | extern STATUS dpmDrvRemove(void);
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| 110 |
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| 111 | /* Add a dpm device. */
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| 112 | extern STATUS dpmDevCreate(
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| 113 | int modno,
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| 114 | UINT baddr
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| 115 | );
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| 116 |
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| 117 | /* Delete a dpm device. */
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| 118 | extern STATUS dpmDevDelete(
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| 119 | const char *name
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| 120 | );
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| 121 |
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| 122 | /* Main ioctl function. */
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| 123 | extern dpmIoctl(
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| 124 | int modno,
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| 125 | int cmd,
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| 126 | int arg
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| 127 | );
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| 128 |
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| 129 | /* interrupt function. */
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| 130 | extern void dpmInt (int modno);
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| 131 |
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| 132 |
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| 133 | /*** DPMW: Special Driver Functions (Driver management) *********************/
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| 134 |
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| 135 | /* Create the dpmw driver. */
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| 136 | extern STATUS dpmwDrv(void);
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| 137 |
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| 138 | /* Remove the dpmw driver from the system. */
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| 139 | extern STATUS dpmwDrvRemove(void);
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| 140 |
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| 141 | /* Add a dpmw device. */
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| 142 | extern STATUS dpmwDevCreate(
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| 143 | const char *name,
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| 144 | int modno,
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| 145 | UINT baddr,
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| 146 | int vector,
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| 147 | int level
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| 148 | );
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| 149 |
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| 150 | /* Delete a dpmw device. */
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| 151 | extern STATUS dpmwDevDelete(
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| 152 | const char *name
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| 153 | );
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| 154 | #endif
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| 155 |
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| 156 | /*** IOCTL commands *****************************************************/
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| 157 | #define WOS 0x8000 /* offset into user fuction codes */
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| 158 |
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| 159 | /* getstat: */
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| 160 | #define DPM_READ_MBOX (128 + WOS) /* function code READ */
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| 161 | #define DPM_COPY_FROM (129 + WOS) /* copy data from dpm */
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| 162 | #define DPM_READ_FAST_MBOX (130 + WOS) /* function code READ FAST */
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| 163 |
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| 164 | /* putstat: */
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| 165 | #define DPM_WRITE_MBOX (528 + WOS) /* function code WRITE mid prio */
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| 166 | #define DPM_WRITE_MBOX_HI (539 + WOS) /* function code WRITE high prio*/
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| 167 | #define DPM_WRITE_MBOX_LOW (540 + WOS) /* function code WRITE low prio */
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| 168 | #define DPM_COPY_TO (529 + WOS) /* copy data to dpm */
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| 169 | #define DPM_DEL_SIGNAL (530 + WOS) /* delete signal entry */
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| 170 | #define DPM_SET_SIGNAL (531 + WOS) /* set signal entry */
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| 171 | #define DPM_RESET (532 + WOS) /* reset the module */
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| 172 | #define DPM_INIT_NEW_HOSTIF (533 + WOS) /* init new hostif */
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| 173 | #define DPM_INIT_NEW_HOSTIF_PRIO (545 + WOS) /* init new hostif (priorized) */
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| 174 | #define DPM_SET_SEM (534 + WOS) /* create semaphor for read */
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| 175 | #define DPM_INIT_FAST_CAN (535 + WOS) /* init fast CAN access */
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| 176 | #define DPM_INIT_FAST_CAN_PRIO (551 + WOS) /* init fast CAN access */
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| 177 | #define DPM_WRITE_FAST_CAN (536 + WOS) /* send trougth fast interface */
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| 178 | #define DPM_WRITE_FAST_CAN_PRIO (552 + WOS) /* send trougth prioritized fast interface */
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| 179 |
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| 180 | #define DPM_DEINIT_FAST_CAN (537 + WOS) /* deinit fast CAN access */
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| 181 | #define DPM_DEL_SEM (538 + WOS) /* delete semaphor for read */
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| 182 | /* (539 + WOS) see above! */
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| 183 | /* (540 + WOS) see above! */
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| 184 | #define DPM_INIT_ID_MSG_Q_TABLE (541 + WOS) /* allocates memory for table, */
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| 185 | /* where message-queue-Ids for */
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| 186 | /* fast can access are stored */
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| 187 | #define DPM_DEINIT_ID_MSG_Q_TABLE (542 + WOS) /* deallocates memory for table */
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| 188 | #define DPM_ADD_ID_TO_MSG_Q_TABLE (543 + WOS) /* adds queue entry to ID-table */
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| 189 | #define DPM_REM_ID_FROM_MSG_Q_TABLE (544 + WOS) /* removes entry from ID-table */
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| 190 | /* (545 + WOS) see above! */
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| 191 | #define DPM_INIT_L2_ROUTING (546 + WOS) /* inits the Layer2 routing cap */
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| 192 | #define DPM_DEINIT_L2_ROUTING (547 + WOS) /* deinits Layer2 routing cap */
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| 193 | #define DPM_INIT_ROUTE_ID (548 + WOS) /* lets _one_ ID being routable */
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| 194 | #define DPM_ADD_ROUTE_TO_ID (549 + WOS) /* adds _one_ routing way to ID */
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| 195 | #define DPM_MAP_FD_TO_MOD (550 + WOS) /* map the fd to board/module */
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| 196 |
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| 197 | #define DPM_DEV_CREATE (600 + WOS) /* WINDOWS specific ioctl function code */
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| 198 | #define DPM_DEV_DELETE (601 + WOS) /* deletes device from slot */
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| 199 | #define DPM_READ_INTCOUNT (602 + WOS)
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| 200 | #define DPM_REGISTER_APC (603 + WOS) /* Register APC function */
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| 201 | #define DPM_TPU_REQ (604 + WOS) /* initiates TPU request IR */
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| 202 | #define DPM_OBJDIC_REQ (605 + WOS) /* access to object dict. */
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| 203 |
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| 204 | #define DPM_DRV_IDVERS (606 + WOS) /* get driver version */
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| 205 | #define DPM_WRITE_PP (607 + WOS) /* write CANopen process picture */
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| 206 | #define DPM_READ_PP (608 + WOS) /* read CANopen process picture */
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| 207 |
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| 208 |
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| 209 | struct signal_dpm {
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| 210 | int task_id;
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| 211 | int signal_code;
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| 212 | unsigned char *param_addr;
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| 213 | };
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| 214 |
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| 215 | struct dpm_copy_desc {
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| 216 | unsigned int memory;
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| 217 | unsigned int dpm;
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| 218 | int len;
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| 219 | };
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| 220 |
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| 221 | struct dpm_rw_can_desc {
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| 222 | int rval;
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| 223 | Message *pm;
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| 224 | };
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| 225 |
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| 226 | struct dpm_new_hostif_desc {
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| 227 | int fromhost_len;
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| 228 | int tohost_len;
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| 229 | };
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| 230 |
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| 231 | struct dpm_new_hostif_desc_prio {
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| 232 | int fromhost_hi_len;
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| 233 | int fromhost_low_len;
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| 234 | int fromhost_len;
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| 235 | int tohost_len;
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| 236 | };
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| 237 |
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| 238 | struct dpm_fast_can_desc {
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| 239 | int fromhost_len;
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| 240 | int tohost_len;
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| 241 | /* MSG_Q_ID read_queue; */
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| 242 | };
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| 243 |
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| 244 | struct dpm_fast_can_desc_prio {
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| 245 | int numOfPrioQueues;
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| 246 | int fromhost_len;
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| 247 | int tohost_len;
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| 248 | /* MSG_Q_ID read_queue; */
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| 249 | };
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| 250 |
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| 251 | struct dpm_write_fast_can_desc {
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| 252 | int rval;
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| 253 | FastMessage *pm;
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| 254 | };
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| 255 |
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| 256 | struct dpm_write_fast_can_desc_prio {
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| 257 | int rval;
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| 258 | int prioQueue;
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| 259 | FastMessage *pm;
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| 260 | };
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| 261 |
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| 262 | struct dpm_fast_can_desc_win {
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| 263 | int fromhost_len;
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| 264 | int tohost_len;
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| 265 | int fkt_addr;
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| 266 | };
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| 267 |
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| 268 | struct dpm_msg_q_id_desc {
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| 269 | unsigned short id;
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| 270 | /* MSG_Q_ID target_queue; */
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| 271 | };
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| 272 |
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| 273 | struct dpm_layer_2_routing_desc {
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| 274 | int rval;
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| 275 | int Id;
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| 276 | int max_routes;
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| 277 | int source_Id;
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| 278 | int dest_Id;
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| 279 | int dest_Board;
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| 280 | int dest_Modul;
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| 281 | };
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| 282 |
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| 283 | struct io_args {
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| 284 | int modno; /* slot of interesing module */
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| 285 | int arg; /* place of some arguments */
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| 286 | };
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| 287 |
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| 288 |
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| 289 | struct dpm_dev_create_desc {
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| 290 | int modno;
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| 291 | };
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| 292 |
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| 293 | struct dpm_objdic_desc {
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| 294 | int objdic_index;
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| 295 | int objdic_subindex;
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| 296 | int access_type;
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| 297 | void *entry_structure;
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| 298 | };
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| 299 |
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| 300 | struct dpm_readpp_desc {
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| 301 | int dataSize;
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| 302 | int offset;
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| 303 | int dataValid;
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| 304 | char *buffer;
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| 305 | };
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| 306 |
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| 307 | struct dpm_writepp_desc {
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| 308 | int dataSize;
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| 309 | int offset;
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| 310 | char *buffer;
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| 311 | };
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| 312 |
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| 313 | #define TS_TO_HOST 1 /* read modules timestamp counter */
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| 314 | /* of last SYNC message */
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| 315 | #define TS_TO_MODULE 0 /* synchronizing module by writing timestamp */
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| 316 |
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| 317 |
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| 318 | #ifdef INKERNEL
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| 319 | /************************************************************************/
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| 320 | /* DEFINES */
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| 321 | /************************************************************************/
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| 322 |
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| 323 | #define MAXNDEV 1 /* I/O-channel per module */
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| 324 | #define BOARDTYP (1<<7) /* d7=1 VMOD-IG, d7=0 VMOD-IO */
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| 325 | #define I_ENABLE 1
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| 326 |
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| 327 | /* MICAN3 */
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| 328 | #define DPM_PAGEWIDTH 256 /* ICAN3 */
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| 329 |
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| 330 | #ifdef BIG_ENDIAN
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| 331 | struct dpmw { /* structure for BIG_ENDIAN */
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| 332 | unsigned char unused;
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| 333 | unsigned char spec; /* message specifier */
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| 334 | unsigned char len_l; /* data length low byte */
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| 335 | unsigned char len_h; /* data length high byte */
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| 336 | unsigned char data[MSGLEN]; /* raw data */
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| 337 | unsigned char page_sel; /* page selector */
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| 338 | unsigned char gap1;
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| 339 | unsigned char intgen; /* wr: generate inter. on ICAN3 */
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| 340 | /* rd: clear MODULbus interrupt */
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| 341 | unsigned char gap2;
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| 342 | unsigned char reset; /* generate reset on ICAN3 */
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| 343 | unsigned char gap3;
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| 344 | unsigned char tpureq; /* signal to tpu on ICAN3 */
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| 345 | };
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| 346 | #endif
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| 347 |
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| 348 | #ifdef LITTLE_ENDIAN
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| 349 | struct dpmw { /* structure for LITTLE_ENDIAN */
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| 350 | unsigned char spec; /* message specifier */
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| 351 | unsigned char unused;
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| 352 | unsigned char len_h; /* data length high byte */
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| 353 | unsigned char len_l; /* data length low byte */
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| 354 | unsigned char data[MSGLEN]; /* raw data */
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| 355 | unsigned char gap1;
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| 356 | unsigned char page_sel; /* page selector */
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| 357 | unsigned char gap2;
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| 358 | unsigned char intgen; /* wr: generate inter. on ICAN3 */
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| 359 | /* rd: clear MODULbus interrupt */
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| 360 | unsigned char gap3;
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| 361 | unsigned char reset; /* generate reset on ICAN3 */
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| 362 | unsigned char gap4;
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| 363 | unsigned char tpureq; /* signal to tpu on ICAN3 */
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| 364 | };
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| 365 | #endif
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| 366 |
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| 367 |
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| 368 | #define START_BUFF 9 /* first free page within DPM */
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| 369 |
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| 370 | /* New stylish host interface */
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| 371 |
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| 372 | #ifdef BIG_ENDIAN
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| 373 | struct dpmw_desc {
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| 374 | unsigned char control; /* control byte */
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| 375 | unsigned char buffer; /* buffer pointer */
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| 376 | };
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| 377 | #endif
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| 378 |
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| 379 | #ifdef LITTLE_ENDIAN
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| 380 | struct dpmw_desc {
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| 381 | unsigned char buffer; /* buffer pointer */
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| 382 | unsigned char control; /* control byte */
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| 383 | };
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| 384 | #endif
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| 385 |
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| 386 | #define DPM_DESC_VALID (1<<7)
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| 387 | #define DPM_DESC_WRAP (1<<6)
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| 388 | #define DPM_DESC_INTR (1<<5)
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| 389 | #define DPM_DESC_IVALID (1<<4)
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| 390 | #define DPM_DESC_LEN (7<<0)
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| 391 |
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| 392 |
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| 393 | /* Fast dpmqueue host interface */
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| 394 |
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| 395 | #define FDPMQUEUE_LEN 14 /* data elements in each buffer */
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| 396 |
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| 397 |
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| 398 | #ifdef BIG_ENDIAN
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| 399 | struct fdpmw_desc {
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| 400 | unsigned char control;
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| 401 | unsigned char spec;
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| 402 | unsigned char data[FDPMQUEUE_LEN];
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| 403 | };
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| 404 | #endif
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| 405 |
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| 406 | #ifdef LITTLE_ENDIAN
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| 407 | struct fdpmw_desc {
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| 408 | unsigned char spec;
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| 409 | unsigned char control;
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| 410 | unsigned char data[FDPMQUEUE_LEN];
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| 411 | };
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| 412 | #endif
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| 413 |
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| 414 | #define FDPM_DESC_VALID (1<<7)
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| 415 | #define FDPM_DESC_WRAP (1<<6)
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| 416 | #define FDPM_DESC_IVALID (1<<4)
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| 417 |
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| 418 | /* Definition of fast-queue-fromhost priorization */
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| 419 | #define FDPMQUEUE_FROMHOST_NO_INIT 0
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| 420 | #define FDPMQUEUE_FROMHOST_1_PRIO 1
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| 421 | #define FDPMQUEUE_FROMHOST_N_PRIO 3
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| 422 |
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| 423 | #ifdef BIG_ENDIAN
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| 424 | #define DPMW_MSYNC_LOCL_ADDR 0x1
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| 425 | #define DPMW_MSYNC_PEER_ADDR 0x0
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| 426 | #define DPMW_TARGET_RUN_ADDR 0x2
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| 427 | #define TIME_STAMP_0_ADDR 0x10
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| 428 | #define TIME_STAMP_1_ADDR 0x11
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| 429 | #define TIME_STAMP_2_ADDR 0x12
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| 430 | #define TIME_STAMP_3_ADDR 0x13
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| 431 | #endif
|
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| 432 |
|
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| 433 | #ifdef LITTLE_ENDIAN
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| 434 | #define DPMW_MSYNC_LOCL_ADDR 0x0
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| 435 | #define DPMW_MSYNC_PEER_ADDR 0x1
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| 436 | #define DPMW_TARGET_RUN_ADDR 0x3
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| 437 | #define TIME_STAMP_0_ADDR 0x12
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| 438 | #define TIME_STAMP_1_ADDR 0x13
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| 439 | #define TIME_STAMP_2_ADDR 0x10
|
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| 440 | #define TIME_STAMP_3_ADDR 0x11
|
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| 441 | #endif
|
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| 442 |
|
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| 443 | /* end of defined MICAN3 */
|
|---|
| 444 |
|
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| 445 | /* MICAN2 */
|
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| 446 |
|
|---|
| 447 | #ifdef BIG_ENDIAN
|
|---|
| 448 | struct dpm { /* structure for MOTOROLA type */
|
|---|
| 449 | unsigned char page_sel; /* page selector */
|
|---|
| 450 | unsigned char unused;
|
|---|
| 451 | unsigned char intgen; /* wr: generate inter. on ICAN2 */
|
|---|
| 452 | /* rd: clear MODULbus interrupt */
|
|---|
| 453 | unsigned char spec; /* message specifier */
|
|---|
| 454 | unsigned char reset; /* generate reset on ICAN2 */
|
|---|
| 455 | unsigned char len_l; /* data length low byte */
|
|---|
| 456 | unsigned char gap0;
|
|---|
| 457 | unsigned char len_h; /* data length high byte */
|
|---|
| 458 | unsigned char gap_1;
|
|---|
| 459 | unsigned char data[MSGLEN * 2]; /* raw data */
|
|---|
| 460 | };
|
|---|
| 461 | #endif
|
|---|
| 462 |
|
|---|
| 463 | #ifdef LITTLE_ENDIAN
|
|---|
| 464 | struct dpm { /* structure for INTEL-LIKE type */
|
|---|
| 465 | unsigned char unused;
|
|---|
| 466 | unsigned char page_sel; /* page selector */
|
|---|
| 467 | unsigned char spec; /* message specifier */
|
|---|
| 468 | unsigned char intgen; /* wr: generate inter. on ICAN2 */
|
|---|
| 469 | /* rd: clear MODULbus interrupt */
|
|---|
| 470 | unsigned char len_l; /* data length low byte */
|
|---|
| 471 | unsigned char reset; /* generate reset on ICAN2 */
|
|---|
| 472 | unsigned char len_h; /* data length high byte */
|
|---|
| 473 | unsigned char gap0;
|
|---|
| 474 | unsigned char data[MSGLEN * 2]; /* raw data */
|
|---|
| 475 | unsigned char gap_1;
|
|---|
| 476 | };
|
|---|
| 477 | #endif
|
|---|
| 478 |
|
|---|
| 479 | /* New stylish host interface */
|
|---|
| 480 |
|
|---|
| 481 | #ifdef BIG_ENDIAN
|
|---|
| 482 | struct dpm_desc {
|
|---|
| 483 | unsigned char gap1;
|
|---|
| 484 | unsigned char control; /* control byte */
|
|---|
| 485 | unsigned char gap2;
|
|---|
| 486 | unsigned char buffer; /* buffer pointer */
|
|---|
| 487 | };
|
|---|
| 488 | #endif
|
|---|
| 489 |
|
|---|
| 490 | #ifdef LITTLE_ENDIAN
|
|---|
| 491 | struct dpm_desc {
|
|---|
| 492 | unsigned char control; /* control byte */
|
|---|
| 493 | unsigned char gap1;
|
|---|
| 494 | unsigned char buffer; /* buffer pointer */
|
|---|
| 495 | unsigned char gap2;
|
|---|
| 496 | };
|
|---|
| 497 | #endif
|
|---|
| 498 |
|
|---|
| 499 | #define DPM_DESC_VALID (1<<7)
|
|---|
| 500 | #define DPM_DESC_WRAP (1<<6)
|
|---|
| 501 | #define DPM_DESC_INTR (1<<5)
|
|---|
| 502 | #define DPM_DESC_IVALID (1<<4)
|
|---|
| 503 | #define DPM_DESC_LEN (7<<0)
|
|---|
| 504 |
|
|---|
| 505 |
|
|---|
| 506 | /* Fast dpmqueue host interface */
|
|---|
| 507 |
|
|---|
| 508 | #define FDPMQUEUE_LEN 14
|
|---|
| 509 |
|
|---|
| 510 | #ifdef BIG_ENDIAN
|
|---|
| 511 | struct fdpm_desc {
|
|---|
| 512 | unsigned char gap1;
|
|---|
| 513 | unsigned char control;
|
|---|
| 514 | unsigned char gap2;
|
|---|
| 515 | unsigned char spec;
|
|---|
| 516 | unsigned char gap3;
|
|---|
| 517 | unsigned char data[2*FDPMQUEUE_LEN-1];
|
|---|
| 518 | };
|
|---|
| 519 | #endif
|
|---|
| 520 |
|
|---|
| 521 | #ifdef LITTLE_ENDIAN
|
|---|
| 522 | struct fdpm_desc {
|
|---|
| 523 | unsigned char control;
|
|---|
| 524 | unsigned char gap1;
|
|---|
| 525 | unsigned char spec;
|
|---|
| 526 | unsigned char gap2;
|
|---|
| 527 | unsigned char data[2*FDPMQUEUE_LEN-1];
|
|---|
| 528 | unsigned char gap3;
|
|---|
| 529 | };
|
|---|
| 530 | #endif
|
|---|
| 531 |
|
|---|
| 532 | #ifdef BIG_ENDIAN
|
|---|
| 533 | #define DPM_MSYNC_LOCL_ADDR 0x3
|
|---|
| 534 | #define DPM_MSYNC_PEER_ADDR 0x1
|
|---|
| 535 | #define DPM_TARGET_RUN_ADDR 0x5
|
|---|
| 536 | #endif
|
|---|
| 537 |
|
|---|
| 538 | #ifdef LITTLE_ENDIAN
|
|---|
| 539 | #define DPM_MSYNC_LOCL_ADDR 0x2
|
|---|
| 540 | #define DPM_MSYNC_PEER_ADDR 0x0
|
|---|
| 541 | #define DPM_TARGET_RUN_ADDR 0x4
|
|---|
| 542 | #endif
|
|---|
| 543 |
|
|---|
| 544 | /* swap macro for MOTOROLA <-> INTEL access on ICAN3 */
|
|---|
| 545 | #ifdef LITTLE_ENDIAN
|
|---|
| 546 | #define SWAP_WORD(x) (((x & 0xff) << 8) | (0xff & (x >> 8)))
|
|---|
| 547 | #endif
|
|---|
| 548 | #ifdef BIG_ENDIAN
|
|---|
| 549 | #define SWAP_WORD(x) (x)
|
|---|
| 550 | #endif
|
|---|
| 551 |
|
|---|
| 552 | #endif /* #ifdef INKERNEL */
|
|---|
| 553 |
|
|---|
| 554 | #define TOHOST_DPM_QUEUE_PAGE 5 /* tohost_dpmqueue page */
|
|---|
| 555 | #define FROMHOST_DPM_QUEUE_PAGE 6 /* fromhost_dpmqueue page prio mid */
|
|---|
| 556 | #define FROMHOST_DPM_QUEUE_HI_PAGE 7 /* fromhost_dpmqueue page prio high */
|
|---|
| 557 | #define FROMHOST_DPM_QUEUE_LOW_PAGE 8 /* fromhost_dpmqueue page prio low */
|
|---|
| 558 | #define START_BUFF 9 /* first free page within DPM */
|
|---|
| 559 |
|
|---|
| 560 |
|
|---|
| 561 | /*----------routing specific defines ------------------------*/
|
|---|
| 562 |
|
|---|
| 563 | /* CAN Identifiers used by CAL (cf. CiA/DS204-1, Annex I) */
|
|---|
| 564 | #define ID_START_STOP 0 /* Node Start, Stop, Disconnect */
|
|---|
| 565 | #define ID_CMS_NIL 0 /* invalid CMS Id */
|
|---|
| 566 | #define ID_CMS_MIN 1 /* range of CMS */
|
|---|
| 567 | #define ID_CMS_MAX 1760 /* identifiers */
|
|---|
| 568 | #define ID_GUARD_NIL 0 /* invalid guard Id */
|
|---|
| 569 | #define ID_GUARD_MIN 1761 /* range of guarding */
|
|---|
| 570 | #define ID_GUARD_MAX 2015 /* identifiers */
|
|---|
| 571 | #define ID_LMT_S 2020 /* from LMT Slave */
|
|---|
| 572 | #define ID_LMT_M 2021 /* from LMT Master */
|
|---|
| 573 | #define ID_NMT_IDENTIFY 2022 /* Identify Node Protocol */
|
|---|
| 574 | #define ID_DBT_S 2023 /* from DBT Slave */
|
|---|
| 575 | #define ID_DBT_M 2024 /* from DBT Master */
|
|---|
| 576 | #define ID_NMT_S 2025 /* from NMT Slave */
|
|---|
| 577 | #define ID_NMT_M 2026 /* from NMT Master */
|
|---|
| 578 | #define ID_SELFTEST 2027 /* for module selftest */
|
|---|
| 579 | #define ID_MIN 0 /* range of identifiers */
|
|---|
| 580 | #define ID_MAX 2031 /* controlled by CiA */
|
|---|
| 581 |
|
|---|
| 582 | #define MAX_ROUTES_PER_ID (ID_MAX * 2)
|
|---|
| 583 | /* should be enough... */
|
|---|
| 584 |
|
|---|
| 585 | #define NIL_ROUT (struct rout_target *) 0
|
|---|
| 586 | /* NIL pointer for "no routing" */
|
|---|
| 587 |
|
|---|
| 588 | #define NIL_NIL_ROUT (struct rout_target **) 0
|
|---|
| 589 | /* NIL pointer for "no routing" */
|
|---|
| 590 |
|
|---|
| 591 | #define NIL_DPM_DEV (DPM_DEV *) -1
|
|---|
| 592 | /* NIL pointer for "no routing" */
|
|---|
| 593 |
|
|---|
| 594 | #define BLANC 0xffff /* empty / last entry indicator in */
|
|---|
| 595 | /* rout_target->target_id struct */
|
|---|
| 596 | /* member */
|
|---|
| 597 |
|
|---|
| 598 | /* prioritized fast-fromhost-queue specific defines/structures */
|
|---|
| 599 |
|
|---|
| 600 | struct fromHostFastDpmQPrioEntry {
|
|---|
| 601 | unsigned short priority;
|
|---|
| 602 | volatile struct fdpmw_desc *fhfdpmQueue;
|
|---|
| 603 | int fhfdpmQueueP;
|
|---|
| 604 | int fhfdpmQueueStartP;
|
|---|
| 605 | struct fromHostFastDpmQPrioEntry *next;
|
|---|
| 606 | };
|
|---|
| 607 | #define NIL_FHFDQ_PRIO_ENTRY (struct fromHostFastDpmQPrioEntry *)0
|
|---|
| 608 |
|
|---|
| 609 | #ifdef __cplusplus
|
|---|
| 610 | }
|
|---|
| 611 | #endif
|
|---|
| 612 |
|
|---|
| 613 | #endif /* __INCdpmh */
|
|---|
| 614 |
|
|---|
