source: trunk/Cosy/incl/dpm.h@ 14549

Last change on this file since 14549 was 731, checked in by tbretz, 25 years ago
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1/*-----------------------------------------------------------------------------
2dpm.h -- Linux driver of DPM interface to VMOD
3
4Copyright (c) 1996 JANZ Computer AG
5All Rights Reserved
6
7Created 96/01/23 by Stefan Althoefer
8
9Version 1.12 of 96/09/27
10
11This file is for both, the "dpm" and the "dpmw" driver.
12The only difference, besides the names of the driver functions, are the in
13the INKERNEL structures. But these are not visible to the user.
14
15-----------------------------------------------------------------------------*/
16
17#ifndef __INCdpmh
18#define __INCdpmh
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include "defs.h"
25#include "vmod.h"
26
27/* Max. Count of Devices for the dpm driver. */
28/*#define DPM_MAJOR_NUMBER 57 */
29#define MAX_BOARDS 16 /* max. # of boards supported */
30#define MAX_MODUL_BOARDS 4 /* max. # of modules supported */
31 /* with one board */
32#define MAX_DPM_DEV (MAX_BOARDS * MAX_MODUL_BOARDS)
33
34#define FAST_QUEUE '\0' /* flag for fast queue */
35#define PLAIN_QUEUE '\1' /* flag for normal queue */
36
37/* Data type of messages */
38#define MSGLEN 252 /* Maximum length of a message */
39#define MSGHDLEN 4 /* Length of message head */
40
41#define ICAN2 1
42#define ICAN3 2
43
44/* -*-Struct-*-
45 *
46 * Message - local message buffer for standard host interface
47 *
48 * This structure stores a message to be send to or received from
49 * a VMOD-ICAN module via the standard host interface.
50 *
51 * <cmd> is a 8 bit command specifier. Refer to the VMOD-ICAN manual
52 * to find out which services are provided by the different <cmd>
53 * specifiers. The data length to be transfered is stored in <len>, thereby
54 * <len> specifies how many bytes of the vector <data> are valid. The data
55 * have to be interpreted by means of <cmd>.
56 *
57 * At most MSGLEN bytes can be stored in a message. MSGLEN is 252 bytes
58 * for all current VMOD-ICAN modules.
59 */
60typedef struct {
61 BYTE_t cmd; /* Message specifier */
62 BYTE_t gap1;
63 WORD_t len; /* Message length (<= MSGLEN) */
64 BYTE_t data[MSGLEN]; /* Data array of Message */
65} Message;
66
67
68/* -*-Struct-*-
69 *
70 * FastMessage - local message buffer for fast host interface
71 *
72 * This structure stores a CANbus message to be send to or received from
73 * a VMOD-ICAN modules fast interface.
74 *
75 * <cmd> is a 8 bit service multiplexor. Currently only <cmd>='0' is used.
76 *
77 * Through <data> the actual CANbus message is transfered if <cmd> equals '0'.
78 * The first two bytes store the message descriptor, that contains the
79 * ID, RTR-flag and CANbus data length code (DLC), the remaining bytes store
80 * the CANbus data bytes.
81 *
82 * .CS
83 * data[0] = ID/8;
84 * data[1] = 32(ID%8) + 16RTR + DLC
85 * data[2] = CAN BYTE 1
86 * data[:] = :
87 * data[9] = CAN BYTE 8
88 * data[10] = unused
89 * data[:] = :
90 * data[13] = unused
91 * .CE
92 *
93 */
94typedef struct {
95 BYTE_t unused;
96 BYTE_t cmd; /* Service specifier */
97 BYTE_t data[14]; /* Data array */
98} FastMessage;
99
100
101
102/*** DPM: Special Driver Functions (Driver management) *********************/
103#ifdef nodef
104
105/* Create the dpm driver. */
106extern STATUS dpmDrv(void);
107
108/* Remove the dpm driver from the system. */
109extern STATUS dpmDrvRemove(void);
110
111/* Add a dpm device. */
112extern STATUS dpmDevCreate(
113 int modno,
114 UINT baddr
115);
116
117/* Delete a dpm device. */
118extern STATUS dpmDevDelete(
119 const char *name
120);
121
122/* Main ioctl function. */
123extern dpmIoctl(
124 int modno,
125 int cmd,
126 int arg
127);
128
129/* interrupt function. */
130extern void dpmInt (int modno);
131
132
133/*** DPMW: Special Driver Functions (Driver management) *********************/
134
135/* Create the dpmw driver. */
136extern STATUS dpmwDrv(void);
137
138/* Remove the dpmw driver from the system. */
139extern STATUS dpmwDrvRemove(void);
140
141/* Add a dpmw device. */
142extern STATUS dpmwDevCreate(
143 const char *name,
144 int modno,
145 UINT baddr,
146 int vector,
147 int level
148);
149
150/* Delete a dpmw device. */
151extern STATUS dpmwDevDelete(
152 const char *name
153);
154#endif
155
156/*** IOCTL commands *****************************************************/
157#define WOS 0x8000 /* offset into user fuction codes */
158
159 /* getstat: */
160#define DPM_READ_MBOX (128 + WOS) /* function code READ */
161#define DPM_COPY_FROM (129 + WOS) /* copy data from dpm */
162#define DPM_READ_FAST_MBOX (130 + WOS) /* function code READ FAST */
163
164 /* putstat: */
165#define DPM_WRITE_MBOX (528 + WOS) /* function code WRITE mid prio */
166#define DPM_WRITE_MBOX_HI (539 + WOS) /* function code WRITE high prio*/
167#define DPM_WRITE_MBOX_LOW (540 + WOS) /* function code WRITE low prio */
168#define DPM_COPY_TO (529 + WOS) /* copy data to dpm */
169#define DPM_DEL_SIGNAL (530 + WOS) /* delete signal entry */
170#define DPM_SET_SIGNAL (531 + WOS) /* set signal entry */
171#define DPM_RESET (532 + WOS) /* reset the module */
172#define DPM_INIT_NEW_HOSTIF (533 + WOS) /* init new hostif */
173#define DPM_INIT_NEW_HOSTIF_PRIO (545 + WOS) /* init new hostif (priorized) */
174#define DPM_SET_SEM (534 + WOS) /* create semaphor for read */
175#define DPM_INIT_FAST_CAN (535 + WOS) /* init fast CAN access */
176#define DPM_INIT_FAST_CAN_PRIO (551 + WOS) /* init fast CAN access */
177#define DPM_WRITE_FAST_CAN (536 + WOS) /* send trougth fast interface */
178#define DPM_WRITE_FAST_CAN_PRIO (552 + WOS) /* send trougth prioritized fast interface */
179
180#define DPM_DEINIT_FAST_CAN (537 + WOS) /* deinit fast CAN access */
181#define DPM_DEL_SEM (538 + WOS) /* delete semaphor for read */
182 /* (539 + WOS) see above! */
183 /* (540 + WOS) see above! */
184#define DPM_INIT_ID_MSG_Q_TABLE (541 + WOS) /* allocates memory for table, */
185 /* where message-queue-Ids for */
186 /* fast can access are stored */
187#define DPM_DEINIT_ID_MSG_Q_TABLE (542 + WOS) /* deallocates memory for table */
188#define DPM_ADD_ID_TO_MSG_Q_TABLE (543 + WOS) /* adds queue entry to ID-table */
189#define DPM_REM_ID_FROM_MSG_Q_TABLE (544 + WOS) /* removes entry from ID-table */
190 /* (545 + WOS) see above! */
191#define DPM_INIT_L2_ROUTING (546 + WOS) /* inits the Layer2 routing cap */
192#define DPM_DEINIT_L2_ROUTING (547 + WOS) /* deinits Layer2 routing cap */
193#define DPM_INIT_ROUTE_ID (548 + WOS) /* lets _one_ ID being routable */
194#define DPM_ADD_ROUTE_TO_ID (549 + WOS) /* adds _one_ routing way to ID */
195#define DPM_MAP_FD_TO_MOD (550 + WOS) /* map the fd to board/module */
196
197#define DPM_DEV_CREATE (600 + WOS) /* WINDOWS specific ioctl function code */
198#define DPM_DEV_DELETE (601 + WOS) /* deletes device from slot */
199#define DPM_READ_INTCOUNT (602 + WOS)
200#define DPM_REGISTER_APC (603 + WOS) /* Register APC function */
201#define DPM_TPU_REQ (604 + WOS) /* initiates TPU request IR */
202#define DPM_OBJDIC_REQ (605 + WOS) /* access to object dict. */
203
204#define DPM_DRV_IDVERS (606 + WOS) /* get driver version */
205#define DPM_WRITE_PP (607 + WOS) /* write CANopen process picture */
206#define DPM_READ_PP (608 + WOS) /* read CANopen process picture */
207
208
209struct signal_dpm {
210 int task_id;
211 int signal_code;
212 unsigned char *param_addr;
213};
214
215struct dpm_copy_desc {
216 unsigned int memory;
217 unsigned int dpm;
218 int len;
219};
220
221struct dpm_rw_can_desc {
222 int rval;
223 Message *pm;
224};
225
226struct dpm_new_hostif_desc {
227 int fromhost_len;
228 int tohost_len;
229};
230
231struct dpm_new_hostif_desc_prio {
232 int fromhost_hi_len;
233 int fromhost_low_len;
234 int fromhost_len;
235 int tohost_len;
236};
237
238struct dpm_fast_can_desc {
239 int fromhost_len;
240 int tohost_len;
241/* MSG_Q_ID read_queue; */
242};
243
244struct dpm_fast_can_desc_prio {
245 int numOfPrioQueues;
246 int fromhost_len;
247 int tohost_len;
248/* MSG_Q_ID read_queue; */
249};
250
251struct dpm_write_fast_can_desc {
252 int rval;
253 FastMessage *pm;
254};
255
256struct dpm_write_fast_can_desc_prio {
257 int rval;
258 int prioQueue;
259 FastMessage *pm;
260};
261
262struct dpm_fast_can_desc_win {
263 int fromhost_len;
264 int tohost_len;
265 int fkt_addr;
266};
267
268struct dpm_msg_q_id_desc {
269 unsigned short id;
270 /* MSG_Q_ID target_queue; */
271};
272
273struct dpm_layer_2_routing_desc {
274 int rval;
275 int Id;
276 int max_routes;
277 int source_Id;
278 int dest_Id;
279 int dest_Board;
280 int dest_Modul;
281};
282
283struct io_args {
284 int modno; /* slot of interesing module */
285 int arg; /* place of some arguments */
286};
287
288
289struct dpm_dev_create_desc {
290 int modno;
291};
292
293struct dpm_objdic_desc {
294 int objdic_index;
295 int objdic_subindex;
296 int access_type;
297 void *entry_structure;
298};
299
300struct dpm_readpp_desc {
301 int dataSize;
302 int offset;
303 int dataValid;
304 char *buffer;
305};
306
307struct dpm_writepp_desc {
308 int dataSize;
309 int offset;
310 char *buffer;
311};
312
313#define TS_TO_HOST 1 /* read modules timestamp counter */
314 /* of last SYNC message */
315#define TS_TO_MODULE 0 /* synchronizing module by writing timestamp */
316
317
318#ifdef INKERNEL
319/************************************************************************/
320/* DEFINES */
321/************************************************************************/
322
323#define MAXNDEV 1 /* I/O-channel per module */
324#define BOARDTYP (1<<7) /* d7=1 VMOD-IG, d7=0 VMOD-IO */
325#define I_ENABLE 1
326
327/* MICAN3 */
328#define DPM_PAGEWIDTH 256 /* ICAN3 */
329
330#ifdef BIG_ENDIAN
331struct dpmw { /* structure for BIG_ENDIAN */
332 unsigned char unused;
333 unsigned char spec; /* message specifier */
334 unsigned char len_l; /* data length low byte */
335 unsigned char len_h; /* data length high byte */
336 unsigned char data[MSGLEN]; /* raw data */
337 unsigned char page_sel; /* page selector */
338 unsigned char gap1;
339 unsigned char intgen; /* wr: generate inter. on ICAN3 */
340 /* rd: clear MODULbus interrupt */
341 unsigned char gap2;
342 unsigned char reset; /* generate reset on ICAN3 */
343 unsigned char gap3;
344 unsigned char tpureq; /* signal to tpu on ICAN3 */
345};
346#endif
347
348#ifdef LITTLE_ENDIAN
349struct dpmw { /* structure for LITTLE_ENDIAN */
350 unsigned char spec; /* message specifier */
351 unsigned char unused;
352 unsigned char len_h; /* data length high byte */
353 unsigned char len_l; /* data length low byte */
354 unsigned char data[MSGLEN]; /* raw data */
355 unsigned char gap1;
356 unsigned char page_sel; /* page selector */
357 unsigned char gap2;
358 unsigned char intgen; /* wr: generate inter. on ICAN3 */
359 /* rd: clear MODULbus interrupt */
360 unsigned char gap3;
361 unsigned char reset; /* generate reset on ICAN3 */
362 unsigned char gap4;
363 unsigned char tpureq; /* signal to tpu on ICAN3 */
364};
365#endif
366
367
368#define START_BUFF 9 /* first free page within DPM */
369
370/* New stylish host interface */
371
372#ifdef BIG_ENDIAN
373struct dpmw_desc {
374 unsigned char control; /* control byte */
375 unsigned char buffer; /* buffer pointer */
376};
377#endif
378
379#ifdef LITTLE_ENDIAN
380struct dpmw_desc {
381 unsigned char buffer; /* buffer pointer */
382 unsigned char control; /* control byte */
383};
384#endif
385
386#define DPM_DESC_VALID (1<<7)
387#define DPM_DESC_WRAP (1<<6)
388#define DPM_DESC_INTR (1<<5)
389#define DPM_DESC_IVALID (1<<4)
390#define DPM_DESC_LEN (7<<0)
391
392
393/* Fast dpmqueue host interface */
394
395#define FDPMQUEUE_LEN 14 /* data elements in each buffer */
396
397
398#ifdef BIG_ENDIAN
399struct fdpmw_desc {
400 unsigned char control;
401 unsigned char spec;
402 unsigned char data[FDPMQUEUE_LEN];
403};
404#endif
405
406#ifdef LITTLE_ENDIAN
407struct fdpmw_desc {
408 unsigned char spec;
409 unsigned char control;
410 unsigned char data[FDPMQUEUE_LEN];
411};
412#endif
413
414#define FDPM_DESC_VALID (1<<7)
415#define FDPM_DESC_WRAP (1<<6)
416#define FDPM_DESC_IVALID (1<<4)
417
418/* Definition of fast-queue-fromhost priorization */
419#define FDPMQUEUE_FROMHOST_NO_INIT 0
420#define FDPMQUEUE_FROMHOST_1_PRIO 1
421#define FDPMQUEUE_FROMHOST_N_PRIO 3
422
423#ifdef BIG_ENDIAN
424#define DPMW_MSYNC_LOCL_ADDR 0x1
425#define DPMW_MSYNC_PEER_ADDR 0x0
426#define DPMW_TARGET_RUN_ADDR 0x2
427#define TIME_STAMP_0_ADDR 0x10
428#define TIME_STAMP_1_ADDR 0x11
429#define TIME_STAMP_2_ADDR 0x12
430#define TIME_STAMP_3_ADDR 0x13
431#endif
432
433#ifdef LITTLE_ENDIAN
434#define DPMW_MSYNC_LOCL_ADDR 0x0
435#define DPMW_MSYNC_PEER_ADDR 0x1
436#define DPMW_TARGET_RUN_ADDR 0x3
437#define TIME_STAMP_0_ADDR 0x12
438#define TIME_STAMP_1_ADDR 0x13
439#define TIME_STAMP_2_ADDR 0x10
440#define TIME_STAMP_3_ADDR 0x11
441#endif
442
443/* end of defined MICAN3 */
444
445/* MICAN2 */
446
447#ifdef BIG_ENDIAN
448struct dpm { /* structure for MOTOROLA type */
449 unsigned char page_sel; /* page selector */
450 unsigned char unused;
451 unsigned char intgen; /* wr: generate inter. on ICAN2 */
452 /* rd: clear MODULbus interrupt */
453 unsigned char spec; /* message specifier */
454 unsigned char reset; /* generate reset on ICAN2 */
455 unsigned char len_l; /* data length low byte */
456 unsigned char gap0;
457 unsigned char len_h; /* data length high byte */
458 unsigned char gap_1;
459 unsigned char data[MSGLEN * 2]; /* raw data */
460};
461#endif
462
463#ifdef LITTLE_ENDIAN
464struct dpm { /* structure for INTEL-LIKE type */
465 unsigned char unused;
466 unsigned char page_sel; /* page selector */
467 unsigned char spec; /* message specifier */
468 unsigned char intgen; /* wr: generate inter. on ICAN2 */
469 /* rd: clear MODULbus interrupt */
470 unsigned char len_l; /* data length low byte */
471 unsigned char reset; /* generate reset on ICAN2 */
472 unsigned char len_h; /* data length high byte */
473 unsigned char gap0;
474 unsigned char data[MSGLEN * 2]; /* raw data */
475 unsigned char gap_1;
476};
477#endif
478
479/* New stylish host interface */
480
481#ifdef BIG_ENDIAN
482struct dpm_desc {
483 unsigned char gap1;
484 unsigned char control; /* control byte */
485 unsigned char gap2;
486 unsigned char buffer; /* buffer pointer */
487};
488#endif
489
490#ifdef LITTLE_ENDIAN
491struct dpm_desc {
492 unsigned char control; /* control byte */
493 unsigned char gap1;
494 unsigned char buffer; /* buffer pointer */
495 unsigned char gap2;
496};
497#endif
498
499#define DPM_DESC_VALID (1<<7)
500#define DPM_DESC_WRAP (1<<6)
501#define DPM_DESC_INTR (1<<5)
502#define DPM_DESC_IVALID (1<<4)
503#define DPM_DESC_LEN (7<<0)
504
505
506/* Fast dpmqueue host interface */
507
508#define FDPMQUEUE_LEN 14
509
510#ifdef BIG_ENDIAN
511struct fdpm_desc {
512 unsigned char gap1;
513 unsigned char control;
514 unsigned char gap2;
515 unsigned char spec;
516 unsigned char gap3;
517 unsigned char data[2*FDPMQUEUE_LEN-1];
518};
519#endif
520
521#ifdef LITTLE_ENDIAN
522struct fdpm_desc {
523 unsigned char control;
524 unsigned char gap1;
525 unsigned char spec;
526 unsigned char gap2;
527 unsigned char data[2*FDPMQUEUE_LEN-1];
528 unsigned char gap3;
529};
530#endif
531
532#ifdef BIG_ENDIAN
533#define DPM_MSYNC_LOCL_ADDR 0x3
534#define DPM_MSYNC_PEER_ADDR 0x1
535#define DPM_TARGET_RUN_ADDR 0x5
536#endif
537
538#ifdef LITTLE_ENDIAN
539#define DPM_MSYNC_LOCL_ADDR 0x2
540#define DPM_MSYNC_PEER_ADDR 0x0
541#define DPM_TARGET_RUN_ADDR 0x4
542#endif
543
544/* swap macro for MOTOROLA <-> INTEL access on ICAN3 */
545#ifdef LITTLE_ENDIAN
546#define SWAP_WORD(x) (((x & 0xff) << 8) | (0xff & (x >> 8)))
547#endif
548#ifdef BIG_ENDIAN
549#define SWAP_WORD(x) (x)
550#endif
551
552#endif /* #ifdef INKERNEL */
553
554#define TOHOST_DPM_QUEUE_PAGE 5 /* tohost_dpmqueue page */
555#define FROMHOST_DPM_QUEUE_PAGE 6 /* fromhost_dpmqueue page prio mid */
556#define FROMHOST_DPM_QUEUE_HI_PAGE 7 /* fromhost_dpmqueue page prio high */
557#define FROMHOST_DPM_QUEUE_LOW_PAGE 8 /* fromhost_dpmqueue page prio low */
558#define START_BUFF 9 /* first free page within DPM */
559
560
561/*----------routing specific defines ------------------------*/
562
563/* CAN Identifiers used by CAL (cf. CiA/DS204-1, Annex I) */
564#define ID_START_STOP 0 /* Node Start, Stop, Disconnect */
565#define ID_CMS_NIL 0 /* invalid CMS Id */
566#define ID_CMS_MIN 1 /* range of CMS */
567#define ID_CMS_MAX 1760 /* identifiers */
568#define ID_GUARD_NIL 0 /* invalid guard Id */
569#define ID_GUARD_MIN 1761 /* range of guarding */
570#define ID_GUARD_MAX 2015 /* identifiers */
571#define ID_LMT_S 2020 /* from LMT Slave */
572#define ID_LMT_M 2021 /* from LMT Master */
573#define ID_NMT_IDENTIFY 2022 /* Identify Node Protocol */
574#define ID_DBT_S 2023 /* from DBT Slave */
575#define ID_DBT_M 2024 /* from DBT Master */
576#define ID_NMT_S 2025 /* from NMT Slave */
577#define ID_NMT_M 2026 /* from NMT Master */
578#define ID_SELFTEST 2027 /* for module selftest */
579#define ID_MIN 0 /* range of identifiers */
580#define ID_MAX 2031 /* controlled by CiA */
581
582#define MAX_ROUTES_PER_ID (ID_MAX * 2)
583 /* should be enough... */
584
585#define NIL_ROUT (struct rout_target *) 0
586 /* NIL pointer for "no routing" */
587
588#define NIL_NIL_ROUT (struct rout_target **) 0
589 /* NIL pointer for "no routing" */
590
591#define NIL_DPM_DEV (DPM_DEV *) -1
592 /* NIL pointer for "no routing" */
593
594#define BLANC 0xffff /* empty / last entry indicator in */
595 /* rout_target->target_id struct */
596 /* member */
597
598/* prioritized fast-fromhost-queue specific defines/structures */
599
600struct fromHostFastDpmQPrioEntry {
601 unsigned short priority;
602 volatile struct fdpmw_desc *fhfdpmQueue;
603 int fhfdpmQueueP;
604 int fhfdpmQueueStartP;
605 struct fromHostFastDpmQPrioEntry *next;
606};
607#define NIL_FHFDQ_PRIO_ENTRY (struct fromHostFastDpmQPrioEntry *)0
608
609#ifdef __cplusplus
610}
611#endif
612
613#endif /* __INCdpmh */
614
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