source:
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215
Name | Size | Rev | Age | Author | Last Change |
---|---|---|---|---|---|
trigger | 149 | 15 years | Changes to two .py files | ||
tools | 205 | 14 years | Added example socket server code (taken from drsdaq) | ||
pixelmap | 18 | 16 years | change in pixelmap: file now defined via construtor | ||
M0 | 141 | 15 years | some new diretories | ||
hvcontrol | 210 | 14 years | Text output now to new DIM standard service StdOut | ||
FPGA | 215 | 14 years | initial commit (2nd part): only VHDL and UCF files were commited. | ||
Evidence | 213 | 14 years | History read from file if not found in memory | ||
drsdaq | 211 | 14 years | Fix for exit signalling from DimCommand thread | ||
config | 185 | 15 years | Removed unused configuration files | ||
Chief | 190 | 14 years | First version of central control server |
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