Index: firmware/FTU/FTU_control.vhd =================================================================== --- firmware/FTU/FTU_control.vhd (revision 9939) +++ firmware/FTU/FTU_control.vhd (revision 10009) @@ -51,7 +51,9 @@ read_enables : IN std_logic; -- from RS485 module read_prescaling : IN std_logic; -- from RS485 module + ping_pong : IN std_logic; -- from RS485 module dac_array_rs485_out : IN dac_array_type; -- from RS485 module enable_array_rs485_out : IN enable_array_type; -- from RS485 module prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module + dna_ready : IN std_logic; -- from FTU_dna_gen reset : OUT std_logic; config_start : OUT std_logic; @@ -70,8 +72,10 @@ enables_ready : OUT std_logic := '0'; -- to RS485 module prescaling_ready : OUT std_logic := '0'; -- to RS485 module + ping_pong_ready : OUT std_logic := '0'; -- to RS485 module dac_array : OUT dac_array_type; enable_array : OUT enable_array_type; cntr_reset : OUT STD_LOGIC; - prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) + prescaling : OUT STD_LOGIC_VECTOR(7 downto 0); + dna_start : OUT std_logic := '0' -- to FTU_dna_gen ); end FTU_control; @@ -113,5 +117,5 @@ signal new_rates_sig : STD_LOGIC := '0'; - signal new_rates_busy : STD_LOGIC := '0'; + signal new_rates_busy : STD_LOGIC := '1'; -- veto the writing of new rates until in RUNNING signal new_DACs_in_RAM : STD_LOGIC := '0'; @@ -119,8 +123,9 @@ signal new_prescaling_in_RAM : STD_LOGIC := '0'; - type FTU_control_StateType is (IDLE, INIT, RUNNING, - CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, + type FTU_control_StateType is (IDLE, INIT_RAM, INIT_DNA, RUNNING, + CONFIG_ENABLE, CONFIG_DAC, CONFIG_DAC_WAIT, CONFIG_COUNTER, WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING, - READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING); + READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING, + DO_PING_PONG); signal FTU_control_State : FTU_control_StateType; @@ -140,16 +145,20 @@ when IDLE => -- wait for DCMs to lock - config_start_sig <= '0'; - ram_ena_sig <= '0'; - ram_wea_sig <= "0"; if (clk_ready = '1') then - FTU_control_State <= INIT; + FTU_control_State <= INIT_DNA; else FTU_control_State <= IDLE; end if; - - when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info - new_rates_busy <= '1'; - config_start_sig <= '0'; + + when INIT_DNA => -- determine FPGA DNA + if (dna_ready = '1') then + FTU_control_State <= INIT_RAM; + dna_start <= '0'; + else + dna_start <= '1'; + FTU_control_State <= INIT_DNA; + end if; + + when INIT_RAM => -- load default config data to RAM, see also ftu_definitions.vhd for more info ram_ena_sig <= '1'; ram_wea_sig <= "1"; @@ -162,8 +171,8 @@ ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8); end if; - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then -- default counter values ram_dia_sig <= (others => '0'); - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then @@ -180,17 +189,17 @@ end if; end if; - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8); - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register ram_dia_sig <= (others => '0'); - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum ram_dia_sig <= (others => '0'); - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell ram_dia_sig <= (others => '0'); - FTU_control_State <= INIT; + FTU_control_State <= INIT_RAM; else ram_dia_sig <= (others => '0'); @@ -252,4 +261,8 @@ ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); FTU_control_State <= READOUT_PRESCALING; + elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and + read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '0' and + ping_pong = '1') then + FTU_control_State <= DO_PING_PONG; else FTU_control_State <= RUNNING; --no commands from RS485 -> stay running @@ -302,40 +315,43 @@ when CONFIG_DAC => new_rates_busy <= '1'; - if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then - ram_dac_cntr <= ram_dac_cntr + 1; - if (ram_dac_cntr = 0) then - FTU_control_State <= CONFIG_DAC; - ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); - elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then - dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); - ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); - FTU_control_State <= CONFIG_DAC; - elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then - dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); - ram_adb_sig <= (others => '0'); - FTU_control_State <= CONFIG_DAC; - DACs_ready <= '1'; - else - ram_adb_sig <= (others => '0'); - config_start_sig <= '1'; - DACs_ready <= '0'; - FTU_control_State <= CONFIG_DAC; - end if; - else - if (config_ready = '1') then - ram_dac_cntr <= 0; - new_DACs_in_RAM <= '0'; - cntr_reset_sig <= '1'; - new_rates_busy <= '0'; - FTU_control_State <= RUNNING; - elsif (config_ready = '0' and config_started = '1') then - ram_enb_sig <= '0'; - config_start_sig <= '0'; - FTU_control_State <= CONFIG_DAC; - else - FTU_control_State <= CONFIG_DAC; - end if; - end if; - + ram_dac_cntr <= ram_dac_cntr + 1; + if (ram_dac_cntr = 0) then + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); + FTU_control_State <= CONFIG_DAC; + elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then + dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); + ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); + FTU_control_State <= CONFIG_DAC; + elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then + dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); + ram_adb_sig <= (others => '0'); + FTU_control_State <= CONFIG_DAC; + DACs_ready <= '1'; + else + ram_adb_sig <= (others => '0'); + ram_enb_sig <= '0'; + config_start_sig <= '1'; + ram_dac_cntr <= 0; + DACs_ready <= '0'; + FTU_control_State <= CONFIG_DAC_WAIT; + end if; + + when CONFIG_DAC_WAIT => + if (config_ready = '1') then + new_DACs_in_RAM <= '0'; + cntr_reset_sig <= '1'; + new_rates_busy <= '0'; + config_start_sig <= '0'; + FTU_control_State <= RUNNING; + elsif (config_ready = '0' and config_started = '1') then + new_rates_busy <= '1'; + config_start_sig <= '0'; + FTU_control_State <= CONFIG_DAC_WAIT; + else + new_rates_busy <= '1'; + config_start_sig <= '1'; + FTU_control_State <= CONFIG_DAC_WAIT; + end if; + when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A new_rates_busy <= '1'; @@ -535,5 +551,16 @@ FTU_control_State <= RUNNING; end if; - + + when DO_PING_PONG => -- just answer to FTM + wait_cntr <= wait_cntr + 1; + if (wait_cntr = 0) then + ping_pong_ready <= '1'; + FTU_control_State <= DO_PING_PONG; + else + ping_pong_ready <= '0'; + wait_cntr <= 0; + FTU_control_State <= RUNNING; + end if; + end case; end if; Index: firmware/FTU/FTU_top.vhd =================================================================== --- firmware/FTU/FTU_top.vhd (revision 9939) +++ firmware/FTU/FTU_top.vhd (revision 10009) @@ -39,5 +39,5 @@ ext_clk : IN STD_LOGIC; -- external clock from FTU board brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address - brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID -- rate counters LVDS inputs @@ -73,5 +73,5 @@ -- testpoints - TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints + TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints ); end FTU_top; @@ -131,4 +131,5 @@ signal read_enables_sig : std_logic; signal read_prescaling_sig : std_logic; + signal ping_pong_sig : std_logic; signal dac_array_rs485_out_sig : dac_array_type; signal enable_array_rs485_out_sig : enable_array_type; @@ -136,10 +137,16 @@ --signals to RS485 module, all initialized in FTU_control - signal rates_ready_sig : std_logic; - signal DACs_ready_sig : std_logic; - signal enables_ready_sig : std_logic; - signal prescaling_ready_sig : std_logic; + signal rates_ready_sig : std_logic; + signal DACs_ready_sig : std_logic; + signal enables_ready_sig : std_logic; + signal prescaling_ready_sig : std_logic; + signal ping_pong_ready_sig : std_logic; signal rate_array_rs485_sig : rate_array_type; signal overflow_array_rs485_in_sig : STD_LOGIC_VECTOR(7 downto 0); + + --signals for FPGA DNA identifier + signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTU_dna_gen + signal dna_start_sig : STD_LOGIC; -- initialized in FTU_control + signal dna_ready_sig : STD_LOGIC; -- initialized in FTU_dna_gen component FTU_clk_gen @@ -182,7 +189,9 @@ read_enables : IN std_logic; read_prescaling : IN std_logic; + ping_pong : IN std_logic; dac_array_rs485_out : IN dac_array_type; enable_array_rs485_out : IN enable_array_type; prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); + dna_ready : IN std_logic; reset : OUT std_logic; config_start : OUT std_logic; @@ -200,9 +209,11 @@ DACs_ready : OUT std_logic; enables_ready : OUT std_logic; - prescaling_ready : OUT std_logic; + prescaling_ready : OUT std_logic; + ping_pong_ready : OUT std_logic; dac_array : OUT dac_array_type; enable_array : OUT enable_array_type; cntr_reset : OUT STD_LOGIC; - prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) + prescaling : OUT STD_LOGIC_VECTOR(7 downto 0); + dna_start : OUT std_logic ); end component; @@ -229,5 +240,6 @@ DACs_ready : IN std_logic; enables_ready : IN std_logic; - prescaling_ready : IN std_logic; + prescaling_ready : IN std_logic; + ping_pong_ready : IN std_logic; rate_array_rs485 : IN rate_array_type; overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); @@ -235,4 +247,5 @@ enable_array_rs485_in : IN enable_array_type; prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); + dna : IN STD_LOGIC_VECTOR(63 downto 0); rx_en : OUT std_logic; tx_d : OUT std_logic; @@ -245,4 +258,5 @@ read_enables : OUT std_logic; read_prescaling : OUT std_logic; + ping_pong : OUT std_logic; dac_array_rs485_out : OUT dac_array_type; enable_array_rs485_out : OUT enable_array_type; @@ -250,5 +264,14 @@ ); end component; - + + component FTU_dna_gen + port( + clk : IN STD_LOGIC; + start : IN STD_LOGIC; + dna : OUT STD_LOGIC_VECTOR(63 downto 0); + ready : OUT STD_LOGIC + ); + end component; + component FTU_dual_port_ram port( @@ -413,7 +436,9 @@ read_enables => read_enables_sig, read_prescaling => read_prescaling_sig, + ping_pong => ping_pong_sig, dac_array_rs485_out => dac_array_rs485_out_sig, enable_array_rs485_out => enable_array_rs485_out_sig, - prescaling_rs485_out => prescaling_rs485_out_sig, + prescaling_rs485_out => prescaling_rs485_out_sig, + dna_ready => dna_ready_sig, reset => reset_sig, config_start => config_start_sig, @@ -432,8 +457,10 @@ enables_ready => enables_ready_sig, prescaling_ready => prescaling_ready_sig, + ping_pong_ready => ping_pong_ready_sig, dac_array => dac_array_sig, enable_array => enable_array_sig, cntr_reset => cntr_reset_sig, - prescaling => prescaling_sig + prescaling => prescaling_sig, + dna_start => dna_start_sig ); @@ -459,4 +486,5 @@ enables_ready => enables_ready_sig, prescaling_ready => prescaling_ready_sig, + ping_pong_ready => ping_pong_ready_sig, rate_array_rs485 => rate_array_rs485_sig, overflow_array_rs485_in => overflow_array_rs485_in_sig, @@ -464,4 +492,5 @@ enable_array_rs485_in => enable_array_sig, prescaling_rs485_in => prescaling_sig, + dna => dna_sig, rx_en => rx_en, tx_d => tx, @@ -474,7 +503,16 @@ read_enables => read_enables_sig, read_prescaling => read_prescaling_sig, + ping_pong => ping_pong_sig, dac_array_rs485_out => dac_array_rs485_out_sig, enable_array_rs485_out => enable_array_rs485_out_sig, prescaling_rs485_out => prescaling_rs485_out_sig + ); + + Inst_FTU_dna_gen : FTU_dna_gen + port map( + clk => clk_50M_sig, + start => dna_start_sig, + dna => dna_sig, + ready => dna_ready_sig ); @@ -493,5 +531,5 @@ dinb => ram_dib_sig, doutb => ram_dob_sig - ); + ); end Behavioral; Index: firmware/FTU/FTU_top_tb.vhd =================================================================== --- firmware/FTU/FTU_top_tb.vhd (revision 9939) +++ firmware/FTU/FTU_top_tb.vhd (revision 10009) @@ -46,5 +46,5 @@ ext_clk : IN STD_LOGIC; -- external clock from FTU board brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address - brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID + --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID -- rate counters LVDS inputs @@ -87,5 +87,5 @@ signal ext_clk : STD_LOGIC := '0'; signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); - signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); + --signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal patch_A_p : STD_LOGIC := '0'; signal patch_A_n : STD_LOGIC := '0'; @@ -123,5 +123,5 @@ -- Clock period definitions constant ext_clk_period : TIME := 20 ns; - constant baud_rate_period : TIME := 10 us; + constant baud_rate_period : TIME := 4 us; begin @@ -132,5 +132,5 @@ ext_clk => ext_clk, brd_add => brd_add, - brd_id => brd_id, + --brd_id => brd_id, patch_A_p => patch_A_p, patch_A_n => patch_A_n, @@ -285,39 +285,72 @@ --------------------------------------------------------------------------- assign_rs485("01000000"); --start delimiter - wait for 1us; + wait for 0us; assign_rs485("00000000"); --FTU address - wait for 10ns; + wait for 0ns; assign_rs485("11000000"); --FTM address - wait for 100ns; - assign_rs485("00000000"); --instruction - wait for 200us; - assign_rs485("00010000"); --data byte 01 - wait for 100ns; + wait for 0ns; + assign_rs485("00000101"); --instruction + wait for 0us; + assign_rs485("00000001"); --data byte 01 + wait for 0ns; assign_rs485("00000000"); --data byte 02 - wait for 100ns; - assign_rs485("10111100"); --data byte 03 - wait for 100ns; - assign_rs485("00000001"); --data byte 04 - wait for 100ns; - assign_rs485("00000000"); --data byte 05 - wait for 100ns; + wait for 0ns; + assign_rs485("00000010"); --data byte 03 + wait for 0ns; + assign_rs485("00000000"); --data byte 04 + wait for 0ns; + assign_rs485("00000100"); --data byte 05 + wait for 0ns; assign_rs485("00000000"); --data byte 06 - wait for 100ns; - assign_rs485("00000000"); --data byte 07 - wait for 100ns; + wait for 0ns; + assign_rs485("00001000"); --data byte 07 + wait for 0ns; assign_rs485("00000000"); --data byte 08 - wait for 100ns; - assign_rs485("00000000"); --data byte 09 - wait for 100ns; + wait for 0ns; + assign_rs485("00010000"); --data byte 09 + wait for 0ns; assign_rs485("00000000"); --data byte 10 - wait for 100ns; + wait for 0ns; assign_rs485("00000000"); --data byte 11 - wait for 100ns; + wait for 0ns; assign_rs485("00000000"); --check sum - wait for 100ns; - --------------------------------------------------------------------------- - -- keep rx line high - --------------------------------------------------------------------------- - rx <= '1'; + --------------------------------------------------------------------------- + -- wait enough time and send another command + --------------------------------------------------------------------------- + wait for 1ms; + assign_rs485("01000000"); --start delimiter + wait for 0us; + assign_rs485("00000000"); --FTU address + wait for 0ns; + assign_rs485("11000000"); --FTM address + wait for 0ns; + assign_rs485("00000101"); --instruction + wait for 0us; + assign_rs485("00000001"); --data byte 01 + wait for 0ns; + assign_rs485("00000000"); --data byte 02 + wait for 0ns; + assign_rs485("00000010"); --data byte 03 + wait for 0ns; + assign_rs485("00000000"); --data byte 04 + wait for 0ns; + assign_rs485("00000100"); --data byte 05 + wait for 0ns; + assign_rs485("00000000"); --data byte 06 + wait for 0ns; + assign_rs485("00001000"); --data byte 07 + wait for 0ns; + assign_rs485("00000000"); --data byte 08 + wait for 0ns; + assign_rs485("00010000"); --data byte 09 + wait for 0ns; + assign_rs485("00000000"); --data byte 10 + wait for 0ns; + assign_rs485("00000000"); --data byte 11 + wait for 0ns; + assign_rs485("00000000"); --check sum + --------------------------------------------------------------------------- + -- don't forget final wait! + --------------------------------------------------------------------------- wait; Index: firmware/FTU/dna/FTU_dna_gen.vhd =================================================================== --- firmware/FTU/dna/FTU_dna_gen.vhd (revision 10009) +++ firmware/FTU/dna/FTU_dna_gen.vhd (revision 10009) @@ -0,0 +1,112 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: 10/06/2010 +-- Design Name: +-- Module Name: FTU_dna_gen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: entity to read out the FPGA DNA identifier +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftu_definitions; +USE ftu_definitions.ftu_constants.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FTU_dna_gen is + Port ( + clk : IN STD_LOGIC; + start : IN STD_LOGIC; + dna : OUT STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); + ready : OUT STD_LOGIC := '0' + ); +end FTU_dna_gen; + +architecture Behavioral of FTU_dna_gen is + + signal dout_sig : STD_LOGIC := '0'; + signal read_sig : STD_LOGIC := '0'; + signal shift_sig : STD_LOGIC := '0'; + signal dna_sig : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); + + type FTU_dna_gen_StateType is (IDLE, READ_DNA, SHIFT_DNA, DNA_READY); + signal FTU_dna_gen_State : FTU_dna_gen_StateType; + + signal shift_cntr : INTEGER range 0 to 64 := 0; + +begin + + DNA_PORT_inst : DNA_PORT + generic map ( + SIM_DNA_VALUE => DNA_FOR_SIM) -- Specifies the Pre-programmed factory ID value + port map ( + DOUT => dout_sig, -- 1-bit DNA output data + CLK => clk, -- 1-bit clock input + DIN => '0', -- 1-bit user data input pin + READ => read_sig, -- 1-bit input, active high load DNA, active low read + SHIFT => shift_sig -- 1-bit input, active high shift enable + ); + + FTU_dna_gen_FSM : process(clk) + begin + if Falling_edge(clk) then + case FTU_dna_gen_State is + when IDLE => + ready <= '0'; + read_sig <= '0'; + shift_sig <= '0'; + if (start = '1') then + FTU_dna_gen_State <= READ_DNA; + else + FTU_dna_gen_State <= IDLE; + end if; + when READ_DNA => + ready <= '0'; + read_sig <= '1'; + shift_sig <= '0'; + FTU_dna_gen_State <= SHIFT_DNA; + when SHIFT_DNA => + shift_cntr <= shift_cntr + 1; + ready <= '0'; + read_sig <= '0'; + if (shift_cntr < 57) then + dna_sig <= dna_sig(62 downto 0) & dout_sig; -- put in from right + shift_sig <= '1'; + FTU_dna_gen_State <= SHIFT_DNA; + --elsif (shift_cntr = 56) then + --dna_sig <= dna_sig(62 downto 0) & dout_sig; -- put in from right + --shift_sig <= '0'; + --FTU_dna_gen_State <= SHIFT_DNA; + else + shift_sig <= '1'; + FTU_dna_gen_State <= DNA_READY; + end if; + when DNA_READY => + ready <= '1'; + read_sig <= '0'; + shift_sig <= '0'; + end case; + end if; + end process FTU_dna_gen_FSM; + + dna <= dna_sig; + +end Behavioral; Index: firmware/FTU/ftu_board.ucf =================================================================== --- firmware/FTU/ftu_board.ucf (revision 9939) +++ firmware/FTU/ftu_board.ucf (revision 10009) @@ -26,12 +26,12 @@ # local board-ID "solder programmable" ####################################################### -NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 -NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 -NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 -NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 -NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 -NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 -NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 -NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 +#NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 +#NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 +#NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 +#NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 +#NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 +#NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 +#NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 +#NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 Index: firmware/FTU/ftu_definitions.vhd =================================================================== --- firmware/FTU/ftu_definitions.vhd (revision 9939) +++ firmware/FTU/ftu_definitions.vhd (revision 10009) @@ -74,8 +74,11 @@ --communication with FTM - constant RS485_BAUD_RATE : integer := 100000; -- bits / sec in our case + constant RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case constant RS485_BLOCK_WIDTH : integer := 128; -- 16 byte protocol constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 + + --DNA identifier for simulation + constant DNA_FOR_SIM : bit_vector := X"01710000E0000500"; end ftu_constants; Index: firmware/FTU/rs485/FTU_rs485_control.vhd =================================================================== --- firmware/FTU/rs485/FTU_rs485_control.vhd (revision 9939) +++ firmware/FTU/rs485/FTU_rs485_control.vhd (revision 10009) @@ -42,4 +42,5 @@ enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending prescaling_ready : IN std_logic; -- prescaling byte is ok for sending + ping_pong_ready : IN std_logic; -- ping pong successful rate_array_rs485 : IN rate_array_type; overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); @@ -47,4 +48,5 @@ enable_array_rs485_in : IN enable_array_type; prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); + dna : IN STD_LOGIC_VECTOR(63 downto 0); rx_en : OUT std_logic; tx_d : OUT std_logic; @@ -57,4 +59,5 @@ read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value + ping_pong : OUT std_logic := '0'; -- ping pong command from FTM dac_array_rs485_out : OUT dac_array_type; enable_array_rs485_out : OUT enable_array_type; @@ -83,4 +86,5 @@ signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter + signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames @@ -110,4 +114,5 @@ int_read_enables : OUT std_logic; int_read_prescaling : OUT std_logic; + int_ping_pong : OUT std_logic; dac_array_rs485_out : OUT dac_array_type; enable_array_rs485_out : OUT enable_array_type; @@ -136,7 +141,7 @@ type FTU_rs485_control_StateType is (RECEIVE, READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT, - SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, + SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT, READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT, - SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT); + SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT); signal FTU_rs485_control_State : FTU_rs485_control_StateType; @@ -166,4 +171,5 @@ int_read_enables => int_read_enables_sig, int_read_prescaling => int_read_prescaling_sig, + int_ping_pong => int_ping_pong_sig, dac_array_rs485_out => dac_array_rs485_out, enable_array_rs485_out => enable_array_rs485_out, @@ -205,4 +211,5 @@ read_enables <= '0'; read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= SET_DAC_WAIT; elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then @@ -214,4 +221,5 @@ read_enables <= '0'; read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= SET_ENABLE_WAIT; elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then @@ -223,4 +231,5 @@ read_enables <= '0'; read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= SET_PRESCALING_WAIT; elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and @@ -233,4 +242,5 @@ read_enables <= '0'; read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= READ_RATES_WAIT; elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and @@ -243,4 +253,5 @@ read_enables <= '0'; read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= READ_DAC_WAIT; elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and @@ -253,4 +264,5 @@ read_enables <= '1'; read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= READ_ENABLE_WAIT; elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and @@ -263,6 +275,9 @@ read_enables <= '0'; read_prescaling <= '1'; + ping_pong <= '0'; FTU_rs485_control_State <= READ_PRESCALING_WAIT; - else + elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and + int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and + int_ping_pong_sig = '1') then new_DACs <= '0'; new_enables <= '0'; @@ -272,4 +287,15 @@ read_enables <= '0'; read_prescaling <= '0'; + ping_pong <= '1'; + FTU_rs485_control_State <= PING_PONG_WAIT; + else + new_DACs <= '0'; + new_enables <= '0'; + new_prescaling <= '0'; + read_rates <= '0'; + read_DACs <= '0'; + read_enables <= '0'; + read_prescaling <= '0'; + ping_pong <= '0'; FTU_rs485_control_State <= RECEIVE; end if; @@ -338,4 +364,13 @@ end if; + when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM + if (ping_pong_ready = '1') then + ping_pong <= '0'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + else + ping_pong <= '1'; + FTU_rs485_control_State <= PING_PONG_WAIT; + end if; + when SET_DAC_TRANSMIT => if tx_busy_sig = '0' then @@ -869,4 +904,85 @@ FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; end if; + + when PING_PONG_TRANSMIT => + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= RS485_START_DELIM; + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 1 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= FTM_ADDRESS; + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 2 then -- board address + txcnt <= txcnt + 1; + tx_data_sig <= "00" & brd_add; + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 3 then -- mirrored command + txcnt <= txcnt + 1; + tx_data_sig <= "00000101"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 4 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(7 downto 0); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 5 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(15 downto 8); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 6 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(23 downto 16); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 7 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(31 downto 24); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 8 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(39 downto 32); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 9 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(47 downto 40); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 10 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(55 downto 48); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 11 then -- data: device DNA + txcnt <= txcnt + 1; + tx_data_sig <= dna(63 downto 56); + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt < 15 then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + elsif txcnt = 15 then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! + tx_start_sig <= '1'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + else -- transmission finished + txcnt <= 0; + FTU_rs485_control_State <= RECEIVE; + end if; + else + tx_start_sig <= '0'; + FTU_rs485_control_State <= PING_PONG_TRANSMIT; + end if; end case; Index: firmware/FTU/rs485/FTU_rs485_interpreter.vhd =================================================================== --- firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 9939) +++ firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 10009) @@ -46,4 +46,5 @@ int_read_enables : OUT std_logic := '0'; int_read_prescaling : OUT std_logic := '0'; + int_ping_pong : OUT std_logic := '0'; dac_array_rs485_out : OUT dac_array_type; enable_array_rs485_out : OUT enable_array_type; @@ -79,4 +80,5 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; + int_ping_pong <= '0'; if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal FTU_rs485_interpreter_State <= CHECK_HEADER; @@ -93,4 +95,5 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; + int_ping_pong <= '0'; if (data_block(7 downto 0) = RS485_START_DELIM) and (data_block(15 downto 8) = ("00" & brd_add)) and @@ -102,5 +105,5 @@ when DECODE => -- decode instruction - if(data_block(31 downto 24) = "00000000") then + if(data_block(31 downto 24) = "00000000") then -- set DACs int_new_DACs <= '1'; int_new_enables <= '0'; @@ -110,4 +113,5 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; + int_ping_pong <= '0'; dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(43 downto 32))), conv_integer(unsigned(data_block(59 downto 48))), @@ -120,5 +124,5 @@ ); FTU_rs485_interpreter_State <= WAIT_FOR_DATA; - elsif (data_block(31 downto 24) = "00000001") then + elsif (data_block(31 downto 24) = "00000001") then -- read DACs int_new_DACs <= '0'; int_new_enables <= '0'; @@ -128,6 +132,7 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; - FTU_rs485_interpreter_State <= WAIT_FOR_DATA; - elsif (data_block(31 downto 24) = "00000010") then + int_ping_pong <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000010") then -- read rates int_new_DACs <= '0'; int_new_enables <= '0'; @@ -137,6 +142,7 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; - FTU_rs485_interpreter_State <= WAIT_FOR_DATA; - elsif (data_block(31 downto 24) = "00000011") then + int_ping_pong <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000011") then -- set enables int_new_DACs <= '0'; int_new_enables <= '1'; @@ -146,4 +152,5 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; + int_ping_pong <= '0'; enable_array_rs485_out_sig <= (data_block(47 downto 32), data_block(63 downto 48), @@ -152,5 +159,5 @@ ); FTU_rs485_interpreter_State <= WAIT_FOR_DATA; - elsif (data_block(31 downto 24) = "00000100") then + elsif (data_block(31 downto 24) = "00000100") then -- read enables int_new_DACs <= '0'; int_new_enables <= '0'; @@ -160,6 +167,7 @@ int_read_enables <= '1'; int_read_prescaling <= '0'; - FTU_rs485_interpreter_State <= WAIT_FOR_DATA; - elsif (data_block(31 downto 24) = "00000110") then + int_ping_pong <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000110") then -- set counter mode int_new_DACs <= '0'; int_new_enables <= '0'; @@ -169,7 +177,8 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; + int_ping_pong <= '0'; prescaling_rs485_out_sig <= data_block(39 downto 32); FTU_rs485_interpreter_State <= WAIT_FOR_DATA; - elsif (data_block(31 downto 24) = "00000111") then + elsif (data_block(31 downto 24) = "00000111") then -- read counter mode int_new_DACs <= '0'; int_new_enables <= '0'; @@ -179,4 +188,15 @@ int_read_enables <= '0'; int_read_prescaling <= '1'; + int_ping_pong <= '0'; + FTU_rs485_interpreter_State <= WAIT_FOR_DATA; + elsif (data_block(31 downto 24) = "00000101") then -- ping pong + int_new_DACs <= '0'; + int_new_enables <= '0'; + int_new_prescaling <= '0'; + int_read_rates <= '0'; + int_read_DACs <= '0'; + int_read_enables <= '0'; + int_read_prescaling <= '0'; + int_ping_pong <= '1'; FTU_rs485_interpreter_State <= WAIT_FOR_DATA; else @@ -188,4 +208,5 @@ int_read_enables <= '0'; int_read_prescaling <= '0'; + int_ping_pong <= '0'; FTU_rs485_interpreter_State <= WAIT_FOR_DATA; end if;