Index: firmware/FTU/clock/FTU_clk_gen.vhd
===================================================================
--- firmware/FTU/clock/FTU_clk_gen.vhd	(revision 9880)
+++ firmware/FTU/clock/FTU_clk_gen.vhd	(revision 10037)
@@ -34,4 +34,5 @@
     rst    : IN  STD_LOGIC;
     clk_50 : OUT STD_LOGIC;
+    clk_1  : OUT STD_LOGIC;
     ready  : OUT STD_LOGIC
   );
@@ -48,4 +49,14 @@
       LOCKED_OUT      : out   std_logic);
   end component;
+
+  component Clock_Divider
+    port(
+      clock_in  : IN  STD_LOGIC;
+      clock_out : OUT STD_LOGIC
+    );
+  end component;
+
+  signal clk_1M_sig  : std_logic;
+  signal clk_50M_sig : std_logic;
   
 begin
@@ -55,8 +66,62 @@
       CLKIN_IN        => clk,
       RST_IN          => rst,
-      CLKFX_OUT       => clk_50,
+      CLKFX_OUT       => clk_50M_sig,
       CLKIN_IBUFG_OUT => open,
       LOCKED_OUT      => ready
     );
+
+  Inst_Clock_Divider : Clock_Divider
+    port map (
+      clock_in  => clk_50M_sig,
+      clock_out => clk_1M_sig
+    );
+
+  clk_50 <= clk_50M_sig;
+  clk_1  <= clk_1M_sig;
   
 end Behavioral;
+
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library ftu_definitions;
+USE ftu_definitions.ftu_array_types.all;
+USE ftu_definitions.ftu_constants.all;
+
+entity Clock_Divider is
+  generic(
+    divider : integer := INT_CLK_FREQUENCY / COUNTER_FREQUENCY
+  );
+  port(
+    clock_in  : in  std_logic;
+    clock_out : out std_logic := '0'
+  );
+end entity Clock_Divider;
+
+architecture RTL of Clock_Divider is
+
+begin
+    
+  process (clock_in)
+    variable Z: integer range 0 to divider - 1;
+  begin
+    if rising_edge(clock_in) then
+      if (Z < divider - 1) then
+        Z := Z + 1;
+      else
+        Z := 0;
+      end if;
+      if (Z = 0) then
+        clock_out <= '1';
+      end if;
+      if (Z = divider / 2) then
+        clock_out <= '0';
+      end if;
+    end if;
+  end process;
+
+end architecture RTL;