Changeset 10037 for firmware/FTU/counter


Ignore:
Timestamp:
10/25/10 15:29:13 (14 years ago)
Author:
weitzel
Message:
FTU counter changed from 16 to 30 bit
File:
1 edited

Legend:

Unmodified
Added
Removed

  • firmware/FTU/counter/FTU_rate_counter.vhd

    r9939 r10037  
    1515-- Revision:
    1616-- Revision 0.01 - File Created
     17-- Revision 0.02 - counter range changed from 16 to 30 bit, 19.10.2010, Q. Weitzel
     18-- Revision 0.03 - no local clock division anymore, 20.10.2010, Q. Weitzel
    1719-- Additional Comments:
    1820--
    … …  
    3941    trigger    : in  std_logic;
    4042    prescaling : in  std_logic_vector(7 downto 0);
    41     counts     : out integer range 0 to 2**16 - 1 := 0;
     43    counts     : out integer range 0 to 2**30 - 1 := 0;
    4244    overflow   : out std_logic := '0';
    4345    new_rate   : out std_logic
    … …  
    4951  signal counting_period : integer range 0 to 128*COUNTER_FREQUENCY := 128*COUNTER_FREQUENCY;
    5052  signal period_finished : std_logic := '0';
    51   signal trigger_counts  : integer range 0 to 2**16 - 1 := 0;
    52   signal clk_1M_sig      : std_logic;
     53  signal trigger_counts  : integer range 0 to 2**30 - 1 := 0;
    5354  signal overflow_sig    : std_logic := '0';
    5455  signal new_rate_sig    : std_logic := '0';
    55  
    56   component Clock_Divider
    57     port(
    58       clock_in  : IN  STD_LOGIC;
    59       clock_out : OUT STD_LOGIC
    60     );
    61   end component;
    62  
     56   
    6357begin
    6458
    65   Inst_Clock_Divider : Clock_Divider
    66     port map (
    67       clock_in  => clk,
    68       clock_out => clk_1M_sig
    69     );
    70  
    71   process(cntr_reset, clk_1M_sig)
     59  process(cntr_reset, clk)
    7260
    7361    variable clk_cntr : integer range 0 to 128*COUNTER_FREQUENCY := 0;
    … …  
    8371      overflow <= '0';
    8472     
    85     elsif rising_edge(clk_1M_sig) then
     73    elsif rising_edge(clk) then
    8674     
    8775      if (clk_cntr < counting_period - 1) then
    … …  
    10694    else
    10795      if rising_edge(trigger) then
    108         if (trigger_counts < 2**16 - 1) then
     96        if (trigger_counts < 2**30 - 1) then
    10997          trigger_counts <= trigger_counts + 1;
    11098        else
    … …  
    121109      --calculate counting period from prescaling value
    122110      --default is 0.5s - 128s if CNTR_FREQ_DIVIDER = 1
    123       if (prescaling = "00000000") then
    124         counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
    125       elsif (prescaling = "11111111") then
    126         counting_period <= 128 * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
     111      --if (prescaling = "00000000") then
     112        --counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
     113      --elsif (prescaling = "11111111") then
     114        --counting_period <= 128 * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
     115      --else
     116        --counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
     117      --end if;
     118      if ((conv_integer(unsigned(prescaling))) mod 2 = 0) then
     119        counting_period <= ((((conv_integer(unsigned(prescaling)) / 2)) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER)) + (COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER)));
    127120      else
    128         counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
     121        counting_period <= (((conv_integer(unsigned(prescaling)) - 1) / 2) + 1) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
    129122      end if;
    130123    end if;
    … …  
    134127 
    135128end Behavioral;
    136 
    137 ----------------------------------------------------------------------------------
    138 
    139 library IEEE;
    140 use IEEE.STD_LOGIC_1164.ALL;
    141 use IEEE.STD_LOGIC_ARITH.ALL;
    142 use IEEE.STD_LOGIC_UNSIGNED.ALL;
    143 
    144 library ftu_definitions;
    145 USE ftu_definitions.ftu_array_types.all;
    146 USE ftu_definitions.ftu_constants.all;
    147 
    148 entity Clock_Divider is
    149   generic(
    150     divider : integer := INT_CLK_FREQUENCY / COUNTER_FREQUENCY
    151   );
    152   port(
    153     clock_in  : in  std_logic;
    154     clock_out : out std_logic := '0'
    155   );
    156 end entity Clock_Divider;
    157 
    158 architecture RTL of Clock_Divider is
    159 
    160 begin
    161    
    162   process (clock_in)
    163     variable Z: integer range 0 to divider - 1;
    164   begin
    165     if rising_edge(clock_in) then
    166       if (Z < divider - 1) then
    167         Z := Z + 1;
    168       else
    169         Z := 0;
    170       end if;
    171       if (Z = 0) then
    172         clock_out <= '1';
    173       end if;
    174       if (Z = divider / 2) then
    175         clock_out <= '0';
    176       end if;
    177     end if;
    178   end process;
    179 
    180 end architecture RTL;
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