Index: firmware/FTM/test_firmware/FTM_test1/FTM_test1.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test1/FTM_test1.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test1/FTM_test1.vhd (revision 10046) @@ -0,0 +1,370 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 12 August 2010 +-- Design Name: +-- Module Name: FTU_test1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: blinking with the on-board LED's +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTM_test1 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC; -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- + LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red + LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow + LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration +-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ +-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- +-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ +-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs +-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ +-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- +-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ +-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 +-- TIM_Sel : out STD_LOGIC; -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- + TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test1; + + +architecture Behavioral of FTM_test1 is + + component FTM_test1_dcm + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); + end component; + + component Clock_Divider + port( + clock : IN STD_LOGIC; + enable_out : OUT STD_LOGIC + ); + end component; + + signal clk_250M_sig : STD_LOGIC; + signal enable_sig : STD_LOGIC; + + + + +begin + + Inst_FTU_test1_dcm : FTM_test1_dcm + port map( + CLKIN_IN => clk, + CLKFX_OUT => clk_250M_sig, + CLKIN_IBUFG_OUT => open + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock => clk_250M_sig, + enable_out => enable_sig + ); + + LED_red(0) <= enable_sig; + LED_red(1) <= enable_sig; + LED_red(2) <= enable_sig; + LED_red(3) <= enable_sig; + + LED_ye(0) <= enable_sig; + LED_ye(1) <= enable_sig; + + LED_gn(0) <= enable_sig; + LED_gn(1) <= enable_sig; + + TP(0) <= clk_250M_sig; + +end Behavioral; + + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock : in std_logic; + enable_out: out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + --constant max_count : integer := 5000000/1000000; -- for simulation + constant max_count : integer := 250000000/1; -- for implementation + constant final_count : integer := 100; + +begin + + process(clock) + variable count : integer range 0 to max_count; + variable count2 : integer range 0 to final_count; + begin + if rising_edge(clock) then + --enable_out <= '0'; + if count2 = final_count then + enable_out <= '0'; + else + if count < max_count/2 then + enable_out <= '0'; + count := count + 1; + elsif count < max_count then + enable_out <= '1'; + count := count + 1; + else + count := 0; + enable_out <= '0'; + count2 := count2 + 1; + end if; + end if; + end if; + end process; + +end architecture RTL; Index: firmware/FTM/test_firmware/FTM_test1/FTM_test1_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test1/FTM_test1_dcm.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test1/FTM_test1_dcm.vhd (revision 10046) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_test1_dcm.vhd +-- /___/ /\ Timestamp : 08/16/2010 14:30:00 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test1/FTM_Test1_impl/ipcore_dir/FTM_test1_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test1/FTM_Test1_impl/ipcore_dir/FTM_test1_dcm +--Design Name: FTM_test1_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.17 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.69 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_test1_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTM_test1_dcm; + +architecture BEHAVIORAL of FTM_test1_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/test_firmware/FTM_test1/FTM_test1_dcm_arwz.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test1/FTM_test1_dcm_arwz.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test1/FTM_test1_dcm_arwz.ucf (revision 10046) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/test_firmware/FTM_test1/ftm_board.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test1/ftm_board.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test1/ftm_board.ucf (revision 10046) @@ -0,0 +1,408 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 16 August 2010 +######################################################## + + +#Clock +####################################################### +NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +### ### +# OPEN COLLECTOR OUTPUTS FOR THE LEDs # +### ### +# red +NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- + # on IO-Bank2 +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test2/FTM_test2.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test2/FTM_test2.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test2/FTM_test2.vhd (revision 10046) @@ -0,0 +1,523 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 13 October 2010 +-- Design Name: +-- Module Name: FTU_test2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: +-- NIM and LVDS output stages +-- fast signal distribution (partially) +-- crate resets +-- +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FTM_test2 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC; -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow +-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- + Crate_Res0 : out STD_LOGIC; -- + Crate_Res1 : out STD_LOGIC; -- + Crate_Res2 : out STD_LOGIC; -- + Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration + Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ + Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- + Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ + Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs + NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ + NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- + NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ + NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- + RES_p : out STD_LOGIC; -- RES+ Reset + RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + + TRG_p : out STD_LOGIC; -- TRG+ Trigger + TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + + TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker + TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 + TIM_Sel : out STD_LOGIC; -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 + Cal_0_p : out STD_LOGIC; + Cal_0_n : out STD_LOGIC; + Cal_1_p : out STD_LOGIC; + Cal_1_n : out STD_LOGIC; + Cal_2_p : out STD_LOGIC; + Cal_2_n : out STD_LOGIC; + Cal_3_p : out STD_LOGIC; + Cal_3_n : out STD_LOGIC; + +-- to connector J12 + Cal_4_p : out STD_LOGIC; + Cal_4_n : out STD_LOGIC; + Cal_5_p : out STD_LOGIC; + Cal_5_n : out STD_LOGIC; + Cal_6_p : out STD_LOGIC; + Cal_6_n : out STD_LOGIC; + Cal_7_p : out STD_LOGIC; + Cal_7_n : out STD_LOGIC + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test2; + + + + + +architecture Behavioral of FTM_test2 is + + component FTM_test1_dcm + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); + end component; + + component Clock_Divider + port( + clock : IN STD_LOGIC; + enable_out : OUT STD_LOGIC + ); + end component; + + signal clk_200M_sig : STD_LOGIC; + signal enable_sig : STD_LOGIC; + + +begin + + + OBUFDS_inst_TRG : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => TRG_p, -- Diff_p output (connect directly to top-level port) + OB => TRG_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + + + OBUFDS_inst_RES : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => RES_p, -- Diff_p output (connect directly to top-level port) + OB => RES_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + + + OBUFDS_inst_TIM : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => TIM_Run_p, -- Diff_p output (connect directly to top-level port) + OB => TIM_Run_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + TIM_Sel <= '0'; + + Crate_Res0 <= enable_sig; + Crate_Res1 <= enable_sig; + Crate_Res2 <= enable_sig; + Crate_Res3 <= enable_sig; + + + + + + OBUFDS_inst_Cal_NIM1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => Cal_NIM1_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM1_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + + OBUFDS_inst_Cal_NIM2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => Cal_NIM2_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM2_n, -- Diff_n output (connect directly to top-level port) + I => not enable_sig -- Buffer input + ); + + + + + OBUFDS_inst_NIM_Out0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => NIM_Out0_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out0_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + + OBUFDS_inst_NIM_Out1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => NIM_Out1_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out1_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + + + + + OBUFDS_inst_Cal_0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_0_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_1_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_2_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_3_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_4 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_4_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_5 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_5_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_6 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_6_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + OBUFDS_inst_Cal_7 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_7_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig -- Buffer input + ); + + + + + + + + Inst_FTU_test2_dcm : FTM_test1_dcm + port map( + CLKIN_IN => clk, + CLKFX_OUT => clk_200M_sig, + CLKIN_IBUFG_OUT => open + ); + + + Inst_Clock_Divider : Clock_Divider + port map ( + clock => clk_200M_sig, + enable_out => enable_sig + ); + + +end Behavioral; + + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock : in std_logic; + enable_out: out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + --constant max_count : integer := 5000000/1000000; -- for simulation + constant max_count : integer := 2500/1; -- for implementation +-- constant final_count : integer := 100; + +begin + + process(clock) + variable count : integer range 0 to max_count; +-- variable count2 : integer range 0 to final_count; + begin + if rising_edge(clock) then + --enable_out <= '0'; +-- if count2 = final_count then +-- enable_out <= '0'; +-- else + if count < max_count/2 then + enable_out <= '0'; + count := count + 1; + elsif count < max_count then + enable_out <= '1'; + count := count + 1; + else + count := 0; + enable_out <= '0'; +-- count2 := count2 + 1; + end if; +-- end if; + end if; + end process; + +end architecture RTL; + Index: firmware/FTM/test_firmware/FTM_test2/FTM_test2_backup.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test2/FTM_test2_backup.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test2/FTM_test2_backup.vhd (revision 10046) @@ -0,0 +1,617 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 13 October 2010 +-- Design Name: +-- Module Name: FTU_test2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: +-- NIM and LVDS output stages +-- fast signal distribution (partially) +-- crate resets +-- +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FTM_test2 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC; -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow +-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- + Crate_Res0 : out STD_LOGIC; -- + Crate_Res1 : out STD_LOGIC; -- + Crate_Res2 : out STD_LOGIC; -- + Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration + Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ + Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- + Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ + Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs + NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ + NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- + NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ + NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- + RES_p : out STD_LOGIC; -- RES+ Reset + RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + + TRG_p : out STD_LOGIC; -- TRG+ Trigger + TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + + TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker + TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 + TIM_Sel : out STD_LOGIC; -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 + Cal_0_p : out STD_LOGIC; + Cal_0_n : out STD_LOGIC; + Cal_1_p : out STD_LOGIC; + Cal_1_n : out STD_LOGIC; + Cal_2_p : out STD_LOGIC; + Cal_2_n : out STD_LOGIC; + Cal_3_p : out STD_LOGIC; + Cal_3_n : out STD_LOGIC; + +-- to connector J12 + Cal_4_p : out STD_LOGIC; + Cal_4_n : out STD_LOGIC; + Cal_5_p : out STD_LOGIC; + Cal_5_n : out STD_LOGIC; + Cal_6_p : out STD_LOGIC; + Cal_6_n : out STD_LOGIC; + Cal_7_p : out STD_LOGIC; + Cal_7_n : out STD_LOGIC + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test2; + + + + + +architecture Behavioral of FTM_test2 is + + component FTM_test2_dcm + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); + end component; + + component Clock_Divider + port( + clock : IN STD_LOGIC; + enable_out : OUT STD_LOGIC + ); + end component; + + component Clock_Divider_2 + port( + clock : IN STD_LOGIC; + enable_out_2 : OUT STD_LOGIC + ); + end component; + + + signal clk_200M_sig : STD_LOGIC; + signal enable_sig : STD_LOGIC; + signal enable_sig2 : STD_LOGIC; + + +begin + + + + + + + + OBUFDS_inst_TRG : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => TRG_p, -- Diff_p output (connect directly to top-level port) + OB => TRG_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + + + OBUFDS_inst_RES : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => RES_p, -- Diff_p output (connect directly to top-level port) + OB => RES_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + + + OBUFDS_inst_TIM : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => TIM_Run_p, -- Diff_p output (connect directly to top-level port) + OB => TIM_Run_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + TIM_Sel <= '0'; + + Crate_Res0 <= enable_sig; + Crate_Res1 <= enable_sig; + Crate_Res2 <= enable_sig; + Crate_Res3 <= enable_sig; + + + + + + OBUFDS_inst_Cal_NIM1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => Cal_NIM1_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM1_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + + OBUFDS_inst_Cal_NIM2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => Cal_NIM2_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM2_n, -- Diff_n output (connect directly to top-level port) + I => not enable_sig2 -- Buffer input + ); + + + + + OBUFDS_inst_NIM_Out0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( + O => NIM_Out0_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out0_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + + OBUFDS_inst_NIM_Out1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => NIM_Out1_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out1_n, -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + + + + + OBUFDS_inst_Cal_0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_0_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_1_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_2_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_3_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_4 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_4_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_5 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_5_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_6 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_6_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + OBUFDS_inst_Cal_7 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_7_n , -- Diff_n output (connect directly to top-level port) + I => enable_sig2 -- Buffer input + ); + + + + + + + + + + + + + + + + + + Inst_FTU_test2_dcm : FTM_test2_dcm + port map( + CLKIN_IN => clk, + CLKFX_OUT => clk_200M_sig, + CLKIN_IBUFG_OUT => open + ); + + + Inst_Clock_Divider : Clock_Divider + port map ( + clock => clk_200M_sig, + enable_out => enable_sig + ); + + + Inst_Clock_Divider_2 : Clock_Divider_2 + port map ( + clock => clk_200M_sig, + enable_out_2 => enable_sig2 + ); + + + + +end Behavioral; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock : in std_logic; + enable_out: out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + --constant max_count : integer := 5000000/1000000; -- for simulation + constant max_count : integer := 250000/1; -- for implementation +-- constant final_count : integer := 100; + +begin + + process(clock) + variable count : integer range 0 to max_count; +-- variable count2 : integer range 0 to final_count; + begin + if rising_edge(clock) then + --enable_out <= '0'; +-- if count2 = final_count then +-- enable_out <= '0'; +-- else + if count < max_count/2 then + enable_out <= '0'; + count := count + 1; + elsif count < max_count then + enable_out <= '1'; + count := count + 1; + else + count := 0; + enable_out <= '0'; +-- count2 := count2 + 1; + end if; +-- end if; + end if; + end process; + +end architecture RTL; + + + + + +entity Clock_Divider_2 is + port( + clock : in std_logic; + enable_out_2 : out std_logic + ); +end entity Clock_Divider_2; + +architecture RTL of Clock_Divider_2 is + +constant max_count_2 : integer := 200/1; -- for implementation + +begin + + process(clock) + variable count_2 : integer range 0 to max_count_2; + + begin + if rising_edge(clock) then + if count_2 < max_count_2/2 then + enable_out_2 <= '0'; + count_2 := count + 1; + elsif count_2 < max_count then + enable_out_2 <= '1'; + count_2 := count_2 + 1; + else + count_2 := 0; + enable_out_2 <= '0'; + end if; + end if; + end process; + +end architecture RTL; Index: firmware/FTM/test_firmware/FTM_test2/FTM_test2_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test2/FTM_test2_dcm.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test2/FTM_test2_dcm.vhd (revision 10046) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_test1_dcm.vhd +-- /___/ /\ Timestamp : 08/16/2010 14:30:00 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test1/FTM_Test1_impl/ipcore_dir/FTM_test1_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test1/FTM_Test1_impl/ipcore_dir/FTM_test1_dcm +--Design Name: FTM_test1_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.17 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.69 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_test1_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTM_test1_dcm; + +architecture BEHAVIORAL of FTM_test1_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/test_firmware/FTM_test2/FTM_test2_dcm_arwz.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test2/FTM_test2_dcm_arwz.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test2/FTM_test2_dcm_arwz.ucf (revision 10046) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 1; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/test_firmware/FTM_test2/ftm_board_test2.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test2/ftm_board_test2.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test2/ftm_board_test2.ucf (revision 10046) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 5 October 2010 +# +# FTM Test 2: Trigger-Primitives and LVDS outputs +######################################################## + + +#Clock +####################################################### +NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red +# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+ +NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1- +NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+ +NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+ +NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0- +NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+ +NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +NET RES_p LOC = D16 | IOSTANDARD=LVDS_33; # RES+ Reset +NET RES_n LOC = C15 | IOSTANDARD=LVDS_33; # RES- IO-Bank 0 + +NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33; # TRG+ Trigger +NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33; # TRG- IO-Bank 0 + +NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker +NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33; # TIM_Run- + # on IO-Bank2 +NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33; # Cal_0+ +NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33; # Cal_0- +NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33; # Cal_1+ +NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33; # Cal_1- +NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33; # Cal_2+ +NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33; # Cal_2- +NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33; # Cal_3+ +NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33; # Cal_3- + +# to connector J12 +NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33; # Cal_4+ +NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33; # Cal_4- +NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33; # Cal_5+ +NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33; # Cal_5- +NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33; # Cal_6+ +NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33; # Cal_6- +NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33; # Cal_7+ +NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test3/#FTM_test3_microwire_controller.vhd# =================================================================== --- firmware/FTM/test_firmware/FTM_test3/#FTM_test3_microwire_controller.vhd# (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/#FTM_test3_microwire_controller.vhd# (revision 10046) @@ -0,0 +1,103 @@ + + +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +------------------------------------------------------------------------------- +-- +-- modified by Patrick Vogler +-- September 17 2010 +-- +-- modified to be used as a Microwire interface to control the clock +-- conditioner LMK03000 on the FTM board +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +ENTITY FTM_test3_microwire_controller IS + PORT( + -- clk : IN std_logic; -- 250MHz + clk_uwire : IN std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); +END FTM_test3_microwire_controller ; + + +ARCHITECTURE beha OF FTM_test3_microwire_controller IS + + type TYPE_uWire_STATE is (IDLE, LOAD_SHIFT_REG, SHIFT); + signal uwire_state : TYPE_uWire_STATE := IDLE; + signal register_count : integer range 0 to 8 := 0; + signal bit_count : integer range 0 to 31 := 0; + signal shift_reg : std_logic_vector (31 downto 0) := (others => '0'); + + +BEGIN + + uwire_write_proc: process (clk) + begin + + if falling_edge(clk_uwire) then + + case uwire_state is + + when IDLE => + + le_uwire <= '1'; + config_ready <= '1'; + config_started <= '0'; + bit_count <= 0; + register_count <= 0; + data_uwire <= '0'; + + if (config_start = '1') then + config_ready <= '0'; + uwire_state <= LOAD_SHIFT_REG; + end if; + + + when LOAD_SHIFT_REG => + bit_count <= 0; + config_started <= '1'; + le_uwire <= '0'; + shift_reg <= clk_cond_array(register_count)(31 downto 0); + register_count <= register_count + 1; + uwire_state <= SHIFT; + + + when SHIFT => + data_uwire <= shift_reg(31); + shift_reg <= shift_reg(30 downto 0) & shift_reg(31); + bit_count <= bit_count + 1; + if ((bit_count = 8)AND(register_count = 31)) then + uwire_state <= IDLE; + elsif ((bit_count = 8)AND(NOT(register_count = 31))) then + uwire_state <= LOAD_SHIFT_REG; + else + uwire_state <= SHIFT; + end if; + + end case; + end if; + + end process uwire_write_proc:; + +END ARCHITECTURE beha; Index: firmware/FTM/test_firmware/FTM_test3/FTM_definitions_test3.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_definitions_test3.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_definitions_test3.vhd (revision 10046) @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftm_array_types is + + + +--- std_logic_vector (31 downto 0) +--- type clk_cond_array_type is array (0 to 8) of integer range 0 to 2**32 - 1; + + type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0); + constant DEFAULT_Clk_Cond : clk_cond_array_type := (x"80000000", x"00038000", x"00010101", x"10000908", x"A0032A09", x"0082000B", x"020A000D", x"0830280E", x"1400FA0F"); + -- This array contains the settings to be leaded in the clock conditioner + -- LMK03000 on the FTM board + -- The entrys of the array are: + -- R0 for Reset only, i.e. only bit 31 is set this resets the LMK0300 + -- R0 + -- R1 + -- R8 + -- R9 + -- R11 + -- R13 + -- R14 + -- R15 + -- constant DEFAULT_Clk_Cond : clk_cond_array_type := (x"80000000", x"00010100", x"00010101", x"10000908", x"A0032A09", x"0082000B", x"020A000D", x"0830280E", x"2000960F"); +-- OLD: constant DEFAULT_Clk_Cond : clk_cond_array_type := (x"80000000", x"00038000", x"00010101", x"10000908", x"A0032A09", x"0082000B", x"020A000D", x"1830280E", x"1400FA0F"); +end ftm_array_types; Index: firmware/FTM/test_firmware/FTM_test3/FTM_test3.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_test3.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_test3.vhd (revision 10046) @@ -0,0 +1,422 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 17 September 2010 +-- Design Name: +-- Module Name: FTM_test3 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: first test of the clock conditioner +-- LMK03000 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +library FTM_definitions_test3; +USE FTM_definitions_test3.ftm_array_types.all; + + + +entity FTM_test3 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC; -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow + LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- + CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock + LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable + DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization + LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration +-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ +-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- +-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ +-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs +-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ +-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- +-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ +-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 + TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test3; + + +architecture Behavioral of FTM_test3 is + + component FTM_test1_dcm + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); + end component; + + +component FTM_test3_microwire_interface IS + PORT( + clk : IN std_logic; + clk_uwire : OUT std_logic; --- IN or OUT ? + data_uwire : OUT std_logic; + le_uwire : OUT std_logic; + clk_cond_array : IN clk_cond_array_type; + config_start : IN std_logic; + config_ready : OUT std_logic; + config_started : OUT std_logic + ); +end component; + + + + + signal clk_250M_sig : STD_LOGIC; +-- signal enable_sig : STD_LOGIC; + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + + type FTM_test3_StateType is (Running); + signal FTM_test3_State, FTM_test3_NextState: FTM_test3_StateType; + + signal config_ready_sig : STD_LOGIC; + signal clk_uwire_sig : STD_LOGIC; + + signal clk_cond_array_sig : clk_cond_array_type; + + signal config_puls_cnt : integer range 0 to 2000 := 0; + + + +begin + + Inst_FTM_test1_dcm : FTM_test1_dcm + port map( + CLKIN_IN => clk, + CLKFX_OUT => clk_250M_sig, + CLKIN_IBUFG_OUT => open + ); + + + + Inst_FTM_test3_microwire_interface:FTM_test3_microwire_interface + port map ( + clk => clk_250M_sig, + clk_uwire => clk_uwire_sig, + data_uwire => DATA_Clk_Cond, + le_uwire => LE_Clk_Cond, + clk_cond_array => clk_cond_array_sig, -- default array 2GHz DRS and 250MHz TIM + + config_start => reset_sig, + config_ready => config_ready_sig, + config_started => open + ); + + + LED_gn(0) <= NOT (config_ready_sig AND LD_Clk_Cond); -- indicate that PLL is locked + TIM_Sel <= '1'; -- timing calibration signal from Clock + -- conditioner on TIM line + + LED_gn(1) <= '1'; -- switch off unused green LED + + CLK_Clk_Cond <= clk_uwire_sig; + clk_cond_array_sig <= DEFAULT_Clk_Cond; -- Default Clock conditioner settings + -- 2 GHz DRS and 250 MHz TIM + + + + + + + +--FTM main state machine + FTM_test3_Registers: process (clk_250M_sig) + begin + if Rising_edge(clk_250M_sig) then + if (config_puls_cnt < 2000) then + config_puls_cnt <= config_puls_cnt + 1; + end if; + + if (config_puls_cnt < 1000) then + reset_sig <= '0'; + elsif ((config_puls_cnt > 999) and (config_puls_cnt < 1900)) then + reset_sig <= '1'; + else + reset_sig <= '0'; + end if; + + end if; + end process FTM_test3_Registers; + + + + + + + + + + + + + + + + --FTU main state machine (two-process implementation) + +-- FTM_test3_Registers: process (clk_250M_sig) -- TBR +-- begin +-- if Rising_edge(clk_250M_sig) then +-- FTM_test3_State <= FTM_test3_NextState; +-- end if; +-- end process FTM_test3_Registers; + +-- FTM_test3_C_logic: process (FTM_test3_State) +-- begin +-- FTM_test3_NextState <= FTM_test3_State; +-- case FTM_test3_State is +-- when Running => +-- reset_sig <= '0'; +-- end case; +-- end process FTM_test3_C_logic; + + + + + + + + + +end Behavioral; + + Index: firmware/FTM/test_firmware/FTM_test3/FTM_test3_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_test3_dcm.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_test3_dcm.vhd (revision 10046) @@ -0,0 +1,88 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_test1_dcm.vhd +-- /___/ /\ Timestamp : 08/16/2010 14:30:00 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test1/FTM_Test1_impl/ipcore_dir/FTM_test1_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test1/FTM_Test1_impl/ipcore_dir/FTM_test1_dcm +--Design Name: FTM_test1_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_test1_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.17 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.69 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_test1_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic); +end FTM_test1_dcm; + +architecture BEHAVIORAL of FTM_test1_dcm is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/test_firmware/FTM_test3/FTM_test3_dcm_arwz.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_test3_dcm_arwz.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_test3_dcm_arwz.ucf (revision 10046) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +# INST DCM_SP_INST CLK_FEEDBACK = NONE; +# INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +# INST DCM_SP_INST CLKFX_DIVIDE = 1; +# INST DCM_SP_INST CLKFX_MULTIPLY = 5; +# INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +# INST DCM_SP_INST CLKIN_PERIOD = 20.000; +# INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +# INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +# INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +# INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +# INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +# INST DCM_SP_INST FACTORY_JF = C080; +# INST DCM_SP_INST PHASE_SHIFT = 0; +# INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_clock_gen.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_clock_gen.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_clock_gen.vhd (revision 10046) @@ -0,0 +1,58 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Patrick Vogler +-- September 16 2010 +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +library FTM_definitions_test3; +USE FTM_definitions_test3.ftm_array_types.all; + + + + +ENTITY FTM_test3_microwire_clock_gen IS + GENERIC( + CLK_DIVIDER : integer := 125 --2 MHz @ 250 MHz + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END FTM_test3_microwire_clock_gen; + +ARCHITECTURE beha OF FTM_test3_microwire_clock_gen IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_controller.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_controller.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_controller.vhd (revision 10046) @@ -0,0 +1,108 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +------------------------------------------------------------------------------- +-- +-- modified by Patrick Vogler +-- September 17 2010 +-- +-- modified to be used as a Microwire interface to control the clock +-- conditioner LMK03000 on the FTM board +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +library FTM_definitions_test3; +USE FTM_definitions_test3.ftm_array_types.all; + + + +ENTITY FTM_test3_microwire_controller IS + PORT( + -- clk : IN std_logic; -- 250MHz + clk_uwire : IN std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); +END FTM_test3_microwire_controller ; + + +ARCHITECTURE beha OF FTM_test3_microwire_controller IS + + type TYPE_uWire_STATE is (IDLE, LOAD_SHIFT_REG, SHIFT); + signal uwire_state : TYPE_uWire_STATE := IDLE; + signal register_count : integer range 0 to 9 := 0; + signal bit_count : integer range 0 to 32 := 0; + signal shift_reg : std_logic_vector (31 downto 0) := (others => '0'); + + +BEGIN + + uwire_write_proc: process (clk_uwire) + begin + + if falling_edge(clk_uwire) then + + case uwire_state is + + when IDLE => + + le_uwire <= '1'; + config_ready <= '1'; + config_started <= '0'; + bit_count <= 0; + register_count <= 0; + data_uwire <= '0'; + + if (config_start = '1') then + config_ready <= '0'; + uwire_state <= LOAD_SHIFT_REG; + end if; + + + when LOAD_SHIFT_REG => + bit_count <= 0; + config_started <= '1'; + shift_reg <= clk_cond_array(register_count)(31 downto 0); + register_count <= register_count + 1; +-- le_uwire <= '0'; + uwire_state <= SHIFT; + + + when SHIFT => + data_uwire <= shift_reg(31); + le_uwire <= '0'; + shift_reg <= shift_reg(30 downto 0) & shift_reg(31); + bit_count <= bit_count + 1; + if ((bit_count = 32)AND(register_count = 9)) then + le_uwire <= '1'; + uwire_state <= IDLE; + elsif ((bit_count = 32)AND(NOT(register_count = 9))) then + le_uwire <= '1'; + uwire_state <= LOAD_SHIFT_REG; + else + uwire_state <= SHIFT; + end if; + + end case; + end if; + + end process uwire_write_proc; + +END ARCHITECTURE beha; Index: firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_interface.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_interface.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_interface.vhd (revision 10046) @@ -0,0 +1,112 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/14/2010 +-- Design Name: +-- Module Name: FTM_test3_microwire_interface - Behavioral +-- (based on FTU_test5_spi_interface - Behavioral) +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- modified by Patrick Vogler, September 17 2010 +-- for use as a microwire interface to the clock conditioner LMK03000 +-- on the FTM board +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library FTM_definitions_test3; +USE FTM_definitions_test3.ftm_array_types.all; + +------------------------------------------------------------------------------- +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY FTM_test3_microwire_interface IS + PORT( + clk : IN std_logic; -- 250MHz + clk_uwire : OUT std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); +END FTM_test3_microwire_interface; + + +ARCHITECTURE struct OF FTM_test3_microwire_interface IS + + -- Internal signal declarations + SIGNAL clk_uwire_sig : std_logic; + + + -- Component Declarations + COMPONENT FTM_test3_microwire_clock_gen + GENERIC ( + CLK_DIVIDER : integer := 125 --2 MHz @ 250 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + + + COMPONENT FTM_test3_microwire_controller + PORT ( + clk_uwire : IN std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); + END COMPONENT; + + + +BEGIN + + -- Instance port mappings. + Inst_FTM_test3_microwire_clock_gen : FTM_test3_microwire_clock_gen + GENERIC MAP ( + CLK_DIVIDER => 125 --2 MHz @ 250 MHz + ) + PORT MAP ( + clk => clk, + sclk => clk_uwire_sig + ); + + Inst_FTM_test3_microwire_controller : FTM_test3_microwire_controller + PORT MAP ( + clk_uwire => clk_uwire_sig, + data_uwire => data_uwire, + le_uwire => le_uwire, + clk_cond_array => clk_cond_array, + config_start => config_start, + config_ready => config_ready, + config_started => config_started + ); + + clk_uwire<= clk_uwire_sig; + +END struct; Index: firmware/FTM/test_firmware/FTM_test3/ftm_board_test3.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test3/ftm_board_test3.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test3/ftm_board_test3.ucf (revision 10046) @@ -0,0 +1,405 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 18 August 2010 +######################################################## + + +#Clock +####################################################### +NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red +# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- + # on IO-Bank2 +NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test4/FTM_test4.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test4/FTM_test4.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/FTM_test4.vhd (revision 10046) @@ -0,0 +1,404 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 12 October 2010 +-- Design Name: +-- Module Name: FTM_test4 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: first of the ethernet interface +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- library FTM_definitions_test3; +-- USE FTM_definitions_test3.ftm_array_types.all; + + + +entity FTM_test4 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus + W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus + W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 + W_CS : out STD_LOGIC; -- W5300 chip select + W_INT : IN STD_LOGIC; -- interrupt + W_RD : out STD_LOGIC; -- read + W_WR : out STD_LOGIC; -- write + W_RES : out STD_LOGIC -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow +-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration +-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ +-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- +-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ +-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs +-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ +-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- +-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ +-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 +-- TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test4; + + +architecture Behavioral of FTM_test4 is + +-- dcm 40 MHz -> 50 MHz +component FTM_test4_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic); +end component; + +-- w5300 +component w5300_modul IS + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic; + addr : OUT std_logic_vector (9 DOWNTO 0); -- Address 0 unused + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic; + wr : OUT std_logic; + led : OUT std_logic_vector (7 DOWNTO 0); + rd : OUT std_logic; + int : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (13 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (13 DOWNTO 0); + data_valid : IN std_logic; + data_valid_ack : OUT std_logic; + busy : OUT std_logic; + write_header_flag, write_end_flag : IN std_logic; + fifo_channels : IN std_logic_vector (3 downto 0); + s_trigger : OUT std_logic; + new_config : OUT std_logic; + config_started : in std_logic; + config_addr : out std_logic_vector (7 downto 0); + config_data : inout std_logic_vector (15 downto 0); + config_wr_en : out std_logic; + config_rd_en : out std_logic; + -- -- + config_rw_ack, config_rw_ready : in std_logic; + -- -- + config_busy : in std_logic + ); +end component; + + +signal CLK_50_internal : STD_LOGIC; +signal W5300_address : std_logic_vector (9 downto 0); + +begin + + Inst_FTM_test4_dcm : FTM_test4_dcm + port map( + CLKIN_IN => clk, + CLKFX_OUT => CLK_50_internal, + CLKIN_IBUFG_OUT => open, + CLK0_OUT => open + ); + + + + I_main_ethernet : w5300_modul +-- GENERIC MAP ( +-- RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 +-- ) + PORT MAP ( + clk => CLK_50_internal, + wiz_reset => W_RES, -- + addr => W5300_address, -- Address 0 ?? shift_reg <= shift_reg(30 downto 0) & shift_reg(31); + data => W_D, -- + cs => W_CS, -- + wr => W_WR, -- + led => open, -- + rd => W_RD, -- + int => W_INT, -- + write_length => "00000000000000001", -- + ram_start_addr => "00000000000000", -- + ram_data => "0000000000000000", -- + ram_addr => open, -- + data_valid => '0', + data_valid_ack => open, -- + busy => open, -- + write_header_flag => '0', + write_end_flag => '0', + fifo_channels => "0000", -- + s_trigger => open, -- + new_config => open, -- + config_started => '0', + config_addr => open, -- + config_data => open, -- inout open ?? + config_wr_en => open, -- + config_rd_en => open, -- + config_busy => '0', -- + + config_rw_ack => '0', + config_rw_ready => '0' + + -- denable => denable, + -- dwrite_enable => dwrite_enable, + -- sclk_enable => sclk_enable + ); + + W_A <= W5300_address (9 downto 1); + +--FTM main state machine +-- FTM_test4_Registers: process (clk_250M_sig) +-- begin +-- if Rising_edge(clk_250M_sig) then +-- if (config_puls_cnt < 2000) then +-- config_puls_cnt <= config_puls_cnt + 1; +-- end if; +-- +-- if (config_puls_cnt < 1000) then +-- reset_sig <= '0'; +-- elsif ((config_puls_cnt > 999) and (config_puls_cnt < 1900)) then +-- reset_sig <= '1'; +-- else +-- reset_sig <= '0'; +-- end if; +-- +-- end if; +-- end process FTM_test4_Registers; + +end Behavioral; + + Index: firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.vhd (revision 10046) @@ -0,0 +1,96 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_test4_dcm.vhd +-- /___/ /\ Timestamp : 10/11/2010 13:44:50 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/ISDC_repos/firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.xaw /ihp/home01/pavogler/ISDC_repos/firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm +--Design Name: FTM_test4_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_test4_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_test4_dcm is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic); +end FTM_test4_dcm; + +architecture BEHAVIORAL of FTM_test4_dcm is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.xaw =================================================================== --- firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.xaw (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm.xaw (revision 10046) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$9:x13=(aaz$dbcj00-sesi`dlx$E^JL_sgskv)aa{g|mk FUO,p`usWocyazo}e.DWIZrb{}>$JYCPtdqw0Zbde'rj{<5?4:2-412<8'2==6?;;03-1==6>.bH<5>=;0Z2?70<:<$;<=?4439744=2:2?;;6O]CIUJ^418:CQS_YHFESTOAEFN^G[P@TIIE;>7L\XZ^MMH\YDDBCES[OCUD3a?DTPRVEE@TQKCL]PSLRD@@DLSNBD119BVR\XGGFRSIJ]_B224>GU_SUDBAWPDEP\G4763HX\VRAALX]G@WYDDB;=7L\XZ^MMH\YCL[UM@D^ILNR21>GU_SUDBAWPFC]F\QCUFHF:>6O]W[]LJI_XAGY_SC[Be:CQS_YHFEST\@MK149BVR\XGGFRS_K\EU]OKBOD911J^ZTPOONZ[SGKAMUOJ^QBOEGb?DUTGJU\EYFi;@UY[FJLJ\L_U]K>179BS_YDDBH^JYW_E0]MK@BN\890MZTPCMI\KPRW]]U_U]Kl;@UY[CJH_]S[I55NW[]SEWRc3H]QS^WATIVLKI2EKC;=;96MCK3Z;?FJL:Q;3<85LLJ;31>EKCM\h7NBDDW]GMSOCM<1H@FHM8:AOOCDXAG?0OAEIX99@HN@_91:27NBDFY]AQC`EKC@DT__MPTXRF57=DDBE^XR^GARG\WMOA\j1H@FQIEDFAEFM>3JEFADZ[EE58GWCF\LN=7IMB_RRa?AEJWZZTEC][d:FFWNCPWHNAY^Z>2:FEWZ@UMX_NBNWPMNFFe>BKDVKEHRHW139GHIYAZL[^ICMV_LMGA0=C[ZOE=85KUU[\G\EKMVID^_KLTHMM3>BX^HF^I55JXUGQJDJf3OKHXB\V_KD6?CGK[L30JOQ\OTP@Af=AMLNIMNEPBTD:?COIW\DBX^64FNWW[VRUi2LDYYQZNHVPe>@H]]U]MA[J1:K6?LDRNN20ECZJROCO54=MA]^N^RGAPTV\P\VBk2@BXYK]_QI1TNeJHIMOO:6B@CJGG7>JH_:1FDW94M^TBHPC03GO_[B\D4:LLJ@75]SU`8WLABP]OYBLB9;RKMCICd3Z^J^Y[__VCJP3=T\H^^_<<4SXQWAHYTQGIC^B@@UR18PJV33]X^I55ZSD]AQCA>3\YNSO[IGR78RLCP9k1SMZQYESQJKK7c3QCGECV"XE@#4+7'[]_I,= > @Q@ML0]729W>7V>57\68ewq};2nhao5yesqjkk&6&9>0zejc109{g6uc;=:;m :ig7557>~t|tJK|>94@Az3>C<328qX89472;:7>455j>386<9=62ym3`<63g=m685+7e84g>{T<:03>76;:011f2?428hjjk5\5e8;6?>32899n:7<:0`f<1=T<:03>76;:011f2?428hm=?5k8383>4<6sZ>?65<5858277d01:0:;?8<;wV4e?6=93;14v];4;:1>=2=9:8i;4=516057>d0>3:1<7:58z&f>=5<,;:1485+208;2>"5:32<7)9m:49a03<72891<7>t$7c900=#n38n7)??:608 44=:<1/=>4=5:&20?4>3-;>6?;4$04920=#9>0<>6*>8;68 4?=>:1/=l4:0:&2f?443->96:5+2g8;?!512h1/?:4l;%1b>06<,:l156*;0;6f?!262?90(995749'0a<33->368h4$5c91c=#490:&61?073-?=6i5+5`860>"193k0(;851:&47?373-=36:74$039f>"6n3>27);l:39'1g<43`926=4+688;4>"1j3=<76g<0;29 3?=091/:o487:9j35<72-<265>4$7:932==07d8i:18'2<=n=?>10c?;50;&5=?>73->65`2e83>!0>21:07b<6:18'2<l4?:%4:>=6<3f8n6=4+688;4>=h:k0;6)86:928?j4d290/:4470:9l77<72-<265>4$7`932=#9m09865`3283>!0>21:07b9;:18'2<7<729q/:l4:8:k63?6=,?314=5+6c843>=h>=0;6)86:928 3d=?>10qo<8:181>5<7s-5}#>h0986g:7;29 3?=091/:o487:9l21<72-<265>4$7`932=6?<5:i1:95+1b80`>{t;80;6?u247804>;5?31v>:50;0x910=;;16?84:7:p7`<728q6?n4:7:&45?303ty847>51z?01?033-=:6;:4}r1g>5<7s-=:6;:4}r0;>5<7s-=:6;:4}|l13?6=9rwe>54?:0y~j7?=83;pqc4}zf;n1<7?t}o0f>5<6stwvqMNL{25904e>?lo=qMNM{1CDU}zHI Index: firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm_arwz.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm_arwz.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/FTM_test4_dcm_arwz.ucf (revision 10046) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 4; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/test_firmware/FTM_test4/ftm_board_test4.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test4/ftm_board_test4.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/ftm_board_test4.ucf (revision 10046) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 4 October 2010 +# +# Pin location for FTM test 4 (ethernet controller) +######################################################## + + +#Clock +####################################################### +NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red +# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- + # on IO-Bank2 +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test4/ftm_test4_definitions.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test4/ftm_test4_definitions.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/ftm_test4_definitions.vhd (revision 10046) @@ -0,0 +1,117 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- use IEEE.NUMERIC_STD.ALL; + +package ftm_definitions is + + +-- Declare constants + +-- Network Settings + type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); + constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); + + type ip_type is array (0 to 3) of integer; + constant NETMASK : ip_type := (255, 255, 248, 0); + constant IP_ADDRESS : ip_type := (192, 33, 99, 226); + constant GATEWAY : ip_type := (192, 33, 96, 1); + constant FIRST_PORT : integer := 5000; + + constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; + constant PACKAGE_HEADER_LENGTH : integer := 22; + constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag + + constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset + +-- W5300 Registers + constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); + constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; + constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; + constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; + constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; + constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; + constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; + constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; + constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; + constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; + constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; + constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; + constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; + constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; + constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; + constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; + constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; + constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; + constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; + + constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; + constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; + constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; + constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; + constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; + constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; + constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; + constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; + constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; + constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; + constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; + constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; + constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; +-- End W5300 registers + +-- + constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes + constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words + + constant RAM_SIZE_64B : integer := 4096; + constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; + + + + + +-- TYPE definitions +-- type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0); +-- type roi_array_type is array (0 to 35) of integer range 0 to 1024; +-- type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0); +-- type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0); + +-- type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1; +-- type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; + +-- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106, +-- 181, 121, 189, 101, 101, 187, 56, 187, 101, +-- 2, 141, 101, 100, 10, 100, 178, 101, 174, +-- 12, 181, 100, 102, 101, 102, 0, 101, 108); +-- constant DEFAULT_ROI : roi_array_type := (others => 50); + +-- constant DEFAULT_DAC : dac_array_type := (5001, 5002, 5003, 5004, 5005, 5006, 5007, 5008); +-- constant DEFAULT_DAC : dac_array_type := (others => 0); + +-- Commands + constant CMD_START : std_logic_vector := X"C0"; + constant CMD_STOP : std_logic_vector := X"30"; + constant CMD_TRIGGER : std_logic_vector := X"A0"; + constant CMD_TRIGGER_C : std_logic_vector := X"B0"; + constant CMD_TRIGGER_S : std_logic_vector := X"20"; + constant CMD_READ : std_logic_vector := X"0A"; + constant CMD_WRITE : std_logic_vector := X"05"; + +-- DRS Registers +-- constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; + +-- Declare functions and procedure + + +end ftm_definitions; + + Index: firmware/FTM/test_firmware/FTM_test4/w5300_modul.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test4/w5300_modul.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test4/w5300_modul.vhd (revision 10046) @@ -0,0 +1,833 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:48:48 11/10/2009 +-- Design Name: +-- Module Name: w5300_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftm_test4_definitions; +use ftm_test4_definitions.ftm_definitions.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY w5300_modul IS + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (13 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (13 DOWNTO 0); + data_valid : IN std_logic; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag, write_end_flag : IN std_logic; + fifo_channels : IN std_logic_vector (3 downto 0); + s_trigger : OUT std_logic := '0'; + new_config : OUT std_logic := '0'; + config_started : in std_logic; + config_addr : out std_logic_vector (7 downto 0); + config_data : inout std_logic_vector (15 downto 0) := (others => 'Z'); + config_wr_en : out std_logic := '0'; + config_rd_en : out std_logic := '0'; + -- -- + config_rw_ack, config_rw_ready : in std_logic; + -- -- + config_busy : in std_logic + ); + +-- Declarations + +END w5300_modul ; + +architecture Behavioral of w5300_modul is + +type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); +type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); +type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); +type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); + +signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; + +signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); +signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal adc_data_addr : std_logic_vector (13 DOWNTO 0); + +signal state_init, next_state , next_state_tmp : state_init_type := RESET; +signal count : std_logic_vector (2 downto 0) := "000"; +signal state_write : state_write_type := WR_START; +signal state_interrupt_1 : state_interrupt_1_type := IR1_01; +signal state_interrupt_2 : state_interrupt_2_type := IR2_01; +signal state_read_data : state_read_data_type := RD_1; + +signal interrupt_ignore : std_logic := '1'; +signal int_flag : std_logic := '0'; +signal ram_access : std_logic := '0'; + +signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); +signal data_cnt : integer := 0; +signal drs_cnt : integer :=0; +signal channel_cnt : integer range 0 to 9 :=0; +signal socket_cnt : std_logic_vector (2 downto 0) := "000"; +signal roi_max : std_logic_vector (10 downto 0); +signal data_end : integer := 0; + +signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); +signal write_length_bytes : std_logic_vector (16 downto 0); + +signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); +signal chk_recv_cntr : integer range 0 to 10000 := 0; + +-- -- +signal wait_cntr : integer range 0 to 10000 := 0; +-- -- + +signal rx_packets_cnt : std_logic_vector (15 downto 0); +signal next_packet_data : std_logic := '0'; +signal new_config_flag : std_logic := '0'; + +signal trigger_stop : std_logic := '1'; + +signal local_write_length : std_logic_vector (16 DOWNTO 0); +signal local_ram_start_addr : std_logic_vector (13 DOWNTO 0); +signal local_ram_addr : std_logic_vector (13 downto 0); +signal local_socket_nr : std_logic_vector (2 DOWNTO 0); +signal local_write_header_flag, local_write_end_flag : std_logic; +signal local_fifo_channels : std_logic_vector (3 downto 0); + +signal data_valid_int : std_logic := '0'; + +-- only for debugging +--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); +--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0'); + + +begin + + --synthesis translate_off + RST_TIME <= X"00120"; + --synthesis translate_on + + + w5300_init_proc : process (clk, int) + begin + + if rising_edge (clk) then + + + -- Interrupt low + if (int = '0') and (interrupt_ignore = '0') then + case state_interrupt_1 is + when IR1_01 => + int_flag <= '1'; + busy <= '1'; + state_interrupt_1 <= IR1_02; + when IR1_02 => + state_interrupt_1 <= IR1_03; + when IR1_03 => + state_init <= INTERRUPT; + socket_cnt <= "000"; + ram_access <= '0'; + zaehler <= X"00000"; + count <= "000"; + int_flag <= '0'; + interrupt_ignore <= '1'; + state_interrupt_1 <= IR1_04; + when others => + null; + end case; + end if; -- int = '0' + + if int_flag = '0' then + case state_init is + -- Interrupt + when INTERRUPT => + case state_interrupt_2 is + when IR2_01 => + par_addr <= W5300_IR; + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_02; + when IR2_02 => + if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_03; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_02; + end if; + end if; + when IR2_03 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_04; + when IR2_04 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + par_data <= data_read; -- clear Interrupts + state_init <= WRITE_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_05; + when IR2_05 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0010"; -- CLOSE + state_init <= WRITE_REG; + next_state <= INTERRUPT; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_01; + end if; + + when IR2_06 => + state_interrupt_1 <= IR1_01; + state_interrupt_2 <= IR2_01; + socket_cnt <= "000"; + state_init <= RESET; + end case; + + -- reset W5300 + when RESET => + busy <= '1'; + zaehler <= zaehler + 1; + wiz_reset <= '0'; +-- led <= X"FF"; + if (zaehler >= X"00064") then -- wait 2s + wiz_reset <= '1'; + end if; + if (zaehler = RST_TIME) then -- wait 10ms + zaehler <= X"00000"; + socket_cnt <= "000"; + count <= "000"; + ram_access <= '0'; + interrupt_ignore <= '0'; + rd <= '1'; + wr <= '1'; + cs <= '1'; + state_write <= WR_START; + state_init <= INIT; + end if; + + -- Init + when INIT => + par_addr <= W5300_MR; + par_data <= X"0000"; + state_init <= WRITE_REG; + next_state <= IM; + + -- Interrupt Mask + when IM => + par_addr <= W5300_IMR; + par_data <= X"00FF"; -- S0-S7 Interrupts + state_init <= WRITE_REG; + next_state <= MT; + + -- Memory Type + when MT => + par_addr <= W5300_MTYPER; + par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer + state_init <= WRITE_REG; + next_state <= STX; + + -- Socket TX Memory Size + when STX => + par_data <= X"0F0F"; -- 15K TX + + par_addr <= W5300_TMS01R; + state_init <=WRITE_REG; + next_state <= STX1; + when STX1 => + par_addr <= W5300_TMS23R; + state_init <=WRITE_REG; + next_state <= STX2; + when STX2 => + par_addr <= W5300_TMS45R; + state_init <=WRITE_REG; + next_state <= STX3; + when STX3 => + par_addr <= W5300_TMS67R; + state_init <=WRITE_REG; + next_state <= SRX; + + -- Socket RX Memory Size + when SRX => + par_data <= X"0101"; -- 1K RX + + par_addr <= W5300_RMS01R; + state_init <=WRITE_REG; + next_state <= SRX1; + when SRX1 => + par_addr <= W5300_RMS23R; + state_init <=WRITE_REG; + next_state <= SRX2; + when SRX2 => + par_addr <= W5300_RMS45R; + state_init <=WRITE_REG; + next_state <= SRX3; + when SRX3 => + par_addr <= W5300_RMS67R; + state_init <=WRITE_REG; + next_state <= MAC; + + -- MAC + when MAC => + par_addr <= W5300_SHAR; + par_data <= MAC_ADDRESS (0); + state_init <= WRITE_REG; + next_state <= MAC1; + when MAC1 => + par_addr <= W5300_SHAR + 2; + par_data <= MAC_ADDRESS (1); + state_init <= WRITE_REG; + next_state <= MAC2; + when MAC2 => + par_addr <= W5300_SHAR + 4; + par_data <= MAC_ADDRESS (2); + state_init <= WRITE_REG; + next_state <= GW; + + -- Gateway + when GW => + par_addr <= W5300_GAR; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8); + state_init <= WRITE_REG; + next_state <= GW1; + when GW1 => + par_addr <= W5300_GAR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8); + state_init <= WRITE_REG; + next_state <= SNM; + + -- Subnet Mask + when SNM => + par_addr <= W5300_SUBR; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8); + state_init <= WRITE_REG; + next_state <= SNM1; + when SNM1 => + par_addr <= W5300_SUBR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8); + state_init <= WRITE_REG; + next_state <= IP; + -- Own IP-Address + when IP => + par_addr <= W5300_SIPR; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8); + state_init <= WRITE_REG; + next_state <= IP1; + when IP1 => + par_addr <= W5300_SIPR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); + state_init <= WRITE_REG; + next_state <= SI; +-- when TIMEOUT => +-- par_addr <= W5300_RTR; +-- par_data <= X"07D0"; -- 0x07D0 = 200ms +-- state_init <= WRITE_REG; +-- next_state <= RETRY; +-- when RETRY => +-- par_addr <= W5300_RCR; +-- par_data <= X"0008"; +-- state_init <= WRITE_REG; +-- next_state <= SI; +-- + + -- Socket Init + when SI => + par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + par_data <= X"0101"; -- ALIGN, TCP + state_init <= WRITE_REG; + next_state <= SI1; + -- Sx Interrupt Mask + when SI1 => + par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + par_data <= X"000A"; -- TIMEOUT, DISCON + state_init <= WRITE_REG; + next_state <= SI2; + when SI2 => + par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + state_init <= WRITE_REG; + next_state <= SI3; + when SI3 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0001"; -- OPEN + state_init <= WRITE_REG; + next_state <= SI4; + when SI4 => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= SI5; + when SI5 => + if (data_read (7 downto 0) = X"13") then -- is open? + state_init <= SI6; + else + state_init <= SI4; + end if; + when SI6 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0002"; -- LISTEN + state_init <= WRITE_REG; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + socket_cnt <= "000"; + next_state <= ESTABLISH; -- All Sockets open + else + next_state <= SI; -- Next Socket + end if; + -- End Socket Init + + when ESTABLISH => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= EST1; + when EST1 => +-- led <= data_read (7 downto 0); +-- led <= X"00"; + case data_read (7 downto 0) is + when X"17" => -- established + if (socket_cnt = 7) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; + when others => + state_init <= ESTABLISH; + end case; + + when CONFIG => + new_config <= '1'; + if (config_started = '1') then + new_config <= '0'; + state_init <= MAIN; + end if; + + -- main "loop" + when MAIN => + if (trigger_stop = '1') then + s_trigger <= '0'; + end if; + data_valid_ack <= '0'; + state_init <= MAIN1; + data_valid_int <= data_valid; + when MAIN1 => + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + chk_recv_cntr <= chk_recv_cntr + 1; + state_init <= MAIN2; + end if; + when MAIN2 => + busy <= '0'; + if (data_valid = '1') then + data_valid_int <= '0'; + busy <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; +-- data_valid_ack <= '1'; +-- next_state <= MAIN; +-- state_init <= WRITE_DATA; + state_init <= MAIN3; + else + state_init <= MAIN1; + end if; + when MAIN3 => +-- led <= local_ram_start_addr (7 downto 0); + data_valid_ack <= '1'; + next_state <= MAIN; + state_init <= WRITE_DATA; + + + -- read data from socket 0 + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_6; + else + state_read_data <= RD_END; + end if; + when RD_6 => + -- read command + if (next_packet_data = '0') then + case data_read (15 downto 8) is + when CMD_TRIGGER => + trigger_stop <= '1'; + s_trigger <= '1'; + state_read_data <= RD_5; + when CMD_TRIGGER_C => + trigger_stop <= '0'; + s_trigger <= '1'; + state_read_data <= RD_5; + when CMD_TRIGGER_S => + trigger_stop <= '1'; + state_read_data <= RD_5; + when CMD_WRITE => + next_packet_data <= '1'; + config_addr <= data_read (7 downto 0); + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; + -- read data + else + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + next_packet_data <= '0'; + state_read_data <= RD_WAIT; + end if; + end if; + when RD_WAIT => + if (config_rw_ack = '1') then + state_read_data <= RD_WAIT1; + end if; + when RD_WAIT1 => + if (config_rw_ready = '1') then + config_data <= (others => 'Z'); + config_wr_en <= '0'; + state_read_data <= RD_5; + end if; + when RD_END => + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else + next_state <= MAIN; + end if; + + end case; -- state_data_read + + + + when WRITE_DATA => + case state_write is + when WR_START => + if (local_write_header_flag = '1') then + ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? + end if; + state_write <= WR_WAIT1; + when WR_WAIT1 => + state_write <= WR_LENGTH; + when WR_LENGTH => + if (local_write_header_flag = '1') then + local_socket_nr <= ram_data (2 downto 0); +-- local_socket_nr <= "000"; + end if; + next_state_tmp <= next_state; + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_cnt <= 0; + state_write <= WR_01; + -- Check FIFO Size + when WR_01 => + par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_02; + when WR_02 => + socket_tx_free (31 downto 16) <= data_read; + par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_03; + when WR_03 => + socket_tx_free (15 downto 0) <= data_read; + state_write <= WR_04; + when WR_04 => + +-- led <= socket_tx_free (15 downto 8); + +-- if (socket_tx_free (16 downto 0) < write_length_bytes) then + if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then + state_write <= WR_01; + else + if (local_write_header_flag = '1') then + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + end if; + + -- Fill FIFO + + -- Write Header + when WR_FIFO => + ram_addr <= local_ram_start_addr + local_ram_addr; + state_write <= WR_FIFO1; + when WR_FIFO1 => + data_cnt <= data_cnt + 1; + if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? + local_ram_addr <= local_ram_addr + 1; + if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words + local_ram_addr <= local_ram_addr + 2; + end if; + if (data_cnt = 9) then -- skip empty words + local_ram_addr <= local_ram_addr + 4; + end if; + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO; + else + state_write <= WR_ADC; + end if; + -- End Write Header + + -- Write ADC-Data + ---- Start... + when WR_ADC => + adc_data_addr <= local_ram_start_addr + local_ram_addr; + drs_cnt <= 0; + channel_cnt <= 1; + data_cnt <= 0; + roi_max <= (others => '0'); + data_end <= 3; + state_write <= WR_ADC1; + + ---- Write Channel + when WR_ADC1 => + -- read ROI and set end of Channel-Data + if (data_cnt = 3) then + data_end <= conv_integer (ram_data) + 3; + if (ram_data > roi_max) then + roi_max <= ram_data (10 downto 0); + end if; + end if; + ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); + state_write <= WR_ADC2; + when WR_ADC2 => + if (data_cnt < data_end) then + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + data_cnt <= data_cnt + 1; + state_write <= WR_ADC1; + else + -- Next DRS + if (drs_cnt < 3) then + drs_cnt <= drs_cnt + 1; + data_cnt <= 0; + data_end <= 3; + state_write <= WR_ADC1; + else + -- Next Channel + if (channel_cnt < local_fifo_channels) then + channel_cnt <= channel_cnt + 1; + roi_max <= (others => '0'); + drs_cnt <= 0; + data_cnt <= 0; + data_end <= 3; + adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ADC1; + else + -- Ready + if (local_write_end_flag = '1') then + state_write <= WR_ENDFLAG; + else + state_write <= WR_05; + end if; + end if; + end if; + end if; + -- End Write ADC-Data + + -- Write End Package Flag + when WR_ENDFLAG => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4); + state_write <= WR_ENDFLAG1; + when WR_ENDFLAG1 => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + ram_access <= '1'; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_ENDFLAG2; + when WR_ENDFLAG2 => + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1; + state_write <= WR_ENDFLAG3; + when WR_ENDFLAG3 => + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_05a; + + -- End Write End Package Flag + + -- Wait???? + when WR_05a => + if (wait_cntr < 10) then -- 3000 works??? + wait_cntr <= wait_cntr + 1; + else + wait_cntr <= 0; + state_write <= WR_05b; + end if; + when WR_05b => + state_write <= WR_05; + + --Send FIFO + when WR_05 => + ram_access <= '0'; + par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + par_data <= (0 => write_length_bytes (16), others => '0'); + state_init <= WRITE_REG; + state_write <= WR_06; + when WR_06 => + par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + par_data <= write_length_bytes (15 downto 0); + state_init <= WRITE_REG; + state_write <= WR_07; + when WR_07 => + par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + par_data <= X"0020"; -- Send + state_init <= WRITE_REG; + state_write <= WR_08; + when others => + state_init <= next_state_tmp; + state_write <= WR_START; + end case; + -- End WRITE_DATA + + when READ_REG => + case count is + when "000" => + cs <= '0'; + rd <= '0'; + wr <= '1'; + data <= (others => 'Z'); -- !!!!!!!!!! + count <= "001"; + addr <= par_addr; + when "001" => + count <= "010"; + when "010" => + count <= "100"; + when "100" => + data_read <= data; + count <= "110"; + when "110" => + count <= "111"; + when "111" => + cs <= '1'; + rd <= '1'; + count <= "000"; + state_init <= next_state; + when others => + null; + end case; + + when WRITE_REG => + case count is + when "000" => + cs <= '0'; + wr <= '0'; + rd <= '1'; + addr <= par_addr; + if (ram_access = '1') then + data <= ram_data; + else + data <= par_data; + end if; + count <= "100"; + when "100" => + count <= "101"; + when "101" => + count <= "110"; + when "110" => + cs <= '1'; + wr <= '1'; + state_init <= next_state; + count <= "000"; + when others => + null; + end case; + + when others => + null; + end case; + end if; -- int_flag = '0' + + end if; -- rising_edge (clk) + + end process w5300_init_proc; + +end Behavioral; + Index: firmware/FTM/test_firmware/FTM_test5/FTM_test5.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test5/FTM_test5.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test5/FTM_test5.vhd (revision 10046) @@ -0,0 +1,361 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 15 October 2010 +-- Design Name: +-- Module Name: FTM_test5 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: trigger primitives input +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +Library UNISIM; +use UNISIM.vcomponents.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- library FTM_definitions_test3; +-- USE FTM_definitions_test3.ftm_array_types.all; + + + +entity FTM_test5 is + port( + + +-- Clock +-- clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- + Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 + Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 + Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 + Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow +-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration + Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ + Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- + Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ + Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs + NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ + NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- + NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ + NIM_Out1_n : out STD_LOGIC -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 +-- TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test5; + + +architecture Behavioral of FTM_test5 is + + + +-- signal CLK_internal : STD_LOGIC; +signal crate_0 : std_logic; +signal crate_1 : std_logic; +signal crate_2 : std_logic; +signal crate_3 : std_logic; + + +begin + + +crate_0 <= Trig_Prim_A(0)or Trig_Prim_A(1)or Trig_Prim_A(2)or Trig_Prim_A(3)or Trig_Prim_A(4)or Trig_Prim_A(5)or Trig_Prim_A(6)or Trig_Prim_A(7)or Trig_Prim_A(8)or Trig_Prim_A(9); +crate_1 <= Trig_Prim_B(0)or Trig_Prim_B(1)or Trig_Prim_B(2)or Trig_Prim_B(3)or Trig_Prim_B(4)or Trig_Prim_B(5)or Trig_Prim_B(6)or Trig_Prim_B(7)or Trig_Prim_B(8)or Trig_Prim_B(9); +crate_2 <= Trig_Prim_C(0)or Trig_Prim_C(1)or Trig_Prim_C(2)or Trig_Prim_C(3)or Trig_Prim_C(4)or Trig_Prim_C(5)or Trig_Prim_C(6)or Trig_Prim_C(7)or Trig_Prim_C(8)or Trig_Prim_C(9); +crate_3 <= Trig_Prim_D(0)or Trig_Prim_D(1)or Trig_Prim_D(2)or Trig_Prim_D(3)or Trig_Prim_D(4)or Trig_Prim_D(5)or Trig_Prim_D(6)or Trig_Prim_D(7)or Trig_Prim_D(8)or Trig_Prim_D(9); + + + OBUFDS_inst_crate_0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_NIM1_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM1_n, -- Diff_n output (connect directly to top-level port) + I => crate_0 -- Buffer input + ); + + + OBUFDS_inst_crate_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_NIM2_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM2_n, -- Diff_n output (connect directly to top-level port) + I => crate_1 -- Buffer input + ); + + + OBUFDS_inst_crate_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => NIM_Out0_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out0_n, -- Diff_n output (connect directly to top-level port) + I => crate_2 -- Buffer input + ); + + + OBUFDS_inst_crate_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => NIM_Out1_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out1_n, -- Diff_n output (connect directly to top-level port) + I => crate_3 -- Buffer input + ); + + + +--FTM main state machine +-- FTM_test4_Registers: process (clk_250M_sig) +-- begin +-- if Rising_edge(clk_250M_sig) then +-- if (config_puls_cnt < 2000) then +-- config_puls_cnt <= config_puls_cnt + 1; +-- end if; +-- +-- if (config_puls_cnt < 1000) then +-- reset_sig <= '0'; +-- elsif ((config_puls_cnt > 999) and (config_puls_cnt < 1900)) then +-- reset_sig <= '1'; +-- else +-- reset_sig <= '0'; +-- end if; +-- +-- end if; +-- end process FTM_test4_Registers; + +end Behavioral; + + Index: firmware/FTM/test_firmware/FTM_test5/ftm_board_test5.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test5/ftm_board_test5.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test5/ftm_board_test5.ucf (revision 10046) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 15 October 2010 +# +# Pin location for FTM test 4 (ethernet controller) +######################################################## + + +#Clock +####################################################### +# NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red +# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+ +NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1- +NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+ +NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+ +NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0- +NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+ +NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- + # on IO-Bank2 +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test6/FTM_test6.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test6/FTM_test6.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test6/FTM_test6.vhd (revision 10046) @@ -0,0 +1,407 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 18 October 2010 +-- Design Name: +-- Module Name: FTM_test5 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: external NIM inputs test +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +Library UNISIM; +use UNISIM.vcomponents.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- library FTM_definitions_test3; +-- USE FTM_definitions_test3.ftm_array_types.all; + + + +entity FTM_test6 is + port( + + +-- Clock +-- clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 + ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input + Veto : in STD_LOGIC; -- trigger veto input + NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 + NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow +-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control +-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable +-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC; -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration + Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ + Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- + Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ + Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs + NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ + NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- + NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ + NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- + RES_p : out STD_LOGIC; -- RES+ Reset + RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + + TRG_p : out STD_LOGIC; -- TRG+ Trigger + TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + + TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker + TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 + TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test6; + + +architecture Behavioral of FTM_test6 is + + + +signal ext_Trig_sig_1 : std_logic; +signal ext_Trig_sig_2 : std_logic; + + +signal Veto_sig : std_logic; +signal NIM_In_sig_0 : std_logic; +signal NIM_In_sig_1 : std_logic; +signal NIM_In_sig_2 : std_logic; +signal NIM_In3_GCLK_sig : std_logic; + + + + + +begin + + + ext_Trig_sig_1 <= ext_Trig(1); + ext_Trig_sig_2 <= ext_Trig(2); + Veto_sig <= Veto; + NIM_In_sig_0 <= NIM_In(0); + NIM_In_sig_1 <= NIM_In(1); + NIM_In_sig_2 <= NIM_In(2); + NIM_In3_GCLK_sig <= NIM_In3_GCLK; + + + + + + + OBUFDS_inst_crate_0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_NIM1_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM1_n, -- Diff_n output (connect directly to top-level port) + I => ext_Trig_sig_1 -- Buffer input + ); + + + OBUFDS_inst_crate_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_NIM2_p, -- Diff_p output (connect directly to top-level port) + OB => Cal_NIM2_n, -- Diff_n output (connect directly to top-level port) + I => ext_Trig_sig_2 -- Buffer input + ); + + + OBUFDS_inst_crate_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => NIM_Out0_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out0_n, -- Diff_n output (connect directly to top-level port) + I => Veto_sig -- Buffer input + ); + + + OBUFDS_inst_crate_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => NIM_Out1_p, -- Diff_p output (connect directly to top-level port) + OB => NIM_Out1_n, -- Diff_n output (connect directly to top-level port) + I => NIM_In_sig_0 -- Buffer input + ); + + + + OBUFDS_inst_NIM_IN_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => RES_p, -- Diff_p output (connect directly to top-level port) + OB => RES_n, -- Diff_n output (connect directly to top-level port) + I => NIM_In_sig_1 -- Buffer input + ); + + + OBUFDS_inst_NIM_IN_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => TRG_p, -- Diff_p output (connect directly to top-level port) + OB => TRG_n, -- Diff_n output (connect directly to top-level port) + I => NIM_In_sig_2 -- Buffer input + ); + + + OBUFDS_inst_NIM_IN_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O =>TIM_Run_p , -- Diff_p output (connect directly to top-level port) + OB => TIM_Run_n, -- Diff_n output (connect directly to top-level port) + I => NIM_In3_GCLK_sig -- Buffer input + ); + + + TIM_Sel <= '0'; + + + + +--FTM main state machine +-- FTM_test4_Registers: process (clk_250M_sig) +-- begin +-- if Rising_edge(clk_250M_sig) then +-- if (config_puls_cnt < 2000) then +-- config_puls_cnt <= config_puls_cnt + 1; +-- end if; +-- +-- if (config_puls_cnt < 1000) then +-- reset_sig <= '0'; +-- elsif ((config_puls_cnt > 999) and (config_puls_cnt < 1900)) then +-- reset_sig <= '1'; +-- else +-- reset_sig <= '0'; +-- end if; +-- +-- end if; +-- end process FTM_test4_Registers; + +end Behavioral; + + Index: firmware/FTM/test_firmware/FTM_test6/ftm_board_test6.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test6/ftm_board_test6.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test6/ftm_board_test6.ucf (revision 10046) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 15 October 2010 +# +# Pin location for FTM test 4 (ethernet controller) +######################################################## + + +#Clock +####################################################### +# NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red +# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control +# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+ +NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1- +NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+ +NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+ +NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0- +NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+ +NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +NET RES_p LOC = D16 | IOSTANDARD=LVDS_33; # RES+ Reset +NET RES_n LOC = C15 | IOSTANDARD=LVDS_33; # RES- IO-Bank 0 + +NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33; # TRG+ Trigger +NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33; # TRG- IO-Bank 0 + +NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker +NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33; # TIM_Run- + # on IO-Bank2 +NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test7/FTM_Test7_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test7/FTM_Test7_dcm.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test7/FTM_Test7_dcm.vhd (revision 10046) @@ -0,0 +1,98 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_Test7_dcm.vhd +-- /___/ /\ Timestamp : 10/18/2010 16:17:48 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test7/FTM_Test7/ipcore_dir/FTM_Test7_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test7/FTM_Test7/ipcore_dir/FTM_Test7_dcm +--Design Name: FTM_Test7_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_Test7_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 5.54 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_Test7_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_Test7_dcm; + +architecture BEHAVIORAL of FTM_Test7_dcm is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 16, + CLKFX_MULTIPLY => 2, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/test_firmware/FTM_test7/FTM_Test7_dcm_arwz.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test7/FTM_Test7_dcm_arwz.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test7/FTM_Test7_dcm_arwz.ucf (revision 10046) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 16; +INST DCM_SP_INST CLKFX_MULTIPLY = 2; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/test_firmware/FTM_test7/FTM_test7.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test7/FTM_test7.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test7/FTM_test7.vhd (revision 10046) @@ -0,0 +1,385 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 18 October 2010 +-- Design Name: +-- Module Name: FTM_test5 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: RS-485 outputs +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +Library UNISIM; +use UNISIM.vcomponents.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- library FTM_definitions_test3; +-- USE FTM_definitions_test3.ftm_array_types.all; + + + +entity FTM_test7 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- +-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red +-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow +-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control + Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable + Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + +-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0 + Bus1_TxD_0 : out STD_LOGIC; + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 + Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 + Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 + Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards + Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable + Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 + Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 + Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 + Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 + Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- + Aux_Tx_D : out STD_LOGIC; -- + Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable + Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- + TrID_Tx_D : out STD_LOGIC -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration +-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ +-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- +-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ +-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs +-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ +-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- +-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ +-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 +-- TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test7; + + +architecture Behavioral of FTM_test7 is + +COMPONENT FTM_Test7_dcm + PORT( + CLKIN_IN : IN std_logic; + CLKFX_OUT : OUT std_logic; + CLKIN_IBUFG_OUT : OUT std_logic; + CLK0_OUT : OUT std_logic; + LOCKED_OUT : OUT std_logic + ); + END COMPONENT; + + + component Clock_Divider + port( + clock_in : IN STD_LOGIC; + clock_out : OUT STD_LOGIC + ); + end component; + + +signal clk_50k_sig : std_logic; +signal clk_5M_sig : std_logic; + + + +begin + + Bus1_TxD_0 <= clk_50k_sig; + Bus1_TxD_1 <= clk_50k_sig; + Bus1_TxD_2 <= clk_50k_sig; + Bus1_TxD_3 <= clk_50k_sig; + + Bus2_TxD_0 <= clk_50k_sig; + Bus2_TxD_1 <= clk_50k_sig; + Bus2_TxD_2 <= clk_50k_sig; + Bus2_TxD_3 <= clk_50k_sig; + + Aux_Tx_D <= clk_50k_sig; + TrID_Tx_D <= clk_50k_sig; + + Bus1_Tx_En <= '1'; + Bus1_Rx_En <= '1'; + Bus2_Tx_En <= '1'; + Bus2_Rx_En <= '1'; + Aux_Rx_En <= '1'; + Aux_Tx_En <= '1'; + + + Inst_FTM_Test7_dcm: FTM_Test7_dcm PORT MAP( + CLKIN_IN => clk, + CLKFX_OUT => clk_5M_sig, + CLKIN_IBUFG_OUT => open, + CLK0_OUT => open, + LOCKED_OUT => open + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock_in => clk_5M_sig, + clock_out => clk_50k_sig + ); + +end Behavioral; + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Clock_Divider is + port( + clock_in : in std_logic; + clock_out : out std_logic + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + + constant max_count : integer := 5000000/50000; -- for implementation + +begin + + process(clock_in) + variable count : integer range 0 to max_count; + begin + if rising_edge(clock_in) then + if count < max_count/2 then + clock_out <= '0'; + count := count + 1; + elsif count < max_count then + clock_out <= '1'; + count := count + 1; + else + count := 0; + clock_out <= '0'; + end if; + end if; + end process; + +end architecture RTL; Index: firmware/FTM/test_firmware/FTM_test7/ftm_board_test7.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test7/ftm_board_test7.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test7/ftm_board_test7.ucf (revision 10046) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 18 October 2010 +# +# Pin location for FTM test 7 : RS-485 Transmitter +######################################################## + + +#Clock +####################################################### + NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red +# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control + NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards + NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable + NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33; # TIM_Run- + # on IO-Bank2 +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # + Index: firmware/FTM/test_firmware/FTM_test8/FTM_Test8_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_Test8_dcm.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/FTM_Test8_dcm.vhd (revision 10046) @@ -0,0 +1,91 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_Test8_dcm.vhd +-- /___/ /\ Timestamp : 10/21/2010 10:40:59 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test8/FTM_Test8/ipcore_dir/FTM_Test8_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test8/FTM_Test8/ipcore_dir/FTM_Test8_dcm +--Design Name: FTM_Test8_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_Test8_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_Test8_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_Test8_dcm; + +architecture BEHAVIORAL of FTM_Test8_dcm is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/test_firmware/FTM_test8/FTM_Test8_dcm_arwz.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_Test8_dcm_arwz.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/FTM_Test8_dcm_arwz.ucf (revision 10046) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = 1X; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 4; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd (revision 10046) @@ -0,0 +1,507 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 21 October 2010 +-- Design Name: +-- Module Name: FTM_test8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: test a RS-485 input +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +Library UNISIM; +use UNISIM.vcomponents.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +-- library FTM_definitions_test3; +-- USE FTM_definitions_test3.ftm_array_types.all; + + + +entity FTM_test8 is + port( + + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 + +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- + LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red + LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow + LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + + + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control + Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable + Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + + Bus1_RxD_0 : in STD_LOGIC; -- crate 0 + Bus1_TxD_0 : out STD_LOGIC + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration +-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ +-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- +-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ +-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs +-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ +-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- +-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ +-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 +-- TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test8; + + +architecture Behavioral of FTM_test8 is + + + + + + COMPONENT FTM_Test8_dcm + PORT( + CLKIN_IN : IN std_logic; + RST_IN : IN std_logic; + CLKFX_OUT : OUT std_logic; + CLK0_OUT : OUT std_logic; + LOCKED_OUT : OUT std_logic + ); + END COMPONENT; + + + + component FTM_test8_rs485_interface + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; -- Hertz + BAUD_RATE : integer := 250000 -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector(7 DOWNTO 0); + -- rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector(7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + + -- signal enable_sig : enable_array_type := DEFAULT_ENABLE; + + + signal rx_en_sig : STD_LOGIC := '0'; + signal tx_en_sig : STD_LOGIC := '0'; + signal rx_sig : STD_LOGIC; + signal tx_sig : STD_LOGIC := 'X'; + signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + -- signal rx_busy_sig : STD_LOGIC; + signal rx_valid_sig : STD_LOGIC; + + type FTM_test8_StateType is (INIT, RUN1, RUN2, RUN3, RUN4); + signal FTM_test8_State, FTM_test8_NextState: FTM_test8_StateType; + + + + + +begin + +Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP( + CLKIN_IN => clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLK0_OUT => open, + LOCKED_OUT => open + ); + + + + Inst_FTM_test8_rs485_interface : FTM_test8_rs485_interface + generic map( + CLOCK_FREQUENCY => 50000000, + -- BAUD_RATE => 10000000 --simulation + BAUD_RATE => 25000 --implement + ) + port map( + clk => clk_50M_sig, + -- RS485 + rx_d => rx_sig, + rx_en => rx_en_sig, + tx_d => tx_sig, + tx_en => tx_en_sig, + -- FPGA + rx_data => rx_data_sig, + -- rx_busy => rx_busy_sig, + rx_valid => rx_valid_sig, + tx_data => (others => '0'), + tx_busy => open, + tx_start => '0' + ); + +-- enables_A <= enable_sig(0)(8 downto 0); +-- enables_B <= enable_sig(1)(8 downto 0); +-- enables_C <= enable_sig(2)(8 downto 0); +-- enables_D <= enable_sig(3)(8 downto 0); + + + Bus1_Rx_En <= rx_en_sig; + Bus1_Tx_En <= tx_en_sig; + Bus1_TxD_0 <= tx_sig; + rx_sig <= Bus1_RxD_0; + + + + + --FTM main state machine (two-process implementation) + + FTM_test8_Registers: process (clk_50M_sig) + begin + if Rising_edge(clk_50M_sig) then + FTM_test8_State <= FTM_test8_NextState; + end if; + end process FTM_test8_Registers; + + FTM_test8_C_logic: process (FTM_test8_State, rx_data_sig, rx_valid_sig) + begin + FTM_test8_NextState <= FTM_test8_State; + case FTM_test8_State is + when INIT => + reset_sig <= '0'; + + LED_red <= ("0000"); + + if (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN4; + else + FTM_test8_NextState <= INIT; + end if; + when RUN1 => + reset_sig <= '0'; + + -- enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111"); + LED_red <= ("0001"); + + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTM_test8_NextState <= INIT; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN4; + else + FTM_test8_NextState <= RUN1; + end if; + when RUN2 => + reset_sig <= '0'; + + -- enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111"); + LED_red <= ("0010"); + + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTM_test8_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN1; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN3; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN4; + else + FTM_test8_NextState <= RUN2; + end if; + when RUN3 => + reset_sig <= '0'; + + -- enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111"); + LED_red <= ("0100"); + + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTM_test8_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN2; + elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN4; + else + FTM_test8_NextState <= RUN3; + end if; + when RUN4 => + reset_sig <= '0'; + + -- enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000"); + LED_red <= ("1000"); + + if (rx_data_sig = "00110000" and rx_valid_sig = '1') then + FTM_test8_NextState <= INIT; + elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN1; + elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN2; + elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then + FTM_test8_NextState <= RUN3; + else + FTM_test8_NextState <= RUN4; + end if; + end case; + end process FTM_test8_C_logic; + + + + + +LED_ye <= ("11"); +LED_gn <= ("11"); + + + + +end Behavioral; + + + + Index: firmware/FTM/test_firmware/FTM_test8/FTM_test8_rs485_interface.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_test8_rs485_interface.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/FTM_test8_rs485_interface.vhd (revision 10046) @@ -0,0 +1,126 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified for FTU design by Q. Weitzel, 30 July 2010 +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +-- library ftu_definitions; +-- USE ftu_definitions.ftu_array_types.all; +-- USE ftu_definitions.ftu_constants.all; + +ENTITY FTM_test8_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; + BAUD_RATE : integer := 250000 + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + --rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +END FTM_test8_rs485_interface; + +ARCHITECTURE beha OF FTM_test8_rs485_interface IS + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + --transmit + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bits + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + --receive + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + --rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; Index: firmware/FTM/test_firmware/FTM_test8/FTM_test8_rs485_interface_OLD.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_test8_rs485_interface_OLD.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/FTM_test8_rs485_interface_OLD.vhd (revision 10046) @@ -0,0 +1,124 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified by Q. Weitzel, 30 July 2010 +-- modified by Patrick Vogler, 21 October 2010 +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY FTM_test8_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; -- Hertz + BAUD_RATE : integer := 250000 -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +-- Declarations + +END FTM_test8_rs485_interface; + +ARCHITECTURE beha OF FTM_test8_rs485_interface IS + + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bit + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; + Index: firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf (revision 10046) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 18 October 2010 +# +# Pin location for FTM test 7 : RS-485 Transmitter +######################################################## + + +#Clock +####################################################### + NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red + NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow +# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green +# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 +# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control + NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 + NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33; # TIM_Run- + # on IO-Bank2 +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # +