Index: firmware/FTU/rs485/FTU_rs485_control.vhd
===================================================================
--- firmware/FTU/rs485/FTU_rs485_control.vhd	(revision 10037)
+++ firmware/FTU/rs485/FTU_rs485_control.vhd	(revision 10050)
@@ -89,4 +89,28 @@
 
   signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0;  -- count 28 1-byte frames 
+
+  signal reset_crc_sig     : std_logic := '0';
+  signal crc_enable_sig    : std_logic := '0';
+  signal crc_input_sig     : std_logic_vector(RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
+  signal crc_sig           : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0');
+  signal crc_sig_inv       : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0');
+  signal crc_error_cnt_sig : integer range 0 to 255 := 0;
+
+  component ucrc_par
+    generic(
+      POLYNOMIAL : std_logic_vector;
+      INIT_VALUE : std_logic_vector;
+      DATA_WIDTH : integer range 2 to 256;
+      SYNC_RESET : integer range 0 to 1
+    );
+    port(
+      clk_i   : in  std_logic;
+      rst_i   : in  std_logic;
+      clken_i : in  std_logic;
+      data_i  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+      match_o : out std_logic;
+      crc_o   : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
+    );
+  end component;
   
   component FTU_rs485_receiver
@@ -107,4 +131,5 @@
       block_valid            : IN  std_logic;
       brd_add                : IN  std_logic_vector(5 downto 0);
+      crc_error_cnt          : OUT integer range 0 to 255;
       int_new_DACs           : OUT std_logic;
       int_new_enables        : OUT std_logic;
@@ -139,7 +164,9 @@
   end component;
 
-  type FTU_rs485_control_StateType is (RECEIVE,
+  type FTU_rs485_control_StateType is (INIT, RECEIVE,
                                        READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT,
-                                       SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT,
+                                       READ_RATES_WAIT_2, READ_DAC_WAIT_2, READ_ENABLE_WAIT_2, READ_PRESCALING_WAIT_2,
+                                       SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT,                                       
+                                       SET_DAC_WAIT_2, SET_ENABLE_WAIT_2, SET_PRESCALING_WAIT_2, PING_PONG_WAIT_2,
                                        READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT,
                                        SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT);
@@ -147,4 +174,22 @@
   
 begin
+
+  crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
+  
+  Inst_ucrc_par : ucrc_par
+    generic map(
+      POLYNOMIAL => CRC_POLYNOMIAL,
+      INIT_VALUE => CRC_INIT_VALUE,
+      DATA_WIDTH => 216,
+      SYNC_RESET => 1
+    )
+    port map(
+      clk_i   => main_clk,
+      rst_i   => reset_crc_sig,
+      clken_i => crc_enable_sig,
+      data_i  => crc_input_sig,
+      match_o => open,
+      crc_o   => crc_sig_inv
+    );
   
   Inst_FTU_rs485_receiver : FTU_rs485_receiver
@@ -164,4 +209,5 @@
       block_valid            => block_valid_sig,
       brd_add                => brd_add,
+      crc_error_cnt          => crc_error_cnt_sig,
       int_new_DACs           => int_new_DACs_sig,
       int_new_enables        => int_new_enables_sig,
@@ -200,6 +246,12 @@
     if Rising_edge(main_clk) then
       case FTU_rs485_control_State is
+
+        when INIT =>
+          reset_crc_sig <= '1';
+          FTU_rs485_control_State <= RECEIVE;
         
-        when RECEIVE =>  -- default state, receiver on, no transmission          
+        when RECEIVE =>  -- default state, receiver on, no transmission
+          reset_crc_sig <= '0';
+          crc_enable_sig <= '0';
           tx_start_sig <= '0';
           if (int_new_DACs_sig = '1') then
@@ -304,5 +356,16 @@
           if (DACs_ready = '1') then
             new_DACs <= '0';
-            FTU_rs485_control_State <= SET_DAC_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000"
+                             & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000000"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= SET_DAC_WAIT_2;
           else
             new_DACs <= '1';
@@ -310,8 +373,22 @@
           end if;
 
+        when SET_DAC_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= SET_DAC_TRANSMIT;
+          
         when SET_ENABLE_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (enables_ready = '1') then
             new_enables <= '0';
-            FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" 
+                             & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0)
+                             & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0)
+                             & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0)
+                             & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000011"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= SET_ENABLE_WAIT_2;
           else
             new_enables <= '1';
@@ -319,8 +396,20 @@
           end if;
 
+        when SET_ENABLE_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
+          
         when SET_PRESCALING_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (prescaling_ready = '1') then
             new_prescaling <= '0';
-            FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" 
+                             & overflow_array_rs485_in & prescaling_rs485_in & "00000110"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= SET_PRESCALING_WAIT_2;
           else
             new_prescaling <= '1';
@@ -328,8 +417,26 @@
           end if;
 
+        when SET_PRESCALING_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
+          
         when READ_RATES_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (rates_ready = '1') then
             read_rates <= '0';
-            FTU_rs485_control_State <= READ_RATES_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & overflow_array_rs485_in
+                             & conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16) 
+                             & conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0)
+                             & conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16) 
+                             & conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0)
+                             & conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16) 
+                             & conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0)
+                             & conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16) 
+                             & conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0)
+                             & conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16) 
+                             & conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0) & "00000010"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= READ_RATES_WAIT_2;
           else
             read_rates <= '1';
@@ -337,8 +444,23 @@
           end if;
 
+        when READ_RATES_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= READ_RATES_TRANSMIT;
+          
         when READ_DAC_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (DACs_ready = '1') then
             read_DACs <= '0';
-            FTU_rs485_control_State <= READ_DAC_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000"
+                             & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0)
+                             & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000001"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= READ_DAC_WAIT_2;
           else
             read_DACs <= '1';
@@ -346,8 +468,22 @@
           end if;
 
+        when READ_DAC_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= READ_DAC_TRANSMIT;
+          
         when READ_ENABLE_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (enables_ready = '1') then
             read_enables <= '0';
-            FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" 
+                             & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0)
+                             & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0)
+                             & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0)
+                             & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000100"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= READ_ENABLE_WAIT_2;
           else
             read_enables <= '1';
@@ -355,8 +491,20 @@
           end if;
 
+        when READ_ENABLE_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
+          
         when READ_PRESCALING_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (prescaling_ready = '1') then
             read_prescaling <= '0';
-            FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" 
+                             & overflow_array_rs485_in & prescaling_rs485_in & "00000111"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= READ_PRESCALING_WAIT_2;
           else
             read_prescaling <= '1';
@@ -364,12 +512,27 @@
           end if;
 
+        when READ_PRESCALING_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
+          
         when PING_PONG_WAIT =>  -- wait until FTU control says "done" and then answer to FTM
           if (ping_pong_ready = '1') then
             ping_pong <= '0';
-            FTU_rs485_control_State <= PING_PONG_TRANSMIT;
+            crc_enable_sig <= '1';
+            crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8)
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                             & "00000000" & "00000000" & "00000000" 
+                             & dna(63 downto 0) & "00000101"
+                             & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM;
+            FTU_rs485_control_State <= PING_PONG_WAIT_2;
           else
             ping_pong <= '1';
             FTU_rs485_control_State <= PING_PONG_WAIT;
           end if;
+
+        when PING_PONG_WAIT_2 =>
+          crc_enable_sig <= '0';
+          FTU_rs485_control_State <= PING_PONG_TRANSMIT;
           
         when SET_DAC_TRANSMIT =>
@@ -457,14 +620,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
-              tx_start_sig <= '1';
-              FTU_rs485_control_State <= READ_RATES_TRANSMIT;
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
+              tx_start_sig <= '1';
+              FTU_rs485_control_State <= SET_DAC_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= SET_DAC_TRANSMIT;              
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;
@@ -548,14 +712,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;        
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;
@@ -604,14 +769,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if; 
@@ -755,14 +921,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_RATES_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_RATES_TRANSMIT;
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;  
@@ -856,14 +1023,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_DAC_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_DAC_TRANSMIT;              
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;  
@@ -947,14 +1115,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;    
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;  
@@ -1008,14 +1177,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;  
@@ -1026,4 +1196,5 @@
 
         when PING_PONG_TRANSMIT =>
+          crc_enable_sig <= '0';
           if tx_busy_sig = '0' then
             if txcnt = 0 then           -- start delimiter
@@ -1099,14 +1270,15 @@
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then        -- CRC error counter
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8);
               tx_start_sig <= '1';
               FTU_rs485_control_State <= PING_PONG_TRANSMIT;
             elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then        -- check sum
               txcnt <= txcnt + 1;
-              tx_data_sig <= "00000000";  -- NOT YET IMPLEMENTED!!!
+              tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
               FTU_rs485_control_State <= PING_PONG_TRANSMIT;
             else                        -- transmission finished
               txcnt <= 0;
+              reset_crc_sig <= '1';
               FTU_rs485_control_State <= RECEIVE;
             end if;  
