Index: /firmware/FTU/FTU_control.vhd =================================================================== --- /firmware/FTU/FTU_control.vhd (revision 10050) +++ /firmware/FTU/FTU_control.vhd (revision 10051) @@ -201,7 +201,4 @@ ram_dia_sig <= (others => '0'); FTU_control_State <= INIT_RAM; - --elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default CRC errors - --ram_dia_sig <= (others => '0'); - --FTU_control_State <= INIT_RAM; elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then -- empty RAM cells ram_dia_sig <= (others => '0'); @@ -276,5 +273,5 @@ end if; - when CONFIG_COUNTER => + when CONFIG_COUNTER => -- set prescaling value for counters wait_cntr <= wait_cntr + 1; new_rates_busy <= '1'; @@ -296,5 +293,5 @@ end if; - when CONFIG_ENABLE => + when CONFIG_ENABLE => -- set enable patterns for sum trigger stage ram_enable_cntr <= ram_enable_cntr + 1; new_rates_busy <= '1'; @@ -302,9 +299,4 @@ ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); FTU_control_State <= CONFIG_ENABLE; - --elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then - --ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); - --enable_array_sig(ram_enable_cntr - 1) <= ram_dob; - --enables_ready <= '1'; - --FTU_control_State <= CONFIG_ENABLE; elsif (ram_enable_cntr < NO_OF_ENABLE) then ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); @@ -327,5 +319,5 @@ end if; - when CONFIG_DAC => + when CONFIG_DAC => -- start to set thresholds for sum trigger patches new_rates_busy <= '1'; ram_dac_cntr <= ram_dac_cntr + 1; @@ -354,5 +346,5 @@ end if; - when CONFIG_DAC_WAIT => + when CONFIG_DAC_WAIT => -- wait until setting of thresholds has finished if (config_ready = '1') then new_DACs_in_RAM <= '0'; @@ -591,5 +583,5 @@ end if; - when DO_PING_PONG => -- just answer to FTM + when DO_PING_PONG => -- answer to FTM and send DNA wait_cntr <= wait_cntr + 1; if (wait_cntr = 0) then @@ -605,13 +597,4 @@ end if; end process FTU_control_FSM; - - --detect_new_rates: process(new_rates, new_rates_busy) - --begin - --if(new_rates_busy = '1') then - --new_rates_sig <= '0'; - --elsif rising_edge(new_rates) then - --new_rates_sig <= '1'; - --end if; - --end process detect_new_rates; detect_new_rates: process(clk_50MHz) Index: /firmware/FTU/FTU_top.vhd =================================================================== --- /firmware/FTU/FTU_top.vhd (revision 10050) +++ /firmware/FTU/FTU_top.vhd (revision 10051) @@ -58,5 +58,5 @@ sck : OUT STD_LOGIC; -- serial clock to DAC mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in - clr : OUT STD_LOGIC; -- clear signal to DAC + clr : OUT STD_LOGIC; -- clear signal to DAC, not used cs_ld : OUT STD_LOGIC; -- chip select or load to DAC Index: /firmware/FTU/ftu_definitions.vhd =================================================================== --- /firmware/FTU/ftu_definitions.vhd (revision 10050) +++ /firmware/FTU/ftu_definitions.vhd (revision 10051) @@ -60,5 +60,5 @@ constant CNTR_FREQ_DIVIDER : integer := 25000; -- for simulation, should normally be 1 - --32byte dual-port RAM, port A: 8byte, port B: 16byte + --64byte dual-port RAM, port A: 8byte, port B: 16byte constant RAM_ADDR_WIDTH_A : integer := 6; constant RAM_ADDR_WIDTH_B : integer := 5; Index: /firmware/FTU/rs485/FTU_rs485_control.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_control.vhd (revision 10050) +++ /firmware/FTU/rs485/FTU_rs485_control.vhd (revision 10051) @@ -247,5 +247,5 @@ case FTU_rs485_control_State is - when INIT => + when INIT => -- reset CRC register reset_crc_sig <= '1'; FTU_rs485_control_State <= RECEIVE; @@ -373,5 +373,5 @@ end if; - when SET_DAC_WAIT_2 => + when SET_DAC_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= SET_DAC_TRANSMIT; @@ -396,5 +396,5 @@ end if; - when SET_ENABLE_WAIT_2 => + when SET_ENABLE_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; @@ -417,5 +417,5 @@ end if; - when SET_PRESCALING_WAIT_2 => + when SET_PRESCALING_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; @@ -444,5 +444,5 @@ end if; - when READ_RATES_WAIT_2 => + when READ_RATES_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= READ_RATES_TRANSMIT; @@ -468,5 +468,5 @@ end if; - when READ_DAC_WAIT_2 => + when READ_DAC_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= READ_DAC_TRANSMIT; @@ -491,5 +491,5 @@ end if; - when READ_ENABLE_WAIT_2 => + when READ_ENABLE_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; @@ -512,5 +512,5 @@ end if; - when READ_PRESCALING_WAIT_2 => + when READ_PRESCALING_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; @@ -532,5 +532,5 @@ end if; - when PING_PONG_WAIT_2 => + when PING_PONG_WAIT_2 => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_control_State <= PING_PONG_TRANSMIT; Index: /firmware/FTU/rs485/FTU_rs485_interpreter.vhd =================================================================== --- /firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 10050) +++ /firmware/FTU/rs485/FTU_rs485_interpreter.vhd (revision 10051) @@ -110,5 +110,5 @@ case FTU_rs485_interpreter_State is - when INIT => + when INIT => -- reset CRC register reset_crc_sig <= '1'; FTU_rs485_interpreter_State <= WAIT_FOR_DATA; @@ -134,9 +134,9 @@ reset_crc_sig <= '0'; - when WAIT_CRC => + when WAIT_CRC => -- wait one cycle for CRC calculation crc_enable_sig <= '0'; FTU_rs485_interpreter_State <= CHECK_CRC; - when CHECK_CRC => + when CHECK_CRC => -- check whether CRC matches reset_crc_sig <= '1'; if (crc_match_sig = '1') then