Changeset 10058

Timestamp:

11/23/10 14:44:36 (14 years ago)

Author:

weitzel

Message:

Some modifications and a test bench for FTM_test8

Location:

firmware/FTM/test_firmware/FTM_test8

Files:

• FTM_test8.vhd (modified) (17 diffs)
• FTM_test8_tb.vhd (added)
• ftm_board_test8.ucf (modified) (1 diff)

firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd

@@ -16 +16 @@
 -- Revision: 
 -- Revision 0.01 - File Created
+-- Revision 0.02 - Some modifications, November 15, 2010, Q. Weitzel
 -- Additional Comments: 
 --
@@ -25 +26 @@
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-
 Library UNISIM;
 use UNISIM.vcomponents.all;
@@ -34 +34 @@
 --use UNISIM.VComponents.all;
 
-
 --  library FTM_definitions_test3;
 --  USE FTM_definitions_test3.ftm_array_types.all;
 
-
-
 entity FTM_test8 is
   port(
-
     
 -- Clock
    clk   : IN  STD_LOGIC;                     -- external clock from
                                               -- oscillator U47
-
 -- connection to the WIZnet W5300 ethernet controller
 -- on IO-Bank 1
@@ -123 +118 @@
    LED_gn   : out STD_LOGIC_VECTOR(1 downto 0);    -- green
 
-   
-   
 -- Clock conditioner LMK03000
 -- on IO-Bank 3
@@ -135 +128 @@
 --   LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                  
    
-  
-
-
 -- various RS-485 Interfaces
 -- on IO-Bank 3
@@ -280 +270 @@
 end FTM_test8;
 
-
 architecture Behavioral of FTM_test8 is
 
-
-
-
-  
-        COMPONENT FTM_Test8_dcm
-        PORT(
-                CLKIN_IN : IN std_logic;
-                RST_IN : IN std_logic;          
-                CLKFX_OUT : OUT std_logic;
-                CLK0_OUT : OUT std_logic;
-                LOCKED_OUT : OUT std_logic
-                );
-        END COMPONENT;
-
-
+  COMPONENT FTM_Test8_dcm
+    PORT(
+      CLKIN_IN : IN std_logic;
+      RST_IN : IN std_logic;          
+      CLKFX_OUT : OUT std_logic;
+      CLK0_OUT : OUT std_logic;
+      LOCKED_OUT : OUT std_logic
+      );
+  END COMPONENT;
 
   component FTM_test8_rs485_interface
     GENERIC( 
-      CLOCK_FREQUENCY : integer := 50000000;      -- Hertz
-      BAUD_RATE       : integer := 250000         -- bits / sec
+      CLOCK_FREQUENCY : integer;      -- Hertz
+      BAUD_RATE       : integer       -- bits / sec
     );
     PORT( 
@@ -313 +296 @@
       -- FPGA
       rx_data  : OUT    std_logic_vector(7 DOWNTO 0);
-   --   rx_busy  : OUT    std_logic := '0';
+      -- rx_busy  : OUT    std_logic := '0';
       rx_valid : OUT    std_logic := '0';
       tx_data  : IN     std_logic_vector(7 DOWNTO 0);
@@ -323 +306 @@
   signal reset_sig   : STD_LOGIC := '0'; -- initialize reset to 0 at power up 
   signal clk_50M_sig : STD_LOGIC;
-
   
  -- signal enable_sig : enable_array_type := DEFAULT_ENABLE;                  
-
   
   signal rx_en_sig    : STD_LOGIC := '0';
@@ -339 +320 @@
   signal FTM_test8_State, FTM_test8_NextState: FTM_test8_StateType;
 
-
-
-
-
 begin
 
-Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP(
-                CLKIN_IN => clk,
-                RST_IN => reset_sig,
-                CLKFX_OUT => clk_50M_sig,
-                CLK0_OUT => open,
-                LOCKED_OUT => open
-        );
-
-
+  Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP(
+    CLKIN_IN => clk,
+    RST_IN => reset_sig,
+    CLKFX_OUT => clk_50M_sig,
+    CLK0_OUT => open,
+    LOCKED_OUT => open
+  );
 
   Inst_FTM_test8_rs485_interface : FTM_test8_rs485_interface
@@ -359 +334 @@
       CLOCK_FREQUENCY => 50000000,
   --  BAUD_RATE       => 10000000       --simulation
-      BAUD_RATE       => 25000          --implement
+      BAUD_RATE       => 250000          --implement
     )
     port map(
@@ -376 +351 @@
       tx_start => '0'
     );
-  
---  enables_A <= enable_sig(0)(8 downto 0);
---  enables_B <= enable_sig(1)(8 downto 0);
---  enables_C <= enable_sig(2)(8 downto 0);
---  enables_D <= enable_sig(3)(8 downto 0);
-  
-  
+    
   Bus1_Rx_En <= rx_en_sig;
   Bus1_Tx_En <= tx_en_sig;
   Bus1_TxD_0 <= tx_sig;
   rx_sig     <= Bus1_RxD_0;
-
-
-
   
   --FTM main state machine (two-process implementation)
@@ -405 +371 @@
     case FTM_test8_State is
       when INIT =>
-        reset_sig <= '0';
-        
-                  LED_red <= ("0000");
-                  
+        reset_sig <= '0';        
+        LED_red <= "0000";        
         if (rx_data_sig = "00110001" and rx_valid_sig = '1') then
           FTM_test8_NextState <= RUN1;
@@ -422 +386 @@
       when RUN1 =>
         reset_sig <= '0';
-        
-       -- enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111");
-        LED_red <= ("0001");
-        
+        LED_red <= "0001";
         if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
           FTM_test8_NextState <= INIT;
@@ -439 +400 @@
       when RUN2 =>
         reset_sig <= '0';
-        
-      --  enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111");
-        LED_red <= ("0010");
-        
+        LED_red <= "0010";        
         if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
           FTM_test8_NextState <= INIT;
@@ -456 +414 @@
       when RUN3 =>
         reset_sig <= '0';
-        
-     --   enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111");
-        LED_red <= ("0100");
-        
+        LED_red <= "0100";
         if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
           FTM_test8_NextState <= INIT;
@@ -473 +428 @@
       when RUN4 =>
         reset_sig <= '0';
-        
-      --  enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000");
-        LED_red <= ("1000");
-        
+        LED_red <= "1000";        
         if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
           FTM_test8_NextState <= INIT;
@@ -491 +443 @@
   end process FTM_test8_C_logic;
  
-
-
-
-
-LED_ye  <= ("11");
-LED_gn  <= ("11");
-
-
-  
+  LED_ye  <= "11";
+  LED_gn  <= "11";
 
 end Behavioral;

firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf

@@ -173 +173 @@
 
 # yellow
-# NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
-# NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
+ NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0  
+ NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
 
 # green
-# NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
-# NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
+ NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0  
+ NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0