Index: firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd (revision 10058) @@ -16,4 +16,5 @@ -- Revision: -- Revision 0.01 - File Created +-- Revision 0.02 - Some modifications, November 15, 2010, Q. Weitzel -- Additional Comments: -- @@ -25,5 +26,4 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; - Library UNISIM; use UNISIM.vcomponents.all; @@ -34,18 +34,13 @@ --use UNISIM.VComponents.all; - -- library FTM_definitions_test3; -- USE FTM_definitions_test3.ftm_array_types.all; - - entity FTM_test8 is port( - -- Clock clk : IN STD_LOGIC; -- external clock from -- oscillator U47 - -- connection to the WIZnet W5300 ethernet controller -- on IO-Bank 1 @@ -123,6 +118,4 @@ LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green - - -- Clock conditioner LMK03000 -- on IO-Bank 3 @@ -135,7 +128,4 @@ -- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect - - - -- various RS-485 Interfaces -- on IO-Bank 3 @@ -280,27 +270,20 @@ end FTM_test8; - architecture Behavioral of FTM_test8 is - - - - - COMPONENT FTM_Test8_dcm - PORT( - CLKIN_IN : IN std_logic; - RST_IN : IN std_logic; - CLKFX_OUT : OUT std_logic; - CLK0_OUT : OUT std_logic; - LOCKED_OUT : OUT std_logic - ); - END COMPONENT; - - + COMPONENT FTM_Test8_dcm + PORT( + CLKIN_IN : IN std_logic; + RST_IN : IN std_logic; + CLKFX_OUT : OUT std_logic; + CLK0_OUT : OUT std_logic; + LOCKED_OUT : OUT std_logic + ); + END COMPONENT; component FTM_test8_rs485_interface GENERIC( - CLOCK_FREQUENCY : integer := 50000000; -- Hertz - BAUD_RATE : integer := 250000 -- bits / sec + CLOCK_FREQUENCY : integer; -- Hertz + BAUD_RATE : integer -- bits / sec ); PORT( @@ -313,5 +296,5 @@ -- FPGA rx_data : OUT std_logic_vector(7 DOWNTO 0); - -- rx_busy : OUT std_logic := '0'; + -- rx_busy : OUT std_logic := '0'; rx_valid : OUT std_logic := '0'; tx_data : IN std_logic_vector(7 DOWNTO 0); @@ -323,8 +306,6 @@ signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up signal clk_50M_sig : STD_LOGIC; - -- signal enable_sig : enable_array_type := DEFAULT_ENABLE; - signal rx_en_sig : STD_LOGIC := '0'; @@ -339,19 +320,13 @@ signal FTM_test8_State, FTM_test8_NextState: FTM_test8_StateType; - - - - begin -Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP( - CLKIN_IN => clk, - RST_IN => reset_sig, - CLKFX_OUT => clk_50M_sig, - CLK0_OUT => open, - LOCKED_OUT => open - ); - - + Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP( + CLKIN_IN => clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLK0_OUT => open, + LOCKED_OUT => open + ); Inst_FTM_test8_rs485_interface : FTM_test8_rs485_interface @@ -359,5 +334,5 @@ CLOCK_FREQUENCY => 50000000, -- BAUD_RATE => 10000000 --simulation - BAUD_RATE => 25000 --implement + BAUD_RATE => 250000 --implement ) port map( @@ -376,18 +351,9 @@ tx_start => '0' ); - --- enables_A <= enable_sig(0)(8 downto 0); --- enables_B <= enable_sig(1)(8 downto 0); --- enables_C <= enable_sig(2)(8 downto 0); --- enables_D <= enable_sig(3)(8 downto 0); - - + Bus1_Rx_En <= rx_en_sig; Bus1_Tx_En <= tx_en_sig; Bus1_TxD_0 <= tx_sig; rx_sig <= Bus1_RxD_0; - - - --FTM main state machine (two-process implementation) @@ -405,8 +371,6 @@ case FTM_test8_State is when INIT => - reset_sig <= '0'; - - LED_red <= ("0000"); - + reset_sig <= '0'; + LED_red <= "0000"; if (rx_data_sig = "00110001" and rx_valid_sig = '1') then FTM_test8_NextState <= RUN1; @@ -422,8 +386,5 @@ when RUN1 => reset_sig <= '0'; - - -- enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111"); - LED_red <= ("0001"); - + LED_red <= "0001"; if (rx_data_sig = "00110000" and rx_valid_sig = '1') then FTM_test8_NextState <= INIT; @@ -439,8 +400,5 @@ when RUN2 => reset_sig <= '0'; - - -- enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111"); - LED_red <= ("0010"); - + LED_red <= "0010"; if (rx_data_sig = "00110000" and rx_valid_sig = '1') then FTM_test8_NextState <= INIT; @@ -456,8 +414,5 @@ when RUN3 => reset_sig <= '0'; - - -- enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111"); - LED_red <= ("0100"); - + LED_red <= "0100"; if (rx_data_sig = "00110000" and rx_valid_sig = '1') then FTM_test8_NextState <= INIT; @@ -473,8 +428,5 @@ when RUN4 => reset_sig <= '0'; - - -- enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000"); - LED_red <= ("1000"); - + LED_red <= "1000"; if (rx_data_sig = "00110000" and rx_valid_sig = '1') then FTM_test8_NextState <= INIT; @@ -491,13 +443,6 @@ end process FTM_test8_C_logic; - - - - -LED_ye <= ("11"); -LED_gn <= ("11"); - - - + LED_ye <= "11"; + LED_gn <= "11"; end Behavioral; Index: firmware/FTM/test_firmware/FTM_test8/FTM_test8_tb.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test8/FTM_test8_tb.vhd (revision 10058) +++ firmware/FTM/test_firmware/FTM_test8/FTM_test8_tb.vhd (revision 10058) @@ -0,0 +1,159 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel, P. Vogler +-- +-- Create Date: 16.11.2010 +-- Design Name: +-- Module Name: FTM_test8_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for FTM RS485 test +-- +-- VHDL Test Bench Created by ISE for module: FTM_test8 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity FTU_test8_tb is +end FTU_test8_tb; + +architecture behavior of FTU_test8_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTM_test8 + port( + clk : in STD_LOGIC; + LED_red : out STD_LOGIC_VECTOR(3 downto 0); + LED_ye : out STD_LOGIC_VECTOR(1 downto 0); + LED_gn : out STD_LOGIC_VECTOR(1 downto 0); + Bus1_Tx_En : out STD_LOGIC; + Bus1_Rx_En : out STD_LOGIC; + Bus1_RxD_0 : in STD_LOGIC; + Bus1_TxD_0 : out STD_LOGIC + ); + end component; + + --Inputs + signal clk_sig : STD_LOGIC := '0'; + signal Bus1_RxD_0_sig : STD_LOGIC := '1'; + + --Outputs + signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0); + signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0); + signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0); + signal Bus1_Tx_En_sig : STD_LOGIC; + signal Bus1_Rx_En_sig : STD_LOGIC; + signal Bus1_TxD_0_sig : STD_LOGIC; + + -- Clock period definitions + constant clk_period : TIME := 25 ns; + constant baud_rate_period : TIME := 4 us; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTM_test8 + port map( + clk => clk_sig, + LED_red => LED_red_sig, + LED_ye => LED_ye_sig, + LED_gn => LED_gn_sig, + Bus1_Tx_En => Bus1_Tx_En_sig, + Bus1_Rx_En => Bus1_Rx_En_sig, + Bus1_RxD_0 => Bus1_RxD_0_sig, + Bus1_TxD_0 => Bus1_TxD_0_sig + ); + + -- Stimulus process for clock + clk_proc: process + begin + clk_sig <= '0'; + wait for clk_period/2; + clk_sig <= '1'; + wait for clk_period/2; + end process clk_proc; + + -- Stimulus process for RS485 + rs485_proc: process + + procedure assign_rs485 (data: std_logic_vector(7 downto 0)) is + begin + Bus1_RxD_0_sig <= '0'; --start bit + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(0); --bit 0 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(1); --bit 1 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(2); --bit 2 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(3); --bit 3 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(4); --bit 4 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(5); --bit 5 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(6); --bit 6 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(7); --bit 7 + wait for baud_rate_period; + Bus1_RxD_0_sig <= '1'; --stop bit + wait for baud_rate_period; + Bus1_RxD_0_sig <= '1'; --stop bit + wait for baud_rate_period; + end assign_rs485; + + begin + wait for 1us; + --------------------------------------------------------------------------- + -- send a '1' character + --------------------------------------------------------------------------- + assign_rs485("00110001"); + wait for 1us; + --------------------------------------------------------------------------- + -- send a '2' character + --------------------------------------------------------------------------- + assign_rs485("00110010"); + wait for 1us; + --------------------------------------------------------------------------- + -- send a '3' character + --------------------------------------------------------------------------- + assign_rs485("00110011"); + wait for 1us; + --------------------------------------------------------------------------- + -- send a '4' character + --------------------------------------------------------------------------- + assign_rs485("00110100"); + wait for 1us; + --------------------------------------------------------------------------- + -- send a '0' character + --------------------------------------------------------------------------- + assign_rs485("00110000"); + wait for 1us; + --------------------------------------------------------------------------- + -- don't forget final wait! + --------------------------------------------------------------------------- + wait; + + end process rs485_proc; + +end; Index: firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf (revision 10046) +++ firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf (revision 10058) @@ -173,10 +173,10 @@ # yellow -# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 -# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 # green -# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 -# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0