Ignore:
Timestamp:
01/03/11 15:26:12 (14 years ago)
Author:
neise
Message:
block to block communication 
debugged - part 1
File:
1 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd

    r9912 r10072  
    3232      config_data_valid : OUT    std_logic := '0';
    3333      config_busy       : OUT    std_logic := '0';
     34      -- --
     35      config_rw_ack, config_rw_ready : out std_logic := '0';
     36      -- --
    3437      ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
    3538      ram_data_in       : OUT    std_logic_vector (15 DOWNTO 0);
    3639      ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
    3740      dac_array         : OUT    dac_array_type;
    38       roi_array         : OUT    roi_array_type;
    39       drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
    40       drs_address_mode  : OUT    std_logic
     41      roi_array         : OUT    roi_array_type
    4142   );
    4243
     
    4748ARCHITECTURE beha OF control_manager IS
    4849 
    49   type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE,
     50  type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, CTRL_WRITE_READY,
    5051                           CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA,
    5152                           CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA);
     
    5556  signal int_dac_array : dac_array_type := DEFAULT_DAC;
    5657  signal int_roi_array : roi_array_type := DEFAULT_ROI;
    57   signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR;
    58   signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE;
    5958
    6059BEGIN
     
    8180          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
    8281            ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16);
    83           elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
    84             ram_data_in <=  "0000" & "0000"
    85                             & "000" & conv_std_logic_vector(int_drs_address_mode, 1)
    86                             & int_drs_address;
    8782          else
    8883            ram_write_en <= "0";
     
    9186     
    9287        when CTRL_IDLE =>
    93           --
    9488          addr_cntr <= 0;
    9589          ram_write_en <= "0";
     
    10397          if (config_wr_en = '1') then
    10498            config_busy <= '1';
     99            config_rw_ack <= '1';
     100            config_rw_ready <= '0';
    105101            config_data <= (others => 'Z');
    106102            ctrl_state <= CTRL_WRITE;
     
    129125            dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out);
    130126            ctrl_state <= CTRL_LOAD_ADDR;
    131           elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
    132              drs_address <= ram_data_out(3 downto 0);
    133              drs_address_mode <= ram_data_out(4);
    134              ctrl_state <= CTRL_LOAD_ADDR;
    135           else
     127          else
    136128            addr_cntr <= 0;
    137129            config_started <= '0';
     
    144136          ram_addr <= config_addr;
    145137          ram_write_en <= "1";
    146           ctrl_state <= CTRL_IDLE;
     138          ctrl_state <= CTRL_WRITE_READY;
     139        when CTRL_WRITE_READY =>
     140          config_rw_ack <= '0';
     141          config_rw_ready <= '1';
     142          if (config_wr_en = '0') then
     143            ctrl_state <= CTRL_IDLE;
     144          end if;
    147145       
    148146        -- *** IMPORTANT ***
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