Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 10072) @@ -32,11 +32,12 @@ config_data_valid : OUT std_logic := '0'; config_busy : OUT std_logic := '0'; + -- -- + config_rw_ack, config_rw_ready : out std_logic := '0'; + -- -- ram_addr : OUT std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0); ram_data_in : OUT std_logic_vector (15 DOWNTO 0); ram_write_en : OUT std_logic_vector (0 DOWNTO 0); dac_array : OUT dac_array_type; - roi_array : OUT roi_array_type; - drs_address : OUT std_logic_vector (3 DOWNTO 0); - drs_address_mode : OUT std_logic + roi_array : OUT roi_array_type ); @@ -47,5 +48,5 @@ ARCHITECTURE beha OF control_manager IS - type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, + type TYPE_CTRL_STATE is (CTRL_INIT, CTRL_IDLE, CTRL_WAIT_IDLE, CTRL_WRITE, CTRL_WRITE_READY, CTRL_LOAD_ADDR, CTRL_LOAD_WAIT, CTRL_LOAD_DATA, CTRL_READ_ADDR, CTRL_READ_WAIT, CTRL_READ_DATA); @@ -55,6 +56,4 @@ signal int_dac_array : dac_array_type := DEFAULT_DAC; signal int_roi_array : roi_array_type := DEFAULT_ROI; - signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR; - signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE; BEGIN @@ -81,8 +80,4 @@ elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); - elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then - ram_data_in <= "0000" & "0000" - & "000" & conv_std_logic_vector(int_drs_address_mode, 1) - & int_drs_address; else ram_write_en <= "0"; @@ -91,5 +86,4 @@ when CTRL_IDLE => - -- addr_cntr <= 0; ram_write_en <= "0"; @@ -103,4 +97,6 @@ if (config_wr_en = '1') then config_busy <= '1'; + config_rw_ack <= '1'; + config_rw_ready <= '0'; config_data <= (others => 'Z'); ctrl_state <= CTRL_WRITE; @@ -129,9 +125,5 @@ dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); ctrl_state <= CTRL_LOAD_ADDR; - elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then - drs_address <= ram_data_out(3 downto 0); - drs_address_mode <= ram_data_out(4); - ctrl_state <= CTRL_LOAD_ADDR; - else + else addr_cntr <= 0; config_started <= '0'; @@ -144,5 +136,11 @@ ram_addr <= config_addr; ram_write_en <= "1"; - ctrl_state <= CTRL_IDLE; + ctrl_state <= CTRL_WRITE_READY; + when CTRL_WRITE_READY => + config_rw_ack <= '0'; + config_rw_ready <= '1'; + if (config_wr_en = '0') then + ctrl_state <= CTRL_IDLE; + end if; -- *** IMPORTANT *** Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10072) @@ -25,4 +25,6 @@ ); port( +-- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + clk : in std_logic; data_out : out std_logic_vector (63 downto 0); @@ -32,4 +34,7 @@ ram_write_ea : in std_logic; ram_write_ready : out std_logic := '0'; + -- -- + ram_write_ready_ack : IN std_logic; + -- -- config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; @@ -45,5 +50,5 @@ trigger_id : in std_logic_vector (47 downto 0); trigger : in std_logic; - s_trigger : in std_logic; +-- s_trigger : in std_logic; new_config : in std_logic; config_started : out std_logic := '0'; @@ -55,4 +60,10 @@ drs_dwrite : out std_logic := '1'; drs_clk_en, drs_read_s_cell : out std_logic := '0'; + + drs_srin_write_8b : out std_logic := '0'; + drs_srin_write_ack : in std_logic; + drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0'); + drs_srin_write_ready : in std_logic; + drs_read_s_cell_ready : in std_logic; drs_s_cell_array : in drs_s_cell_array_type @@ -62,5 +73,5 @@ architecture Behavioral of data_generator is -type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, +type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, WRITE_END_FLAG, WRITE_DATA_STOP, @@ -76,6 +87,9 @@ signal adc_wait_cnt : integer range 0 to 7 := 0; -signal trigger_flag : std_logic := '0'; - +signal trigger_flag :std_logic := '0'; +signal ram_write_ea_flag : std_logic := '0'; +signal new_config_int : std_logic := '0'; + +signal roi_max_int : roi_max_type; begin @@ -95,31 +109,49 @@ when CONFIG => config_started <= '1'; - -- config config manager - config_start_cm <= '1'; - if (config_started_cm = '1') then - state_generate <= CONFIG1; + if (new_config = '0') then + config_started <= '0'; + -- config config manager + config_start_cm <= '1'; + if (config_started_cm = '1') then + config_start_cm <= '0'; + state_generate <= CONFIG1; + end if; end if; when CONFIG1 => if (config_ready_cm = '1') then - config_started <= '0'; - config_start_cm <= '0'; config_start_mm <= '1'; end if; if (config_started_mm = '1') then + config_start_mm <= '0'; state_generate <= CONFIG2; end if; when CONFIG2 => if (config_ready_mm = '1') then - config_start_mm <= '0'; config_start_spi <= '1'; end if; if (config_started_spi = '1') then + config_start_spi <= '0'; state_generate <= CONFIG3; end if; when CONFIG3 => if (config_ready_spi = '1') then - config_start_spi <= '0'; + state_generate <= CONFIG4; +-- state_generate <= WRITE_DATA_IDLE; + end if; + -- configure DRS + when CONFIG4 => + drs_channel_id <= DRS_WRITE_SHIFT_REG; + drs_srin_data <= "10101010"; + drs_srin_write_8b <= '1'; + if (drs_srin_write_ack = '1') then + drs_srin_write_8b <= '0'; + state_generate <= CONFIG5; + end if; + when CONFIG5 => + if (drs_srin_write_ready = '1') then + roi_max_int <= roi_max; state_generate <= WRITE_DATA_IDLE; end if; + -- end configure DRS when WRITE_DATA_IDLE => @@ -127,5 +159,6 @@ state_generate <= CONFIG; end if; - if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then +-- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then + if (ram_write_ea = '1' and trigger_flag = '1') then -- stop drs, dwrite low drs_dwrite <= '0'; @@ -248,5 +281,6 @@ when WRITE_EXTERNAL_TRIGGER => -- external trigger ID addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); - data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); +-- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); + data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); state_generate <= WRITE_INTERNAL_TRIGGER; when WRITE_INTERNAL_TRIGGER => -- internal trigger ID @@ -263,13 +297,24 @@ state_generate <= WRITE_DATA_END_WAIT; when WRITE_DATA_END_WAIT => - state_generate <= WRITE_DATA_STOP; + -- -- + if (ram_write_ready_ack = '1') then + state_generate <= WRITE_DATA_STOP; + -- -- + ram_write_ready <= '0'; + -- -- + end if; + -- -- when WRITE_DATA_STOP => - drs_dwrite <= '1'; - data_cntr <= 0; - addr_cntr <= 0; - channel_id <= 0; - ram_write_ready <= '0'; - state_generate <= WRITE_DATA_IDLE; - + -- -- + if (ram_write_ready_ack = '0') then + -- -- + drs_dwrite <= '1'; + data_cntr <= 0; + addr_cntr <= 0; + channel_id <= 0; + state_generate <= WRITE_DATA_IDLE; + -- -- + end if; + -- -- when others => null; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 10072) @@ -76,4 +76,6 @@ signal adc_wait_cnt : integer range 0 to 7 := 0; +signal trigger_flag : std_logic := '0'; + begin @@ -83,4 +85,5 @@ begin if rising_edge (clk) then + trigger_flag <= trigger; addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); @@ -124,5 +127,5 @@ state_generate <= CONFIG; end if; - if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then + if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then -- stop drs, dwrite low drs_dwrite <= '0'; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd (revision 10072) @@ -23,4 +23,10 @@ stop_pos_valid : out std_logic := '0'; + start_srin_write_8b : in std_logic; + srin_write_ready : out std_logic := '0'; + srin_write_ack : out std_logic := '0'; + srin_data : in std_logic_vector (7 downto 0); + SRIN_out : out std_logic := '0'; + RSRLOAD : out std_logic := '0'; SRCLK : out std_logic := '0' @@ -31,5 +37,5 @@ ARCHITECTURE behavior of drs_pulser IS -type state_main_type is (MAIN, READ_STOP_POS, ENDLESS_MODE); +type state_main_type is (MAIN, SRIN_WRITE_8B, SRIN_WRITE_END, READ_STOP_POS, ENDLESS_MODE); signal state_main : state_main_type := MAIN; signal stop_pos_cntr, wait_cntr : integer range 0 to 31 := 0; @@ -37,4 +43,6 @@ signal stop_pos_int : drs_s_cell_array_type; signal RSRLOAD_EN, SRCLK_EN : std_logic := '0'; + +signal srin_cntr : integer range 0 to 7 := 1; begin @@ -49,4 +57,11 @@ case state_main is when MAIN => + if (start_srin_write_8b = '1') then + srin_write_ready <= '0'; + srin_write_ack <= '1'; + srin_cntr <= 0; + SRCLK_EN <= '1'; + state_main <= SRIN_WRITE_8B; + end if; if (start_read_stop_pos_mode = '1') then RSRLOAD_EN <= '1'; @@ -58,4 +73,19 @@ state_main <= ENDLESS_MODE; end if; + + when SRIN_WRITE_8B => + srin_out <= srin_data (7 - srin_cntr); + if (srin_cntr = 7) then + SRCLK_EN <= '0'; + state_main <= SRIN_WRITE_END; + else + srin_cntr <= srin_cntr + 1; + end if; + when SRIN_WRITE_END => + srin_out <= '0'; + srin_write_ready <= '1'; + srin_write_ack <= '0'; + state_main <= MAIN; + when ENDLESS_MODE => Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10072) @@ -79,5 +79,6 @@ -- - constant W5300_TX_FIFO_SIZE : integer := (15360 / 2); -- Socket TX FIFO-Size in 16 Bit Words + constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes + constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words constant LOG2_OF_RAM_SIZE_64B : integer := 15; @@ -119,4 +120,7 @@ constant CMD_READ : std_logic_vector := X"0A"; constant CMD_WRITE : std_logic_vector := X"05"; +-- Config-RAM + constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values + constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values constant CMD_DENABLE : std_logic_vector := X"06"; @@ -135,5 +139,6 @@ constant CMD_PS_RESET : std_logic_vector := X"17"; - +-- DRS Registers + constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10072) @@ -36,4 +36,7 @@ config_start : IN std_logic; ram_write_ready : IN std_logic; + -- -- + ram_write_ready_ack : OUT std_logic := '0'; + -- -- roi_array : IN roi_array_type; ram_write_ea : OUT std_logic := '0'; @@ -59,5 +62,5 @@ ARCHITECTURE beha OF memory_manager IS -type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1); +type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1, MM_MAIN2, MM_MAIN3, MM_MAIN4); signal state_mm : state_mm_type := MM_CONFIG; @@ -93,5 +96,5 @@ signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); signal event_ready_flag : std_logic := '0'; -signal wiz_ack_flag : std_logic := '0'; +signal wiz_ack_flag, wiz_write_ea_flag: std_logic := '0'; signal roi_index : integer range 0 to 45 := 0; @@ -99,4 +102,6 @@ BEGIN + +-- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; mm : process (clk) @@ -207,22 +212,12 @@ roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); end loop; + + event_ready_flag <= '0'; + wiz_ack_flag <= '0'; + wiz_write_ea_flag <= '0'; state_mm <= MM_MAIN; when MM_MAIN => state_mm <= MM_MAIN1; - if ((ram_write_ready = '1') and (event_ready_flag = '0')) then - ram_write_ea <= '0'; - events_in_ram <= events_in_ram + 1; - if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then - event_start_addr <= event_start_addr + event_size_ram_64b; - else - event_start_addr <= 0; - end if; - event_ready_flag <= '1'; - end if; - - - when MM_MAIN1 => - state_mm <= MM_MAIN; if (config_start = '1') then config_ready <= '0'; @@ -231,12 +226,55 @@ end if; end if; - if (event_ready_flag = '1') then + + when MM_MAIN1 => + state_mm <= MM_MAIN2; + if ((ram_write_ready = '1') and (event_ready_flag = '0')) then + ram_write_ea <= '0'; + -- -- + ram_write_ready_ack <= '1'; + -- -- + events_in_ram <= events_in_ram + 1; + if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then + event_start_addr <= event_start_addr + event_size_ram_64b; + else + event_start_addr <= 0; + end if; + event_ready_flag <= '1'; + end if; + + + when MM_MAIN2 => + state_mm <= MM_MAIN3; + if ((event_ready_flag = '1') and (ram_write_ready = '0')) then if (events_in_ram < max_events_ram) then ram_write_ea <= '1'; ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); event_ready_flag <= '0'; - end if; - end if; - + -- -- + ram_write_ready_ack <= '0'; + -- -- + end if; + end if; + + when MM_MAIN3 => + state_mm <= MM_MAIN4; + if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then + wiz_ack_flag <= '1'; + wiz_write_ea <= '0'; + package_index <= package_index + 1; + if (package_index = (number_of_packages - 1)) then + -- next address + if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + else + write_start_addr <= 0; + end if; + else + write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); + end if; + end if; -- wiz_ack_int + + when MM_MAIN4 => + state_mm <= MM_MAIN; if ((events_in_ram > 0) and (wiz_busy = '0')) then if (package_index < number_of_packages) then @@ -264,20 +302,5 @@ end if; - if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then - wiz_ack_flag <= '1'; - wiz_write_ea <= '0'; - package_index <= package_index + 1; - if (package_index = (number_of_packages - 1)) then - -- next address - if ((write_start_addr + fifo_package_size_ram (package_index)) < (RAM_SIZE_16B - event_size_ram)) then - write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); - else - write_start_addr <= 0; - end if; - else - write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); - end if; - end if; -- wiz_ack - + end case; -- state_mm end if; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 9916) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10072) @@ -60,4 +60,7 @@ config_wr_en : out std_logic := '0'; config_rd_en : out std_logic := '0'; + -- -- + config_rw_ack, config_rw_ready : in std_logic; + -- -- config_busy : in std_logic; @@ -82,6 +85,6 @@ type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, - SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA); -type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); +type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); @@ -120,4 +123,9 @@ signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); signal chk_recv_cntr : integer range 0 to 10000 := 0; + +-- -- +signal wait_cntr : integer range 0 to 10000 := 0; +-- -- + signal rx_packets_cnt : std_logic_vector (15 downto 0); signal next_packet_data : std_logic := '0'; @@ -133,4 +141,11 @@ signal local_fifo_channels : std_logic_vector (3 downto 0); +signal data_valid_int : std_logic := '0'; + +-- only for debugging +--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); +--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0'); + + begin @@ -138,4 +153,5 @@ RST_TIME <= X"00120"; --synthesis translate_on + w5300_init_proc : process (clk, int) @@ -220,7 +236,8 @@ -- reset W5300 when RESET => + busy <= '1'; zaehler <= zaehler + 1; wiz_reset <= '0'; - led <= X"FF"; +-- led <= X"FF"; if (zaehler >= X"00064") then -- wait 2µs wiz_reset <= '1'; @@ -356,15 +373,16 @@ par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8); state_init <= WRITE_REG; - next_state <= TIMEOUT; - when TIMEOUT => - par_addr <= W5300_RTR; - par_data <= X"07D0"; -- 0x07D0 = 200ms - state_init <= WRITE_REG; - next_state <= RETRY; - when RETRY => - par_addr <= W5300_RCR; - par_data <= X"0008"; - state_init <= WRITE_REG; next_state <= SI; +-- when TIMEOUT => +-- par_addr <= W5300_RTR; +-- par_data <= X"07D0"; -- 0x07D0 = 200ms +-- state_init <= WRITE_REG; +-- next_state <= RETRY; +-- when RETRY => +-- par_addr <= W5300_RCR; +-- par_data <= X"0008"; +-- state_init <= WRITE_REG; +-- next_state <= SI; +-- -- Socket Init @@ -418,5 +436,6 @@ next_state <= EST1; when EST1 => - led <= data_read (7 downto 0); +-- led <= data_read (7 downto 0); +-- led <= X"00"; case data_read (7 downto 0) is when X"17" => -- established @@ -434,10 +453,9 @@ when CONFIG => - led <= X"F0"; +-- led <= X"F0"; new_config <= '1'; if (config_started = '1') then - led <= X"0F"; +-- led <= X"0F"; new_config <= '0'; - busy <= '0'; state_init <= MAIN; end if; @@ -448,6 +466,10 @@ ps_reset <= '0'; if (trigger_stop = '1') then - s_trigger <= '0'; - end if; + s_trigger <= '0'; + end if; + data_valid_ack <= '0'; + state_init <= MAIN1; + data_valid_int <= data_valid; + when MAIN1 => if (chk_recv_cntr = 1000) then chk_recv_cntr <= 0; @@ -456,20 +478,31 @@ busy <= '1'; else - busy <= '0'; - data_valid_ack <= '0'; chk_recv_cntr <= chk_recv_cntr + 1; - if (data_valid = '1') then - data_valid_ack <= '1'; - local_write_length <= write_length; - local_ram_start_addr <= ram_start_addr; - local_ram_addr <= (others => '0'); - local_write_header_flag <= write_header_flag; - local_write_end_flag <= write_end_flag; - local_fifo_channels <= fifo_channels; - next_state <= MAIN; - state_init <= WRITE_DATA; - busy <= '1'; - end if; - end if; + state_init <= MAIN2; + end if; + when MAIN2 => + busy <= '0'; + if (data_valid = '1') then + data_valid_int <= '0'; + busy <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; +-- data_valid_ack <= '1'; +-- next_state <= MAIN; +-- state_init <= WRITE_DATA; + state_init <= MAIN3; + else + state_init <= MAIN1; + end if; + when MAIN3 => +-- led <= local_ram_start_addr (7 downto 0); + data_valid_ack <= '1'; + next_state <= MAIN; + state_init <= WRITE_DATA; + -- read data from socket 0 @@ -507,14 +540,7 @@ else state_read_data <= RD_END; --- if (new_config_flag = '1') then --- new_config_flag <= '0'; --- state_init <= CONFIG; --- else --- busy <= '0'; --- state_init <= MAIN; --- end if; end if; when RD_6 => - led <= data_read (15 downto 8); +-- led <= data_read (15 downto 8); -- read command if (next_packet_data = '0') then @@ -523,49 +549,49 @@ trigger_stop <= '1'; s_trigger <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_DWRITE_RUN => dwrite_enable <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_DWRITE_STOP => dwrite_enable <= '0'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_SCLK_ON => sclk_enable <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_SCLK_OFF => sclk_enable <= '0'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_DENABLE => denable <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_DDISABLE => denable <= '0'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_TRIGGER_C => trigger_stop <= '0'; s_trigger <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_TRIGGER_S => trigger_stop <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; -- phase shift commands here: when CMD_PS_DO => ps_do_phase_shift <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_PS_DIRINC => ps_direction <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_PS_RESET => ps_reset <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_SRCLK_ON => srclk_enable <= '1'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_SRCLK_OFF => srclk_enable <= '0'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_PS_DIRDEC => ps_direction <= '0'; - state_read_data <= RD_WAIT; + state_read_data <= RD_5; when CMD_WRITE => next_packet_data <= '1'; @@ -586,9 +612,13 @@ end if; when RD_WAIT => - state_read_data <= RD_WAIT1; + if (config_rw_ack = '1') then + state_read_data <= RD_WAIT1; + end if; when RD_WAIT1 => - config_data <= (others => 'Z'); - config_wr_en <= '0'; - state_read_data <= RD_5; + if (config_rw_ready = '1') then + config_data <= (others => 'Z'); + config_wr_en <= '0'; + state_read_data <= RD_5; + end if; when RD_END => par_addr <= W5300_S0_CR; @@ -599,5 +629,4 @@ next_state <= CONFIG; else --- busy <= '0'; next_state <= MAIN; end if; @@ -619,4 +648,5 @@ if (local_write_header_flag = '1') then local_socket_nr <= ram_data (2 downto 0); +-- local_socket_nr <= "000"; end if; next_state_tmp <= next_state; @@ -640,5 +670,9 @@ state_write <= WR_04; when WR_04 => - if (socket_tx_free (16 downto 0) < write_length_bytes) then + +-- led <= socket_tx_free (15 downto 8); + +-- if (socket_tx_free (16 downto 0) < write_length_bytes) then + if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then state_write <= WR_01; else @@ -751,7 +785,18 @@ state_init <= WRITE_REG; next_state <= WRITE_DATA; - state_write <= WR_05; + state_write <= WR_05a; -- End Write End Package Flag + + -- Wait???? + when WR_05a => + if (wait_cntr < 10) then -- 3000 works??? + wait_cntr <= wait_cntr + 1; + else + wait_cntr <= 0; + state_write <= WR_05b; + end if; + when WR_05b => + state_write <= WR_05; --Send FIFO @@ -773,5 +818,4 @@ state_write <= WR_08; when others => --- busy <= '0'; state_init <= next_state_tmp; state_write <= WR_START;