Changeset 10073 for firmware


Ignore:
Timestamp:
01/04/11 10:03:04 (14 years ago)
Author:
neise
Message:
 
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
25 edited

Legend:

Unmodified
Added
Removed

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r9912 r10073  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 10:49:24 30.08.2010
     5--          at - 14:00:25 01.10.2010
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    4141-- Created:
    4242--          by - dneise.UNKNOWN (E5B-LABOR6)
    43 --          at - 10:49:25 30.08.2010
     43--          at - 14:00:25 01.10.2010
    4444--
    4545-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd

    r9912 r10073  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 09:42:04 30.07.2010
     5--          at - 17:00:23 03.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    2323      config_data_valid : OUT    std_logic;
    2424      config_ready      : OUT    std_logic;
     25      -- --
     26      config_rw_ack     : OUT    std_logic  := '0';
     27      -- --
     28      config_rw_ready   : OUT    std_logic  := '0';
    2529      config_started    : OUT    std_logic  := '0';
    2630      dac_array         : OUT    dac_array_type;
    27       drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
    28       drs_address_mode  : OUT    std_logic;
    2931      roi_array         : OUT    roi_array_type;
    3032      config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
    … …  
    4042-- Created:
    4143--          by - dneise.UNKNOWN (E5B-LABOR6)
    42 --          at - 09:42:04 30.07.2010
     44--          at - 17:00:23 03.01.2011
    4345--
    4446-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    9193      config_data_valid : OUT    std_logic                      := '0';
    9294      config_busy       : OUT    std_logic                      := '0';
     95      -- --
     96      config_rw_ack     : OUT    std_logic                      := '0';
     97      -- --
     98      config_rw_ready   : OUT    std_logic                      := '0';
     99      -- --
    93100      ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
    94101      ram_data_in       : OUT    std_logic_vector (15 DOWNTO 0);
    95102      ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
    96103      dac_array         : OUT    dac_array_type ;
    97       roi_array         : OUT    roi_array_type ;
    98       drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
    99       drs_address_mode  : OUT    std_logic
     104      roi_array         : OUT    roi_array_type
    100105   );
    101106   END COMPONENT;
    … …  
    137142         config_data_valid => config_data_valid,
    138143         config_busy       => config_busy,
     144         config_rw_ack     => config_rw_ack,
     145         config_rw_ready   => config_rw_ready,
    139146         ram_addr          => ram_addr,
    140147         ram_data_in       => ram_data_in,
    141148         ram_write_en      => ram_wren,
    142149         dac_array         => dac_array,
    143          roi_array         => roi_array,
    144          drs_address       => drs_address,
    145          drs_address_mode  => drs_address_mode
     150         roi_array         => roi_array
    146151      );
    147152

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10072 r10073  
    142142        when CONFIG4 =>
    143143          drs_channel_id <= DRS_WRITE_SHIFT_REG;
    144           drs_srin_data <= "10101010";
     144          drs_srin_data <= "11111111";
    145145          drs_srin_write_8b <= '1';
    146146          if (drs_srin_write_ack = '1') then

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

    r10072 r10073  
    2525  );
    2626   port(
     27--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     28
    2729      clk            : in     std_logic;
    2830      data_out       : out    std_logic_vector (63 downto 0);
    … …  
    3234      ram_write_ea : in std_logic;
    3335      ram_write_ready : out std_logic := '0';
     36      -- --
     37      ram_write_ready_ack : IN std_logic;
     38      -- --
    3439      config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
    3540      config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
    … …  
    4550      trigger_id     : in std_logic_vector (47 downto 0);
    4651      trigger        : in std_logic;
    47       s_trigger      : in std_logic;
     52--      s_trigger      : in std_logic;
    4853      new_config     : in std_logic;
    4954      config_started : out std_logic := '0';
    … …  
    5560      drs_dwrite : out std_logic := '1';
    5661      drs_clk_en, drs_read_s_cell : out std_logic := '0';
     62
     63      drs_srin_write_8b : out std_logic := '0';
     64      drs_srin_write_ack : in std_logic;
     65      drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0');
     66      drs_srin_write_ready : in std_logic;
     67
    5768      drs_read_s_cell_ready : in std_logic;
    5869      drs_s_cell_array : in drs_s_cell_array_type
    … …  
    6273architecture Behavioral of data_generator is
    6374
    64 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
     75type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    6576                             WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    6677                             WRITE_END_FLAG, WRITE_DATA_STOP,
    … …  
    7687signal adc_wait_cnt : integer range 0 to 7 := 0;
    7788
    78 signal trigger_flag : std_logic := '0';
    79 
     89signal trigger_flag :std_logic := '0';
     90signal ram_write_ea_flag : std_logic := '0';
     91signal new_config_int : std_logic := '0';
     92
     93signal roi_max_int : roi_max_type;
    8094
    8195begin
    … …  
    95109        when CONFIG =>
    96110          config_started <= '1';
    97           -- config config manager
    98           config_start_cm <= '1';
    99           if (config_started_cm = '1') then
    100             state_generate <= CONFIG1;
     111          if (new_config = '0') then
     112            config_started <= '0';
     113            -- config config manager
     114            config_start_cm <= '1';
     115            if (config_started_cm = '1') then
     116              config_start_cm <= '0';
     117              state_generate <= CONFIG1;
     118            end if;
    101119          end if;
    102120        when CONFIG1 =>
    103121          if (config_ready_cm = '1') then
    104             config_started <= '0';
    105             config_start_cm <= '0';
    106122            config_start_mm <= '1';
    107123          end if;
    108124          if (config_started_mm = '1') then
     125            config_start_mm <= '0';
    109126            state_generate <= CONFIG2;
    110127          end if;
    111128        when CONFIG2 =>
    112129          if (config_ready_mm = '1') then
    113             config_start_mm <= '0';
    114130            config_start_spi <= '1';
    115131          end if;
    116132          if (config_started_spi = '1') then
     133            config_start_spi <= '0';
    117134            state_generate <= CONFIG3;
    118135          end if;
    119136        when CONFIG3 =>
    120137          if (config_ready_spi = '1') then
    121             config_start_spi <= '0';
     138            state_generate <= CONFIG4;
     139--            state_generate <= WRITE_DATA_IDLE;
     140          end if;
     141        -- configure DRS
     142        when CONFIG4 =>
     143          drs_channel_id <= DRS_WRITE_SHIFT_REG;
     144          drs_srin_data <= "10101010";
     145          drs_srin_write_8b <= '1';
     146          if (drs_srin_write_ack = '1') then
     147            drs_srin_write_8b <= '0';
     148            state_generate <= CONFIG5;
     149          end if;
     150        when CONFIG5 =>
     151          if (drs_srin_write_ready = '1') then
     152            roi_max_int <= roi_max;
    122153            state_generate <= WRITE_DATA_IDLE;
    123154          end if;
     155        -- end configure DRS
    124156
    125157        when WRITE_DATA_IDLE =>
    … …  
    127159            state_generate <= CONFIG;
    128160          end if;
    129           if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
     161--          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
     162          if (ram_write_ea = '1' and trigger_flag = '1') then
    130163            -- stop drs, dwrite low
    131164            drs_dwrite <= '0';
    … …  
    248281        when WRITE_EXTERNAL_TRIGGER =>    -- external trigger ID
    249282          addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
    250           data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
     283--          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
     284          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
    251285          state_generate <= WRITE_INTERNAL_TRIGGER;
    252286        when WRITE_INTERNAL_TRIGGER =>    -- internal trigger ID
    … …  
    263297                                        state_generate <= WRITE_DATA_END_WAIT;
    264298                                when WRITE_DATA_END_WAIT =>
    265                                   state_generate <= WRITE_DATA_STOP;
     299          -- --
     300                                  if (ram_write_ready_ack = '1') then
     301                                    state_generate <= WRITE_DATA_STOP;
     302                                    -- --
     303            ram_write_ready <= '0';
     304            -- --
     305                                  end if;
     306                                  -- --
    266307                when WRITE_DATA_STOP =>
    267           drs_dwrite <= '1';
    268                                         data_cntr <= 0;
    269                                         addr_cntr <= 0;
    270                                         channel_id <= 0;
    271                                         ram_write_ready <= '0';
    272                                         state_generate <= WRITE_DATA_IDLE;
    273                                
     308                  -- --
     309                  if (ram_write_ready_ack = '0') then
     310                  -- --
     311            drs_dwrite <= '1';
     312                                          data_cntr <= 0;
     313                                          addr_cntr <= 0;
     314                                          channel_id <= 0;
     315                                          state_generate <= WRITE_DATA_IDLE;
     316                                        -- --
     317                                        end if;
     318                                  -- --
    274319                                when others =>
    275320                                        null;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf

    r9912 r10073  
    2525NET RS485_C_DE LOC  = C5 | IOSTANDARD=LVCMOS33;         #ok
    2626NET RS485_C_RE LOC  = C6 | IOSTANDARD=LVCMOS33;         #ok
    27 #NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;                #ok
    28 #NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;                #ok
     27NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;         #ok
     28NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;         #ok
    2929
    3030NET RS485_E_DE LOC  = D20 | IOSTANDARD=LVCMOS33;                #ok
    3131NET RS485_E_RE LOC  = D21 | IOSTANDARD=LVCMOS33;                #ok
    32 #NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;               #ok
    33 #NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;               #ok
     32NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;                #ok
     33NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;                #ok
    3434
    3535

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r9912 r10073  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 10:49:29 30.08.2010
     5--          at - 17:00:27 03.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    2323      D3_SROUT   : IN     std_logic;
    2424      D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0);
     25      RS485_C_DI : IN     std_logic;
     26      RS485_E_DI : IN     std_logic;
     27      RS485_E_DO : IN     std_logic;
    2528      TRG        : IN     STD_LOGIC;
    2629      W_INT      : IN     std_logic;
    … …  
    4447      OE_ADC     : OUT    STD_LOGIC;
    4548      RS485_C_DE : OUT    std_logic;
     49      RS485_C_DO : OUT    std_logic;
    4650      RS485_C_RE : OUT    std_logic;
    4751      RS485_E_DE : OUT    std_logic;
    4852      RS485_E_RE : OUT    std_logic;
    4953      RSRLOAD    : OUT    std_logic                       := '0';
    50       SRIN       : OUT    std_logic;
     54      SRIN       : OUT    std_logic                       := '0';
    5155      S_CLK      : OUT    std_logic;
    5256      T0_CS      : OUT    std_logic;
    … …  
    7377-- Created:
    7478--          by - dneise.UNKNOWN (E5B-LABOR6)
    75 --          at - 10:49:29 30.08.2010
     79--          at - 17:00:27 03.01.2011
    7680--
    7781-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    152156      RSRLOAD         : OUT    std_logic                     := '0';
    153157      SRCLK           : OUT    std_logic                     := '0';
     158      SRIN_out        : OUT    std_logic                     := '0';
    154159      adc_clk_en      : OUT    std_logic                     := '0';
    155160      adc_oeb         : OUT    std_logic                     := '1';
    … …  
    220225   -- MISC 6     
    221226   TRG_V <= '0';
    222    RS485_C_RE <= '1';
     227   RS485_C_RE <= '0';
    223228   RS485_C_DE <= '0';   
    224    RS485_E_RE <= '1';     
     229   RS485_C_DO <= RS485_C_DI;
     230   
     231   RS485_E_RE <= '0';     
    225232   RS485_E_DE <= '0';
     233   --RS485_E_DO <= RS485_E_DI;
    226234   
    227235   -- DENABLE <= '0'; -- domino wave stopped
    228236   -- DENABLE <= '1'; -- domino wave running
    229237   
    230    SRIN <= '1';
     238   
    231239   EE_CS <= '1';
    232240   -- LEDs are low active
    … …  
    305313         RSRLOAD         => RSRLOAD,
    306314         SRCLK           => SRCLK,
     315         SRIN_out        => SRIN,
    307316         adc_clk_en      => adc_clk_en,
    308317         adc_oeb         => OE_ADC,

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r9912 r10073  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 10:49:27 30.08.2010
     5--          at - 17:00:23 03.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    4444      RSRLOAD         : OUT    std_logic                     := '0';
    4545      SRCLK           : OUT    std_logic                     := '0';
     46      SRIN_out        : OUT    std_logic                     := '0';
    4647      adc_clk_en      : OUT    std_logic                     := '0';
    4748      adc_oeb         : OUT    std_logic                     := '1';
    … …  
    7677-- Created:
    7778--          by - dneise.UNKNOWN (E5B-LABOR6)
    78 --          at - 10:49:28 30.08.2010
     79--          at - 17:00:24 03.01.2011
    7980--
    8081-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    113114   SIGNAL config_ready_cm        : std_logic;
    114115   SIGNAL config_ready_spi       : std_logic;
     116   -- --
     117   SIGNAL config_rw_ack          : std_logic                                    := '0';
     118   -- --
     119   SIGNAL config_rw_ready        : std_logic                                    := '0';
    115120   SIGNAL config_start           : std_logic                                    := '0';
    116121   SIGNAL config_start_cm        : std_logic;
    … …  
    130135   SIGNAL drs_read_s_cell_ready  : std_logic;
    131136   SIGNAL drs_s_cell_array       : drs_s_cell_array_type;
     137   SIGNAL drs_srin_data          : std_logic_vector(7 DOWNTO 0)                 := (others => '0');
    132138   SIGNAL dwrite                 : std_logic                                    := '1';
    133139   SIGNAL dwrite_enable          : std_logic                                    := '1';
    … …  
    142148   SIGNAL ram_write_ea           : std_logic;
    143149   SIGNAL ram_write_ready        : std_logic                                    := '0';
     150   -- --
     151   SIGNAL ram_write_ready_ack    : std_logic                                    := '0';
    144152   SIGNAL roi_array              : roi_array_type;
    145153   SIGNAL roi_max                : roi_max_type;
    146    SIGNAL s_trigger              : std_logic                                    := '0';
     154   SIGNAL s_trigger              : std_logic;
    147155   SIGNAL sclk1                  : std_logic;
    148156   SIGNAL sclk_enable            : std_logic;
    … …  
    150158   SIGNAL sensor_ready           : std_logic;
    151159   SIGNAL srclk_enable           : std_logic                                    := '0';
     160   SIGNAL srin_write_ack         : std_logic                                    := '0';
     161   SIGNAL srin_write_ready       : std_logic                                    := '0';
     162   SIGNAL start_srin_write_8b    : std_logic;
    152163   SIGNAL trigger_id             : std_logic_vector(47 DOWNTO 0);
     164   SIGNAL trigger_out            : std_logic;
    153165   SIGNAL wiz_ack                : std_logic;
    154166   SIGNAL wiz_busy               : std_logic;
    … …  
    207219      config_data_valid : OUT    std_logic ;
    208220      config_ready      : OUT    std_logic ;
     221      -- --
     222      config_rw_ack     : OUT    std_logic  := '0';
     223      -- --
     224      config_rw_ready   : OUT    std_logic  := '0';
    209225      config_started    : OUT    std_logic  := '0';
    210226      dac_array         : OUT    dac_array_type ;
    211       drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
    212       drs_address_mode  : OUT    std_logic ;
    213227      roi_array         : OUT    roi_array_type ;
    214228      config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
    … …  
    231245   );
    232246   PORT (
     247      --      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    233248      clk                   : IN     std_logic ;
    234249      data_out              : OUT    std_logic_vector (63 DOWNTO 0);
    … …  
    238253      ram_write_ea          : IN     std_logic ;
    239254      ram_write_ready       : OUT    std_logic                     := '0';
     255      -- --
     256      ram_write_ready_ack   : IN     std_logic ;
     257      -- --
    240258      config_start_mm       : OUT    std_logic                     := '0';
     259      -- --
    241260      config_start_cm       : OUT    std_logic                     := '0';
     261      -- --
    242262      config_start_spi      : OUT    std_logic                     := '0';
    243263      config_ready_mm       : IN     std_logic ;
    … …  
    257277      trigger_id            : IN     std_logic_vector (47 DOWNTO 0);
    258278      trigger               : IN     std_logic ;
    259       s_trigger             : IN     std_logic ;
     279      --      s_trigger      : in std_logic;
    260280      new_config            : IN     std_logic ;
    261281      config_started        : OUT    std_logic                     := '0';
    … …  
    268288      drs_clk_en            : OUT    std_logic                     := '0';
    269289      drs_read_s_cell       : OUT    std_logic                     := '0';
     290      drs_srin_write_8b     : OUT    std_logic                     := '0';
     291      drs_srin_write_ack    : IN     std_logic ;
     292      drs_srin_data         : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
     293      drs_srin_write_ready  : IN     std_logic ;
    270294      drs_read_s_cell_ready : IN     std_logic ;
    271295      drs_s_cell_array      : IN     drs_s_cell_array_type
    … …  
    279303      SROUT_in_2               : IN     std_logic;
    280304      SROUT_in_3               : IN     std_logic;
     305      srin_data                : IN     std_logic_vector (7 DOWNTO 0);
    281306      start_endless_mode       : IN     std_logic;
    282307      start_read_stop_pos_mode : IN     std_logic;
     308      start_srin_write_8b      : IN     std_logic;
    283309      RSRLOAD                  : OUT    std_logic  := '0';
    284310      SRCLK                    : OUT    std_logic  := '0';
     311      SRIN_out                 : OUT    std_logic  := '0';
     312      srin_write_ack           : OUT    std_logic  := '0';
     313      srin_write_ready         : OUT    std_logic  := '0';
    285314      stop_pos                 : OUT    drs_s_cell_array_type;
    286315      stop_pos_valid           : OUT    std_logic  := '0'
    … …  
    296325      config_start           : IN     std_logic ;
    297326      ram_write_ready        : IN     std_logic ;
     327      -- --
     328      ram_write_ready_ack    : OUT    std_logic                                        := '0';
     329      -- --
    298330      roi_array              : IN     roi_array_type ;
    299331      ram_write_ea           : OUT    std_logic                                        := '0';
    … …  
    367399      config_wr_en      : OUT    std_logic                      := '0';
    368400      config_rd_en      : OUT    std_logic                      := '0';
     401      -- --
     402      config_rw_ack     : IN     std_logic ;
     403      -- --
     404      config_rw_ready   : IN     std_logic ;
     405      -- --
    369406      config_busy       : IN     std_logic ;
    370407      denable           : OUT    std_logic                      := '0';           -- default domino wave off
    … …  
    429466      END CASE;
    430467   END PROCESS u_0combo_proc;
     468
     469   -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
     470   trigger_out <= s_trigger OR trigger;
    431471
    432472   -- Instance port mappings.
    … …  
    468508         config_data_valid => config_data_valid,
    469509         config_ready      => config_ready_cm,
     510         config_rw_ack     => config_rw_ack,
     511         config_rw_ready   => config_rw_ready,
    470512         config_started    => config_started_cu,
    471513         dac_array         => dac_array,
    472          drs_address       => drs_address,
    473          drs_address_mode  => drs_address_mode,
    474514         roi_array         => roi_array,
    475515         config_data       => config_data
    … …  
    497537         ram_write_ea          => ram_write_ea,
    498538         ram_write_ready       => ram_write_ready,
     539         ram_write_ready_ack   => ram_write_ready_ack,
    499540         config_start_mm       => config_start,
    500541         config_start_cm       => config_start_cm,
    … …  
    515556         crate_id              => crate_id,
    516557         trigger_id            => trigger_id,
    517          trigger               => trigger,
    518          s_trigger             => s_trigger,
     558         trigger               => trigger_out,
    519559         new_config            => new_config,
    520560         config_started        => config_started,
    … …  
    527567         drs_clk_en            => drs_clk_en,
    528568         drs_read_s_cell       => drs_read_s_cell,
     569         drs_srin_write_8b     => start_srin_write_8b,
     570         drs_srin_write_ack    => srin_write_ack,
     571         drs_srin_data         => drs_srin_data,
     572         drs_srin_write_ready  => srin_write_ready,
    529573         drs_read_s_cell_ready => drs_read_s_cell_ready,
    530574         drs_s_cell_array      => drs_s_cell_array
    … …  
    541585         stop_pos                 => drs_s_cell_array,
    542586         stop_pos_valid           => drs_read_s_cell_ready,
     587         start_srin_write_8b      => start_srin_write_8b,
     588         srin_write_ready         => srin_write_ready,
     589         srin_write_ack           => srin_write_ack,
     590         srin_data                => drs_srin_data,
     591         SRIN_out                 => SRIN_out,
    543592         RSRLOAD                  => RSRLOAD,
    544593         SRCLK                    => SRCLK1
    … …  
    553602         config_start           => config_start,
    554603         ram_write_ready        => ram_write_ready,
     604         ram_write_ready_ack    => ram_write_ready_ack,
    555605         roi_array              => roi_array,
    556606         ram_write_ea           => ram_write_ea,
    … …  
    587637      PORT MAP (
    588638         trigger_id => trigger_id,
    589          trigger    => trigger,
     639         trigger    => trigger_out,
    590640         clk        => CLK_25_PS_internal
    591641      );
    … …  
    621671         config_wr_en      => config_wr_en,
    622672         config_rd_en      => config_rd_en,
     673         config_rw_ack     => config_rw_ack,
     674         config_rw_ready   => config_rw_ready,
    623675         config_busy       => config_busy,
    624676         denable           => denable,

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd

    r9912 r10073  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 09:42:04 30.07.2010
     5--          at - 14:00:24 01.10.2010
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    3838-- Created:
    3939--          by - dneise.UNKNOWN (E5B-LABOR6)
    40 --          at - 09:42:04 30.07.2010
     40--          at - 14:00:25 01.10.2010
    4141--
    4242-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf

    r9912 r10073  
    3131DESIGN control_unit
    3232VIEW symbol.sb
    33 GRAPHIC 350,0 24 0
    34 DESIGN control_unit
    35 VIEW symbol.sb
    36 GRAPHIC 165,0 25 0
    37 DESIGN control_unit
    38 VIEW symbol.sb
    39 GRAPHIC 521,0 26 0
    40 DESIGN control_unit
    41 VIEW symbol.sb
    42 GRAPHIC 526,0 27 0
    43 DESIGN control_unit
    44 VIEW symbol.sb
    45 GRAPHIC 155,0 28 0
    46 DESIGN control_unit
    47 VIEW symbol.sb
    48 GRAPHIC 150,0 29 0
    49 DESIGN control_unit
    50 VIEW symbol.sb
    51 GRAPHIC 1,0 32 0
    52 DESIGN control_unit
    53 VIEW symbol.sb
    54 GRAPHIC 1,0 33 0
    55 DESIGN control_unit
    56 VIEW struct.bd
    57 NO_GRAPHIC 36
    58 DESIGN control_unit
    59 VIEW struct.bd
    60 GRAPHIC 41,0 45 0
    61 DESIGN control_unit
    62 VIEW struct.bd
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    64 DESIGN control_unit
    65 VIEW struct.bd
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    67 DESIGN control_unit
    68 VIEW struct.bd
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    70 DESIGN control_unit
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    73 DESIGN control_unit
    74 VIEW struct.bd
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    76 DESIGN control_unit
    77 VIEW struct.bd
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    79 DESIGN control_unit
    80 VIEW struct.bd
    81 NO_GRAPHIC 62
    82 DESIGN control_unit
    83 VIEW struct.bd
    84 NO_GRAPHIC 63
     33GRAPHIC 558,0 25 0
     34DESIGN control_unit
     35VIEW symbol.sb
     36GRAPHIC 564,0 27 0
     37DESIGN control_unit
     38VIEW symbol.sb
     39GRAPHIC 350,0 28 0
     40DESIGN control_unit
     41VIEW symbol.sb
     42GRAPHIC 165,0 29 0
     43DESIGN control_unit
     44VIEW symbol.sb
     45GRAPHIC 155,0 30 0
     46DESIGN control_unit
     47VIEW symbol.sb
     48GRAPHIC 150,0 31 0
     49DESIGN control_unit
     50VIEW symbol.sb
     51GRAPHIC 1,0 34 0
     52DESIGN control_unit
     53VIEW symbol.sb
     54GRAPHIC 1,0 35 0
     55DESIGN control_unit
     56VIEW struct.bd
     57NO_GRAPHIC 38
     58DESIGN control_unit
     59VIEW struct.bd
     60GRAPHIC 41,0 47 0
     61DESIGN control_unit
     62VIEW struct.bd
     63NO_GRAPHIC 52
     64DESIGN control_unit
     65VIEW struct.bd
     66GRAPHIC 0,0 55 2
     67DESIGN control_unit
     68VIEW struct.bd
     69GRAPHIC 345,0 60 0
     70DESIGN control_unit
     71VIEW struct.bd
     72GRAPHIC 333,0 61 0
     73DESIGN control_unit
     74VIEW struct.bd
     75GRAPHIC 349,0 62 0
     76DESIGN control_unit
     77VIEW struct.bd
     78GRAPHIC 329,0 63 0
     79DESIGN control_unit
     80VIEW struct.bd
     81NO_GRAPHIC 64
     82DESIGN control_unit
     83VIEW struct.bd
     84NO_GRAPHIC 65
    8585LIBRARY FACT_FAD_lib
    8686DESIGN control@r@a@m_16bit_x256
    8787VIEW control@r@a@m_16bit_x256_a
    88 GRAPHIC 993,0 65 0
    89 DESIGN control@r@a@m_16bit_x256
    90 VIEW control@r@a@m_16bit_x256_a
    91 GRAPHIC 48,0 67 0
    92 DESIGN control@r@a@m_16bit_x256
    93 VIEW control@r@a@m_16bit_x256_a
    94 GRAPHIC 53,0 68 0
    95 DESIGN control@r@a@m_16bit_x256
    96 VIEW control@r@a@m_16bit_x256_a
    97 GRAPHIC 58,0 69 0
    98 DESIGN control@r@a@m_16bit_x256
    99 VIEW control@r@a@m_16bit_x256_a
    100 GRAPHIC 63,0 70 0
    101 DESIGN control@r@a@m_16bit_x256
    102 VIEW control@r@a@m_16bit_x256_a
    103 GRAPHIC 68,0 71 0
    104 DESIGN control_unit
    105 VIEW struct.bd
    106 GRAPHIC 960,0 74 0
    107 DESIGN control_manager
    108 VIEW symbol.sb
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    110 DESIGN control_manager
    111 VIEW beha
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    113 DESIGN control_manager
    114 VIEW beha
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    116 DESIGN control_manager
    117 VIEW beha
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    119 DESIGN control_manager
    120 VIEW beha
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    122 DESIGN control_manager
    123 VIEW beha
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    125 DESIGN control_manager
    126 VIEW beha
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    128 DESIGN control_manager
    129 VIEW beha
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    131 DESIGN control_manager
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    134 DESIGN control_manager
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    137 DESIGN control_manager
    138 VIEW beha
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    140 DESIGN control_manager
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    143 DESIGN control_manager
    144 VIEW beha
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    146 DESIGN control_manager
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    149 DESIGN control_manager
    150 VIEW beha
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    152 DESIGN control_manager
    153 VIEW beha
    154 GRAPHIC 118,0 95 0
    155 DESIGN control_manager
    156 VIEW beha
    157 GRAPHIC 123,0 96 0
    158 DESIGN control_manager
    159 VIEW beha
    160 GRAPHIC 528,0 97 0
    161 DESIGN control_manager
    162 VIEW beha
    163 GRAPHIC 533,0 98 0
     88GRAPHIC 993,0 67 0
     89DESIGN control@r@a@m_16bit_x256
     90VIEW control@r@a@m_16bit_x256_a
     91GRAPHIC 48,0 69 0
     92DESIGN control@r@a@m_16bit_x256
     93VIEW control@r@a@m_16bit_x256_a
     94GRAPHIC 53,0 70 0
     95DESIGN control@r@a@m_16bit_x256
     96VIEW control@r@a@m_16bit_x256_a
     97GRAPHIC 58,0 71 0
     98DESIGN control@r@a@m_16bit_x256
     99VIEW control@r@a@m_16bit_x256_a
     100GRAPHIC 63,0 72 0
     101DESIGN control@r@a@m_16bit_x256
     102VIEW control@r@a@m_16bit_x256_a
     103GRAPHIC 68,0 73 0
     104DESIGN control_unit
     105VIEW struct.bd
     106GRAPHIC 960,0 76 0
     107DESIGN control_manager
     108VIEW symbol.sb
     109GRAPHIC 14,0 77 1
     110DESIGN control_manager
     111VIEW beha
     112GRAPHIC 48,0 83 0
     113DESIGN control_manager
     114VIEW beha
     115GRAPHIC 310,0 84 0
     116DESIGN control_manager
     117VIEW beha
     118GRAPHIC 58,0 85 0
     119DESIGN control_manager
     120VIEW beha
     121GRAPHIC 492,0 86 0
     122DESIGN control_manager
     123VIEW beha
     124GRAPHIC 63,0 87 0
     125DESIGN control_manager
     126VIEW beha
     127GRAPHIC 68,0 88 0
     128DESIGN control_manager
     129VIEW beha
     130GRAPHIC 73,0 89 0
     131DESIGN control_manager
     132VIEW beha
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     134DESIGN control_manager
     135VIEW beha
     136GRAPHIC 83,0 91 0
     137DESIGN control_manager
     138VIEW beha
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     140DESIGN control_manager
     141VIEW beha
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     143DESIGN control_manager
     144VIEW beha
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     146DESIGN control_manager
     147VIEW beha
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     149DESIGN control_manager
     150VIEW beha
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     152DESIGN control_manager
     153VIEW beha
     154GRAPHIC 263,0 100 0
     155DESIGN control_manager
     156VIEW beha
     157GRAPHIC 268,0 101 0
     158DESIGN control_manager
     159VIEW beha
     160GRAPHIC 118,0 102 0
     161DESIGN control_manager
     162VIEW beha
     163GRAPHIC 123,0 103 0
    164164LIBRARY FACT_FAD_lib
    165165DESIGN control_unit
    166166VIEW struct.bd
    167 NO_GRAPHIC 101
    168 DESIGN control_unit
    169 VIEW struct.bd
    170 GRAPHIC 993,0 104 0
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    172 VIEW struct.bd
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    175 VIEW struct.bd
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    177 DESIGN control_unit
    178 VIEW struct.bd
    179 NO_GRAPHIC 110
    180 DESIGN control_unit
    181 VIEW struct.bd
    182 GRAPHIC 993,0 112 0
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r9912 r10073  
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    250262LIBRARY FACT_FAD_lib
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

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    394 GRAPHIC 544,0 187 0
     421GRAPHIC 544,0 199 0
    395422DESIGN clock_generator_var_ps
    396423VIEW symbol.sb
    397 GRAPHIC 524,0 188 0
     424GRAPHIC 524,0 200 0
    398425DESIGN clock_generator_var_ps
    399426VIEW symbol.sb
    400 GRAPHIC 539,0 189 0
     427GRAPHIC 539,0 201 0
    401428DESIGN clock_generator_var_ps
    402429VIEW symbol.sb
    403 GRAPHIC 529,0 190 0
     430GRAPHIC 529,0 202 0
    404431DESIGN clock_generator_var_ps
    405432VIEW symbol.sb
    406 GRAPHIC 534,0 191 0
     433GRAPHIC 534,0 203 0
    407434DESIGN clock_generator_var_ps
    408435VIEW symbol.sb
    409 GRAPHIC 475,0 192 0
     436GRAPHIC 475,0 204 0
    410437DESIGN clock_generator_var_ps
    411438VIEW symbol.sb
    412 GRAPHIC 463,0 193 0
     439GRAPHIC 463,0 205 0
    413440DESIGN clock_generator_var_ps
    414441VIEW symbol.sb
    415 GRAPHIC 469,0 194 0
    416 DESIGN @f@a@d_main
    417 VIEW struct.bd
    418 GRAPHIC 5072,0 198 0
     442GRAPHIC 469,0 206 0
     443DESIGN @f@a@d_main
     444VIEW struct.bd
     445GRAPHIC 5072,0 210 0
    419446DESIGN control_unit
    420447VIEW symbol.sb
    421 GRAPHIC 130,0 200 0
     448GRAPHIC 130,0 212 0
    422449DESIGN control_unit
    423450VIEW symbol.sb
    424 GRAPHIC 135,0 201 0
     451GRAPHIC 135,0 213 0
    425452DESIGN control_unit
    426453VIEW symbol.sb
    427 GRAPHIC 170,0 202 0
     454GRAPHIC 170,0 214 0
    428455DESIGN control_unit
    429456VIEW symbol.sb
    430 GRAPHIC 175,0 203 0
     457GRAPHIC 175,0 215 0
    431458DESIGN control_unit
    432459VIEW symbol.sb
    433 GRAPHIC 160,0 204 0
     460GRAPHIC 160,0 216 0
    434461DESIGN control_unit
    435462VIEW symbol.sb
    436 GRAPHIC 145,0 205 0
     463GRAPHIC 145,0 217 0
    437464DESIGN control_unit
    438465VIEW symbol.sb
    439 GRAPHIC 140,0 206 0
     466GRAPHIC 140,0 218 0
    440467DESIGN control_unit
    441468VIEW symbol.sb
    442 GRAPHIC 180,0 207 0
     469GRAPHIC 180,0 219 0
    443470DESIGN control_unit
    444471VIEW symbol.sb
    445 GRAPHIC 350,0 208 0
     472GRAPHIC 558,0 220 0
    446473DESIGN control_unit
    447474VIEW symbol.sb
    448 GRAPHIC 165,0 209 0
     475GRAPHIC 564,0 222 0
    449476DESIGN control_unit
    450477VIEW symbol.sb
    451 GRAPHIC 521,0 210 0
     478GRAPHIC 350,0 224 0
    452479DESIGN control_unit
    453480VIEW symbol.sb
    454 GRAPHIC 526,0 211 0
     481GRAPHIC 165,0 225 0
    455482DESIGN control_unit
    456483VIEW symbol.sb
    457 GRAPHIC 155,0 212 0
     484GRAPHIC 155,0 226 0
    458485DESIGN control_unit
    459486VIEW symbol.sb
    460 GRAPHIC 150,0 213 0
    461 DESIGN @f@a@d_main
    462 VIEW struct.bd
    463 GRAPHIC 8277,0 216 0
     487GRAPHIC 150,0 227 0
     488DESIGN @f@a@d_main
     489VIEW struct.bd
     490GRAPHIC 8277,0 230 0
    464491DESIGN data@r@a@m_64b_16b_width14_5
    465492VIEW data@r@a@m_64b_16b_width14_5_a
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     493GRAPHIC 48,0 232 0
    467494DESIGN data@r@a@m_64b_16b_width14_5
    468495VIEW data@r@a@m_64b_16b_width14_5_a
    469 GRAPHIC 53,0 219 0
     496GRAPHIC 53,0 233 0
    470497DESIGN data@r@a@m_64b_16b_width14_5
    471498VIEW data@r@a@m_64b_16b_width14_5_a
    472 GRAPHIC 58,0 220 0
     499GRAPHIC 58,0 234 0
    473500DESIGN data@r@a@m_64b_16b_width14_5
    474501VIEW data@r@a@m_64b_16b_width14_5_a
    475 GRAPHIC 63,0 221 0
     502GRAPHIC 63,0 235 0
    476503DESIGN data@r@a@m_64b_16b_width14_5
    477504VIEW data@r@a@m_64b_16b_width14_5_a
    478 GRAPHIC 68,0 222 0
     505GRAPHIC 68,0 236 0
    479506DESIGN data@r@a@m_64b_16b_width14_5
    480507VIEW data@r@a@m_64b_16b_width14_5_a
    481 GRAPHIC 73,0 223 0
     508GRAPHIC 73,0 237 0
    482509DESIGN data@r@a@m_64b_16b_width14_5
    483510VIEW data@r@a@m_64b_16b_width14_5_a
    484 GRAPHIC 78,0 224 0
    485 DESIGN @f@a@d_main
    486 VIEW struct.bd
    487 GRAPHIC 1399,0 227 0
    488 DESIGN data_generator
    489 VIEW symbol.sb
    490 GRAPHIC 14,0 228 1
    491 DESIGN data_generator
    492 VIEW @behavioral
    493 GRAPHIC 48,0 232 0
    494 DESIGN data_generator
    495 VIEW @behavioral
    496 GRAPHIC 53,0 233 0
    497 DESIGN data_generator
    498 VIEW @behavioral
    499 GRAPHIC 58,0 234 0
    500 DESIGN data_generator
    501 VIEW @behavioral
    502 GRAPHIC 73,0 235 0
    503 DESIGN data_generator
    504 VIEW @behavioral
    505 GRAPHIC 78,0 236 0
    506 DESIGN data_generator
    507 VIEW @behavioral
    508 GRAPHIC 402,0 237 0
    509 DESIGN data_generator
    510 VIEW @behavioral
    511 GRAPHIC 407,0 238 0
    512 DESIGN data_generator
    513 VIEW @behavioral
    514 GRAPHIC 1122,0 239 0
    515 DESIGN data_generator
    516 VIEW @behavioral
    517 GRAPHIC 963,0 240 0
    518 DESIGN data_generator
    519 VIEW @behavioral
    520 GRAPHIC 1127,0 241 0
    521 DESIGN data_generator
    522 VIEW @behavioral
    523 GRAPHIC 1048,0 242 0
    524 DESIGN data_generator
    525 VIEW @behavioral
    526 GRAPHIC 958,0 243 0
    527 DESIGN data_generator
    528 VIEW @behavioral
    529 GRAPHIC 1053,0 244 0
    530 DESIGN data_generator
    531 VIEW @behavioral
    532 GRAPHIC 1201,0 245 0
    533 DESIGN data_generator
    534 VIEW @behavioral
    535 GRAPHIC 1196,0 246 0
    536 DESIGN data_generator
    537 VIEW @behavioral
    538 GRAPHIC 1206,0 247 0
    539 DESIGN data_generator
    540 VIEW @behavioral
    541 GRAPHIC 473,0 248 0
    542 DESIGN data_generator
    543 VIEW @behavioral
    544 GRAPHIC 412,0 249 0
    545 DESIGN data_generator
    546 VIEW @behavioral
    547 GRAPHIC 1085,0 250 0
    548 DESIGN data_generator
    549 VIEW @behavioral
    550 GRAPHIC 1090,0 251 0
    551 DESIGN data_generator
    552 VIEW @behavioral
    553 GRAPHIC 1240,0 252 0
    554 DESIGN data_generator
    555 VIEW @behavioral
    556 GRAPHIC 526,0 253 0
    557 DESIGN data_generator
    558 VIEW @behavioral
    559 GRAPHIC 88,0 254 0
    560 DESIGN data_generator
    561 VIEW @behavioral
    562 GRAPHIC 285,0 255 0
    563 DESIGN data_generator
    564 VIEW @behavioral
    565 GRAPHIC 93,0 256 0
    566 DESIGN data_generator
    567 VIEW @behavioral
    568 GRAPHIC 98,0 257 0
    569 DESIGN data_generator
    570 VIEW @behavioral
    571 GRAPHIC 1018,0 258 0
    572 DESIGN data_generator
    573 VIEW @behavioral
    574 GRAPHIC 1164,0 259 0
    575 DESIGN data_generator
    576 VIEW @behavioral
    577 GRAPHIC 1159,0 260 0
    578 DESIGN data_generator
    579 VIEW @behavioral
    580 GRAPHIC 898,0 261 0
    581 DESIGN data_generator
    582 VIEW @behavioral
    583 GRAPHIC 637,0 262 0
    584 DESIGN data_generator
    585 VIEW @behavioral
    586 GRAPHIC 1395,0 263 0
    587 DESIGN data_generator
    588 VIEW @behavioral
    589 GRAPHIC 1427,0 264 0
    590 DESIGN data_generator
    591 VIEW @behavioral
    592 GRAPHIC 676,0 265 0
    593 DESIGN data_generator
    594 VIEW @behavioral
    595 GRAPHIC 845,0 266 0
    596 DESIGN data_generator
    597 VIEW @behavioral
    598 GRAPHIC 681,0 267 0
    599 DESIGN data_generator
    600 VIEW @behavioral
    601 GRAPHIC 801,0 268 0
    602 DESIGN data_generator
    603 VIEW @behavioral
    604 GRAPHIC 806,0 269 0
    605 DESIGN data_generator
    606 VIEW @behavioral
    607 GRAPHIC 811,0 270 0
    608 DESIGN @f@a@d_main
    609 VIEW struct.bd
    610 GRAPHIC 4903,0 273 0
    611 DESIGN @f@a@d_main
    612 VIEW struct.bd
    613 NO_GRAPHIC 286
    614 DESIGN @f@a@d_main
    615 VIEW struct.bd
    616 GRAPHIC 2311,0 288 0
    617 DESIGN memory_manager
    618 VIEW symbol.sb
    619 GRAPHIC 14,0 289 1
    620 DESIGN memory_manager
    621 VIEW beha
    622 GRAPHIC 138,0 294 0
    623 DESIGN memory_manager
    624 VIEW beha
    625 GRAPHIC 194,0 295 0
    626 DESIGN memory_manager
    627 VIEW beha
    628 GRAPHIC 349,0 296 0
    629 DESIGN memory_manager
    630 VIEW beha
    631 GRAPHIC 569,0 297 0
    632 DESIGN memory_manager
    633 VIEW beha
    634 GRAPHIC 224,0 298 0
    635 DESIGN memory_manager
    636 VIEW beha
    637 GRAPHIC 254,0 299 0
    638 DESIGN memory_manager
    639 VIEW beha
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    641 DESIGN memory_manager
    642 VIEW beha
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    644 DESIGN memory_manager
    645 VIEW beha
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    647 DESIGN memory_manager
    648 VIEW beha
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    650 DESIGN memory_manager
    651 VIEW beha
    652 GRAPHIC 309,0 304 0
    653 DESIGN memory_manager
    654 VIEW beha
    655 GRAPHIC 284,0 305 0
    656 DESIGN memory_manager
    657 VIEW beha
    658 GRAPHIC 294,0 306 0
    659 DESIGN memory_manager
    660 VIEW beha
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    662 DESIGN memory_manager
    663 VIEW beha
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    665 DESIGN memory_manager
    666 VIEW beha
    667 GRAPHIC 379,0 309 0
    668 DESIGN memory_manager
    669 VIEW beha
    670 GRAPHIC 915,0 310 0
    671 DESIGN memory_manager
    672 VIEW beha
    673 GRAPHIC 51,0 311 0
    674 DESIGN @f@a@d_main
    675 VIEW struct.bd
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     511GRAPHIC 78,0 238 0
     512DESIGN @f@a@d_main
     513VIEW struct.bd
     514GRAPHIC 1399,0 241 0
     515DESIGN data_generator
     516VIEW symbol.sb
     517GRAPHIC 14,0 242 1
     518DESIGN data_generator
     519VIEW @behavioral
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     521DESIGN data_generator
     522VIEW @behavioral
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     524DESIGN data_generator
     525VIEW @behavioral
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     527DESIGN data_generator
     528VIEW @behavioral
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     530DESIGN data_generator
     531VIEW @behavioral
     532GRAPHIC 78,0 251 0
     533DESIGN data_generator
     534VIEW @behavioral
     535GRAPHIC 402,0 252 0
     536DESIGN data_generator
     537VIEW @behavioral
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     539DESIGN data_generator
     540VIEW @behavioral
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     542DESIGN data_generator
     543VIEW @behavioral
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     545DESIGN data_generator
     546VIEW @behavioral
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     548DESIGN data_generator
     549VIEW @behavioral
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     551DESIGN data_generator
     552VIEW @behavioral
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     554DESIGN data_generator
     555VIEW @behavioral
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     557DESIGN data_generator
     558VIEW @behavioral
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     560DESIGN data_generator
     561VIEW @behavioral
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     563DESIGN data_generator
     564VIEW @behavioral
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     566DESIGN data_generator
     567VIEW @behavioral
     568GRAPHIC 1206,0 267 0
     569DESIGN data_generator
     570VIEW @behavioral
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     572DESIGN data_generator
     573VIEW @behavioral
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     575DESIGN data_generator
     576VIEW @behavioral
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     578DESIGN data_generator
     579VIEW @behavioral
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     581DESIGN data_generator
     582VIEW @behavioral
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     584DESIGN data_generator
     585VIEW @behavioral
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     587DESIGN data_generator
     588VIEW @behavioral
     589GRAPHIC 88,0 274 0
     590DESIGN data_generator
     591VIEW @behavioral
     592GRAPHIC 285,0 275 0
     593DESIGN data_generator
     594VIEW @behavioral
     595GRAPHIC 93,0 276 0
     596DESIGN data_generator
     597VIEW @behavioral
     598GRAPHIC 98,0 277 0
     599DESIGN data_generator
     600VIEW @behavioral
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     602DESIGN data_generator
     603VIEW @behavioral
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     605DESIGN data_generator
     606VIEW @behavioral
     607GRAPHIC 898,0 281 0
     608DESIGN data_generator
     609VIEW @behavioral
     610GRAPHIC 637,0 282 0
     611DESIGN data_generator
     612VIEW @behavioral
     613GRAPHIC 1395,0 283 0
     614DESIGN data_generator
     615VIEW @behavioral
     616GRAPHIC 1427,0 284 0
     617DESIGN data_generator
     618VIEW @behavioral
     619GRAPHIC 676,0 285 0
     620DESIGN data_generator
     621VIEW @behavioral
     622GRAPHIC 845,0 286 0
     623DESIGN data_generator
     624VIEW @behavioral
     625GRAPHIC 681,0 287 0
     626DESIGN data_generator
     627VIEW @behavioral
     628GRAPHIC 801,0 288 0
     629DESIGN data_generator
     630VIEW @behavioral
     631GRAPHIC 1464,0 289 0
     632DESIGN data_generator
     633VIEW @behavioral
     634GRAPHIC 1469,0 290 0
     635DESIGN data_generator
     636VIEW @behavioral
     637GRAPHIC 1459,0 291 0
     638DESIGN data_generator
     639VIEW @behavioral
     640GRAPHIC 1474,0 292 0
     641DESIGN data_generator
     642VIEW @behavioral
     643GRAPHIC 806,0 293 0
     644DESIGN data_generator
     645VIEW @behavioral
     646GRAPHIC 811,0 294 0
     647DESIGN @f@a@d_main
     648VIEW struct.bd
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     650DESIGN @f@a@d_main
     651VIEW struct.bd
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     653DESIGN @f@a@d_main
     654VIEW struct.bd
     655GRAPHIC 2311,0 317 0
     656DESIGN memory_manager
     657VIEW symbol.sb
     658GRAPHIC 14,0 318 1
     659DESIGN memory_manager
     660VIEW beha
     661GRAPHIC 138,0 323 0
     662DESIGN memory_manager
     663VIEW beha
     664GRAPHIC 194,0 324 0
     665DESIGN memory_manager
     666VIEW beha
     667GRAPHIC 349,0 325 0
     668DESIGN memory_manager
     669VIEW beha
     670GRAPHIC 949,0 326 0
     671DESIGN memory_manager
     672VIEW beha
     673GRAPHIC 569,0 328 0
     674DESIGN memory_manager
     675VIEW beha
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     677DESIGN memory_manager
     678VIEW beha
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     680DESIGN memory_manager
     681VIEW beha
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     683DESIGN memory_manager
     684VIEW beha
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     686DESIGN memory_manager
     687VIEW beha
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     689DESIGN memory_manager
     690VIEW beha
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     692DESIGN memory_manager
     693VIEW beha
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     695DESIGN memory_manager
     696VIEW beha
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     698DESIGN memory_manager
     699VIEW beha
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     701DESIGN memory_manager
     702VIEW beha
     703GRAPHIC 304,0 339 0
     704DESIGN memory_manager
     705VIEW beha
     706GRAPHIC 299,0 340 0
     707DESIGN memory_manager
     708VIEW beha
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     710DESIGN memory_manager
     711VIEW beha
     712GRAPHIC 915,0 342 0
     713DESIGN memory_manager
     714VIEW beha
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     716DESIGN @f@a@d_main
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    677719DESIGN spi_interface
    678720VIEW symbol.sb
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     721GRAPHIC 1121,0 348 0
    680722DESIGN spi_interface
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     724GRAPHIC 326,0 349 0
    683725DESIGN spi_interface
    684726VIEW symbol.sb
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    686728DESIGN spi_interface
    687729VIEW symbol.sb
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    689731DESIGN spi_interface
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    692734DESIGN spi_interface
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     736GRAPHIC 1017,0 353 0
    695737DESIGN spi_interface
    696738VIEW symbol.sb
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    698740DESIGN spi_interface
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    701743DESIGN spi_interface
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    704746DESIGN spi_interface
    705747VIEW symbol.sb
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    707749DESIGN spi_interface
    708750VIEW symbol.sb
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    710752DESIGN spi_interface
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    714 VIEW struct.bd
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     755DESIGN @f@a@d_main
     756VIEW struct.bd
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     760GRAPHIC 48,0 364 0
    719761DESIGN trigger_counter
    720762VIEW beha
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     763GRAPHIC 53,0 365 0
    722764DESIGN trigger_counter
    723765VIEW beha
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    725 DESIGN @f@a@d_main
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    728 DESIGN w5300_modul
    729 VIEW symbol.sb
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    731 DESIGN w5300_modul
    732 VIEW @behavioral
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    734 DESIGN w5300_modul
    735 VIEW @behavioral
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    737 DESIGN w5300_modul
    738 VIEW @behavioral
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    740 DESIGN w5300_modul
    741 VIEW @behavioral
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    743 DESIGN w5300_modul
    744 VIEW @behavioral
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    746 DESIGN w5300_modul
    747 VIEW @behavioral
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    749 DESIGN w5300_modul
    750 VIEW @behavioral
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    752 DESIGN w5300_modul
    753 VIEW @behavioral
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    755 DESIGN w5300_modul
    756 VIEW @behavioral
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    758 DESIGN w5300_modul
    759 VIEW @behavioral
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    761 DESIGN w5300_modul
    762 VIEW @behavioral
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    764 DESIGN w5300_modul
    765 VIEW @behavioral
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    767 DESIGN w5300_modul
    768 VIEW @behavioral
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    770 DESIGN w5300_modul
    771 VIEW @behavioral
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    773 DESIGN w5300_modul
    774 VIEW @behavioral
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    776 DESIGN w5300_modul
    777 VIEW @behavioral
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    779 DESIGN w5300_modul
    780 VIEW @behavioral
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    782 DESIGN w5300_modul
    783 VIEW @behavioral
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    785 DESIGN w5300_modul
    786 VIEW @behavioral
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    788 DESIGN w5300_modul
    789 VIEW @behavioral
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    791 DESIGN w5300_modul
    792 VIEW @behavioral
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    794 DESIGN w5300_modul
    795 VIEW @behavioral
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    797 DESIGN w5300_modul
    798 VIEW @behavioral
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    800 DESIGN w5300_modul
    801 VIEW @behavioral
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    803 DESIGN w5300_modul
    804 VIEW @behavioral
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    806 DESIGN w5300_modul
    807 VIEW @behavioral
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    809 DESIGN w5300_modul
    810 VIEW @behavioral
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    812 DESIGN w5300_modul
    813 VIEW @behavioral
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    815 DESIGN w5300_modul
    816 VIEW @behavioral
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    818 DESIGN w5300_modul
    819 VIEW @behavioral
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    821 DESIGN w5300_modul
    822 VIEW @behavioral
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    824 DESIGN w5300_modul
    825 VIEW @behavioral
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    827 DESIGN w5300_modul
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     1398DESIGN @f@a@d_main
     1399VIEW struct.bd
     1400GRAPHIC 376,0 647 0
     1401DESIGN @f@a@d_main
     1402VIEW struct.bd
     1403GRAPHIC 384,0 648 0
     1404DESIGN @f@a@d_main
     1405VIEW struct.bd
     1406GRAPHIC 392,0 649 0
     1407DESIGN @f@a@d_main
     1408VIEW struct.bd
     1409GRAPHIC 400,0 650 0
     1410DESIGN @f@a@d_main
     1411VIEW struct.bd
     1412GRAPHIC 408,0 651 0
     1413DESIGN @f@a@d_main
     1414VIEW struct.bd
     1415GRAPHIC 5222,0 652 0
     1416DESIGN @f@a@d_main
     1417VIEW struct.bd
     1418GRAPHIC 424,0 653 0
     1419DESIGN @f@a@d_main
     1420VIEW struct.bd
     1421GRAPHIC 432,0 654 0
     1422DESIGN @f@a@d_main
     1423VIEW struct.bd
     1424GRAPHIC 2482,0 655 0
     1425DESIGN @f@a@d_main
     1426VIEW struct.bd
     1427GRAPHIC 2488,0 656 0
     1428DESIGN @f@a@d_main
     1429VIEW struct.bd
     1430GRAPHIC 370,0 657 0
     1431DESIGN @f@a@d_main
     1432VIEW struct.bd
     1433GRAPHIC 364,0 658 0
     1434DESIGN @f@a@d_main
     1435VIEW struct.bd
     1436GRAPHIC 2476,0 659 0
     1437DESIGN @f@a@d_main
     1438VIEW struct.bd
     1439GRAPHIC 8416,0 660 0
     1440DESIGN @f@a@d_main
     1441VIEW struct.bd
     1442GRAPHIC 2470,0 661 0
     1443DESIGN @f@a@d_main
     1444VIEW struct.bd
     1445GRAPHIC 2506,0 662 0
     1446DESIGN @f@a@d_main
     1447VIEW struct.bd
     1448GRAPHIC 2500,0 663 0
     1449DESIGN @f@a@d_main
     1450VIEW struct.bd
     1451GRAPHIC 2494,0 664 0
     1452DESIGN @f@a@d_main
     1453VIEW struct.bd
     1454GRAPHIC 10266,0 665 0
     1455DESIGN @f@a@d_main
     1456VIEW struct.bd
     1457GRAPHIC 5950,0 666 0
     1458DESIGN @f@a@d_main
     1459VIEW struct.bd
     1460GRAPHIC 5962,0 667 0
     1461DESIGN @f@a@d_main
     1462VIEW struct.bd
     1463GRAPHIC 5090,0 668 0
     1464DESIGN @f@a@d_main
     1465VIEW struct.bd
     1466GRAPHIC 5114,0 669 0
     1467DESIGN @f@a@d_main
     1468VIEW struct.bd
     1469GRAPHIC 5122,0 670 0
     1470DESIGN @f@a@d_main
     1471VIEW struct.bd
     1472GRAPHIC 5130,0 671 0
     1473DESIGN @f@a@d_main
     1474VIEW struct.bd
     1475GRAPHIC 10194,0 672 0
     1476DESIGN @f@a@d_main
     1477VIEW struct.bd
     1478GRAPHIC 10202,0 673 0
     1479DESIGN @f@a@d_main
     1480VIEW struct.bd
     1481GRAPHIC 5106,0 674 0
     1482DESIGN @f@a@d_main
     1483VIEW struct.bd
     1484GRAPHIC 6362,0 675 0
     1485DESIGN @f@a@d_main
     1486VIEW struct.bd
     1487GRAPHIC 6452,0 676 0
     1488DESIGN @f@a@d_main
     1489VIEW struct.bd
     1490GRAPHIC 8752,0 677 0
     1491DESIGN @f@a@d_main
     1492VIEW struct.bd
     1493GRAPHIC 9233,0 678 0
     1494DESIGN @f@a@d_main
     1495VIEW struct.bd
     1496GRAPHIC 9241,0 679 0
     1497DESIGN @f@a@d_main
     1498VIEW struct.bd
     1499GRAPHIC 9943,0 680 0
     1500DESIGN @f@a@d_main
     1501VIEW struct.bd
     1502GRAPHIC 9951,0 681 0
     1503DESIGN @f@a@d_main
     1504VIEW struct.bd
     1505GRAPHIC 6276,0 685 0
     1506DESIGN @f@a@d_main
     1507VIEW struct.bd
     1508GRAPHIC 3888,0 686 0
     1509DESIGN @f@a@d_main
     1510VIEW struct.bd
     1511NO_GRAPHIC 688

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r9912 r10073  
    109109(vvPair
    110110variable "HDLDir"
    111 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
     111value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
    112112)
    113113(vvPair
    114114variable "HDSDir"
    115 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
     115value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    116116)
    117117(vvPair
    118118variable "SideDataDesignDir"
    119 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     119value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    120120)
    121121(vvPair
    122122variable "SideDataUserDir"
    123 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     123value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    124124)
    125125(vvPair
    126126variable "SourceDir"
    127 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
     127value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    128128)
    129129(vvPair
    … …  
    141141(vvPair
    142142variable "d"
    143 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     143value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    144144)
    145145(vvPair
    146146variable "d_logical"
    147 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"
     147value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
    148148)
    149149(vvPair
    150150variable "date"
    151 value "27.08.2010"
     151value "03.01.2011"
    152152)
    153153(vvPair
    154154variable "day"
    155 value "Fr"
     155value "Mo"
    156156)
    157157(vvPair
    158158variable "day_long"
    159 value "Freitag"
     159value "Montag"
    160160)
    161161(vvPair
    162162variable "dd"
    163 value "27"
     163value "03"
    164164)
    165165(vvPair
    … …  
    221221(vvPair
    222222variable "mm"
    223 value "08"
     223value "01"
    224224)
    225225(vvPair
    … …  
    229229(vvPair
    230230variable "month"
    231 value "Aug"
     231value "Jan"
    232232)
    233233(vvPair
    234234variable "month_long"
    235 value "August"
     235value "Januar"
    236236)
    237237(vvPair
    238238variable "p"
    239 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     239value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    240240)
    241241(vvPair
    242242variable "p_logical"
    243 value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     243value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    244244)
    245245(vvPair
    … …  
    297297(vvPair
    298298variable "time"
    299 value "17:10:56"
     299value "16:58:24"
    300300)
    301301(vvPair
    … …  
    317317(vvPair
    318318variable "year"
    319 value "2010"
     319value "2011"
    320320)
    321321(vvPair
    322322variable "yy"
    323 value "10"
     323value "11"
    324324)
    325325]
    … …  
    349349bg "0,0,32768"
    350350)
    351 xt "99200,4000,108900,5000"
     351xt "99200,4000,108700,5000"
    352352st "
    353353by %user on %dd %month %year
    … …  
    688688n "wiz_reset"
    689689t "std_logic"
    690 o 43
     690o 44
    691691suid 2,0
    692692i "'1'"
    … …  
    727727b "(7 DOWNTO 0)"
    728728posAdd 0
    729 o 33
     729o 34
    730730suid 7,0
    731731i "(OTHERS => '0')"
    … …  
    799799n "adc_oeb"
    800800t "std_logic"
    801 o 28
     801o 29
    802802suid 21,0
    803803i "'1'"
    … …  
    909909t "std_logic_vector"
    910910b "(9 DOWNTO 0)"
    911 o 40
     911o 41
    912912suid 26,0
    913913)
    … …  
    945945n "wiz_cs"
    946946t "std_logic"
    947 o 41
     947o 42
    948948suid 28,0
    949949i "'1'"
    … …  
    983983t "std_logic_vector"
    984984b "(15 DOWNTO 0)"
    985 o 46
     985o 47
    986986suid 27,0
    987987)
    … …  
    10541054n "wiz_rd"
    10551055t "std_logic"
    1056 o 42
     1056o 43
    10571057suid 30,0
    10581058i "'1'"
    … …  
    10911091n "wiz_wr"
    10921092t "std_logic"
    1093 o 44
     1093o 45
    10941094suid 29,0
    10951095i "'1'"
    … …  
    13011301t "std_logic_vector"
    13021302b "(3 downto 0)"
    1303 o 31
     1303o 32
    13041304suid 48,0
    13051305i "(others => '0')"
    … …  
    13371337n "drs_dwrite"
    13381338t "std_logic"
    1339 o 32
     1339o 33
    13401340suid 49,0
    13411341i "'1'"
    … …  
    15821582n "dac_cs"
    15831583t "std_logic"
    1584 o 29
     1584o 30
    15851585suid 64,0
    15861586)
    … …  
    16181618n "sclk"
    16191619t "std_logic"
    1620 o 37
     1620o 38
    16211621suid 62,0
    16221622)
    … …  
    16551655t "std_logic_vector"
    16561656b "(3 DOWNTO 0)"
    1657 o 38
     1657o 39
    16581658suid 65,0
    16591659)
    … …  
    16931693preAdd 0
    16941694posAdd 0
    1695 o 45
     1695o 46
    16961696suid 63,0
    16971697)
    … …  
    17291729n "mosi"
    17301730t "std_logic"
    1731 o 34
     1731o 35
    17321732suid 66,0
    17331733i "'0'"
    … …  
    17681768eolc "-- default domino wave off"
    17691769posAdd 0
    1770 o 30
     1770o 31
    17711771suid 67,0
    17721772i "'0'"
    … …  
    18041804n "adc_clk_en"
    18051805t "std_logic"
    1806 o 27
     1806o 28
    18071807suid 69,0
    18081808i "'0'"
    … …  
    19181918preAdd 0
    19191919posAdd 0
    1920 o 35
     1920o 36
    19211921suid 77,0
    19221922i "(OTHERS => '0')"
    … …  
    21732173preAdd 0
    21742174posAdd 0
    2175 o 36
     2175o 37
    21762176suid 79,0
    21772177i "'0'"
    … …  
    22132213preAdd 0
    22142214posAdd 0
    2215 o 39
     2215o 40
    22162216suid 78,0
    22172217i "'0'"
    … …  
    23272327)
    23282328)
     2329*59 (CptPort
     2330uid 12314,0
     2331ps "OnEdgeStrategy"
     2332shape (Triangle
     2333uid 12315,0
     2334ro 90
     2335va (VaSet
     2336vasetType 1
     2337fg "0,65535,0"
     2338)
     2339xt "80000,139625,80750,140375"
     2340)
     2341tg (CPTG
     2342uid 12316,0
     2343ps "CptPortTextPlaceStrategy"
     2344stg "RightVerticalLayoutStrategy"
     2345f (Text
     2346uid 12317,0
     2347va (VaSet
     2348)
     2349xt "75300,139500,79000,140500"
     2350st "SRIN_out"
     2351ju 2
     2352blo "79000,140300"
     2353)
     2354)
     2355thePort (LogicalPort
     2356m 1
     2357decl (Decl
     2358n "SRIN_out"
     2359t "std_logic"
     2360o 27
     2361suid 85,0
     2362i "'0'"
     2363)
     2364)
     2365)
    23292366]
    23302367shape (Rectangle
    … …  
    23362373lineWidth 2
    23372374)
    2338 xt "52000,66000,80000,140000"
     2375xt "52000,66000,80000,141000"
    23392376)
    23402377oxt "15000,-1000,43000,27000"
    … …  
    23442381stg "VerticalLayoutStrategy"
    23452382textVec [
    2346 *59 (Text
     2383*60 (Text
    23472384uid 172,0
    23482385va (VaSet
    … …  
    23542391tm "BdLibraryNameMgr"
    23552392)
    2356 *60 (Text
     2393*61 (Text
    23572394uid 173,0
    23582395va (VaSet
    … …  
    23642401tm "CptNameMgr"
    23652402)
    2366 *61 (Text
     2403*62 (Text
    23672404uid 174,0
    23682405va (VaSet
    … …  
    24062443fg "49152,49152,49152"
    24072444)
    2408 xt "52250,138250,53750,139750"
     2445xt "52250,139250,53750,140750"
    24092446iconName "BlockDiagram.png"
    24102447iconMaskName "BlockDiagram.msk"
    … …  
    24162453archFileType "UNKNOWN"
    24172454)
    2418 *62 (PortIoIn
     2455*63 (PortIoIn
    24192456uid 231,0
    24202457shape (CompositeShape
    … …  
    24612498)
    24622499)
    2463 *63 (PortIoIn
     2500*64 (PortIoIn
    24642501uid 251,0
    24652502shape (CompositeShape
    … …  
    25062543)
    25072544)
    2508 *64 (HdlText
     2545*65 (HdlText
    25092546uid 265,0
    25102547optionalChildren [
    2511 *65 (EmbeddedText
     2548*66 (EmbeddedText
    25122549uid 271,0
    25132550commentText (CommentText
    … …  
    25592596stg "VerticalLayoutStrategy"
    25602597textVec [
    2561 *66 (Text
     2598*67 (Text
    25622599uid 268,0
    25632600va (VaSet
    … …  
    25692606tm "HdlTextNameMgr"
    25702607)
    2571 *67 (Text
     2608*68 (Text
    25722609uid 269,0
    25732610va (VaSet
    … …  
    25952632viewiconposition 0
    25962633)
    2597 *68 (Net
     2634*69 (Net
    25982635uid 275,0
    25992636decl (Decl
    … …  
    26032640preAdd 0
    26042641posAdd 0
    2605 o 55
     2642o 69
    26062643suid 5,0
    26072644)
    … …  
    26112648font "Courier New,8,0"
    26122649)
    2613 xt "39000,57600,67500,58400"
     2650xt "39000,60800,67500,61600"
    26142651st "SIGNAL board_id        : std_logic_vector(3 downto 0)
    26152652"
    26162653)
    26172654)
    2618 *69 (Net
     2655*70 (Net
    26192656uid 283,0
    26202657decl (Decl
    … …  
    26222659t "std_logic_vector"
    26232660b "(1 downto 0)"
    2624 o 56
     2661o 70
    26252662suid 6,0
    26262663)
    … …  
    26302667font "Courier New,8,0"
    26312668)
    2632 xt "39000,58400,67500,59200"
     2669xt "39000,61600,67500,62400"
    26332670st "SIGNAL crate_id        : std_logic_vector(1 downto 0)
    26342671"
    26352672)
    26362673)
    2637 *70 (PortIoOut
     2674*71 (PortIoOut
    26382675uid 472,0
    26392676shape (CompositeShape
    … …  
    26792716)
    26802717)
    2681 *71 (PortIoOut
     2718*72 (PortIoOut
    26822719uid 478,0
    26832720shape (CompositeShape
    … …  
    27232760)
    27242761)
    2725 *72 (PortIoOut
     2762*73 (PortIoOut
    27262763uid 484,0
    27272764shape (CompositeShape
    … …  
    27672804)
    27682805)
    2769 *73 (PortIoInOut
     2806*74 (PortIoInOut
    27702807uid 490,0
    27712808shape (CompositeShape
    … …  
    28092846)
    28102847)
    2811 *74 (PortIoIn
     2848*75 (PortIoIn
    28122849uid 496,0
    28132850shape (CompositeShape
    … …  
    28532890)
    28542891)
    2855 *75 (PortIoOut
     2892*76 (PortIoOut
    28562893uid 502,0
    28572894shape (CompositeShape
    … …  
    28972934)
    28982935)
    2899 *76 (PortIoOut
     2936*77 (PortIoOut
    29002937uid 508,0
    29012938shape (CompositeShape
    … …  
    29412978)
    29422979)
    2943 *77 (Net
     2980*78 (Net
    29442981uid 1465,0
    29452982decl (Decl
    29462983n "adc_data_array"
    29472984t "adc_data_array_type"
    2948 o 54
     2985o 68
    29492986suid 29,0
    29502987)
    … …  
    29542991font "Courier New,8,0"
    29552992)
    2956 xt "39000,56800,63000,57600"
     2993xt "39000,60000,63000,60800"
    29572994st "SIGNAL adc_data_array  : adc_data_array_type
    29582995"
    29592996)
    29602997)
    2961 *78 (Net
     2998*79 (Net
    29622999uid 2407,0
    29633000decl (Decl
    29643001n "RSRLOAD"
    29653002t "std_logic"
    2966 o 35
     3003o 37
    29673004suid 57,0
    29683005i "'0'"
    … …  
    29733010font "Courier New,8,0"
    29743011)
    2975 xt "39000,31000,68500,31800"
     3012xt "39000,34200,68500,35000"
    29763013st "RSRLOAD         : std_logic                      := '0'
    29773014"
    29783015)
    29793016)
    2980 *79 (PortIoOut
     3017*80 (PortIoOut
    29813018uid 2415,0
    29823019shape (CompositeShape
    … …  
    30233060)
    30243061)
    3025 *80 (Net
     3062*81 (Net
    30263063uid 2421,0
    30273064decl (Decl
    30283065n "SRCLK"
    30293066t "std_logic"
    3030 o 52
     3067o 66
    30313068suid 58,0
    30323069i "'0'"
    … …  
    30373074font "Courier New,8,0"
    30383075)
    3039 xt "39000,55200,72000,56000"
     3076xt "39000,58400,72000,59200"
    30403077st "SIGNAL SRCLK           : std_logic                      := '0'
    30413078"
    30423079)
    30433080)
    3044 *81 (Net
     3081*82 (Net
    30453082uid 3019,0
    30463083decl (Decl
    … …  
    30483085t "std_logic_vector"
    30493086b "(3 DOWNTO 0)"
    3050 o 59
     3087o 74
    30513088suid 65,0
    30523089)
    … …  
    30563093font "Courier New,8,0"
    30573094)
    3058 xt "39000,61600,67500,62400"
     3095xt "39000,64800,67500,65600"
    30593096st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)
    30603097"
    30613098)
    30623099)
    3063 *82 (Net
     3100*83 (Net
    30643101uid 3025,0
    30653102decl (Decl
    30663103n "DAC_CS"
    30673104t "std_logic"
    3068 o 21
     3105o 22
    30693106suid 66,0
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