Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd	(revision 10073)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 10:49:24 30.08.2010
+--          at - 14:00:25 01.10.2010
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -41,5 +41,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 10:49:25 30.08.2010
+--          at - 14:00:25 01.10.2010
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd	(revision 10073)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 09:42:04 30.07.2010
+--          at - 17:00:23 03.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -23,8 +23,10 @@
       config_data_valid : OUT    std_logic;
       config_ready      : OUT    std_logic;
+      -- --
+      config_rw_ack     : OUT    std_logic  := '0';
+      -- --
+      config_rw_ready   : OUT    std_logic  := '0';
       config_started    : OUT    std_logic  := '0';
       dac_array         : OUT    dac_array_type;
-      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
-      drs_address_mode  : OUT    std_logic;
       roi_array         : OUT    roi_array_type;
       config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
@@ -40,5 +42,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 09:42:04 30.07.2010
+--          at - 17:00:23 03.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -91,11 +93,14 @@
       config_data_valid : OUT    std_logic                      := '0';
       config_busy       : OUT    std_logic                      := '0';
+      -- --
+      config_rw_ack     : OUT    std_logic                      := '0';
+      -- --
+      config_rw_ready   : OUT    std_logic                      := '0';
+      -- --
       ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0);
       ram_data_in       : OUT    std_logic_vector (15 DOWNTO 0);
       ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
       dac_array         : OUT    dac_array_type ;
-      roi_array         : OUT    roi_array_type ;
-      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
-      drs_address_mode  : OUT    std_logic 
+      roi_array         : OUT    roi_array_type 
    );
    END COMPONENT;
@@ -137,11 +142,11 @@
          config_data_valid => config_data_valid,
          config_busy       => config_busy,
+         config_rw_ack     => config_rw_ack,
+         config_rw_ready   => config_rw_ready,
          ram_addr          => ram_addr,
          ram_data_in       => ram_data_in,
          ram_write_en      => ram_wren,
          dac_array         => dac_array,
-         roi_array         => roi_array,
-         drs_address       => drs_address,
-         drs_address_mode  => drs_address_mode
+         roi_array         => roi_array
       );
 
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd	(revision 10073)
@@ -142,5 +142,5 @@
         when CONFIG4 =>
           drs_channel_id <= DRS_WRITE_SHIFT_REG;
-          drs_srin_data <= "10101010";
+          drs_srin_data <= "11111111";
           drs_srin_write_8b <= '1';
           if (drs_srin_write_ack = '1') then
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak	(revision 10073)
@@ -25,4 +25,6 @@
   );
    port( 
+--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+
       clk            : in     std_logic;
       data_out       : out    std_logic_vector (63 downto 0);
@@ -32,4 +34,7 @@
       ram_write_ea : in std_logic;
       ram_write_ready : out std_logic := '0';
+      -- --
+      ram_write_ready_ack : IN std_logic;
+      -- --
       config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
       config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
@@ -45,5 +50,5 @@
       trigger_id     : in std_logic_vector (47 downto 0);
       trigger        : in std_logic;
-      s_trigger      : in std_logic;
+--      s_trigger      : in std_logic;
       new_config     : in std_logic;
       config_started : out std_logic := '0';
@@ -55,4 +60,10 @@
       drs_dwrite : out std_logic := '1';
       drs_clk_en, drs_read_s_cell : out std_logic := '0';
+
+      drs_srin_write_8b : out std_logic := '0';
+      drs_srin_write_ack : in std_logic;
+      drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0');
+      drs_srin_write_ready : in std_logic;
+
       drs_read_s_cell_ready : in std_logic;
       drs_s_cell_array : in drs_s_cell_array_type
@@ -62,5 +73,5 @@
 architecture Behavioral of data_generator is
 
-type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
+type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
                              WRITE_END_FLAG, WRITE_DATA_STOP,
@@ -76,6 +87,9 @@
 signal adc_wait_cnt : integer range 0 to 7 := 0;
 
-signal trigger_flag : std_logic := '0';
-
+signal trigger_flag :std_logic := '0';
+signal ram_write_ea_flag : std_logic := '0';
+signal new_config_int : std_logic := '0';
+
+signal roi_max_int : roi_max_type;
 
 begin
@@ -95,31 +109,49 @@
         when CONFIG =>
           config_started <= '1';
-          -- config config manager
-          config_start_cm <= '1';
-          if (config_started_cm = '1') then
-            state_generate <= CONFIG1;
+          if (new_config = '0') then
+            config_started <= '0';
+            -- config config manager
+            config_start_cm <= '1';
+            if (config_started_cm = '1') then
+              config_start_cm <= '0';
+              state_generate <= CONFIG1;
+            end if;
           end if;
         when CONFIG1 =>
           if (config_ready_cm = '1') then
-            config_started <= '0';
-            config_start_cm <= '0';
             config_start_mm <= '1';
           end if;
           if (config_started_mm = '1') then
+            config_start_mm <= '0';
             state_generate <= CONFIG2;
           end if;
         when CONFIG2 =>
           if (config_ready_mm = '1') then
-            config_start_mm <= '0';
             config_start_spi <= '1';
           end if;
           if (config_started_spi = '1') then
+            config_start_spi <= '0';
             state_generate <= CONFIG3;
           end if;
         when CONFIG3 =>
           if (config_ready_spi = '1') then
-            config_start_spi <= '0';
+            state_generate <= CONFIG4;
+--            state_generate <= WRITE_DATA_IDLE;
+          end if;
+        -- configure DRS
+        when CONFIG4 =>
+          drs_channel_id <= DRS_WRITE_SHIFT_REG;
+          drs_srin_data <= "10101010";
+          drs_srin_write_8b <= '1';
+          if (drs_srin_write_ack = '1') then
+            drs_srin_write_8b <= '0';
+            state_generate <= CONFIG5;
+          end if;
+        when CONFIG5 =>
+          if (drs_srin_write_ready = '1') then
+            roi_max_int <= roi_max;
             state_generate <= WRITE_DATA_IDLE;
           end if;
+        -- end configure DRS
 
         when WRITE_DATA_IDLE =>
@@ -127,5 +159,6 @@
             state_generate <= CONFIG;
           end if;
-          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
+--          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
+          if (ram_write_ea = '1' and trigger_flag = '1') then
             -- stop drs, dwrite low
             drs_dwrite <= '0';
@@ -248,5 +281,6 @@
         when WRITE_EXTERNAL_TRIGGER =>    -- external trigger ID
           addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
-          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
+--          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
+          data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
           state_generate <= WRITE_INTERNAL_TRIGGER;
         when WRITE_INTERNAL_TRIGGER =>    -- internal trigger ID
@@ -263,13 +297,24 @@
 					state_generate <= WRITE_DATA_END_WAIT;
 				when WRITE_DATA_END_WAIT =>
-				  state_generate <= WRITE_DATA_STOP;
+          -- --
+				  if (ram_write_ready_ack = '1') then
+				    state_generate <= WRITE_DATA_STOP;
+				    -- --
+            ram_write_ready <= '0';
+            -- --
+				  end if;
+				  -- --
       		when WRITE_DATA_STOP =>
-          drs_dwrite <= '1';
-					data_cntr <= 0;
-					addr_cntr <= 0;
-					channel_id <= 0;
-					ram_write_ready <= '0';
-					state_generate <= WRITE_DATA_IDLE;
-				
+      		  -- --
+      		  if (ram_write_ready_ack = '0') then
+      		  -- --
+            drs_dwrite <= '1';
+					  data_cntr <= 0;
+					  addr_cntr <= 0;
+					  channel_id <= 0;
+					  state_generate <= WRITE_DATA_IDLE;
+					-- --
+					end if;
+				  -- --
 				when others =>
 					null;
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf	(revision 10073)
@@ -25,11 +25,11 @@
 NET RS485_C_DE LOC  = C5 | IOSTANDARD=LVCMOS33;		#ok
 NET RS485_C_RE LOC  = C6 | IOSTANDARD=LVCMOS33;		#ok
-#NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;		#ok
-#NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;		#ok
+NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;		#ok
+NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;		#ok
 
 NET RS485_E_DE LOC  = D20 | IOSTANDARD=LVCMOS33;		#ok
 NET RS485_E_RE LOC  = D21 | IOSTANDARD=LVCMOS33;		#ok
-#NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;		#ok
-#NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;		#ok
+NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;		#ok
+NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;		#ok
 
 
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd	(revision 10073)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 10:49:29 30.08.2010
+--          at - 17:00:27 03.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -23,4 +23,7 @@
       D3_SROUT   : IN     std_logic;
       D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0);
+      RS485_C_DI : IN     std_logic;
+      RS485_E_DI : IN     std_logic;
+      RS485_E_DO : IN     std_logic;
       TRG        : IN     STD_LOGIC;
       W_INT      : IN     std_logic;
@@ -44,9 +47,10 @@
       OE_ADC     : OUT    STD_LOGIC;
       RS485_C_DE : OUT    std_logic;
+      RS485_C_DO : OUT    std_logic;
       RS485_C_RE : OUT    std_logic;
       RS485_E_DE : OUT    std_logic;
       RS485_E_RE : OUT    std_logic;
       RSRLOAD    : OUT    std_logic                       := '0';
-      SRIN       : OUT    std_logic;
+      SRIN       : OUT    std_logic                       := '0';
       S_CLK      : OUT    std_logic;
       T0_CS      : OUT    std_logic;
@@ -73,5 +77,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 10:49:29 30.08.2010
+--          at - 17:00:27 03.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -152,4 +156,5 @@
       RSRLOAD         : OUT    std_logic                     := '0';
       SRCLK           : OUT    std_logic                     := '0';
+      SRIN_out        : OUT    std_logic                     := '0';
       adc_clk_en      : OUT    std_logic                     := '0';
       adc_oeb         : OUT    std_logic                     := '1';
@@ -220,13 +225,16 @@
    -- MISC 6     
    TRG_V <= '0';
-   RS485_C_RE <= '1'; 
+   RS485_C_RE <= '0'; 
    RS485_C_DE <= '0';   
-   RS485_E_RE <= '1';      
+   RS485_C_DO <= RS485_C_DI;
+   
+   RS485_E_RE <= '0';      
    RS485_E_DE <= '0'; 
+   --RS485_E_DO <= RS485_E_DI;
    
    -- DENABLE <= '0'; -- domino wave stopped
    -- DENABLE <= '1'; -- domino wave running
    
-   SRIN <= '1';
+   
    EE_CS <= '1';
    -- LEDs are low active
@@ -305,4 +313,5 @@
          RSRLOAD         => RSRLOAD,
          SRCLK           => SRCLK,
+         SRIN_out        => SRIN,
          adc_clk_en      => adc_clk_en,
          adc_oeb         => OE_ADC,
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd	(revision 10073)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 10:49:27 30.08.2010
+--          at - 17:00:23 03.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -44,4 +44,5 @@
       RSRLOAD         : OUT    std_logic                     := '0';
       SRCLK           : OUT    std_logic                     := '0';
+      SRIN_out        : OUT    std_logic                     := '0';
       adc_clk_en      : OUT    std_logic                     := '0';
       adc_oeb         : OUT    std_logic                     := '1';
@@ -76,5 +77,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 10:49:28 30.08.2010
+--          at - 17:00:24 03.01.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -113,4 +114,8 @@
    SIGNAL config_ready_cm        : std_logic;
    SIGNAL config_ready_spi       : std_logic;
+   -- --
+   SIGNAL config_rw_ack          : std_logic                                    := '0';
+   -- --
+   SIGNAL config_rw_ready        : std_logic                                    := '0';
    SIGNAL config_start           : std_logic                                    := '0';
    SIGNAL config_start_cm        : std_logic;
@@ -130,4 +135,5 @@
    SIGNAL drs_read_s_cell_ready  : std_logic;
    SIGNAL drs_s_cell_array       : drs_s_cell_array_type;
+   SIGNAL drs_srin_data          : std_logic_vector(7 DOWNTO 0)                 := (others => '0');
    SIGNAL dwrite                 : std_logic                                    := '1';
    SIGNAL dwrite_enable          : std_logic                                    := '1';
@@ -142,7 +148,9 @@
    SIGNAL ram_write_ea           : std_logic;
    SIGNAL ram_write_ready        : std_logic                                    := '0';
+   -- --
+   SIGNAL ram_write_ready_ack    : std_logic                                    := '0';
    SIGNAL roi_array              : roi_array_type;
    SIGNAL roi_max                : roi_max_type;
-   SIGNAL s_trigger              : std_logic                                    := '0';
+   SIGNAL s_trigger              : std_logic;
    SIGNAL sclk1                  : std_logic;
    SIGNAL sclk_enable            : std_logic;
@@ -150,5 +158,9 @@
    SIGNAL sensor_ready           : std_logic;
    SIGNAL srclk_enable           : std_logic                                    := '0';
+   SIGNAL srin_write_ack         : std_logic                                    := '0';
+   SIGNAL srin_write_ready       : std_logic                                    := '0';
+   SIGNAL start_srin_write_8b    : std_logic;
    SIGNAL trigger_id             : std_logic_vector(47 DOWNTO 0);
+   SIGNAL trigger_out            : std_logic;
    SIGNAL wiz_ack                : std_logic;
    SIGNAL wiz_busy               : std_logic;
@@ -207,8 +219,10 @@
       config_data_valid : OUT    std_logic ;
       config_ready      : OUT    std_logic ;
+      -- --
+      config_rw_ack     : OUT    std_logic  := '0';
+      -- --
+      config_rw_ready   : OUT    std_logic  := '0';
       config_started    : OUT    std_logic  := '0';
       dac_array         : OUT    dac_array_type ;
-      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
-      drs_address_mode  : OUT    std_logic ;
       roi_array         : OUT    roi_array_type ;
       config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
@@ -231,4 +245,5 @@
    );
    PORT (
+      --      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
       clk                   : IN     std_logic ;
       data_out              : OUT    std_logic_vector (63 DOWNTO 0);
@@ -238,6 +253,11 @@
       ram_write_ea          : IN     std_logic ;
       ram_write_ready       : OUT    std_logic                     := '0';
+      -- --
+      ram_write_ready_ack   : IN     std_logic ;
+      -- --
       config_start_mm       : OUT    std_logic                     := '0';
+      -- --
       config_start_cm       : OUT    std_logic                     := '0';
+      -- --
       config_start_spi      : OUT    std_logic                     := '0';
       config_ready_mm       : IN     std_logic ;
@@ -257,5 +277,5 @@
       trigger_id            : IN     std_logic_vector (47 DOWNTO 0);
       trigger               : IN     std_logic ;
-      s_trigger             : IN     std_logic ;
+      --      s_trigger      : in std_logic;
       new_config            : IN     std_logic ;
       config_started        : OUT    std_logic                     := '0';
@@ -268,4 +288,8 @@
       drs_clk_en            : OUT    std_logic                     := '0';
       drs_read_s_cell       : OUT    std_logic                     := '0';
+      drs_srin_write_8b     : OUT    std_logic                     := '0';
+      drs_srin_write_ack    : IN     std_logic ;
+      drs_srin_data         : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
+      drs_srin_write_ready  : IN     std_logic ;
       drs_read_s_cell_ready : IN     std_logic ;
       drs_s_cell_array      : IN     drs_s_cell_array_type 
@@ -279,8 +303,13 @@
       SROUT_in_2               : IN     std_logic;
       SROUT_in_3               : IN     std_logic;
+      srin_data                : IN     std_logic_vector (7 DOWNTO 0);
       start_endless_mode       : IN     std_logic;
       start_read_stop_pos_mode : IN     std_logic;
+      start_srin_write_8b      : IN     std_logic;
       RSRLOAD                  : OUT    std_logic  := '0';
       SRCLK                    : OUT    std_logic  := '0';
+      SRIN_out                 : OUT    std_logic  := '0';
+      srin_write_ack           : OUT    std_logic  := '0';
+      srin_write_ready         : OUT    std_logic  := '0';
       stop_pos                 : OUT    drs_s_cell_array_type;
       stop_pos_valid           : OUT    std_logic  := '0'
@@ -296,4 +325,7 @@
       config_start           : IN     std_logic ;
       ram_write_ready        : IN     std_logic ;
+      -- --
+      ram_write_ready_ack    : OUT    std_logic                                        := '0';
+      -- --
       roi_array              : IN     roi_array_type ;
       ram_write_ea           : OUT    std_logic                                        := '0';
@@ -367,4 +399,9 @@
       config_wr_en      : OUT    std_logic                      := '0';
       config_rd_en      : OUT    std_logic                      := '0';
+      -- --
+      config_rw_ack     : IN     std_logic ;
+      -- --
+      config_rw_ready   : IN     std_logic ;
+      -- --
       config_busy       : IN     std_logic ;
       denable           : OUT    std_logic                      := '0';           -- default domino wave off
@@ -429,4 +466,7 @@
       END CASE;
    END PROCESS u_0combo_proc;
+
+   -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
+   trigger_out <= s_trigger OR trigger;
 
    -- Instance port mappings.
@@ -468,8 +508,8 @@
          config_data_valid => config_data_valid,
          config_ready      => config_ready_cm,
+         config_rw_ack     => config_rw_ack,
+         config_rw_ready   => config_rw_ready,
          config_started    => config_started_cu,
          dac_array         => dac_array,
-         drs_address       => drs_address,
-         drs_address_mode  => drs_address_mode,
          roi_array         => roi_array,
          config_data       => config_data
@@ -497,4 +537,5 @@
          ram_write_ea          => ram_write_ea,
          ram_write_ready       => ram_write_ready,
+         ram_write_ready_ack   => ram_write_ready_ack,
          config_start_mm       => config_start,
          config_start_cm       => config_start_cm,
@@ -515,6 +556,5 @@
          crate_id              => crate_id,
          trigger_id            => trigger_id,
-         trigger               => trigger,
-         s_trigger             => s_trigger,
+         trigger               => trigger_out,
          new_config            => new_config,
          config_started        => config_started,
@@ -527,4 +567,8 @@
          drs_clk_en            => drs_clk_en,
          drs_read_s_cell       => drs_read_s_cell,
+         drs_srin_write_8b     => start_srin_write_8b,
+         drs_srin_write_ack    => srin_write_ack,
+         drs_srin_data         => drs_srin_data,
+         drs_srin_write_ready  => srin_write_ready,
          drs_read_s_cell_ready => drs_read_s_cell_ready,
          drs_s_cell_array      => drs_s_cell_array
@@ -541,4 +585,9 @@
          stop_pos                 => drs_s_cell_array,
          stop_pos_valid           => drs_read_s_cell_ready,
+         start_srin_write_8b      => start_srin_write_8b,
+         srin_write_ready         => srin_write_ready,
+         srin_write_ack           => srin_write_ack,
+         srin_data                => drs_srin_data,
+         SRIN_out                 => SRIN_out,
          RSRLOAD                  => RSRLOAD,
          SRCLK                    => SRCLK1
@@ -553,4 +602,5 @@
          config_start           => config_start,
          ram_write_ready        => ram_write_ready,
+         ram_write_ready_ack    => ram_write_ready_ack,
          roi_array              => roi_array,
          ram_write_ea           => ram_write_ea,
@@ -587,5 +637,5 @@
       PORT MAP (
          trigger_id => trigger_id,
-         trigger    => trigger,
+         trigger    => trigger_out,
          clk        => CLK_25_PS_internal
       );
@@ -621,4 +671,6 @@
          config_wr_en      => config_wr_en,
          config_rd_en      => config_rd_en,
+         config_rw_ack     => config_rw_ack,
+         config_rw_ready   => config_rw_ready,
          config_busy       => config_busy,
          denable           => denable,
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd	(revision 10073)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 09:42:04 30.07.2010
+--          at - 14:00:24 01.10.2010
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -38,5 +38,5 @@
 -- Created:
 --          by - dneise.UNKNOWN (E5B-LABOR6)
---          at - 09:42:04 30.07.2010
+--          at - 14:00:25 01.10.2010
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf	(revision 10073)
@@ -31,230 +31,230 @@
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 350,0 24 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 165,0 25 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 521,0 26 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 526,0 27 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 155,0 28 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 150,0 29 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 1,0 32 0 
-DESIGN control_unit
-VIEW symbol.sb
-GRAPHIC 1,0 33 0 
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 36
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 41,0 45 0 
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 50
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 0,0 53 2 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 345,0 58 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 333,0 59 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 349,0 60 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 329,0 61 0 
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 62
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 63
+GRAPHIC 558,0 25 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 564,0 27 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 350,0 28 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 165,0 29 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 155,0 30 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 150,0 31 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 1,0 34 0 
+DESIGN control_unit
+VIEW symbol.sb
+GRAPHIC 1,0 35 0 
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 38
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 41,0 47 0 
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 52
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 0,0 55 2 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 345,0 60 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 333,0 61 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 349,0 62 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 329,0 63 0 
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 64
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 65
 LIBRARY FACT_FAD_lib
 DESIGN control@r@a@m_16bit_x256
 VIEW control@r@a@m_16bit_x256_a
-GRAPHIC 993,0 65 0 
-DESIGN control@r@a@m_16bit_x256
-VIEW control@r@a@m_16bit_x256_a
-GRAPHIC 48,0 67 0 
-DESIGN control@r@a@m_16bit_x256
-VIEW control@r@a@m_16bit_x256_a
-GRAPHIC 53,0 68 0 
-DESIGN control@r@a@m_16bit_x256
-VIEW control@r@a@m_16bit_x256_a
-GRAPHIC 58,0 69 0 
-DESIGN control@r@a@m_16bit_x256
-VIEW control@r@a@m_16bit_x256_a
-GRAPHIC 63,0 70 0 
-DESIGN control@r@a@m_16bit_x256
-VIEW control@r@a@m_16bit_x256_a
-GRAPHIC 68,0 71 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 960,0 74 0 
-DESIGN control_manager
-VIEW symbol.sb
-GRAPHIC 14,0 75 1 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 48,0 81 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 310,0 82 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 58,0 83 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 492,0 84 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 63,0 85 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 68,0 86 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 73,0 87 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 78,0 88 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 83,0 89 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 88,0 90 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 93,0 91 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 346,0 92 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 263,0 93 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 268,0 94 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 118,0 95 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 123,0 96 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 528,0 97 0 
-DESIGN control_manager
-VIEW beha
-GRAPHIC 533,0 98 0 
+GRAPHIC 993,0 67 0 
+DESIGN control@r@a@m_16bit_x256
+VIEW control@r@a@m_16bit_x256_a
+GRAPHIC 48,0 69 0 
+DESIGN control@r@a@m_16bit_x256
+VIEW control@r@a@m_16bit_x256_a
+GRAPHIC 53,0 70 0 
+DESIGN control@r@a@m_16bit_x256
+VIEW control@r@a@m_16bit_x256_a
+GRAPHIC 58,0 71 0 
+DESIGN control@r@a@m_16bit_x256
+VIEW control@r@a@m_16bit_x256_a
+GRAPHIC 63,0 72 0 
+DESIGN control@r@a@m_16bit_x256
+VIEW control@r@a@m_16bit_x256_a
+GRAPHIC 68,0 73 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 960,0 76 0 
+DESIGN control_manager
+VIEW symbol.sb
+GRAPHIC 14,0 77 1 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 48,0 83 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 310,0 84 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 58,0 85 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 492,0 86 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 63,0 87 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 68,0 88 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 73,0 89 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 78,0 90 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 83,0 91 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 88,0 92 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 93,0 93 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 571,0 94 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 576,0 96 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 346,0 98 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 263,0 100 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 268,0 101 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 118,0 102 0 
+DESIGN control_manager
+VIEW beha
+GRAPHIC 123,0 103 0 
 LIBRARY FACT_FAD_lib
 DESIGN control_unit
 VIEW struct.bd
-NO_GRAPHIC 101
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 993,0 104 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 960,0 105 0 
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 108
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 110
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 993,0 112 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 279,0 114 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 237,0 115 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 285,0 116 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 233,0 117 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 301,0 118 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 960,0 120 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 967,0 121 1 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 241,0 127 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 301,0 128 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 321,0 129 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 1084,0 130 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 289,0 131 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 267,0 132 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 227,0 133 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 295,0 134 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 311,0 135 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 255,0 136 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 261,0 137 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 285,0 138 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 237,0 139 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 233,0 140 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 305,0 141 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 273,0 142 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 1208,0 143 0 
-DESIGN control_unit
-VIEW struct.bd
-GRAPHIC 1222,0 144 0 
-DESIGN control_unit
-VIEW struct.bd
-NO_GRAPHIC 147
+NO_GRAPHIC 106
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 993,0 109 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 960,0 110 0 
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 113
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 115
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 993,0 117 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 279,0 119 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 237,0 120 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 285,0 121 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 233,0 122 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 301,0 123 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 960,0 125 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 967,0 126 1 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 241,0 132 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 301,0 133 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 321,0 134 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 1084,0 135 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 289,0 136 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 267,0 137 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 227,0 138 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 295,0 139 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 311,0 140 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 255,0 141 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 261,0 142 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 1281,0 143 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 1295,0 144 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 285,0 145 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 237,0 146 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 233,0 147 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 305,0 148 0 
+DESIGN control_unit
+VIEW struct.bd
+GRAPHIC 273,0 149 0 
+DESIGN control_unit
+VIEW struct.bd
+NO_GRAPHIC 152
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf	(revision 10073)
@@ -37,575 +37,593 @@
 DESIGN @f@a@d_@board
 VIEW symbol.sb
-GRAPHIC 1121,0 24 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1421,0 25 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1116,0 26 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 3456,0 27 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 3026,0 28 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1126,0 29 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1227,0 30 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1232,0 31 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1237,0 32 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1242,0 33 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1363,0 34 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1701,0 35 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1308,0 36 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1302,0 37 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 2068,0 38 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 2949,0 39 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1711,0 40 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 2375,0 41 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1620,0 42 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1166,0 43 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1686,0 44 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1681,0 45 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1696,0 46 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1691,0 47 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 693,0 48 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1706,0 49 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1388,0 50 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1368,0 51 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1373,0 52 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1378,0 53 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1383,0 54 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1676,0 55 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1393,0 56 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1426,0 57 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1409,0 58 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1403,0 59 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1415,0 60 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1626,0 61 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1398,0 62 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1,0 65 0 
-DESIGN @f@a@d_@board
-VIEW symbol.sb
-GRAPHIC 1,0 66 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-NO_GRAPHIC 69
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 41,0 78 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-NO_GRAPHIC 86
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 0,0 89 2 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10504,0 94 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10512,0 95 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10496,0 96 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 3268,0 97 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10032,0 98 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 9500,0 99 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10552,0 100 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10592,0 101 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10584,0 102 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10576,0 103 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10536,0 104 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10544,0 105 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10520,0 106 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10528,0 107 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 2421,0 108 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10050,0 109 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 1465,0 110 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 275,0 111 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 283,0 112 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 8851,0 113 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 7485,0 114 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10560,0 115 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 3019,0 116 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-GRAPHIC 10568,0 118 0 
-DESIGN @f@a@d_@board
-VIEW struct.bd
-NO_GRAPHIC 119
-DESIGN @f@a@d_@board
-VIEW struct.bd
-NO_GRAPHIC 120
+GRAPHIC 3581,0 24 0 
+DESIGN @f@a@d_@board
+VIEW symbol.sb
+GRAPHIC 3687,0 25 0 
+DESIGN @f@a@d_@board
+VIEW symbol.sb
+GRAPHIC 3692,0 26 0 
+DESIGN @f@a@d_@board
+VIEW symbol.sb
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+DESIGN @f@a@d_@board
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf	(revision 10073)
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 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 168,0 179 0 
+GRAPHIC 168,0 191 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 848,0 180 0 
+GRAPHIC 848,0 192 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 703,0 181 0 
+GRAPHIC 703,0 193 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 698,0 182 0 
+GRAPHIC 698,0 194 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 126,0 183 0 
+GRAPHIC 126,0 195 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 643,0 184 0 
+GRAPHIC 643,0 196 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 121,0 185 0 
+GRAPHIC 121,0 197 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 481,0 186 0 
+GRAPHIC 481,0 198 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 544,0 187 0 
+GRAPHIC 544,0 199 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 524,0 188 0 
+GRAPHIC 524,0 200 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 539,0 189 0 
+GRAPHIC 539,0 201 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 529,0 190 0 
+GRAPHIC 529,0 202 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 534,0 191 0 
+GRAPHIC 534,0 203 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 475,0 192 0 
+GRAPHIC 475,0 204 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 463,0 193 0 
+GRAPHIC 463,0 205 0 
 DESIGN clock_generator_var_ps
 VIEW symbol.sb
-GRAPHIC 469,0 194 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 5072,0 198 0 
+GRAPHIC 469,0 206 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5072,0 210 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 130,0 200 0 
+GRAPHIC 130,0 212 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 135,0 201 0 
+GRAPHIC 135,0 213 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 170,0 202 0 
+GRAPHIC 170,0 214 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 175,0 203 0 
+GRAPHIC 175,0 215 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 160,0 204 0 
+GRAPHIC 160,0 216 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 145,0 205 0 
+GRAPHIC 145,0 217 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 140,0 206 0 
+GRAPHIC 140,0 218 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 180,0 207 0 
+GRAPHIC 180,0 219 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 350,0 208 0 
+GRAPHIC 558,0 220 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 165,0 209 0 
+GRAPHIC 564,0 222 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 521,0 210 0 
+GRAPHIC 350,0 224 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 526,0 211 0 
+GRAPHIC 165,0 225 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 155,0 212 0 
+GRAPHIC 155,0 226 0 
 DESIGN control_unit
 VIEW symbol.sb
-GRAPHIC 150,0 213 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 8277,0 216 0 
+GRAPHIC 150,0 227 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 8277,0 230 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 48,0 218 0 
+GRAPHIC 48,0 232 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 53,0 219 0 
+GRAPHIC 53,0 233 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 58,0 220 0 
+GRAPHIC 58,0 234 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 63,0 221 0 
+GRAPHIC 63,0 235 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 68,0 222 0 
+GRAPHIC 68,0 236 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 73,0 223 0 
+GRAPHIC 73,0 237 0 
 DESIGN data@r@a@m_64b_16b_width14_5
 VIEW data@r@a@m_64b_16b_width14_5_a
-GRAPHIC 78,0 224 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 1399,0 227 0 
-DESIGN data_generator
-VIEW symbol.sb
-GRAPHIC 14,0 228 1 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 48,0 232 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 53,0 233 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 58,0 234 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 73,0 235 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 78,0 236 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 402,0 237 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 407,0 238 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1122,0 239 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 963,0 240 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1127,0 241 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1048,0 242 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 958,0 243 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1053,0 244 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1201,0 245 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1196,0 246 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1206,0 247 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 473,0 248 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 412,0 249 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1085,0 250 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1090,0 251 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1240,0 252 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 526,0 253 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 88,0 254 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 285,0 255 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 93,0 256 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 98,0 257 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1018,0 258 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1164,0 259 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1159,0 260 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 898,0 261 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 637,0 262 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1395,0 263 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 1427,0 264 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 676,0 265 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 845,0 266 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 681,0 267 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 801,0 268 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 806,0 269 0 
-DESIGN data_generator
-VIEW @behavioral
-GRAPHIC 811,0 270 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 4903,0 273 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-NO_GRAPHIC 286
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 2311,0 288 0 
-DESIGN memory_manager
-VIEW symbol.sb
-GRAPHIC 14,0 289 1 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 138,0 294 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 194,0 295 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 349,0 296 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 569,0 297 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 224,0 298 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 254,0 299 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 804,0 300 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 433,0 301 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 622,0 302 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 289,0 303 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 309,0 304 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 284,0 305 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 294,0 306 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 304,0 307 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 299,0 308 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 379,0 309 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 915,0 310 0 
-DESIGN memory_manager
-VIEW beha
-GRAPHIC 51,0 311 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 5793,0 314 0 
+GRAPHIC 78,0 238 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1399,0 241 0 
+DESIGN data_generator
+VIEW symbol.sb
+GRAPHIC 14,0 242 1 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 48,0 246 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 53,0 248 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 58,0 249 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 73,0 250 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 78,0 251 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 402,0 252 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 407,0 253 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1479,0 254 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1122,0 256 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 963,0 258 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1127,0 260 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1048,0 262 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 958,0 263 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1053,0 264 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1201,0 265 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1196,0 266 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1206,0 267 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 473,0 268 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 412,0 269 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1085,0 270 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1090,0 271 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1240,0 272 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 526,0 273 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 88,0 274 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 285,0 275 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 93,0 276 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 98,0 277 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1164,0 278 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1159,0 280 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 898,0 281 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 637,0 282 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1395,0 283 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1427,0 284 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 676,0 285 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 845,0 286 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 681,0 287 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 801,0 288 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1464,0 289 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1469,0 290 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1459,0 291 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 1474,0 292 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 806,0 293 0 
+DESIGN data_generator
+VIEW @behavioral
+GRAPHIC 811,0 294 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4903,0 297 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+NO_GRAPHIC 315
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2311,0 317 0 
+DESIGN memory_manager
+VIEW symbol.sb
+GRAPHIC 14,0 318 1 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 138,0 323 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 194,0 324 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 349,0 325 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 949,0 326 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 569,0 328 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 224,0 330 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 254,0 331 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 804,0 332 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 433,0 333 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 622,0 334 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 289,0 335 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 309,0 336 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 284,0 337 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 294,0 338 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 304,0 339 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 299,0 340 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 379,0 341 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 915,0 342 0 
+DESIGN memory_manager
+VIEW beha
+GRAPHIC 51,0 343 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5793,0 346 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 1121,0 316 0 
+GRAPHIC 1121,0 348 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 326,0 317 0 
+GRAPHIC 326,0 349 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 197,0 318 0 
+GRAPHIC 197,0 350 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 321,0 319 0 
+GRAPHIC 321,0 351 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 1198,0 320 0 
+GRAPHIC 1198,0 352 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 1017,0 321 0 
+GRAPHIC 1017,0 353 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 1229,0 322 0 
+GRAPHIC 1229,0 354 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 126,0 323 0 
+GRAPHIC 126,0 355 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 819,0 324 0 
+GRAPHIC 819,0 356 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 1022,0 325 0 
+GRAPHIC 1022,0 357 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 824,0 326 0 
+GRAPHIC 824,0 358 0 
 DESIGN spi_interface
 VIEW symbol.sb
-GRAPHIC 1283,0 327 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 1768,0 330 0 
+GRAPHIC 1283,0 359 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1768,0 362 0 
 DESIGN trigger_counter
 VIEW beha
-GRAPHIC 48,0 332 0 
+GRAPHIC 48,0 364 0 
 DESIGN trigger_counter
 VIEW beha
-GRAPHIC 53,0 333 0 
+GRAPHIC 53,0 365 0 
 DESIGN trigger_counter
 VIEW beha
-GRAPHIC 148,0 334 0 
-DESIGN @f@a@d_main
-VIEW struct.bd
-GRAPHIC 1606,0 337 0 
-DESIGN w5300_modul
-VIEW symbol.sb
-GRAPHIC 14,0 338 1 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 48,0 342 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 53,0 343 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 58,0 344 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 63,0 345 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 68,0 346 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 73,0 347 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 491,0 348 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 83,0 349 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 88,0 350 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 93,0 351 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 98,0 352 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 103,0 353 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 108,0 354 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 113,0 355 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 885,0 356 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 118,0 357 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 353,0 358 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 348,0 359 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 385,0 360 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 521,0 361 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 576,0 362 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 566,0 363 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 551,0 364 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 561,0 365 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 571,0 366 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 640,0 367 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 556,0 368 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 670,0 369 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 723,0 370 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 917,0 371 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 949,0 372 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 954,0 373 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 988,0 374 0 
-DESIGN w5300_modul
-VIEW @behavioral
-GRAPHIC 1020,0 375 0 
+GRAPHIC 148,0 366 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1606,0 369 0 
+DESIGN w5300_modul
+VIEW symbol.sb
+GRAPHIC 14,0 370 1 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 48,0 374 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 53,0 375 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 58,0 376 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 63,0 377 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 68,0 378 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 73,0 379 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 491,0 380 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 83,0 381 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 88,0 382 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 93,0 383 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 98,0 384 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 103,0 385 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 108,0 386 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 113,0 387 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 885,0 388 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 118,0 389 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 353,0 390 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 348,0 391 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 385,0 392 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 521,0 393 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 576,0 394 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 566,0 395 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 551,0 396 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 561,0 397 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 571,0 398 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 640,0 399 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 1052,0 400 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 1057,0 402 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 556,0 404 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 670,0 406 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 723,0 407 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 917,0 408 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 949,0 409 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 954,0 410 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 988,0 411 0 
+DESIGN w5300_modul
+VIEW @behavioral
+GRAPHIC 1020,0 412 0 
 LIBRARY FACT_FAD_lib
 DESIGN @f@a@d_main
 VIEW struct.bd
-NO_GRAPHIC 378
-DESIGN @f@a@d_main
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+GRAPHIC 5602,0 518 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 334,0 519 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 328,0 520 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 322,0 521 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4240,0 522 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 364,0 523 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 370,0 524 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1399,0 526 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1406,0 527 1 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5602,0 531 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 334,0 532 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 328,0 533 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 322,0 534 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2299,0 535 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2576,0 536 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2582,0 537 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10467,0 538 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2588,0 539 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5184,0 540 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5745,0 541 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2594,0 542 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5190,0 543 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5404,0 544 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6018,0 545 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6002,0 546 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6008,0 547 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5138,0 548 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2600,0 549 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5480,0 550 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5474,0 551 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6064,0 552 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2642,0 553 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1411,0 554 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1682,0 555 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1983,0 556 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10439,0 557 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5950,0 558 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5962,0 559 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5626,0 560 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2778,0 561 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 9006,0 562 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5634,0 563 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 8577,0 564 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6540,0 565 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4401,0 566 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4419,0 567 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10298,0 568 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10304,0 569 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10316,0 570 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10310,0 571 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4743,0 572 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4407,0 573 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4903,0 575 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4757,0 577 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4401,0 578 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4419,0 579 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4671,0 580 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4679,0 581 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4687,0 582 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4695,0 583 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4407,0 584 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4743,0 585 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10298,0 586 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10310,0 587 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10304,0 588 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10316,0 589 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10322,0 590 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 4948,0 591 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10010,0 592 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2311,0 594 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2318,0 595 1 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6082,0 600 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2588,0 601 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2582,0 602 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10467,0 603 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5168,0 604 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2576,0 605 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2594,0 606 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6018,0 607 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2600,0 608 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2642,0 609 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2488,0 610 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2482,0 611 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2494,0 612 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2476,0 613 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2506,0 614 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2500,0 615 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2470,0 616 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 8416,0 617 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2299,0 618 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5793,0 620 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5805,0 622 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5745,0 623 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5146,0 624 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5404,0 625 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6008,0 626 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5829,0 627 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6160,0 628 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 8732,0 629 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5480,0 630 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5837,0 631 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5474,0 632 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5821,0 633 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1768,0 635 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1983,0 637 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10443,0 638 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6276,0 639 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1606,0 641 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 1613,0 642 1 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 3888,0 646 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 376,0 647 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 384,0 648 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 392,0 649 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 400,0 650 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 408,0 651 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5222,0 652 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 424,0 653 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 432,0 654 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2482,0 655 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2488,0 656 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 370,0 657 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 364,0 658 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2476,0 659 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 8416,0 660 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2470,0 661 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2506,0 662 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2500,0 663 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 2494,0 664 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10266,0 665 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5950,0 666 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5962,0 667 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5090,0 668 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5114,0 669 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5122,0 670 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5130,0 671 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10194,0 672 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 10202,0 673 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 5106,0 674 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6362,0 675 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6452,0 676 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 8752,0 677 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 9233,0 678 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 9241,0 679 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 9943,0 680 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 9951,0 681 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 6276,0 685 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+GRAPHIC 3888,0 686 0 
+DESIGN @f@a@d_main
+VIEW struct.bd
+NO_GRAPHIC 688
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd	(revision 10073)
@@ -109,21 +109,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -141,25 +141,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
 )
 (vvPair
 variable "date"
-value "27.08.2010"
+value "03.01.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Mo"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Montag"
 )
 (vvPair
 variable "dd"
-value "27"
+value "03"
 )
 (vvPair
@@ -221,5 +221,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -229,17 +229,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
 )
 (vvPair
@@ -297,5 +297,5 @@
 (vvPair
 variable "time"
-value "17:10:56"
+value "16:58:24"
 )
 (vvPair
@@ -317,9 +317,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -349,5 +349,5 @@
 bg "0,0,32768"
 )
-xt "99200,4000,108900,5000"
+xt "99200,4000,108700,5000"
 st "
 by %user on %dd %month %year
@@ -688,5 +688,5 @@
 n "wiz_reset"
 t "std_logic"
-o 43
+o 44
 suid 2,0
 i "'1'"
@@ -727,5 +727,5 @@
 b "(7 DOWNTO 0)"
 posAdd 0
-o 33
+o 34
 suid 7,0
 i "(OTHERS => '0')"
@@ -799,5 +799,5 @@
 n "adc_oeb"
 t "std_logic"
-o 28
+o 29
 suid 21,0
 i "'1'"
@@ -909,5 +909,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 40
+o 41
 suid 26,0
 )
@@ -945,5 +945,5 @@
 n "wiz_cs"
 t "std_logic"
-o 41
+o 42
 suid 28,0
 i "'1'"
@@ -983,5 +983,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 46
+o 47
 suid 27,0
 )
@@ -1054,5 +1054,5 @@
 n "wiz_rd"
 t "std_logic"
-o 42
+o 43
 suid 30,0
 i "'1'"
@@ -1091,5 +1091,5 @@
 n "wiz_wr"
 t "std_logic"
-o 44
+o 45
 suid 29,0
 i "'1'"
@@ -1301,5 +1301,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 31
+o 32
 suid 48,0
 i "(others => '0')"
@@ -1337,5 +1337,5 @@
 n "drs_dwrite"
 t "std_logic"
-o 32
+o 33
 suid 49,0
 i "'1'"
@@ -1582,5 +1582,5 @@
 n "dac_cs"
 t "std_logic"
-o 29
+o 30
 suid 64,0
 )
@@ -1618,5 +1618,5 @@
 n "sclk"
 t "std_logic"
-o 37
+o 38
 suid 62,0
 )
@@ -1655,5 +1655,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 38
+o 39
 suid 65,0
 )
@@ -1693,5 +1693,5 @@
 preAdd 0
 posAdd 0
-o 45
+o 46
 suid 63,0
 )
@@ -1729,5 +1729,5 @@
 n "mosi"
 t "std_logic"
-o 34
+o 35
 suid 66,0
 i "'0'"
@@ -1768,5 +1768,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 30
+o 31
 suid 67,0
 i "'0'"
@@ -1804,5 +1804,5 @@
 n "adc_clk_en"
 t "std_logic"
-o 27
+o 28
 suid 69,0
 i "'0'"
@@ -1918,5 +1918,5 @@
 preAdd 0
 posAdd 0
-o 35
+o 36
 suid 77,0
 i "(OTHERS => '0')"
@@ -2173,5 +2173,5 @@
 preAdd 0
 posAdd 0
-o 36
+o 37
 suid 79,0
 i "'0'"
@@ -2213,5 +2213,5 @@
 preAdd 0
 posAdd 0
-o 39
+o 40
 suid 78,0
 i "'0'"
@@ -2327,4 +2327,41 @@
 )
 )
+*59 (CptPort
+uid 12314,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 12315,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "80000,139625,80750,140375"
+)
+tg (CPTG
+uid 12316,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 12317,0
+va (VaSet
+)
+xt "75300,139500,79000,140500"
+st "SRIN_out"
+ju 2
+blo "79000,140300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 27
+suid 85,0
+i "'0'"
+)
+)
+)
 ]
 shape (Rectangle
@@ -2336,5 +2373,5 @@
 lineWidth 2
 )
-xt "52000,66000,80000,140000"
+xt "52000,66000,80000,141000"
 )
 oxt "15000,-1000,43000,27000"
@@ -2344,5 +2381,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*59 (Text
+*60 (Text
 uid 172,0
 va (VaSet
@@ -2354,5 +2391,5 @@
 tm "BdLibraryNameMgr"
 )
-*60 (Text
+*61 (Text
 uid 173,0
 va (VaSet
@@ -2364,5 +2401,5 @@
 tm "CptNameMgr"
 )
-*61 (Text
+*62 (Text
 uid 174,0
 va (VaSet
@@ -2406,5 +2443,5 @@
 fg "49152,49152,49152"
 )
-xt "52250,138250,53750,139750"
+xt "52250,139250,53750,140750"
 iconName "BlockDiagram.png"
 iconMaskName "BlockDiagram.msk"
@@ -2416,5 +2453,5 @@
 archFileType "UNKNOWN"
 )
-*62 (PortIoIn
+*63 (PortIoIn
 uid 231,0
 shape (CompositeShape
@@ -2461,5 +2498,5 @@
 )
 )
-*63 (PortIoIn
+*64 (PortIoIn
 uid 251,0
 shape (CompositeShape
@@ -2506,8 +2543,8 @@
 )
 )
-*64 (HdlText
+*65 (HdlText
 uid 265,0
 optionalChildren [
-*65 (EmbeddedText
+*66 (EmbeddedText
 uid 271,0
 commentText (CommentText
@@ -2559,5 +2596,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*66 (Text
+*67 (Text
 uid 268,0
 va (VaSet
@@ -2569,5 +2606,5 @@
 tm "HdlTextNameMgr"
 )
-*67 (Text
+*68 (Text
 uid 269,0
 va (VaSet
@@ -2595,5 +2632,5 @@
 viewiconposition 0
 )
-*68 (Net
+*69 (Net
 uid 275,0
 decl (Decl
@@ -2603,5 +2640,5 @@
 preAdd 0
 posAdd 0
-o 55
+o 69
 suid 5,0
 )
@@ -2611,10 +2648,10 @@
 font "Courier New,8,0"
 )
-xt "39000,57600,67500,58400"
+xt "39000,60800,67500,61600"
 st "SIGNAL board_id        : std_logic_vector(3 downto 0)
 "
 )
 )
-*69 (Net
+*70 (Net
 uid 283,0
 decl (Decl
@@ -2622,5 +2659,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 56
+o 70
 suid 6,0
 )
@@ -2630,10 +2667,10 @@
 font "Courier New,8,0"
 )
-xt "39000,58400,67500,59200"
+xt "39000,61600,67500,62400"
 st "SIGNAL crate_id        : std_logic_vector(1 downto 0)
 "
 )
 )
-*70 (PortIoOut
+*71 (PortIoOut
 uid 472,0
 shape (CompositeShape
@@ -2679,5 +2716,5 @@
 )
 )
-*71 (PortIoOut
+*72 (PortIoOut
 uid 478,0
 shape (CompositeShape
@@ -2723,5 +2760,5 @@
 )
 )
-*72 (PortIoOut
+*73 (PortIoOut
 uid 484,0
 shape (CompositeShape
@@ -2767,5 +2804,5 @@
 )
 )
-*73 (PortIoInOut
+*74 (PortIoInOut
 uid 490,0
 shape (CompositeShape
@@ -2809,5 +2846,5 @@
 )
 )
-*74 (PortIoIn
+*75 (PortIoIn
 uid 496,0
 shape (CompositeShape
@@ -2853,5 +2890,5 @@
 )
 )
-*75 (PortIoOut
+*76 (PortIoOut
 uid 502,0
 shape (CompositeShape
@@ -2897,5 +2934,5 @@
 )
 )
-*76 (PortIoOut
+*77 (PortIoOut
 uid 508,0
 shape (CompositeShape
@@ -2941,10 +2978,10 @@
 )
 )
-*77 (Net
+*78 (Net
 uid 1465,0
 decl (Decl
 n "adc_data_array"
 t "adc_data_array_type"
-o 54
+o 68
 suid 29,0
 )
@@ -2954,15 +2991,15 @@
 font "Courier New,8,0"
 )
-xt "39000,56800,63000,57600"
+xt "39000,60000,63000,60800"
 st "SIGNAL adc_data_array  : adc_data_array_type
 "
 )
 )
-*78 (Net
+*79 (Net
 uid 2407,0
 decl (Decl
 n "RSRLOAD"
 t "std_logic"
-o 35
+o 37
 suid 57,0
 i "'0'"
@@ -2973,10 +3010,10 @@
 font "Courier New,8,0"
 )
-xt "39000,31000,68500,31800"
+xt "39000,34200,68500,35000"
 st "RSRLOAD         : std_logic                      := '0'
 "
 )
 )
-*79 (PortIoOut
+*80 (PortIoOut
 uid 2415,0
 shape (CompositeShape
@@ -3023,10 +3060,10 @@
 )
 )
-*80 (Net
+*81 (Net
 uid 2421,0
 decl (Decl
 n "SRCLK"
 t "std_logic"
-o 52
+o 66
 suid 58,0
 i "'0'"
@@ -3037,10 +3074,10 @@
 font "Courier New,8,0"
 )
-xt "39000,55200,72000,56000"
+xt "39000,58400,72000,59200"
 st "SIGNAL SRCLK           : std_logic                      := '0'
 "
 )
 )
-*81 (Net
+*82 (Net
 uid 3019,0
 decl (Decl
@@ -3048,5 +3085,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 59
+o 74
 suid 65,0
 )
@@ -3056,15 +3093,15 @@
 font "Courier New,8,0"
 )
-xt "39000,61600,67500,62400"
+xt "39000,64800,67500,65600"
 st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)
 "
 )
 )
-*82 (Net
+*83 (Net
 uid 3025,0
 decl (Decl
 n "DAC_CS"
 t "std_logic"
-o 21
+o 22
 suid 66,0
 )
@@ -3074,10 +3111,10 @@
 font "Courier New,8,0"
 )
-xt "39000,19800,54000,20600"
+xt "39000,22200,54000,23000"
 st "DAC_CS          : std_logic
 "
 )
 )
-*83 (PortIoOut
+*84 (PortIoOut
 uid 3153,0
 shape (CompositeShape
@@ -3124,5 +3161,5 @@
 )
 )
-*84 (Net
+*85 (Net
 uid 3216,0
 decl (Decl
@@ -3139,10 +3176,10 @@
 font "Courier New,8,0"
 )
-xt "39000,13400,54000,14200"
+xt "39000,15800,54000,16600"
 st "X_50M           : STD_LOGIC
 "
 )
 )
-*85 (Net
+*86 (Net
 uid 3226,0
 decl (Decl
@@ -3157,13 +3194,13 @@
 font "Courier New,8,0"
 )
-xt "39000,11800,54000,12600"
+xt "39000,14200,54000,15000"
 st "TRG             : STD_LOGIC
 "
 )
 )
-*86 (HdlText
+*87 (HdlText
 uid 3248,0
 optionalChildren [
-*87 (EmbeddedText
+*88 (EmbeddedText
 uid 3254,0
 commentText (CommentText
@@ -3217,5 +3254,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*88 (Text
+*89 (Text
 uid 3251,0
 va (VaSet
@@ -3227,5 +3264,5 @@
 tm "HdlTextNameMgr"
 )
-*89 (Text
+*90 (Text
 uid 3252,0
 va (VaSet
@@ -3253,5 +3290,5 @@
 viewiconposition 0
 )
-*90 (Net
+*91 (Net
 uid 3266,0
 decl (Decl
@@ -3259,5 +3296,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 16
+o 17
 suid 71,0
 )
@@ -3267,15 +3304,15 @@
 font "Courier New,8,0"
 )
-xt "39000,15800,64000,16600"
+xt "39000,18200,64000,19000"
 st "A_CLK           : std_logic_vector(3 downto 0)
 "
 )
 )
-*91 (Net
+*92 (Net
 uid 3268,0
 decl (Decl
 n "CLK_25_PS"
 t "std_logic"
-o 50
+o 55
 suid 72,0
 )
@@ -3285,10 +3322,10 @@
 font "Courier New,8,0"
 )
-xt "39000,46400,57500,47200"
+xt "39000,49600,57500,50400"
 st "SIGNAL CLK_25_PS       : std_logic
 "
 )
 )
-*92 (PortIoOut
+*93 (PortIoOut
 uid 3284,0
 shape (CompositeShape
@@ -3335,5 +3372,5 @@
 )
 )
-*93 (Net
+*94 (Net
 uid 3290,0
 decl (Decl
@@ -3342,5 +3379,5 @@
 preAdd 0
 posAdd 0
-o 30
+o 31
 suid 73,0
 )
@@ -3350,10 +3387,10 @@
 font "Courier New,8,0"
 )
-xt "39000,27000,54000,27800"
+xt "39000,29400,54000,30200"
 st "OE_ADC          : STD_LOGIC
 "
 )
 )
-*94 (PortIoIn
+*95 (PortIoIn
 uid 3292,0
 shape (CompositeShape
@@ -3400,5 +3437,5 @@
 )
 )
-*95 (Net
+*96 (Net
 uid 3298,0
 decl (Decl
@@ -3419,8 +3456,8 @@
 )
 )
-*96 (HdlText
+*97 (HdlText
 uid 3300,0
 optionalChildren [
-*97 (EmbeddedText
+*98 (EmbeddedText
 uid 3306,0
 commentText (CommentText
@@ -3474,5 +3511,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*98 (Text
+*99 (Text
 uid 3303,0
 va (VaSet
@@ -3484,5 +3521,5 @@
 tm "HdlTextNameMgr"
 )
-*99 (Text
+*100 (Text
 uid 3304,0
 va (VaSet
@@ -3510,5 +3547,5 @@
 viewiconposition 0
 )
-*100 (PortIoIn
+*101 (PortIoIn
 uid 3310,0
 shape (CompositeShape
@@ -3555,5 +3592,5 @@
 )
 )
-*101 (PortIoIn
+*102 (PortIoIn
 uid 3332,0
 shape (CompositeShape
@@ -3600,5 +3637,5 @@
 )
 )
-*102 (PortIoIn
+*103 (PortIoIn
 uid 3338,0
 shape (CompositeShape
@@ -3645,5 +3682,5 @@
 )
 )
-*103 (PortIoIn
+*104 (PortIoIn
 uid 3344,0
 shape (CompositeShape
@@ -3690,5 +3727,5 @@
 )
 )
-*104 (Net
+*105 (Net
 uid 3374,0
 decl (Decl
@@ -3709,5 +3746,5 @@
 )
 )
-*105 (Net
+*106 (Net
 uid 3376,0
 decl (Decl
@@ -3728,5 +3765,5 @@
 )
 )
-*106 (Net
+*107 (Net
 uid 3378,0
 decl (Decl
@@ -3747,5 +3784,5 @@
 )
 )
-*107 (Net
+*108 (Net
 uid 3380,0
 decl (Decl
@@ -3766,8 +3803,8 @@
 )
 )
-*108 (HdlText
+*109 (HdlText
 uid 3394,0
 optionalChildren [
-*109 (EmbeddedText
+*110 (EmbeddedText
 uid 3400,0
 commentText (CommentText
@@ -3821,5 +3858,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*110 (Text
+*111 (Text
 uid 3397,0
 va (VaSet
@@ -3831,5 +3868,5 @@
 tm "HdlTextNameMgr"
 )
-*111 (Text
+*112 (Text
 uid 3398,0
 va (VaSet
@@ -3857,10 +3894,10 @@
 viewiconposition 0
 )
-*112 (Net
+*113 (Net
 uid 3460,0
 decl (Decl
 n "D0_SRCLK"
 t "STD_LOGIC"
-o 17
+o 18
 suid 87,0
 )
@@ -3870,15 +3907,15 @@
 font "Courier New,8,0"
 )
-xt "39000,16600,54000,17400"
+xt "39000,19000,54000,19800"
 st "D0_SRCLK        : STD_LOGIC
 "
 )
 )
-*113 (Net
+*114 (Net
 uid 3462,0
 decl (Decl
 n "D1_SRCLK"
 t "STD_LOGIC"
-o 18
+o 19
 suid 88,0
 )
@@ -3888,15 +3925,15 @@
 font "Courier New,8,0"
 )
-xt "39000,17400,54000,18200"
+xt "39000,19800,54000,20600"
 st "D1_SRCLK        : STD_LOGIC
 "
 )
 )
-*114 (Net
+*115 (Net
 uid 3464,0
 decl (Decl
 n "D2_SRCLK"
 t "STD_LOGIC"
-o 19
+o 20
 suid 89,0
 )
@@ -3906,15 +3943,15 @@
 font "Courier New,8,0"
 )
-xt "39000,18200,54000,19000"
+xt "39000,20600,54000,21400"
 st "D2_SRCLK        : STD_LOGIC
 "
 )
 )
-*115 (Net
+*116 (Net
 uid 3466,0
 decl (Decl
 n "D3_SRCLK"
 t "STD_LOGIC"
-o 20
+o 21
 suid 90,0
 )
@@ -3924,10 +3961,10 @@
 font "Courier New,8,0"
 )
-xt "39000,19000,54000,19800"
+xt "39000,21400,54000,22200"
 st "D3_SRCLK        : STD_LOGIC
 "
 )
 )
-*116 (PortIoIn
+*117 (PortIoIn
 uid 3476,0
 shape (CompositeShape
@@ -3974,5 +4011,5 @@
 )
 )
-*117 (PortIoIn
+*118 (PortIoIn
 uid 3482,0
 shape (CompositeShape
@@ -4019,5 +4056,5 @@
 )
 )
-*118 (PortIoIn
+*119 (PortIoIn
 uid 3488,0
 shape (CompositeShape
@@ -4064,5 +4101,5 @@
 )
 )
-*119 (PortIoIn
+*120 (PortIoIn
 uid 3494,0
 shape (CompositeShape
@@ -4109,5 +4146,5 @@
 )
 )
-*120 (Net
+*121 (Net
 uid 3500,0
 decl (Decl
@@ -4127,5 +4164,5 @@
 )
 )
-*121 (Net
+*122 (Net
 uid 3502,0
 decl (Decl
@@ -4145,5 +4182,5 @@
 )
 )
-*122 (Net
+*123 (Net
 uid 3504,0
 decl (Decl
@@ -4163,5 +4200,5 @@
 )
 )
-*123 (Net
+*124 (Net
 uid 3506,0
 decl (Decl
@@ -4181,5 +4218,5 @@
 )
 )
-*124 (PortIoOut
+*125 (PortIoOut
 uid 3508,0
 shape (CompositeShape
@@ -4226,5 +4263,5 @@
 )
 )
-*125 (Net
+*126 (Net
 uid 3514,0
 decl (Decl
@@ -4232,5 +4269,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 24
+o 25
 suid 95,0
 i "(others => '0')"
@@ -4241,10 +4278,10 @@
 font "Courier New,8,0"
 )
-xt "39000,22200,74500,23000"
+xt "39000,24600,74500,25400"
 st "D_A             : std_logic_vector(3 DOWNTO 0)   := (others => '0')
 "
 )
 )
-*126 (PortIoOut
+*127 (PortIoOut
 uid 3516,0
 shape (CompositeShape
@@ -4291,10 +4328,10 @@
 )
 )
-*127 (Net
+*128 (Net
 uid 3522,0
 decl (Decl
 n "DWRITE"
 t "std_logic"
-o 23
+o 24
 suid 96,0
 i "'0'"
@@ -4305,10 +4342,10 @@
 font "Courier New,8,0"
 )
-xt "39000,21400,68500,22200"
+xt "39000,23800,68500,24600"
 st "DWRITE          : std_logic                      := '0'
 "
 )
 )
-*128 (PortIoOut
+*129 (PortIoOut
 uid 3536,0
 shape (CompositeShape
@@ -4354,8 +4391,8 @@
 )
 )
-*129 (HdlText
+*130 (HdlText
 uid 3542,0
 optionalChildren [
-*130 (EmbeddedText
+*131 (EmbeddedText
 uid 3612,0
 commentText (CommentText
@@ -4409,5 +4446,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*131 (Text
+*132 (Text
 uid 3545,0
 va (VaSet
@@ -4419,5 +4456,5 @@
 tm "HdlTextNameMgr"
 )
-*132 (Text
+*133 (Text
 uid 3546,0
 va (VaSet
@@ -4445,5 +4482,5 @@
 viewiconposition 0
 )
-*133 (PortIoOut
+*134 (PortIoOut
 uid 3548,0
 shape (CompositeShape
@@ -4489,5 +4526,5 @@
 )
 )
-*134 (PortIoOut
+*135 (PortIoOut
 uid 3554,0
 shape (CompositeShape
@@ -4533,5 +4570,5 @@
 )
 )
-*135 (PortIoOut
+*136 (PortIoOut
 uid 3560,0
 shape (CompositeShape
@@ -4577,5 +4614,5 @@
 )
 )
-*136 (PortIoOut
+*137 (PortIoOut
 uid 3566,0
 shape (CompositeShape
@@ -4621,10 +4658,10 @@
 )
 )
-*137 (Net
+*138 (Net
 uid 3604,0
 decl (Decl
 n "T0_CS"
 t "std_logic"
-o 38
+o 40
 suid 101,0
 )
@@ -4634,15 +4671,15 @@
 font "Courier New,8,0"
 )
-xt "39000,33400,54000,34200"
+xt "39000,36600,54000,37400"
 st "T0_CS           : std_logic
 "
 )
 )
-*138 (Net
+*139 (Net
 uid 3606,0
 decl (Decl
 n "T1_CS"
 t "std_logic"
-o 39
+o 41
 suid 102,0
 )
@@ -4652,15 +4689,15 @@
 font "Courier New,8,0"
 )
-xt "39000,34200,54000,35000"
+xt "39000,37400,54000,38200"
 st "T1_CS           : std_logic
 "
 )
 )
-*139 (Net
+*140 (Net
 uid 3608,0
 decl (Decl
 n "T2_CS"
 t "std_logic"
-o 40
+o 42
 suid 103,0
 )
@@ -4670,15 +4707,15 @@
 font "Courier New,8,0"
 )
-xt "39000,35000,54000,35800"
+xt "39000,38200,54000,39000"
 st "T2_CS           : std_logic
 "
 )
 )
-*140 (Net
+*141 (Net
 uid 3610,0
 decl (Decl
 n "T3_CS"
 t "std_logic"
-o 41
+o 43
 suid 104,0
 )
@@ -4688,10 +4725,10 @@
 font "Courier New,8,0"
 )
-xt "39000,35800,54000,36600"
+xt "39000,39000,54000,39800"
 st "T3_CS           : std_logic
 "
 )
 )
-*141 (PortIoOut
+*142 (PortIoOut
 uid 3624,0
 shape (CompositeShape
@@ -4737,10 +4774,10 @@
 )
 )
-*142 (Net
+*143 (Net
 uid 3630,0
 decl (Decl
 n "S_CLK"
 t "std_logic"
-o 37
+o 39
 suid 105,0
 )
@@ -4750,10 +4787,10 @@
 font "Courier New,8,0"
 )
-xt "39000,32600,54000,33400"
+xt "39000,35800,54000,36600"
 st "S_CLK           : std_logic
 "
 )
 )
-*143 (Net
+*144 (Net
 uid 3632,0
 decl (Decl
@@ -4761,5 +4798,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 43
+o 45
 suid 106,0
 )
@@ -4769,10 +4806,10 @@
 font "Courier New,8,0"
 )
-xt "39000,37400,64000,38200"
+xt "39000,40600,64000,41400"
 st "W_A             : std_logic_vector(9 DOWNTO 0)
 "
 )
 )
-*144 (Net
+*145 (Net
 uid 3634,0
 decl (Decl
@@ -4780,5 +4817,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 49
+o 51
 suid 107,0
 )
@@ -4788,15 +4825,15 @@
 font "Courier New,8,0"
 )
-xt "39000,42200,64500,43000"
+xt "39000,45400,64500,46200"
 st "W_D             : std_logic_vector(15 DOWNTO 0)
 "
 )
 )
-*145 (Net
+*146 (Net
 uid 3636,0
 decl (Decl
 n "W_RES"
 t "std_logic"
-o 46
+o 48
 suid 108,0
 i "'1'"
@@ -4807,15 +4844,15 @@
 font "Courier New,8,0"
 )
-xt "39000,39800,68500,40600"
+xt "39000,43000,68500,43800"
 st "W_RES           : std_logic                      := '1'
 "
 )
 )
-*146 (Net
+*147 (Net
 uid 3638,0
 decl (Decl
 n "W_RD"
 t "std_logic"
-o 45
+o 47
 suid 109,0
 i "'1'"
@@ -4826,15 +4863,15 @@
 font "Courier New,8,0"
 )
-xt "39000,39000,68500,39800"
+xt "39000,42200,68500,43000"
 st "W_RD            : std_logic                      := '1'
 "
 )
 )
-*147 (Net
+*148 (Net
 uid 3640,0
 decl (Decl
 n "W_WR"
 t "std_logic"
-o 47
+o 49
 suid 110,0
 i "'1'"
@@ -4845,10 +4882,10 @@
 font "Courier New,8,0"
 )
-xt "39000,40600,68500,41400"
+xt "39000,43800,68500,44600"
 st "W_WR            : std_logic                      := '1'
 "
 )
 )
-*148 (Net
+*149 (Net
 uid 3642,0
 decl (Decl
@@ -4863,15 +4900,15 @@
 font "Courier New,8,0"
 )
-xt "39000,12600,54000,13400"
+xt "39000,15000,54000,15800"
 st "W_INT           : std_logic
 "
 )
 )
-*149 (Net
+*150 (Net
 uid 3644,0
 decl (Decl
 n "W_CS"
 t "std_logic"
-o 44
+o 46
 suid 112,0
 i "'1'"
@@ -4882,10 +4919,10 @@
 font "Courier New,8,0"
 )
-xt "39000,38200,68500,39000"
+xt "39000,41400,68500,42200"
 st "W_CS            : std_logic                      := '1'
 "
 )
 )
-*150 (PortIoInOut
+*151 (PortIoInOut
 uid 3674,0
 shape (CompositeShape
@@ -4929,10 +4966,10 @@
 )
 )
-*151 (Net
+*152 (Net
 uid 3680,0
 decl (Decl
 n "MOSI"
 t "std_logic"
-o 29
+o 30
 suid 113,0
 i "'0'"
@@ -4943,10 +4980,10 @@
 font "Courier New,8,0"
 )
-xt "39000,26200,68500,27000"
+xt "39000,28600,68500,29400"
 st "MOSI            : std_logic                      := '0'
 "
 )
 )
-*152 (PortIoOut
+*153 (PortIoOut
 uid 3688,0
 shape (CompositeShape
@@ -4992,5 +5029,5 @@
 )
 )
-*153 (Net
+*154 (Net
 uid 3694,0
 decl (Decl
@@ -4999,5 +5036,5 @@
 preAdd 0
 posAdd 0
-o 48
+o 50
 suid 114,0
 )
@@ -5007,13 +5044,13 @@
 font "Courier New,8,0"
 )
-xt "39000,41400,54000,42200"
+xt "39000,44600,54000,45400"
 st "MISO            : std_logic
 "
 )
 )
-*154 (HdlText
+*155 (HdlText
 uid 3700,0
 optionalChildren [
-*155 (EmbeddedText
+*156 (EmbeddedText
 uid 3706,0
 commentText (CommentText
@@ -5028,5 +5065,5 @@
 lineWidth 2
 )
-xt "82000,102000,100000,118000"
+xt "82000,106000,99000,118000"
 )
 oxt "0,0,18000,5000"
@@ -5035,17 +5072,20 @@
 va (VaSet
 )
-xt "82200,102200,98600,118200"
+xt "82200,106200,98600,118200"
 st "
 -- MISC 6     
 TRG_V <= '0';
-RS485_C_RE <= '1'; 
+RS485_C_RE <= '0'; 
 RS485_C_DE <= '0';   
-RS485_E_RE <= '1';      
+RS485_C_DO <= RS485_C_DI;
+
+RS485_E_RE <= '0';      
 RS485_E_DE <= '0'; 
+--RS485_E_DO <= RS485_E_DI;
 
 -- DENABLE <= '0'; -- domino wave stopped
 -- DENABLE <= '1'; -- domino wave running
 
-SRIN <= '1';
+
 EE_CS <= '1';
 -- LEDs are low active
@@ -5060,6 +5100,6 @@
 tm "HdlTextMgr"
 wrapOption 3
-visibleHeight 16000
-visibleWidth 18000
+visibleHeight 12000
+visibleWidth 17000
 )
 )
@@ -5082,5 +5122,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*156 (Text
+*157 (Text
 uid 3703,0
 va (VaSet
@@ -5092,5 +5132,5 @@
 tm "HdlTextNameMgr"
 )
-*157 (Text
+*158 (Text
 uid 3704,0
 va (VaSet
@@ -5118,5 +5158,5 @@
 viewiconposition 0
 )
-*158 (PortIoOut
+*159 (PortIoOut
 uid 3710,0
 shape (CompositeShape
@@ -5162,5 +5202,5 @@
 )
 )
-*159 (PortIoOut
+*160 (PortIoOut
 uid 3716,0
 shape (CompositeShape
@@ -5206,5 +5246,5 @@
 )
 )
-*160 (PortIoOut
+*161 (PortIoOut
 uid 3722,0
 shape (CompositeShape
@@ -5250,5 +5290,5 @@
 )
 )
-*161 (PortIoOut
+*162 (PortIoOut
 uid 3728,0
 shape (CompositeShape
@@ -5294,5 +5334,5 @@
 )
 )
-*162 (PortIoOut
+*163 (PortIoOut
 uid 3734,0
 shape (CompositeShape
@@ -5338,5 +5378,5 @@
 )
 )
-*163 (PortIoOut
+*164 (PortIoOut
 uid 3740,0
 shape (CompositeShape
@@ -5378,48 +5418,4 @@
 st "DENABLE"
 blo "114000,121300"
-tm "WireNameMgr"
-)
-)
-)
-*164 (PortIoOut
-uid 3746,0
-shape (CompositeShape
-uid 3747,0
-va (VaSet
-vasetType 1
-fg "0,0,32768"
-)
-optionalChildren [
-(Pentagon
-uid 3748,0
-sl 0
-ro 270
-xt "111500,108625,113000,109375"
-)
-(Line
-uid 3749,0
-sl 0
-ro 270
-xt "111000,109000,111500,109000"
-pts [
-"111000,109000"
-"111500,109000"
-]
-)
-]
-)
-stc 0
-sf 1
-tg (WTG
-uid 3750,0
-ps "PortIoTextPlaceStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 3751,0
-va (VaSet
-)
-xt "114000,108500,116300,109500"
-st "SRIN"
-blo "114000,109300"
 tm "WireNameMgr"
 )
@@ -5519,5 +5515,5 @@
 n "TRG_V"
 t "std_logic"
-o 42
+o 44
 suid 126,0
 )
@@ -5527,5 +5523,5 @@
 font "Courier New,8,0"
 )
-xt "39000,36600,54000,37400"
+xt "39000,39800,54000,40600"
 st "TRG_V           : std_logic
 "
@@ -5537,5 +5533,5 @@
 n "RS485_C_RE"
 t "std_logic"
-o 32
+o 34
 suid 127,0
 )
@@ -5545,5 +5541,5 @@
 font "Courier New,8,0"
 )
-xt "39000,28600,54000,29400"
+xt "39000,31800,54000,32600"
 st "RS485_C_RE      : std_logic
 "
@@ -5555,5 +5551,5 @@
 n "RS485_C_DE"
 t "std_logic"
-o 31
+o 32
 suid 128,0
 )
@@ -5563,5 +5559,5 @@
 font "Courier New,8,0"
 )
-xt "39000,27800,54000,28600"
+xt "39000,30200,54000,31000"
 st "RS485_C_DE      : std_logic
 "
@@ -5573,5 +5569,5 @@
 n "RS485_E_RE"
 t "std_logic"
-o 34
+o 36
 suid 129,0
 )
@@ -5581,5 +5577,5 @@
 font "Courier New,8,0"
 )
-xt "39000,30200,54000,31000"
+xt "39000,33400,54000,34200"
 st "RS485_E_RE      : std_logic
 "
@@ -5591,5 +5587,5 @@
 n "RS485_E_DE"
 t "std_logic"
-o 33
+o 35
 suid 130,0
 )
@@ -5599,5 +5595,5 @@
 font "Courier New,8,0"
 )
-xt "39000,29400,54000,30200"
+xt "39000,32600,54000,33400"
 st "RS485_E_DE      : std_logic
 "
@@ -5609,5 +5605,5 @@
 n "DENABLE"
 t "std_logic"
-o 22
+o 23
 suid 131,0
 i "'0'"
@@ -5618,5 +5614,5 @@
 font "Courier New,8,0"
 )
-xt "39000,20600,68500,21400"
+xt "39000,23000,68500,23800"
 st "DENABLE         : std_logic                      := '0'
 "
@@ -5624,27 +5620,9 @@
 )
 *173 (Net
-uid 3876,0
-decl (Decl
-n "SRIN"
-t "std_logic"
-o 36
-suid 132,0
-)
-declText (MLText
-uid 3877,0
-va (VaSet
-font "Courier New,8,0"
-)
-xt "39000,31800,54000,32600"
-st "SRIN            : std_logic
-"
-)
-)
-*174 (Net
 uid 3878,0
 decl (Decl
 n "EE_CS"
 t "std_logic"
-o 27
+o 28
 suid 133,0
 )
@@ -5654,10 +5632,10 @@
 font "Courier New,8,0"
 )
-xt "39000,24600,54000,25400"
+xt "39000,27000,54000,27800"
 st "EE_CS           : std_logic
 "
 )
 )
-*175 (Net
+*174 (Net
 uid 3880,0
 decl (Decl
@@ -5665,5 +5643,5 @@
 t "std_logic_vector"
 b "( 2 DOWNTO 0 )"
-o 28
+o 29
 suid 134,0
 i "(others => '1')"
@@ -5674,10 +5652,10 @@
 font "Courier New,8,0"
 )
-xt "39000,25400,74500,26200"
+xt "39000,27800,74500,28600"
 st "LED             : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')
 "
 )
 )
-*176 (PortIoOut
+*175 (PortIoOut
 uid 3995,0
 shape (CompositeShape
@@ -5724,5 +5702,5 @@
 )
 )
-*177 (PortIoOut
+*176 (PortIoOut
 uid 4001,0
 shape (CompositeShape
@@ -5769,5 +5747,5 @@
 )
 )
-*178 (PortIoOut
+*177 (PortIoOut
 uid 4007,0
 shape (CompositeShape
@@ -5814,5 +5792,5 @@
 )
 )
-*179 (PortIoOut
+*178 (PortIoOut
 uid 4013,0
 shape (CompositeShape
@@ -5859,5 +5837,5 @@
 )
 )
-*180 (PortIoOut
+*179 (PortIoOut
 uid 4916,0
 shape (CompositeShape
@@ -5903,5 +5881,5 @@
 )
 )
-*181 (Net
+*180 (Net
 uid 5320,0
 decl (Decl
@@ -5909,5 +5887,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 25
+o 26
 suid 141,0
 i "(OTHERS => '0')"
@@ -5918,10 +5896,10 @@
 font "Courier New,8,0"
 )
-xt "39000,23000,74500,23800"
+xt "39000,25400,74500,26200"
 st "D_T             : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
 "
 )
 )
-*182 (PortIoIn
+*181 (PortIoIn
 uid 6781,0
 shape (CompositeShape
@@ -5968,5 +5946,5 @@
 )
 )
-*183 (Net
+*182 (Net
 uid 6793,0
 decl (Decl
@@ -5987,5 +5965,5 @@
 )
 )
-*184 (PortIoOut
+*183 (PortIoOut
 uid 6874,0
 shape (CompositeShape
@@ -6031,5 +6009,5 @@
 )
 )
-*185 (Net
+*184 (Net
 uid 6886,0
 decl (Decl
@@ -6037,5 +6015,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 26
+o 27
 suid 154,0
 i "(others => '0')"
@@ -6046,13 +6024,13 @@
 font "Courier New,8,0"
 )
-xt "39000,23800,74500,24600"
+xt "39000,26200,74500,27000"
 st "D_T2            : std_logic_vector(3 DOWNTO 0)   := (others => '0')
 "
 )
 )
-*186 (HdlText
+*185 (HdlText
 uid 6888,0
 optionalChildren [
-*187 (EmbeddedText
+*186 (EmbeddedText
 uid 6894,0
 commentText (CommentText
@@ -6102,5 +6080,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*188 (Text
+*187 (Text
 uid 6891,0
 va (VaSet
@@ -6112,5 +6090,5 @@
 tm "HdlTextNameMgr"
 )
-*189 (Text
+*188 (Text
 uid 6892,0
 va (VaSet
@@ -6138,8 +6116,8 @@
 viewiconposition 0
 )
-*190 (HdlText
+*189 (HdlText
 uid 7092,0
 optionalChildren [
-*191 (EmbeddedText
+*190 (EmbeddedText
 uid 7098,0
 commentText (CommentText
@@ -6191,5 +6169,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*192 (Text
+*191 (Text
 uid 7095,0
 va (VaSet
@@ -6201,5 +6179,5 @@
 tm "HdlTextNameMgr"
 )
-*193 (Text
+*192 (Text
 uid 7096,0
 va (VaSet
@@ -6227,5 +6205,5 @@
 viewiconposition 0
 )
-*194 (PortIoOut
+*193 (PortIoOut
 uid 7138,0
 shape (CompositeShape
@@ -6271,5 +6249,5 @@
 )
 )
-*195 (Net
+*194 (Net
 uid 7150,0
 decl (Decl
@@ -6277,5 +6255,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 15
+o 16
 suid 155,0
 i "(OTHERS => '0')"
@@ -6286,15 +6264,15 @@
 font "Courier New,8,0"
 )
-xt "39000,15000,74500,15800"
+xt "39000,17400,74500,18200"
 st "A1_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
 "
 )
 )
-*196 (Net
+*195 (Net
 uid 7485,0
 decl (Decl
 n "dummy"
 t "std_logic"
-o 58
+o 72
 suid 157,0
 )
@@ -6304,16 +6282,16 @@
 font "Courier New,8,0"
 )
-xt "39000,60000,57500,60800"
+xt "39000,63200,57500,64000"
 st "SIGNAL dummy           : std_logic
 "
 )
 )
-*197 (MWC
+*196 (MWC
 uid 7652,0
 optionalChildren [
-*198 (CptPort
+*197 (CptPort
 uid 7632,0
 optionalChildren [
-*199 (Line
+*198 (Line
 uid 7636,0
 layer 5
@@ -6369,13 +6347,13 @@
 n "s"
 t "std_logic"
-o 58
+o 72
 suid 1,0
 )
 )
 )
-*200 (CptPort
+*199 (CptPort
 uid 7637,0
 optionalChildren [
-*201 (Line
+*200 (Line
 uid 7641,0
 layer 5
@@ -6434,10 +6412,10 @@
 n "t"
 t "std_logic"
-o 21
+o 22
 suid 2,0
 )
 )
 )
-*202 (CommentGraphic
+*201 (CommentGraphic
 uid 7642,0
 shape (PolyLine2D
@@ -6460,5 +6438,5 @@
 oxt "6000,6000,7000,7000"
 )
-*203 (CommentGraphic
+*202 (CommentGraphic
 uid 7644,0
 shape (PolyLine2D
@@ -6481,5 +6459,5 @@
 oxt "6000,7000,7000,8000"
 )
-*204 (CommentGraphic
+*203 (CommentGraphic
 uid 7646,0
 shape (PolyLine2D
@@ -6502,5 +6480,5 @@
 oxt "6988,7329,7988,7329"
 )
-*205 (CommentGraphic
+*204 (CommentGraphic
 uid 7648,0
 shape (PolyLine2D
@@ -6521,5 +6499,5 @@
 oxt "8000,7000,9000,7000"
 )
-*206 (CommentGraphic
+*205 (CommentGraphic
 uid 7650,0
 shape (PolyLine2D
@@ -6562,5 +6540,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*207 (Text
+*206 (Text
 uid 7655,0
 va (VaSet
@@ -6572,5 +6550,5 @@
 blo "90350,83900"
 )
-*208 (Text
+*207 (Text
 uid 7656,0
 va (VaSet
@@ -6581,5 +6559,5 @@
 blo "90350,84900"
 )
-*209 (Text
+*208 (Text
 uid 7657,0
 va (VaSet
@@ -6626,5 +6604,5 @@
 )
 )
-*210 (Net
+*209 (Net
 uid 8851,0
 decl (Decl
@@ -6632,5 +6610,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 57
+o 71
 suid 159,0
 i "(others => '0')"
@@ -6641,15 +6619,15 @@
 font "Courier New,8,0"
 )
-xt "39000,59200,78000,60000"
+xt "39000,62400,78000,63200"
 st "SIGNAL drs_channel_id  : std_logic_vector(3 downto 0)   := (others => '0')
 "
 )
 )
-*211 (Net
+*210 (Net
 uid 9500,0
 decl (Decl
 n "CLK_50"
 t "std_logic"
-o 51
+o 57
 suid 163,0
 )
@@ -6659,16 +6637,16 @@
 font "Courier New,8,0"
 )
-xt "39000,48000,57500,48800"
+xt "39000,51200,57500,52000"
 st "SIGNAL CLK_50          : std_logic
 "
 )
 )
-*212 (MWC
+*211 (MWC
 uid 10023,0
 optionalChildren [
-*213 (CptPort
+*212 (CptPort
 uid 9995,0
 optionalChildren [
-*214 (Line
+*213 (Line
 uid 9999,0
 layer 5
@@ -6683,5 +6661,5 @@
 ]
 )
-*215 (Property
+*214 (Property
 uid 10000,0
 pclass "_MW_GEOM_"
@@ -6722,13 +6700,13 @@
 n "dout"
 t "std_logic"
-o 50
+o 55
 suid 1,0
 )
 )
 )
-*216 (CptPort
+*215 (CptPort
 uid 10001,0
 optionalChildren [
-*217 (Line
+*216 (Line
 uid 10005,0
 layer 5
@@ -6776,5 +6754,5 @@
 n "din0"
 t "std_logic"
-o 59
+o 67
 suid 2,0
 i "'0'"
@@ -6782,8 +6760,8 @@
 )
 )
-*218 (CptPort
+*217 (CptPort
 uid 10006,0
 optionalChildren [
-*219 (Line
+*218 (Line
 uid 10010,0
 layer 5
@@ -6831,13 +6809,13 @@
 n "din1"
 t "std_logic"
-o 58
+o 56
 suid 3,0
 )
 )
 )
-*220 (CommentGraphic
+*219 (CommentGraphic
 uid 10011,0
 optionalChildren [
-*221 (Property
+*220 (Property
 uid 10013,0
 pclass "_MW_GEOM_"
@@ -6863,8 +6841,8 @@
 oxt "11000,6000,11000,6000"
 )
-*222 (CommentGraphic
+*221 (CommentGraphic
 uid 10014,0
 optionalChildren [
-*223 (Property
+*222 (Property
 uid 10016,0
 pclass "_MW_GEOM_"
@@ -6890,8 +6868,8 @@
 oxt "11000,10000,11000,10000"
 )
-*224 (Grouping
+*223 (Grouping
 uid 10017,0
 optionalChildren [
-*225 (CommentGraphic
+*224 (CommentGraphic
 uid 10019,0
 shape (PolyLine2D
@@ -6914,5 +6892,5 @@
 oxt "9000,6000,11000,10000"
 )
-*226 (CommentGraphic
+*225 (CommentGraphic
 uid 10021,0
 shape (Arc2D
@@ -6967,5 +6945,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*227 (Text
+*226 (Text
 uid 10026,0
 va (VaSet
@@ -6977,5 +6955,5 @@
 blo "44500,73300"
 )
-*228 (Text
+*227 (Text
 uid 10027,0
 va (VaSet
@@ -6986,5 +6964,5 @@
 blo "44500,74300"
 )
-*229 (Text
+*228 (Text
 uid 10028,0
 va (VaSet
@@ -7031,10 +7009,10 @@
 )
 )
-*230 (Net
+*229 (Net
 uid 10032,0
 decl (Decl
 n "CLK_25_PS1"
 t "std_logic"
-o 58
+o 56
 suid 164,0
 )
@@ -7044,15 +7022,15 @@
 font "Courier New,8,0"
 )
-xt "39000,47200,57500,48000"
+xt "39000,50400,57500,51200"
 st "SIGNAL CLK_25_PS1      : std_logic
 "
 )
 )
-*231 (Net
+*230 (Net
 uid 10050,0
 decl (Decl
 n "adc_clk_en"
 t "std_logic"
-o 59
+o 67
 suid 165,0
 i "'0'"
@@ -7063,10 +7041,10 @@
 font "Courier New,8,0"
 )
-xt "39000,56000,72000,56800"
+xt "39000,59200,72000,60000"
 st "SIGNAL adc_clk_en      : std_logic                      := '0'
 "
 )
 )
-*232 (PortIoOut
+*231 (PortIoOut
 uid 10296,0
 shape (CompositeShape
@@ -7112,5 +7090,5 @@
 )
 )
-*233 (Net
+*232 (Net
 uid 10308,0
 decl (Decl
@@ -7118,5 +7096,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 60
+o 15
 suid 166,0
 i "(others => '0')"
@@ -7127,13 +7105,13 @@
 font "Courier New,8,0"
 )
-xt "39000,14200,74500,15000"
+xt "39000,16600,74500,17400"
 st "A0_T            : std_logic_vector(7 DOWNTO 0)   := (others => '0')
 "
 )
 )
-*234 (HdlText
+*233 (HdlText
 uid 10310,0
 optionalChildren [
-*235 (EmbeddedText
+*234 (EmbeddedText
 uid 10316,0
 commentText (CommentText
@@ -7201,5 +7179,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*236 (Text
+*235 (Text
 uid 10313,0
 va (VaSet
@@ -7211,5 +7189,5 @@
 tm "HdlTextNameMgr"
 )
-*237 (Text
+*236 (Text
 uid 10314,0
 va (VaSet
@@ -7237,10 +7215,10 @@
 viewiconposition 0
 )
-*238 (Net
+*237 (Net
 uid 10496,0
 decl (Decl
 n "CLK50_OUT"
 t "std_logic"
-o 61
+o 54
 suid 184,0
 )
@@ -7250,15 +7228,15 @@
 font "Courier New,8,0"
 )
-xt "39000,45600,57500,46400"
+xt "39000,48800,57500,49600"
 st "SIGNAL CLK50_OUT       : std_logic
 "
 )
 )
-*239 (Net
+*238 (Net
 uid 10504,0
 decl (Decl
 n "CLK25_OUT"
 t "std_logic"
-o 62
+o 52
 suid 185,0
 )
@@ -7268,15 +7246,15 @@
 font "Courier New,8,0"
 )
-xt "39000,44000,57500,44800"
+xt "39000,47200,57500,48000"
 st "SIGNAL CLK25_OUT       : std_logic
 "
 )
 )
-*240 (Net
+*239 (Net
 uid 10512,0
 decl (Decl
 n "CLK25_PSOUT"
 t "std_logic"
-o 63
+o 53
 suid 186,0
 )
@@ -7286,10 +7264,10 @@
 font "Courier New,8,0"
 )
-xt "39000,44800,57500,45600"
+xt "39000,48000,57500,48800"
 st "SIGNAL CLK25_PSOUT     : std_logic
 "
 )
 )
-*241 (Net
+*240 (Net
 uid 10520,0
 decl (Decl
@@ -7304,10 +7282,10 @@
 font "Courier New,8,0"
 )
-xt "39000,53600,57500,54400"
+xt "39000,56800,57500,57600"
 st "SIGNAL PS_DIR_IN       : std_logic
 "
 )
 )
-*242 (Net
+*241 (Net
 uid 10528,0
 decl (Decl
@@ -7322,15 +7300,15 @@
 font "Courier New,8,0"
 )
-xt "39000,54400,57500,55200"
+xt "39000,57600,57500,58400"
 st "SIGNAL PS_DO_IN        : std_logic
 "
 )
 )
-*243 (Net
+*242 (Net
 uid 10536,0
 decl (Decl
 n "PSEN_OUT"
 t "std_logic"
-o 66
+o 62
 suid 189,0
 )
@@ -7340,15 +7318,15 @@
 font "Courier New,8,0"
 )
-xt "39000,52000,57500,52800"
+xt "39000,55200,57500,56000"
 st "SIGNAL PSEN_OUT        : std_logic
 "
 )
 )
-*244 (Net
+*243 (Net
 uid 10544,0
 decl (Decl
 n "PSINCDEC_OUT"
 t "std_logic"
-o 67
+o 63
 suid 190,0
 )
@@ -7358,10 +7336,10 @@
 font "Courier New,8,0"
 )
-xt "39000,52800,57500,53600"
+xt "39000,56000,57500,56800"
 st "SIGNAL PSINCDEC_OUT    : std_logic
 "
 )
 )
-*245 (Net
+*244 (Net
 uid 10552,0
 decl (Decl
@@ -7370,5 +7348,5 @@
 preAdd 0
 posAdd 0
-o 68
+o 58
 suid 191,0
 )
@@ -7378,10 +7356,10 @@
 font "Courier New,8,0"
 )
-xt "39000,48800,57500,49600"
+xt "39000,52000,57500,52800"
 st "SIGNAL DCM_locked      : std_logic
 "
 )
 )
-*246 (Net
+*245 (Net
 uid 10560,0
 decl (Decl
@@ -7390,5 +7368,5 @@
 preAdd 0
 posAdd 0
-o 69
+o 73
 suid 192,0
 i "'0'"
@@ -7399,10 +7377,10 @@
 font "Courier New,8,0"
 )
-xt "39000,60800,72000,61600"
+xt "39000,64000,72000,64800"
 st "SIGNAL ready           : std_logic                      := '0'
 "
 )
 )
-*247 (Net
+*246 (Net
 uid 10568,0
 decl (Decl
@@ -7412,5 +7390,5 @@
 preAdd 0
 posAdd 0
-o 70
+o 75
 suid 193,0
 i "'0'"
@@ -7421,5 +7399,5 @@
 font "Courier New,8,0"
 )
-xt "39000,62400,72000,64000"
+xt "39000,65600,72000,67200"
 st "-- status:
 SIGNAL shifting        : std_logic                      := '0'
@@ -7427,10 +7405,10 @@
 )
 )
-*248 (Net
+*247 (Net
 uid 10576,0
 decl (Decl
 n "PSDONE_extraOUT"
 t "std_logic"
-o 71
+o 61
 suid 194,0
 )
@@ -7440,15 +7418,15 @@
 font "Courier New,8,0"
 )
-xt "39000,51200,57500,52000"
+xt "39000,54400,57500,55200"
 st "SIGNAL PSDONE_extraOUT : std_logic
 "
 )
 )
-*249 (Net
+*248 (Net
 uid 10584,0
 decl (Decl
 n "PSCLK_OUT"
 t "std_logic"
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 shape (OrthoPolyLine
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+uid 3835,0
 va (VaSet
 vasetType 3
 )
-xt "108000,109000,111000,109000"
-pts [
-"111000,109000"
-"108000,109000"
-]
-)
-start &164
-end &154
+xt "108000,110000,111000,110000"
+pts [
+"111000,110000"
+"108000,110000"
+]
+)
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 sat 32
 eat 2
@@ -9269,42 +9560,4 @@
 si 0
 tg (WTG
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-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 3831,0
-va (VaSet
-isHidden 1
-)
-xt "108000,108000,110300,109000"
-st "SRIN"
-blo "108000,108800"
-tm "WireNameMgr"
-)
-)
-on &173
-)
-*298 (Wire
-uid 3834,0
-shape (OrthoPolyLine
-uid 3835,0
-va (VaSet
-vasetType 3
-)
-xt "108000,110000,111000,110000"
-pts [
-"111000,110000"
-"108000,110000"
-]
-)
-start &165
-end &154
-sat 32
-eat 2
-stc 0
-st 0
-sf 1
-si 0
-tg (WTG
 uid 3838,0
 ps "ConnStartEndStrategy"
@@ -9321,7 +9574,7 @@
 )
 )
-on &174
-)
-*299 (Wire
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+)
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 shape (OrthoPolyLine
@@ -9338,5 +9591,5 @@
 )
 start &166
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 sat 32
 eat 2
@@ -9361,7 +9614,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9378,5 +9631,5 @@
 )
 start &14
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 sat 32
 eat 32
@@ -9401,7 +9654,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9417,5 +9670,5 @@
 )
 start &43
-end &163
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 sat 32
 eat 32
@@ -9441,5 +9694,5 @@
 on &172
 )
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 shape (OrthoPolyLine
@@ -9455,6 +9708,6 @@
 ]
 )
-start &182
-end &186
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 sat 32
 eat 1
@@ -9478,7 +9731,7 @@
 )
 )
-on &183
-)
-*303 (Wire
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+)
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 shape (OrthoPolyLine
@@ -9494,6 +9747,6 @@
 ]
 )
-start &186
-end &184
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 sat 2
 eat 32
@@ -9517,7 +9770,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9533,5 +9786,5 @@
 ]
 )
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 sat 16
 eat 32
@@ -9555,7 +9808,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9571,5 +9824,5 @@
 )
 start &38
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 es 0
 sat 32
@@ -9592,7 +9845,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9611,5 +9864,5 @@
 )
 start &30
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 sat 32
 eat 1
@@ -9632,7 +9885,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9667,7 +9920,7 @@
 )
 )
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-)
-*308 (Wire
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+)
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@@ -9684,5 +9937,5 @@
 )
 start &25
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 sat 32
 eat 32
@@ -9705,7 +9958,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9721,5 +9974,5 @@
 )
 start &44
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 sat 32
 eat 32
@@ -9742,7 +9995,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9758,5 +10011,5 @@
 ]
 )
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 sat 16
 eat 32
@@ -9780,7 +10033,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -9788,4 +10041,5 @@
 va (VaSet
 vasetType 3
+lineWidth 2
 )
 xt "112000,126000,122000,126000"
@@ -9795,7 +10049,8 @@
 ]
 )
-start &234
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 sat 2
 eat 16
+sty 1
 st 0
 sf 1
@@ -9815,7 +10070,7 @@
 )
 )
-on &233
-)
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+)
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 shape (OrthoPolyLine
@@ -9823,4 +10078,5 @@
 va (VaSet
 vasetType 3
+lineWidth 2
 )
 xt "112000,127000,122000,127000"
@@ -9830,7 +10086,8 @@
 ]
 )
-start &234
+start &233
 sat 2
 eat 16
+sty 1
 st 0
 sf 1
@@ -9850,7 +10107,7 @@
 )
 )
-on &195
-)
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+)
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 shape (OrthoPolyLine
@@ -9885,7 +10142,7 @@
 )
 )
-on &238
-)
-*314 (Wire
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+)
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 shape (OrthoPolyLine
@@ -9920,7 +10177,7 @@
 )
 )
-on &239
-)
-*315 (Wire
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+)
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 shape (OrthoPolyLine
@@ -9955,7 +10212,7 @@
 )
 )
-on &240
-)
-*316 (Wire
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+)
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 shape (OrthoPolyLine
@@ -9990,7 +10247,7 @@
 )
 )
-on &241
-)
-*317 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10025,7 +10282,7 @@
 )
 )
-on &242
-)
-*318 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10060,7 +10317,7 @@
 )
 )
-on &243
-)
-*319 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10095,7 +10352,7 @@
 )
 )
-on &244
-)
-*320 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10130,7 +10387,7 @@
 )
 )
-on &245
-)
-*321 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10165,7 +10422,7 @@
 )
 )
-on &246
-)
-*322 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10200,7 +10457,7 @@
 )
 )
-on &247
-)
-*323 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10235,7 +10492,7 @@
 )
 )
-on &248
-)
-*324 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10270,7 +10527,7 @@
 )
 )
-on &249
-)
-*325 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10305,7 +10562,7 @@
 )
 )
-on &250
-)
-*326 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10320,5 +10577,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10340,7 +10597,7 @@
 )
 )
-on &239
-)
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+)
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 shape (OrthoPolyLine
@@ -10355,5 +10612,5 @@
 ]
 )
-end &234
+end &233
 sat 16
 eat 1
@@ -10375,7 +10632,7 @@
 )
 )
-on &240
-)
-*328 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10390,5 +10647,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10410,7 +10667,7 @@
 )
 )
-on &238
-)
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+)
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 shape (OrthoPolyLine
@@ -10425,5 +10682,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10445,7 +10702,7 @@
 )
 )
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-)
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+)
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 shape (OrthoPolyLine
@@ -10460,5 +10717,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10480,7 +10737,7 @@
 )
 )
-on &250
-)
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+)
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 shape (OrthoPolyLine
@@ -10495,5 +10752,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10515,7 +10772,7 @@
 )
 )
-on &249
-)
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+)
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 shape (OrthoPolyLine
@@ -10530,5 +10787,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10550,7 +10807,7 @@
 )
 )
-on &248
-)
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+)
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 shape (OrthoPolyLine
@@ -10565,5 +10822,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10585,7 +10842,7 @@
 )
 )
-on &243
-)
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+)
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 shape (OrthoPolyLine
@@ -10600,5 +10857,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10620,7 +10877,7 @@
 )
 )
-on &244
-)
-*335 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10635,5 +10892,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10655,7 +10912,7 @@
 )
 )
-on &241
-)
-*336 (Wire
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+)
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 shape (OrthoPolyLine
@@ -10670,5 +10927,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10690,7 +10947,7 @@
 )
 )
-on &242
-)
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+)
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 shape (OrthoPolyLine
@@ -10705,5 +10962,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10725,7 +10982,7 @@
 )
 )
-on &246
-)
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+)
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 shape (OrthoPolyLine
@@ -10740,5 +10997,5 @@
 ]
 )
-end &234
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 sat 16
 eat 1
@@ -10760,5 +11017,189 @@
 )
 )
-on &247
+on &246
+)
+*347 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "96000,103000,100000,103000"
+pts [
+"96000,103000"
+"100000,103000"
+]
+)
+start &250
+end &155
+sat 32
+eat 1
+st 0
+sf 1
+si 0
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+f (Text
+uid 11101,0
+va (VaSet
+isHidden 1
+)
+xt "126000,96000,131300,97000"
+st "RS485_C_DI"
+blo "126000,96800"
+tm "WireNameMgr"
+)
+)
+on &251
+)
+*348 (Wire
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+shape (OrthoPolyLine
+uid 11111,0
+va (VaSet
+vasetType 3
+)
+xt "108000,112000,111000,112000"
+pts [
+"108000,112000"
+"111000,112000"
+]
+)
+start &155
+end &252
+sat 2
+eat 32
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+sf 1
+si 0
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11115,0
+va (VaSet
+isHidden 1
+)
+xt "110000,111000,115700,112000"
+st "RS485_C_DO"
+blo "110000,111800"
+tm "WireNameMgr"
+)
+)
+on &253
+)
+*349 (Wire
+uid 11514,0
+shape (OrthoPolyLine
+uid 11515,0
+va (VaSet
+vasetType 3
+)
+xt "123000,116000,127000,116000"
+pts [
+"123000,116000"
+"127000,116000"
+]
+)
+start &254
+sat 32
+eat 16
+st 0
+sf 1
+si 0
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11519,0
+va (VaSet
+isHidden 1
+)
+xt "125000,115000,130200,116000"
+st "RS485_E_DI"
+blo "125000,115800"
+tm "WireNameMgr"
+)
+)
+on &255
+)
+*350 (Wire
+uid 11528,0
+shape (OrthoPolyLine
+uid 11529,0
+va (VaSet
+vasetType 3
+)
+xt "123000,114000,126000,114000"
+pts [
+"123000,114000"
+"126000,114000"
+]
+)
+end &257
+sat 16
+eat 32
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+sf 1
+si 0
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+stg "STSignalDisplayStrategy"
+f (Text
+uid 11533,0
+va (VaSet
+isHidden 1
+)
+xt "125000,113000,130600,114000"
+st "RS485_E_DO"
+blo "125000,113800"
+tm "WireNameMgr"
+)
+)
+on &256
+)
+*351 (Wire
+uid 12320,0
+shape (OrthoPolyLine
+uid 12321,0
+va (VaSet
+vasetType 3
+)
+xt "80750,140000,87000,140000"
+pts [
+"80750,140000"
+"87000,140000"
+]
+)
+start &59
+end &258
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 12324,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 12325,0
+va (VaSet
+isHidden 1
+)
+xt "82000,139000,84300,140000"
+st "SRIN"
+blo "82000,139800"
+tm "WireNameMgr"
+)
+)
+on &259
 )
 ]
@@ -10774,9 +11215,9 @@
 color "26368,26368,26368"
 )
-packageList *339 (PackageList
+packageList *352 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*340 (Text
+*353 (Text
 uid 42,0
 va (VaSet
@@ -10787,5 +11228,5 @@
 blo "0,800"
 )
-*341 (MLText
+*354 (MLText
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 va (VaSet
@@ -10808,5 +11249,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*342 (Text
+*355 (Text
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 va (VaSet
@@ -10818,5 +11259,5 @@
 blo "20000,800"
 )
-*343 (Text
+*356 (Text
 uid 46,0
 va (VaSet
@@ -10828,5 +11269,5 @@
 blo "20000,1800"
 )
-*344 (MLText
+*357 (MLText
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 va (VaSet
@@ -10838,5 +11279,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*345 (Text
+*358 (Text
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 va (VaSet
@@ -10848,5 +11289,5 @@
 blo "20000,4800"
 )
-*346 (MLText
+*359 (MLText
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 va (VaSet
@@ -10856,5 +11297,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*347 (Text
+*360 (Text
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 va (VaSet
@@ -10866,5 +11307,5 @@
 blo "20000,5800"
 )
-*348 (MLText
+*361 (MLText
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 va (VaSet
@@ -10877,6 +11318,6 @@
 associable 1
 )
-windowSize "1280,0,2561,1024"
-viewArea "33652,91254,117471,160379"
+windowSize "0,0,1281,1002"
+viewArea "48828,78798,132010,145674"
 cachedDiagramExtent "0,0,699000,450107"
 pageSetupInfo (PageSetupInfo
@@ -10891,5 +11332,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "0,0"
-lastUid 10906,0
+lastUid 12337,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -10953,5 +11394,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*349 (Text
+*362 (Text
 va (VaSet
 font "Arial,8,1"
@@ -10962,5 +11403,5 @@
 tm "BdLibraryNameMgr"
 )
-*350 (Text
+*363 (Text
 va (VaSet
 font "Arial,8,1"
@@ -10971,5 +11412,5 @@
 tm "BlkNameMgr"
 )
-*351 (Text
+*364 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11022,5 +11463,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*352 (Text
+*365 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11030,5 +11471,5 @@
 blo "550,4300"
 )
-*353 (Text
+*366 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11038,5 +11479,5 @@
 blo "550,5300"
 )
-*354 (Text
+*367 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11087,5 +11528,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*355 (Text
+*368 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11096,5 +11537,5 @@
 tm "BdLibraryNameMgr"
 )
-*356 (Text
+*369 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11105,5 +11546,5 @@
 tm "CptNameMgr"
 )
-*357 (Text
+*370 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11159,5 +11600,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*358 (Text
+*371 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11167,5 +11608,5 @@
 blo "500,4300"
 )
-*359 (Text
+*372 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11175,5 +11616,5 @@
 blo "500,5300"
 )
-*360 (Text
+*373 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11220,5 +11661,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*361 (Text
+*374 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11228,5 +11669,5 @@
 blo "50,4300"
 )
-*362 (Text
+*375 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11236,5 +11677,5 @@
 blo "50,5300"
 )
-*363 (Text
+*376 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11277,5 +11718,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*364 (Text
+*377 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11286,5 +11727,5 @@
 tm "HdlTextNameMgr"
 )
-*365 (Text
+*378 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11689,5 +12130,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*366 (Text
+*379 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11697,5 +12138,5 @@
 blo "14100,20800"
 )
-*367 (MLText
+*380 (MLText
 va (VaSet
 )
@@ -11749,5 +12190,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*368 (Text
+*381 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11757,5 +12198,5 @@
 blo "14100,20800"
 )
-*369 (MLText
+*382 (MLText
 va (VaSet
 )
@@ -11875,7 +12316,7 @@
 font "Arial,8,1"
 )
-xt "37000,43000,44100,44000"
+xt "37000,46200,44100,47200"
 st "Diagram Signals:"
-blo "37000,43800"
+blo "37000,47000"
 )
 postUserLabel (Text
@@ -11901,44 +12342,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 196,0
+suid 203,0
 usingSuid 1
-emptyRow *370 (LEmptyRow
+emptyRow *383 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*371 (RefLabelRowHdr
-)
-*372 (TitleRowHdr
-)
-*373 (FilterRowHdr
-)
-*374 (RefLabelColHdr
+*384 (RefLabelRowHdr
+)
+*385 (TitleRowHdr
+)
+*386 (FilterRowHdr
+)
+*387 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*375 (RowExpandColHdr
+*388 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*376 (GroupColHdr
+*389 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*377 (NameColHdr
+*390 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*378 (ModeColHdr
+*391 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*379 (TypeColHdr
+*392 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*380 (BoundsColHdr
+*393 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*381 (InitColHdr
+*394 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*382 (EolColHdr
+*395 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*383 (LeafLogPort
+*396 (LeafLogPort
 port (LogicalPort
 m 4
@@ -11949,5 +12390,5 @@
 preAdd 0
 posAdd 0
-o 55
+o 69
 suid 5,0
 )
@@ -11955,5 +12396,5 @@
 uid 327,0
 )
-*384 (LeafLogPort
+*397 (LeafLogPort
 port (LogicalPort
 m 4
@@ -11962,5 +12403,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 56
+o 70
 suid 6,0
 )
@@ -11968,5 +12409,5 @@
 uid 329,0
 )
-*385 (LeafLogPort
+*398 (LeafLogPort
 port (LogicalPort
 m 4
@@ -11974,5 +12415,5 @@
 n "adc_data_array"
 t "adc_data_array_type"
-o 54
+o 68
 suid 29,0
 )
@@ -11980,5 +12421,5 @@
 uid 1491,0
 )
-*386 (LeafLogPort
+*399 (LeafLogPort
 port (LogicalPort
 m 1
@@ -11986,5 +12427,5 @@
 n "RSRLOAD"
 t "std_logic"
-o 35
+o 37
 suid 57,0
 i "'0'"
@@ -11993,5 +12434,5 @@
 uid 2435,0
 )
-*387 (LeafLogPort
+*400 (LeafLogPort
 port (LogicalPort
 m 4
@@ -11999,5 +12440,5 @@
 n "SRCLK"
 t "std_logic"
-o 52
+o 66
 suid 58,0
 i "'0'"
@@ -12006,5 +12447,5 @@
 uid 2437,0
 )
-*388 (LeafLogPort
+*401 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12013,5 +12454,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 59
+o 74
 suid 65,0
 )
@@ -12019,5 +12460,5 @@
 uid 3037,0
 )
-*389 (LeafLogPort
+*402 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12025,5 +12466,5 @@
 n "DAC_CS"
 t "std_logic"
-o 21
+o 22
 suid 66,0
 )
@@ -12031,5 +12472,5 @@
 uid 3039,0
 )
-*390 (LeafLogPort
+*403 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12044,5 +12485,5 @@
 uid 3276,0
 )
-*391 (LeafLogPort
+*404 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12055,5 +12496,5 @@
 uid 3278,0
 )
-*392 (LeafLogPort
+*405 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12062,5 +12503,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 16
+o 17
 suid 71,0
 )
@@ -12068,5 +12509,5 @@
 uid 3280,0
 )
-*393 (LeafLogPort
+*406 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12074,5 +12515,5 @@
 n "CLK_25_PS"
 t "std_logic"
-o 50
+o 55
 suid 72,0
 )
@@ -12080,5 +12521,5 @@
 uid 3282,0
 )
-*394 (LeafLogPort
+*407 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12088,5 +12529,5 @@
 preAdd 0
 posAdd 0
-o 30
+o 31
 suid 73,0
 )
@@ -12094,5 +12535,5 @@
 uid 3382,0
 )
-*395 (LeafLogPort
+*408 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12106,5 +12547,5 @@
 uid 3384,0
 )
-*396 (LeafLogPort
+*409 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12118,5 +12559,5 @@
 uid 3386,0
 )
-*397 (LeafLogPort
+*410 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12130,5 +12571,5 @@
 uid 3388,0
 )
-*398 (LeafLogPort
+*411 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12142,5 +12583,5 @@
 uid 3390,0
 )
-*399 (LeafLogPort
+*412 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12154,5 +12595,5 @@
 uid 3392,0
 )
-*400 (LeafLogPort
+*413 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12160,5 +12601,5 @@
 n "D0_SRCLK"
 t "STD_LOGIC"
-o 17
+o 18
 suid 87,0
 )
@@ -12166,5 +12607,5 @@
 uid 3468,0
 )
-*401 (LeafLogPort
+*414 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12172,5 +12613,5 @@
 n "D1_SRCLK"
 t "STD_LOGIC"
-o 18
+o 19
 suid 88,0
 )
@@ -12178,5 +12619,5 @@
 uid 3470,0
 )
-*402 (LeafLogPort
+*415 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12184,5 +12625,5 @@
 n "D2_SRCLK"
 t "STD_LOGIC"
-o 19
+o 20
 suid 89,0
 )
@@ -12190,5 +12631,5 @@
 uid 3472,0
 )
-*403 (LeafLogPort
+*416 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12196,5 +12637,5 @@
 n "D3_SRCLK"
 t "STD_LOGIC"
-o 20
+o 21
 suid 90,0
 )
@@ -12202,5 +12643,5 @@
 uid 3474,0
 )
-*404 (LeafLogPort
+*417 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12213,5 +12654,5 @@
 uid 3524,0
 )
-*405 (LeafLogPort
+*418 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12224,5 +12665,5 @@
 uid 3526,0
 )
-*406 (LeafLogPort
+*419 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12235,5 +12676,5 @@
 uid 3528,0
 )
-*407 (LeafLogPort
+*420 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12246,5 +12687,5 @@
 uid 3530,0
 )
-*408 (LeafLogPort
+*421 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12253,5 +12694,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 24
+o 25
 suid 95,0
 i "(others => '0')"
@@ -12260,5 +12701,5 @@
 uid 3532,0
 )
-*409 (LeafLogPort
+*422 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12266,5 +12707,5 @@
 n "DWRITE"
 t "std_logic"
-o 23
+o 24
 suid 96,0
 i "'0'"
@@ -12273,5 +12714,5 @@
 uid 3534,0
 )
-*410 (LeafLogPort
+*423 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12279,5 +12720,5 @@
 n "T0_CS"
 t "std_logic"
-o 38
+o 40
 suid 101,0
 )
@@ -12285,5 +12726,5 @@
 uid 3646,0
 )
-*411 (LeafLogPort
+*424 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12291,5 +12732,5 @@
 n "T1_CS"
 t "std_logic"
-o 39
+o 41
 suid 102,0
 )
@@ -12297,5 +12738,5 @@
 uid 3648,0
 )
-*412 (LeafLogPort
+*425 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12303,5 +12744,5 @@
 n "T2_CS"
 t "std_logic"
-o 40
+o 42
 suid 103,0
 )
@@ -12309,5 +12750,5 @@
 uid 3650,0
 )
-*413 (LeafLogPort
+*426 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12315,5 +12756,5 @@
 n "T3_CS"
 t "std_logic"
-o 41
+o 43
 suid 104,0
 )
@@ -12321,5 +12762,5 @@
 uid 3652,0
 )
-*414 (LeafLogPort
+*427 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12327,5 +12768,5 @@
 n "S_CLK"
 t "std_logic"
-o 37
+o 39
 suid 105,0
 )
@@ -12333,5 +12774,5 @@
 uid 3654,0
 )
-*415 (LeafLogPort
+*428 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12340,5 +12781,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 43
+o 45
 suid 106,0
 )
@@ -12346,5 +12787,5 @@
 uid 3656,0
 )
-*416 (LeafLogPort
+*429 (LeafLogPort
 port (LogicalPort
 m 2
@@ -12353,172 +12794,9 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 49
+o 51
 suid 107,0
 )
 )
 uid 3658,0
-)
-*417 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_RES"
-t "std_logic"
-o 46
-suid 108,0
-i "'1'"
-)
-)
-uid 3660,0
-)
-*418 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_RD"
-t "std_logic"
-o 45
-suid 109,0
-i "'1'"
-)
-)
-uid 3662,0
-)
-*419 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_WR"
-t "std_logic"
-o 47
-suid 110,0
-i "'1'"
-)
-)
-uid 3664,0
-)
-*420 (LeafLogPort
-port (LogicalPort
-decl (Decl
-n "W_INT"
-t "std_logic"
-o 13
-suid 111,0
-)
-)
-uid 3666,0
-)
-*421 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_CS"
-t "std_logic"
-o 44
-suid 112,0
-i "'1'"
-)
-)
-uid 3668,0
-)
-*422 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "MOSI"
-t "std_logic"
-o 29
-suid 113,0
-i "'0'"
-)
-)
-uid 3696,0
-)
-*423 (LeafLogPort
-port (LogicalPort
-m 2
-decl (Decl
-n "MISO"
-t "std_logic"
-preAdd 0
-posAdd 0
-o 48
-suid 114,0
-)
-)
-uid 3698,0
-)
-*424 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "TRG_V"
-t "std_logic"
-o 42
-suid 126,0
-)
-)
-uid 3886,0
-)
-*425 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_C_RE"
-t "std_logic"
-o 32
-suid 127,0
-)
-)
-uid 3888,0
-)
-*426 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_C_DE"
-t "std_logic"
-o 31
-suid 128,0
-)
-)
-uid 3890,0
-)
-*427 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_E_RE"
-t "std_logic"
-o 34
-suid 129,0
-)
-)
-uid 3892,0
-)
-*428 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_E_DE"
-t "std_logic"
-o 33
-suid 130,0
-)
-)
-uid 3894,0
-)
-*429 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "DENABLE"
-t "std_logic"
-o 22
-suid 131,0
-i "'0'"
-)
-)
-uid 3896,0
 )
 *430 (LeafLogPort
@@ -12526,11 +12804,12 @@
 m 1
 decl (Decl
-n "SRIN"
-t "std_logic"
-o 36
-suid 132,0
-)
-)
-uid 3898,0
+n "W_RES"
+t "std_logic"
+o 48
+suid 108,0
+i "'1'"
+)
+)
+uid 3660,0
 )
 *431 (LeafLogPort
@@ -12538,11 +12817,12 @@
 m 1
 decl (Decl
-n "EE_CS"
-t "std_logic"
-o 27
-suid 133,0
-)
-)
-uid 3900,0
+n "W_RD"
+t "std_logic"
+o 47
+suid 109,0
+i "'1'"
+)
+)
+uid 3662,0
 )
 *432 (LeafLogPort
@@ -12550,8 +12830,157 @@
 m 1
 decl (Decl
+n "W_WR"
+t "std_logic"
+o 49
+suid 110,0
+i "'1'"
+)
+)
+uid 3664,0
+)
+*433 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "W_INT"
+t "std_logic"
+o 13
+suid 111,0
+)
+)
+uid 3666,0
+)
+*434 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "W_CS"
+t "std_logic"
+o 46
+suid 112,0
+i "'1'"
+)
+)
+uid 3668,0
+)
+*435 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "MOSI"
+t "std_logic"
+o 30
+suid 113,0
+i "'0'"
+)
+)
+uid 3696,0
+)
+*436 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "MISO"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 50
+suid 114,0
+)
+)
+uid 3698,0
+)
+*437 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "TRG_V"
+t "std_logic"
+o 44
+suid 126,0
+)
+)
+uid 3886,0
+)
+*438 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_RE"
+t "std_logic"
+o 34
+suid 127,0
+)
+)
+uid 3888,0
+)
+*439 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_DE"
+t "std_logic"
+o 32
+suid 128,0
+)
+)
+uid 3890,0
+)
+*440 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_E_RE"
+t "std_logic"
+o 36
+suid 129,0
+)
+)
+uid 3892,0
+)
+*441 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_E_DE"
+t "std_logic"
+o 35
+suid 130,0
+)
+)
+uid 3894,0
+)
+*442 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "DENABLE"
+t "std_logic"
+o 23
+suid 131,0
+i "'0'"
+)
+)
+uid 3896,0
+)
+*443 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "EE_CS"
+t "std_logic"
+o 28
+suid 133,0
+)
+)
+uid 3900,0
+)
+*444 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
 n "LED"
 t "std_logic_vector"
 b "( 2 DOWNTO 0 )"
-o 28
+o 29
 suid 134,0
 i "(others => '1')"
@@ -12560,5 +12989,5 @@
 uid 3902,0
 )
-*433 (LeafLogPort
+*445 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12567,5 +12996,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 25
+o 26
 suid 141,0
 i "(OTHERS => '0')"
@@ -12574,5 +13003,5 @@
 uid 5322,0
 )
-*434 (LeafLogPort
+*446 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12587,5 +13016,5 @@
 scheme 0
 )
-*435 (LeafLogPort
+*447 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12594,5 +13023,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 26
+o 27
 suid 154,0
 i "(others => '0')"
@@ -12602,5 +13031,5 @@
 scheme 0
 )
-*436 (LeafLogPort
+*448 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12609,5 +13038,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 15
+o 16
 suid 155,0
 i "(OTHERS => '0')"
@@ -12617,5 +13046,5 @@
 scheme 0
 )
-*437 (LeafLogPort
+*449 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12623,5 +13052,5 @@
 n "dummy"
 t "std_logic"
-o 58
+o 72
 suid 157,0
 )
@@ -12630,5 +13059,5 @@
 scheme 0
 )
-*438 (LeafLogPort
+*450 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12637,5 +13066,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 57
+o 71
 suid 159,0
 i "(others => '0')"
@@ -12644,5 +13073,5 @@
 uid 8875,0
 )
-*439 (LeafLogPort
+*451 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12650,5 +13079,5 @@
 n "CLK_50"
 t "std_logic"
-o 51
+o 57
 suid 163,0
 )
@@ -12656,5 +13085,5 @@
 uid 9516,0
 )
-*440 (LeafLogPort
+*452 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12662,5 +13091,5 @@
 n "CLK_25_PS1"
 t "std_logic"
-o 58
+o 56
 suid 164,0
 )
@@ -12668,5 +13097,5 @@
 uid 10056,0
 )
-*441 (LeafLogPort
+*453 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12674,5 +13103,5 @@
 n "adc_clk_en"
 t "std_logic"
-o 59
+o 67
 suid 165,0
 i "'0'"
@@ -12681,5 +13110,5 @@
 uid 10058,0
 )
-*442 (LeafLogPort
+*454 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12688,5 +13117,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 60
+o 15
 suid 166,0
 i "(others => '0')"
@@ -12696,5 +13125,5 @@
 scheme 0
 )
-*443 (LeafLogPort
+*455 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12702,5 +13131,5 @@
 n "CLK50_OUT"
 t "std_logic"
-o 61
+o 54
 suid 184,0
 )
@@ -12708,5 +13137,5 @@
 uid 10704,0
 )
-*444 (LeafLogPort
+*456 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12714,5 +13143,5 @@
 n "CLK25_OUT"
 t "std_logic"
-o 62
+o 52
 suid 185,0
 )
@@ -12720,5 +13149,5 @@
 uid 10706,0
 )
-*445 (LeafLogPort
+*457 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12726,5 +13155,5 @@
 n "CLK25_PSOUT"
 t "std_logic"
-o 63
+o 53
 suid 186,0
 )
@@ -12732,5 +13161,5 @@
 uid 10708,0
 )
-*446 (LeafLogPort
+*458 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12744,5 +13173,5 @@
 uid 10710,0
 )
-*447 (LeafLogPort
+*459 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12756,5 +13185,5 @@
 uid 10712,0
 )
-*448 (LeafLogPort
+*460 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12762,5 +13191,5 @@
 n "PSEN_OUT"
 t "std_logic"
-o 66
+o 62
 suid 189,0
 )
@@ -12768,5 +13197,5 @@
 uid 10714,0
 )
-*449 (LeafLogPort
+*461 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12774,5 +13203,5 @@
 n "PSINCDEC_OUT"
 t "std_logic"
-o 67
+o 63
 suid 190,0
 )
@@ -12780,5 +13209,5 @@
 uid 10716,0
 )
-*450 (LeafLogPort
+*462 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12788,5 +13217,5 @@
 preAdd 0
 posAdd 0
-o 68
+o 58
 suid 191,0
 )
@@ -12794,5 +13223,5 @@
 uid 10718,0
 )
-*451 (LeafLogPort
+*463 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12802,5 +13231,5 @@
 preAdd 0
 posAdd 0
-o 69
+o 73
 suid 192,0
 i "'0'"
@@ -12809,5 +13238,5 @@
 uid 10720,0
 )
-*452 (LeafLogPort
+*464 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12818,5 +13247,5 @@
 preAdd 0
 posAdd 0
-o 70
+o 75
 suid 193,0
 i "'0'"
@@ -12825,5 +13254,5 @@
 uid 10722,0
 )
-*453 (LeafLogPort
+*465 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12831,5 +13260,5 @@
 n "PSDONE_extraOUT"
 t "std_logic"
-o 71
+o 61
 suid 194,0
 )
@@ -12837,5 +13266,5 @@
 uid 10724,0
 )
-*454 (LeafLogPort
+*466 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12843,5 +13272,5 @@
 n "PSCLK_OUT"
 t "std_logic"
-o 72
+o 60
 suid 195,0
 )
@@ -12849,5 +13278,5 @@
 uid 10726,0
 )
-*455 (LeafLogPort
+*467 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12855,9 +13284,71 @@
 n "LOCKED_extraOUT"
 t "std_logic"
-o 73
+o 59
 suid 196,0
 )
 )
 uid 10728,0
+)
+*468 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "RS485_C_DI"
+t "std_logic"
+o 74
+suid 197,0
+)
+)
+uid 11084,0
+scheme 0
+)
+*469 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_DO"
+t "std_logic"
+o 75
+suid 198,0
+)
+)
+uid 11086,0
+scheme 0
+)
+*470 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "RS485_E_DI"
+t "std_logic"
+o 76
+suid 200,0
+)
+)
+uid 11504,0
+scheme 0
+)
+*471 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "RS485_E_DO"
+t "std_logic"
+o 77
+suid 201,0
+)
+)
+uid 11506,0
+scheme 0
+)
+*472 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "SRIN"
+t "std_logic"
+o 78
+suid 203,0
+i "'0'"
+)
+)
+uid 12336,0
 )
 ]
@@ -12868,5 +13359,5 @@
 uid 67,0
 optionalChildren [
-*456 (Sheet
+*473 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -12885,25 +13376,25 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *457 (MRCItem
-litem &370
-pos 73
+emptyMRCItem *474 (MRCItem
+litem &383
+pos 77
 dimension 20
 )
 uid 69,0
 optionalChildren [
-*458 (MRCItem
-litem &371
+*475 (MRCItem
+litem &384
 pos 0
 dimension 20
 uid 70,0
 )
-*459 (MRCItem
-litem &372
+*476 (MRCItem
+litem &385
 pos 1
 dimension 23
 uid 71,0
 )
-*460 (MRCItem
-litem &373
+*477 (MRCItem
+litem &386
 pos 2
 hidden 1
@@ -12911,441 +13402,465 @@
 uid 72,0
 )
-*461 (MRCItem
-litem &383
+*478 (MRCItem
+litem &396
+pos 47
+dimension 20
+uid 328,0
+)
+*479 (MRCItem
+litem &397
 pos 48
 dimension 20
-uid 328,0
-)
-*462 (MRCItem
-litem &384
+uid 330,0
+)
+*480 (MRCItem
+litem &398
 pos 49
 dimension 20
-uid 330,0
-)
-*463 (MRCItem
-litem &385
-pos 50
-dimension 20
 uid 1492,0
 )
-*464 (MRCItem
-litem &386
+*481 (MRCItem
+litem &399
 pos 0
 dimension 20
 uid 2436,0
 )
-*465 (MRCItem
-litem &387
+*482 (MRCItem
+litem &400
+pos 50
+dimension 20
+uid 2438,0
+)
+*483 (MRCItem
+litem &401
 pos 51
 dimension 20
-uid 2438,0
-)
-*466 (MRCItem
-litem &388
-pos 52
-dimension 20
 uid 3038,0
 )
-*467 (MRCItem
-litem &389
+*484 (MRCItem
+litem &402
 pos 1
 dimension 20
 uid 3040,0
 )
-*468 (MRCItem
-litem &390
+*485 (MRCItem
+litem &403
 pos 2
 dimension 20
 uid 3277,0
 )
-*469 (MRCItem
-litem &391
+*486 (MRCItem
+litem &404
 pos 3
 dimension 20
 uid 3279,0
 )
-*470 (MRCItem
-litem &392
+*487 (MRCItem
+litem &405
 pos 4
 dimension 20
 uid 3281,0
 )
-*471 (MRCItem
-litem &393
-pos 53
+*488 (MRCItem
+litem &406
+pos 52
 dimension 20
 uid 3283,0
 )
-*472 (MRCItem
-litem &394
+*489 (MRCItem
+litem &407
 pos 5
 dimension 20
 uid 3383,0
 )
-*473 (MRCItem
-litem &395
+*490 (MRCItem
+litem &408
 pos 6
 dimension 20
 uid 3385,0
 )
-*474 (MRCItem
-litem &396
+*491 (MRCItem
+litem &409
 pos 7
 dimension 20
 uid 3387,0
 )
-*475 (MRCItem
-litem &397
+*492 (MRCItem
+litem &410
 pos 8
 dimension 20
 uid 3389,0
 )
-*476 (MRCItem
-litem &398
+*493 (MRCItem
+litem &411
 pos 9
 dimension 20
 uid 3391,0
 )
-*477 (MRCItem
-litem &399
+*494 (MRCItem
+litem &412
 pos 10
 dimension 20
 uid 3393,0
 )
-*478 (MRCItem
-litem &400
+*495 (MRCItem
+litem &413
 pos 11
 dimension 20
 uid 3469,0
 )
-*479 (MRCItem
-litem &401
+*496 (MRCItem
+litem &414
 pos 12
 dimension 20
 uid 3471,0
 )
-*480 (MRCItem
-litem &402
+*497 (MRCItem
+litem &415
 pos 13
 dimension 20
 uid 3473,0
 )
-*481 (MRCItem
-litem &403
+*498 (MRCItem
+litem &416
 pos 14
 dimension 20
 uid 3475,0
 )
-*482 (MRCItem
-litem &404
+*499 (MRCItem
+litem &417
 pos 15
 dimension 20
 uid 3525,0
 )
-*483 (MRCItem
-litem &405
+*500 (MRCItem
+litem &418
 pos 16
 dimension 20
 uid 3527,0
 )
-*484 (MRCItem
-litem &406
+*501 (MRCItem
+litem &419
 pos 17
 dimension 20
 uid 3529,0
 )
-*485 (MRCItem
-litem &407
+*502 (MRCItem
+litem &420
 pos 18
 dimension 20
 uid 3531,0
 )
-*486 (MRCItem
-litem &408
+*503 (MRCItem
+litem &421
 pos 19
 dimension 20
 uid 3533,0
 )
-*487 (MRCItem
-litem &409
+*504 (MRCItem
+litem &422
 pos 20
 dimension 20
 uid 3535,0
 )
-*488 (MRCItem
-litem &410
+*505 (MRCItem
+litem &423
 pos 21
 dimension 20
 uid 3647,0
 )
-*489 (MRCItem
-litem &411
+*506 (MRCItem
+litem &424
 pos 22
 dimension 20
 uid 3649,0
 )
-*490 (MRCItem
-litem &412
+*507 (MRCItem
+litem &425
 pos 23
 dimension 20
 uid 3651,0
 )
-*491 (MRCItem
-litem &413
+*508 (MRCItem
+litem &426
 pos 24
 dimension 20
 uid 3653,0
 )
-*492 (MRCItem
-litem &414
+*509 (MRCItem
+litem &427
 pos 25
 dimension 20
 uid 3655,0
 )
-*493 (MRCItem
-litem &415
+*510 (MRCItem
+litem &428
 pos 26
 dimension 20
 uid 3657,0
 )
-*494 (MRCItem
-litem &416
+*511 (MRCItem
+litem &429
 pos 27
 dimension 20
 uid 3659,0
 )
-*495 (MRCItem
-litem &417
+*512 (MRCItem
+litem &430
 pos 28
 dimension 20
 uid 3661,0
 )
-*496 (MRCItem
-litem &418
+*513 (MRCItem
+litem &431
 pos 29
 dimension 20
 uid 3663,0
 )
-*497 (MRCItem
-litem &419
+*514 (MRCItem
+litem &432
 pos 30
 dimension 20
 uid 3665,0
 )
-*498 (MRCItem
-litem &420
+*515 (MRCItem
+litem &433
 pos 31
 dimension 20
 uid 3667,0
 )
-*499 (MRCItem
-litem &421
+*516 (MRCItem
+litem &434
 pos 32
 dimension 20
 uid 3669,0
 )
-*500 (MRCItem
-litem &422
+*517 (MRCItem
+litem &435
 pos 33
 dimension 20
 uid 3697,0
 )
-*501 (MRCItem
-litem &423
+*518 (MRCItem
+litem &436
 pos 34
 dimension 20
 uid 3699,0
 )
-*502 (MRCItem
-litem &424
+*519 (MRCItem
+litem &437
 pos 35
 dimension 20
 uid 3887,0
 )
-*503 (MRCItem
-litem &425
+*520 (MRCItem
+litem &438
 pos 36
 dimension 20
 uid 3889,0
 )
-*504 (MRCItem
-litem &426
+*521 (MRCItem
+litem &439
 pos 37
 dimension 20
 uid 3891,0
 )
-*505 (MRCItem
-litem &427
+*522 (MRCItem
+litem &440
 pos 38
 dimension 20
 uid 3893,0
 )
-*506 (MRCItem
-litem &428
+*523 (MRCItem
+litem &441
 pos 39
 dimension 20
 uid 3895,0
 )
-*507 (MRCItem
-litem &429
+*524 (MRCItem
+litem &442
 pos 40
 dimension 20
 uid 3897,0
 )
-*508 (MRCItem
-litem &430
+*525 (MRCItem
+litem &443
 pos 41
 dimension 20
-uid 3899,0
-)
-*509 (MRCItem
-litem &431
+uid 3901,0
+)
+*526 (MRCItem
+litem &444
 pos 42
 dimension 20
-uid 3901,0
-)
-*510 (MRCItem
-litem &432
+uid 3903,0
+)
+*527 (MRCItem
+litem &445
 pos 43
 dimension 20
-uid 3903,0
-)
-*511 (MRCItem
-litem &433
+uid 5323,0
+)
+*528 (MRCItem
+litem &446
 pos 44
 dimension 20
-uid 5323,0
-)
-*512 (MRCItem
-litem &434
+uid 6778,0
+)
+*529 (MRCItem
+litem &447
 pos 45
 dimension 20
-uid 6778,0
-)
-*513 (MRCItem
-litem &435
+uid 6873,0
+)
+*530 (MRCItem
+litem &448
 pos 46
 dimension 20
-uid 6873,0
-)
-*514 (MRCItem
-litem &436
-pos 47
+uid 7135,0
+)
+*531 (MRCItem
+litem &449
+pos 53
 dimension 20
-uid 7135,0
-)
-*515 (MRCItem
-litem &437
+uid 7474,0
+)
+*532 (MRCItem
+litem &450
 pos 54
 dimension 20
-uid 7474,0
-)
-*516 (MRCItem
-litem &438
+uid 8876,0
+)
+*533 (MRCItem
+litem &451
 pos 55
 dimension 20
-uid 8876,0
-)
-*517 (MRCItem
-litem &439
+uid 9517,0
+)
+*534 (MRCItem
+litem &452
 pos 56
 dimension 20
-uid 9517,0
-)
-*518 (MRCItem
-litem &440
+uid 10057,0
+)
+*535 (MRCItem
+litem &453
 pos 57
 dimension 20
-uid 10057,0
-)
-*519 (MRCItem
-litem &441
+uid 10059,0
+)
+*536 (MRCItem
+litem &454
 pos 58
 dimension 20
-uid 10059,0
-)
-*520 (MRCItem
-litem &442
+uid 10295,0
+)
+*537 (MRCItem
+litem &455
 pos 59
 dimension 20
-uid 10295,0
-)
-*521 (MRCItem
-litem &443
+uid 10705,0
+)
+*538 (MRCItem
+litem &456
 pos 60
 dimension 20
-uid 10705,0
-)
-*522 (MRCItem
-litem &444
+uid 10707,0
+)
+*539 (MRCItem
+litem &457
 pos 61
 dimension 20
-uid 10707,0
-)
-*523 (MRCItem
-litem &445
+uid 10709,0
+)
+*540 (MRCItem
+litem &458
 pos 62
 dimension 20
-uid 10709,0
-)
-*524 (MRCItem
-litem &446
+uid 10711,0
+)
+*541 (MRCItem
+litem &459
 pos 63
 dimension 20
-uid 10711,0
-)
-*525 (MRCItem
-litem &447
+uid 10713,0
+)
+*542 (MRCItem
+litem &460
 pos 64
 dimension 20
-uid 10713,0
-)
-*526 (MRCItem
-litem &448
+uid 10715,0
+)
+*543 (MRCItem
+litem &461
 pos 65
 dimension 20
-uid 10715,0
-)
-*527 (MRCItem
-litem &449
+uid 10717,0
+)
+*544 (MRCItem
+litem &462
 pos 66
 dimension 20
-uid 10717,0
-)
-*528 (MRCItem
-litem &450
+uid 10719,0
+)
+*545 (MRCItem
+litem &463
 pos 67
 dimension 20
-uid 10719,0
-)
-*529 (MRCItem
-litem &451
+uid 10721,0
+)
+*546 (MRCItem
+litem &464
 pos 68
 dimension 20
-uid 10721,0
-)
-*530 (MRCItem
-litem &452
+uid 10723,0
+)
+*547 (MRCItem
+litem &465
 pos 69
 dimension 20
-uid 10723,0
-)
-*531 (MRCItem
-litem &453
+uid 10725,0
+)
+*548 (MRCItem
+litem &466
 pos 70
 dimension 20
-uid 10725,0
-)
-*532 (MRCItem
-litem &454
+uid 10727,0
+)
+*549 (MRCItem
+litem &467
 pos 71
 dimension 20
-uid 10727,0
-)
-*533 (MRCItem
-litem &455
+uid 10729,0
+)
+*550 (MRCItem
+litem &468
 pos 72
 dimension 20
-uid 10729,0
+uid 11085,0
+)
+*551 (MRCItem
+litem &469
+pos 73
+dimension 20
+uid 11087,0
+)
+*552 (MRCItem
+litem &470
+pos 74
+dimension 20
+uid 11505,0
+)
+*553 (MRCItem
+litem &471
+pos 75
+dimension 20
+uid 11507,0
+)
+*554 (MRCItem
+litem &472
+pos 76
+dimension 20
+uid 12337,0
 )
 ]
@@ -13360,48 +13875,48 @@
 uid 73,0
 optionalChildren [
-*534 (MRCItem
-litem &374
+*555 (MRCItem
+litem &387
 pos 0
 dimension 20
 uid 74,0
 )
-*535 (MRCItem
-litem &376
+*556 (MRCItem
+litem &389
 pos 1
 dimension 50
 uid 75,0
 )
-*536 (MRCItem
-litem &377
+*557 (MRCItem
+litem &390
 pos 2
 dimension 100
 uid 76,0
 )
-*537 (MRCItem
-litem &378
+*558 (MRCItem
+litem &391
 pos 3
 dimension 50
 uid 77,0
 )
-*538 (MRCItem
-litem &379
+*559 (MRCItem
+litem &392
 pos 4
 dimension 100
 uid 78,0
 )
-*539 (MRCItem
-litem &380
+*560 (MRCItem
+litem &393
 pos 5
 dimension 100
 uid 79,0
 )
-*540 (MRCItem
-litem &381
+*561 (MRCItem
+litem &394
 pos 6
 dimension 92
 uid 80,0
 )
-*541 (MRCItem
-litem &382
+*562 (MRCItem
+litem &395
 pos 7
 dimension 80
@@ -13423,36 +13938,36 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *542 (LEmptyRow
+emptyRow *563 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*543 (RefLabelRowHdr
-)
-*544 (TitleRowHdr
-)
-*545 (FilterRowHdr
-)
-*546 (RefLabelColHdr
+*564 (RefLabelRowHdr
+)
+*565 (TitleRowHdr
+)
+*566 (FilterRowHdr
+)
+*567 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*547 (RowExpandColHdr
+*568 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*548 (GroupColHdr
+*569 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*549 (NameColHdr
+*570 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*550 (TypeColHdr
+*571 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*551 (InitColHdr
+*572 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*552 (PragmaColHdr
+*573 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*553 (EolColHdr
+*574 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
@@ -13464,5 +13979,5 @@
 uid 95,0
 optionalChildren [
-*554 (Sheet
+*575 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -13481,6 +13996,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *555 (MRCItem
-litem &542
+emptyMRCItem *576 (MRCItem
+litem &563
 pos 0
 dimension 20
@@ -13488,18 +14003,18 @@
 uid 97,0
 optionalChildren [
-*556 (MRCItem
-litem &543
+*577 (MRCItem
+litem &564
 pos 0
 dimension 20
 uid 98,0
 )
-*557 (MRCItem
-litem &544
+*578 (MRCItem
+litem &565
 pos 1
 dimension 23
 uid 99,0
 )
-*558 (MRCItem
-litem &545
+*579 (MRCItem
+litem &566
 pos 2
 hidden 1
@@ -13518,42 +14033,42 @@
 uid 101,0
 optionalChildren [
-*559 (MRCItem
-litem &546
+*580 (MRCItem
+litem &567
 pos 0
 dimension 20
 uid 102,0
 )
-*560 (MRCItem
-litem &548
+*581 (MRCItem
+litem &569
 pos 1
 dimension 50
 uid 103,0
 )
-*561 (MRCItem
-litem &549
+*582 (MRCItem
+litem &570
 pos 2
 dimension 100
 uid 104,0
 )
-*562 (MRCItem
-litem &550
+*583 (MRCItem
+litem &571
 pos 3
 dimension 100
 uid 105,0
 )
-*563 (MRCItem
-litem &551
+*584 (MRCItem
+litem &572
 pos 4
 dimension 50
 uid 106,0
 )
-*564 (MRCItem
-litem &552
+*585 (MRCItem
+litem &573
 pos 5
 dimension 50
 uid 107,0
 )
-*565 (MRCItem
-litem &553
+*586 (MRCItem
+litem &574
 pos 6
 dimension 80
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak	(revision 10073)
@@ -109,21 +109,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -141,25 +141,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
 )
 (vvPair
 variable "date"
-value "27.08.2010"
+value "03.01.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Mo"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Montag"
 )
 (vvPair
 variable "dd"
-value "27"
+value "03"
 )
 (vvPair
@@ -221,5 +221,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -229,17 +229,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
 )
 (vvPair
@@ -297,5 +297,5 @@
 (vvPair
 variable "time"
-value "16:35:54"
+value "16:57:01"
 )
 (vvPair
@@ -317,9 +317,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -349,5 +349,5 @@
 bg "0,0,32768"
 )
-xt "99200,4000,108900,5000"
+xt "99200,4000,108700,5000"
 st "
 by %user on %dd %month %year
@@ -1509,5 +1509,5 @@
 n "RSRLOAD"
 t "std_logic"
-o 26
+o 25
 suid 56,0
 i "'0'"
@@ -1545,5 +1545,5 @@
 n "SRCLK"
 t "std_logic"
-o 27
+o 26
 suid 57,0
 i "'0'"
@@ -1849,43 +1849,4 @@
 )
 *46 (CptPort
-uid 10250,0
-ps "OnEdgeStrategy"
-shape (Triangle
-uid 10251,0
-ro 90
-va (VaSet
-vasetType 1
-fg "0,65535,0"
-)
-xt "80000,137625,80750,138375"
-)
-tg (CPTG
-uid 10252,0
-ps "CptPortTextPlaceStrategy"
-stg "RightVerticalLayoutStrategy"
-f (Text
-uid 10253,0
-va (VaSet
-)
-xt "71700,137500,79000,138500"
-st "DCM_status : (7:0)"
-ju 2
-blo "79000,138300"
-)
-)
-thePort (LogicalPort
-m 1
-decl (Decl
-n "DCM_status"
-t "std_logic_vector"
-b "(7 downto 0)"
-preAdd 0
-posAdd 0
-o 18
-suid 75,0
-)
-)
-)
-*47 (CptPort
 uid 10254,0
 ps "OnEdgeStrategy"
@@ -1918,10 +1879,10 @@
 n "LOCKED_extraOUT"
 t "std_logic"
-o 19
+o 18
 suid 70,0
 )
 )
 )
-*48 (CptPort
+*47 (CptPort
 uid 10258,0
 ps "OnEdgeStrategy"
@@ -1963,5 +1924,5 @@
 )
 )
-*49 (CptPort
+*48 (CptPort
 uid 10262,0
 ps "OnEdgeStrategy"
@@ -1994,10 +1955,10 @@
 n "PS_DIR_IN"
 t "std_logic"
-o 24
+o 23
 suid 80,0
 )
 )
 )
-*50 (CptPort
+*49 (CptPort
 uid 10266,0
 ps "OnEdgeStrategy"
@@ -2030,10 +1991,10 @@
 n "PS_DO_IN"
 t "std_logic"
-o 25
+o 24
 suid 81,0
 )
 )
 )
-*51 (CptPort
+*50 (CptPort
 uid 10270,0
 ps "OnEdgeStrategy"
@@ -2066,10 +2027,10 @@
 n "PSCLK_OUT"
 t "std_logic"
-o 20
+o 19
 suid 74,0
 )
 )
 )
-*52 (CptPort
+*51 (CptPort
 uid 10274,0
 ps "OnEdgeStrategy"
@@ -2102,10 +2063,10 @@
 n "PSDONE_extraOUT"
 t "std_logic"
-o 21
+o 20
 suid 71,0
 )
 )
 )
-*53 (CptPort
+*52 (CptPort
 uid 10278,0
 ps "OnEdgeStrategy"
@@ -2138,10 +2099,10 @@
 n "PSEN_OUT"
 t "std_logic"
-o 22
+o 21
 suid 73,0
 )
 )
 )
-*54 (CptPort
+*53 (CptPort
 uid 10282,0
 ps "OnEdgeStrategy"
@@ -2174,10 +2135,10 @@
 n "PSINCDEC_OUT"
 t "std_logic"
-o 23
+o 22
 suid 72,0
 )
 )
 )
-*55 (CptPort
+*54 (CptPort
 uid 10286,0
 ps "OnEdgeStrategy"
@@ -2218,5 +2179,5 @@
 )
 )
-*56 (CptPort
+*55 (CptPort
 uid 10290,0
 ps "OnEdgeStrategy"
@@ -2258,5 +2219,5 @@
 )
 )
-*57 (CptPort
+*56 (CptPort
 uid 10320,0
 ps "OnEdgeStrategy"
@@ -2294,5 +2255,5 @@
 )
 )
-*58 (CptPort
+*57 (CptPort
 uid 10324,0
 ps "OnEdgeStrategy"
@@ -2330,5 +2291,5 @@
 )
 )
-*59 (CptPort
+*58 (CptPort
 uid 10328,0
 ps "OnEdgeStrategy"
@@ -2366,4 +2327,41 @@
 )
 )
+*59 (CptPort
+uid 12314,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 12315,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "80000,139625,80750,140375"
+)
+tg (CPTG
+uid 12316,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 12317,0
+va (VaSet
+)
+xt "75300,139500,79000,140500"
+st "SRIN_out"
+ju 2
+blo "79000,140300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 27
+suid 85,0
+i "'0'"
+)
+)
+)
 ]
 shape (Rectangle
@@ -2375,5 +2373,5 @@
 lineWidth 2
 )
-xt "52000,66000,80000,140000"
+xt "52000,66000,80000,141000"
 )
 oxt "15000,-1000,43000,27000"
@@ -2445,5 +2443,5 @@
 fg "49152,49152,49152"
 )
-xt "52250,138250,53750,139750"
+xt "52250,139250,53750,140750"
 iconName "BlockDiagram.png"
 iconMaskName "BlockDiagram.msk"
@@ -2642,5 +2640,5 @@
 preAdd 0
 posAdd 0
-o 55
+o 69
 suid 5,0
 )
@@ -2650,7 +2648,6 @@
 font "Courier New,8,0"
 )
-xt "39000,57600,67500,58400"
-st "SIGNAL board_id        : std_logic_vector(3 downto 0)
-"
+xt "39000,61600,67500,62400"
+st "SIGNAL board_id        : std_logic_vector(3 downto 0)"
 )
 )
@@ -2661,5 +2658,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 56
+o 70
 suid 6,0
 )
@@ -2669,7 +2666,6 @@
 font "Courier New,8,0"
 )
-xt "39000,58400,67500,59200"
-st "SIGNAL crate_id        : std_logic_vector(1 downto 0)
-"
+xt "39000,62400,67500,63200"
+st "SIGNAL crate_id        : std_logic_vector(1 downto 0)"
 )
 )
@@ -2985,5 +2981,5 @@
 n "adc_data_array"
 t "adc_data_array_type"
-o 54
+o 68
 suid 29,0
 )
@@ -2993,7 +2989,6 @@
 font "Courier New,8,0"
 )
-xt "39000,56800,63000,57600"
-st "SIGNAL adc_data_array  : adc_data_array_type
-"
+xt "39000,60800,63000,61600"
+st "SIGNAL adc_data_array  : adc_data_array_type"
 )
 )
@@ -3003,5 +2998,5 @@
 n "RSRLOAD"
 t "std_logic"
-o 35
+o 37
 suid 57,0
 i "'0'"
@@ -3012,7 +3007,6 @@
 font "Courier New,8,0"
 )
-xt "39000,31000,68500,31800"
-st "RSRLOAD         : std_logic                      := '0'
-"
+xt "39000,34200,68500,35000"
+st "RSRLOAD         : std_logic                      := '0'"
 )
 )
@@ -3067,5 +3061,5 @@
 n "SRCLK"
 t "std_logic"
-o 52
+o 66
 suid 58,0
 i "'0'"
@@ -3076,7 +3070,6 @@
 font "Courier New,8,0"
 )
-xt "39000,55200,72000,56000"
-st "SIGNAL SRCLK           : std_logic                      := '0'
-"
+xt "39000,59200,72000,60000"
+st "SIGNAL SRCLK           : std_logic                      := '0'"
 )
 )
@@ -3087,5 +3080,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 59
+o 74
 suid 65,0
 )
@@ -3095,7 +3088,6 @@
 font "Courier New,8,0"
 )
-xt "39000,61600,67500,62400"
-st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)
-"
+xt "39000,65600,67500,66400"
+st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)"
 )
 )
@@ -3105,5 +3097,5 @@
 n "DAC_CS"
 t "std_logic"
-o 21
+o 22
 suid 66,0
 )
@@ -3113,7 +3105,6 @@
 font "Courier New,8,0"
 )
-xt "39000,19800,54000,20600"
-st "DAC_CS          : std_logic
-"
+xt "39000,22200,54000,23000"
+st "DAC_CS          : std_logic"
 )
 )
@@ -3178,7 +3169,6 @@
 font "Courier New,8,0"
 )
-xt "39000,13400,54000,14200"
-st "X_50M           : STD_LOGIC
-"
+xt "39000,15800,54000,16600"
+st "X_50M           : STD_LOGIC"
 )
 )
@@ -3196,7 +3186,6 @@
 font "Courier New,8,0"
 )
-xt "39000,11800,54000,12600"
-st "TRG             : STD_LOGIC
-"
+xt "39000,14200,54000,15000"
+st "TRG             : STD_LOGIC"
 )
 )
@@ -3298,5 +3287,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 16
+o 17
 suid 71,0
 )
@@ -3306,7 +3295,6 @@
 font "Courier New,8,0"
 )
-xt "39000,15800,64000,16600"
-st "A_CLK           : std_logic_vector(3 downto 0)
-"
+xt "39000,18200,64000,19000"
+st "A_CLK           : std_logic_vector(3 downto 0)"
 )
 )
@@ -3316,5 +3304,5 @@
 n "CLK_25_PS"
 t "std_logic"
-o 50
+o 55
 suid 72,0
 )
@@ -3324,7 +3312,6 @@
 font "Courier New,8,0"
 )
-xt "39000,46400,57500,47200"
-st "SIGNAL CLK_25_PS       : std_logic
-"
+xt "39000,50400,57500,51200"
+st "SIGNAL CLK_25_PS       : std_logic"
 )
 )
@@ -3381,5 +3368,5 @@
 preAdd 0
 posAdd 0
-o 30
+o 31
 suid 73,0
 )
@@ -3389,7 +3376,6 @@
 font "Courier New,8,0"
 )
-xt "39000,27000,54000,27800"
-st "OE_ADC          : STD_LOGIC
-"
+xt "39000,29400,54000,30200"
+st "OE_ADC          : STD_LOGIC"
 )
 )
@@ -3454,6 +3440,5 @@
 )
 xt "39000,7000,64000,7800"
-st "A_OTR           : std_logic_vector(3 DOWNTO 0)
-"
+st "A_OTR           : std_logic_vector(3 DOWNTO 0)"
 )
 )
@@ -3744,6 +3729,5 @@
 )
 xt "39000,3800,64500,4600"
-st "A0_D            : std_logic_vector(11 DOWNTO 0)
-"
+st "A0_D            : std_logic_vector(11 DOWNTO 0)"
 )
 )
@@ -3763,6 +3747,5 @@
 )
 xt "39000,4600,64500,5400"
-st "A1_D            : std_logic_vector(11 DOWNTO 0)
-"
+st "A1_D            : std_logic_vector(11 DOWNTO 0)"
 )
 )
@@ -3782,6 +3765,5 @@
 )
 xt "39000,5400,64500,6200"
-st "A2_D            : std_logic_vector(11 DOWNTO 0)
-"
+st "A2_D            : std_logic_vector(11 DOWNTO 0)"
 )
 )
@@ -3801,6 +3783,5 @@
 )
 xt "39000,6200,64500,7000"
-st "A3_D            : std_logic_vector(11 DOWNTO 0)
-"
+st "A3_D            : std_logic_vector(11 DOWNTO 0)"
 )
 )
@@ -3901,5 +3882,5 @@
 n "D0_SRCLK"
 t "STD_LOGIC"
-o 17
+o 18
 suid 87,0
 )
@@ -3909,7 +3890,6 @@
 font "Courier New,8,0"
 )
-xt "39000,16600,54000,17400"
-st "D0_SRCLK        : STD_LOGIC
-"
+xt "39000,19000,54000,19800"
+st "D0_SRCLK        : STD_LOGIC"
 )
 )
@@ -3919,5 +3899,5 @@
 n "D1_SRCLK"
 t "STD_LOGIC"
-o 18
+o 19
 suid 88,0
 )
@@ -3927,7 +3907,6 @@
 font "Courier New,8,0"
 )
-xt "39000,17400,54000,18200"
-st "D1_SRCLK        : STD_LOGIC
-"
+xt "39000,19800,54000,20600"
+st "D1_SRCLK        : STD_LOGIC"
 )
 )
@@ -3937,5 +3916,5 @@
 n "D2_SRCLK"
 t "STD_LOGIC"
-o 19
+o 20
 suid 89,0
 )
@@ -3945,7 +3924,6 @@
 font "Courier New,8,0"
 )
-xt "39000,18200,54000,19000"
-st "D2_SRCLK        : STD_LOGIC
-"
+xt "39000,20600,54000,21400"
+st "D2_SRCLK        : STD_LOGIC"
 )
 )
@@ -3955,5 +3933,5 @@
 n "D3_SRCLK"
 t "STD_LOGIC"
-o 20
+o 21
 suid 90,0
 )
@@ -3963,7 +3941,6 @@
 font "Courier New,8,0"
 )
-xt "39000,19000,54000,19800"
-st "D3_SRCLK        : STD_LOGIC
-"
+xt "39000,21400,54000,22200"
+st "D3_SRCLK        : STD_LOGIC"
 )
 )
@@ -4162,6 +4139,5 @@
 )
 xt "39000,7800,54000,8600"
-st "D0_SROUT        : std_logic
-"
+st "D0_SROUT        : std_logic"
 )
 )
@@ -4180,6 +4156,5 @@
 )
 xt "39000,8600,54000,9400"
-st "D1_SROUT        : std_logic
-"
+st "D1_SROUT        : std_logic"
 )
 )
@@ -4198,6 +4173,5 @@
 )
 xt "39000,9400,54000,10200"
-st "D2_SROUT        : std_logic
-"
+st "D2_SROUT        : std_logic"
 )
 )
@@ -4216,6 +4190,5 @@
 )
 xt "39000,10200,54000,11000"
-st "D3_SROUT        : std_logic
-"
+st "D3_SROUT        : std_logic"
 )
 )
@@ -4271,5 +4244,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 24
+o 25
 suid 95,0
 i "(others => '0')"
@@ -4280,7 +4253,6 @@
 font "Courier New,8,0"
 )
-xt "39000,22200,74500,23000"
-st "D_A             : std_logic_vector(3 DOWNTO 0)   := (others => '0')
-"
+xt "39000,24600,74500,25400"
+st "D_A             : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
 )
 )
@@ -4335,5 +4307,5 @@
 n "DWRITE"
 t "std_logic"
-o 23
+o 24
 suid 96,0
 i "'0'"
@@ -4344,7 +4316,6 @@
 font "Courier New,8,0"
 )
-xt "39000,21400,68500,22200"
-st "DWRITE          : std_logic                      := '0'
-"
+xt "39000,23800,68500,24600"
+st "DWRITE          : std_logic                      := '0'"
 )
 )
@@ -4665,5 +4636,5 @@
 n "T0_CS"
 t "std_logic"
-o 38
+o 40
 suid 101,0
 )
@@ -4673,7 +4644,6 @@
 font "Courier New,8,0"
 )
-xt "39000,33400,54000,34200"
-st "T0_CS           : std_logic
-"
+xt "39000,37400,54000,38200"
+st "T0_CS           : std_logic"
 )
 )
@@ -4683,5 +4653,5 @@
 n "T1_CS"
 t "std_logic"
-o 39
+o 41
 suid 102,0
 )
@@ -4691,7 +4661,6 @@
 font "Courier New,8,0"
 )
-xt "39000,34200,54000,35000"
-st "T1_CS           : std_logic
-"
+xt "39000,38200,54000,39000"
+st "T1_CS           : std_logic"
 )
 )
@@ -4701,5 +4670,5 @@
 n "T2_CS"
 t "std_logic"
-o 40
+o 42
 suid 103,0
 )
@@ -4709,7 +4678,6 @@
 font "Courier New,8,0"
 )
-xt "39000,35000,54000,35800"
-st "T2_CS           : std_logic
-"
+xt "39000,39000,54000,39800"
+st "T2_CS           : std_logic"
 )
 )
@@ -4719,5 +4687,5 @@
 n "T3_CS"
 t "std_logic"
-o 41
+o 43
 suid 104,0
 )
@@ -4727,7 +4695,6 @@
 font "Courier New,8,0"
 )
-xt "39000,35800,54000,36600"
-st "T3_CS           : std_logic
-"
+xt "39000,39800,54000,40600"
+st "T3_CS           : std_logic"
 )
 )
@@ -4781,5 +4748,5 @@
 n "S_CLK"
 t "std_logic"
-o 37
+o 39
 suid 105,0
 )
@@ -4789,7 +4756,6 @@
 font "Courier New,8,0"
 )
-xt "39000,32600,54000,33400"
-st "S_CLK           : std_logic
-"
+xt "39000,36600,54000,37400"
+st "S_CLK           : std_logic"
 )
 )
@@ -4800,5 +4766,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 43
+o 45
 suid 106,0
 )
@@ -4808,7 +4774,6 @@
 font "Courier New,8,0"
 )
-xt "39000,37400,64000,38200"
-st "W_A             : std_logic_vector(9 DOWNTO 0)
-"
+xt "39000,41400,64000,42200"
+st "W_A             : std_logic_vector(9 DOWNTO 0)"
 )
 )
@@ -4819,5 +4784,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 49
+o 51
 suid 107,0
 )
@@ -4827,7 +4792,6 @@
 font "Courier New,8,0"
 )
-xt "39000,42200,64500,43000"
-st "W_D             : std_logic_vector(15 DOWNTO 0)
-"
+xt "39000,46200,64500,47000"
+st "W_D             : std_logic_vector(15 DOWNTO 0)"
 )
 )
@@ -4837,5 +4801,5 @@
 n "W_RES"
 t "std_logic"
-o 46
+o 48
 suid 108,0
 i "'1'"
@@ -4846,7 +4810,6 @@
 font "Courier New,8,0"
 )
-xt "39000,39800,68500,40600"
-st "W_RES           : std_logic                      := '1'
-"
+xt "39000,43800,68500,44600"
+st "W_RES           : std_logic                      := '1'"
 )
 )
@@ -4856,5 +4819,5 @@
 n "W_RD"
 t "std_logic"
-o 45
+o 47
 suid 109,0
 i "'1'"
@@ -4865,7 +4828,6 @@
 font "Courier New,8,0"
 )
-xt "39000,39000,68500,39800"
-st "W_RD            : std_logic                      := '1'
-"
+xt "39000,43000,68500,43800"
+st "W_RD            : std_logic                      := '1'"
 )
 )
@@ -4875,5 +4837,5 @@
 n "W_WR"
 t "std_logic"
-o 47
+o 49
 suid 110,0
 i "'1'"
@@ -4884,7 +4846,6 @@
 font "Courier New,8,0"
 )
-xt "39000,40600,68500,41400"
-st "W_WR            : std_logic                      := '1'
-"
+xt "39000,44600,68500,45400"
+st "W_WR            : std_logic                      := '1'"
 )
 )
@@ -4902,7 +4863,6 @@
 font "Courier New,8,0"
 )
-xt "39000,12600,54000,13400"
-st "W_INT           : std_logic
-"
+xt "39000,15000,54000,15800"
+st "W_INT           : std_logic"
 )
 )
@@ -4912,5 +4872,5 @@
 n "W_CS"
 t "std_logic"
-o 44
+o 46
 suid 112,0
 i "'1'"
@@ -4921,7 +4881,6 @@
 font "Courier New,8,0"
 )
-xt "39000,38200,68500,39000"
-st "W_CS            : std_logic                      := '1'
-"
+xt "39000,42200,68500,43000"
+st "W_CS            : std_logic                      := '1'"
 )
 )
@@ -4973,5 +4932,5 @@
 n "MOSI"
 t "std_logic"
-o 29
+o 30
 suid 113,0
 i "'0'"
@@ -4982,7 +4941,6 @@
 font "Courier New,8,0"
 )
-xt "39000,26200,68500,27000"
-st "MOSI            : std_logic                      := '0'
-"
+xt "39000,28600,68500,29400"
+st "MOSI            : std_logic                      := '0'"
 )
 )
@@ -5038,5 +4996,5 @@
 preAdd 0
 posAdd 0
-o 48
+o 50
 suid 114,0
 )
@@ -5046,7 +5004,6 @@
 font "Courier New,8,0"
 )
-xt "39000,41400,54000,42200"
-st "MISO            : std_logic
-"
+xt "39000,45400,54000,46200"
+st "MISO            : std_logic"
 )
 )
@@ -5067,5 +5024,5 @@
 lineWidth 2
 )
-xt "82000,102000,100000,118000"
+xt "82000,106000,99000,118000"
 )
 oxt "0,0,18000,5000"
@@ -5074,12 +5031,15 @@
 va (VaSet
 )
-xt "82200,102200,98600,118200"
+xt "82200,106200,98600,118200"
 st "
 -- MISC 6     
 TRG_V <= '0';
-RS485_C_RE <= '1'; 
+RS485_C_RE <= '0'; 
 RS485_C_DE <= '0';   
-RS485_E_RE <= '1';      
+RS485_C_DO <= RS485_C_DI;
+
+RS485_E_RE <= '0';      
 RS485_E_DE <= '0'; 
+--RS485_E_DO <= RS485_E_DI;
 
 -- DENABLE <= '0'; -- domino wave stopped
@@ -5099,6 +5059,6 @@
 tm "HdlTextMgr"
 wrapOption 3
-visibleHeight 16000
-visibleWidth 18000
+visibleHeight 12000
+visibleWidth 17000
 )
 )
@@ -5558,5 +5518,5 @@
 n "TRG_V"
 t "std_logic"
-o 42
+o 44
 suid 126,0
 )
@@ -5566,7 +5526,6 @@
 font "Courier New,8,0"
 )
-xt "39000,36600,54000,37400"
-st "TRG_V           : std_logic
-"
+xt "39000,40600,54000,41400"
+st "TRG_V           : std_logic"
 )
 )
@@ -5576,5 +5535,5 @@
 n "RS485_C_RE"
 t "std_logic"
-o 32
+o 34
 suid 127,0
 )
@@ -5584,7 +5543,6 @@
 font "Courier New,8,0"
 )
-xt "39000,28600,54000,29400"
-st "RS485_C_RE      : std_logic
-"
+xt "39000,31800,54000,32600"
+st "RS485_C_RE      : std_logic"
 )
 )
@@ -5594,5 +5552,5 @@
 n "RS485_C_DE"
 t "std_logic"
-o 31
+o 32
 suid 128,0
 )
@@ -5602,7 +5560,6 @@
 font "Courier New,8,0"
 )
-xt "39000,27800,54000,28600"
-st "RS485_C_DE      : std_logic
-"
+xt "39000,30200,54000,31000"
+st "RS485_C_DE      : std_logic"
 )
 )
@@ -5612,5 +5569,5 @@
 n "RS485_E_RE"
 t "std_logic"
-o 34
+o 36
 suid 129,0
 )
@@ -5620,7 +5577,6 @@
 font "Courier New,8,0"
 )
-xt "39000,30200,54000,31000"
-st "RS485_E_RE      : std_logic
-"
+xt "39000,33400,54000,34200"
+st "RS485_E_RE      : std_logic"
 )
 )
@@ -5630,5 +5586,5 @@
 n "RS485_E_DE"
 t "std_logic"
-o 33
+o 35
 suid 130,0
 )
@@ -5638,7 +5594,6 @@
 font "Courier New,8,0"
 )
-xt "39000,29400,54000,30200"
-st "RS485_E_DE      : std_logic
-"
+xt "39000,32600,54000,33400"
+st "RS485_E_DE      : std_logic"
 )
 )
@@ -5648,5 +5603,5 @@
 n "DENABLE"
 t "std_logic"
-o 22
+o 23
 suid 131,0
 i "'0'"
@@ -5657,7 +5612,6 @@
 font "Courier New,8,0"
 )
-xt "39000,20600,68500,21400"
-st "DENABLE         : std_logic                      := '0'
-"
+xt "39000,23000,68500,23800"
+st "DENABLE         : std_logic                      := '0'"
 )
 )
@@ -5667,5 +5621,5 @@
 n "SRIN"
 t "std_logic"
-o 36
+o 38
 suid 132,0
 )
@@ -5675,7 +5629,6 @@
 font "Courier New,8,0"
 )
-xt "39000,31800,54000,32600"
-st "SRIN            : std_logic
-"
+xt "39000,35000,54000,35800"
+st "SRIN            : std_logic"
 )
 )
@@ -5685,5 +5638,5 @@
 n "EE_CS"
 t "std_logic"
-o 27
+o 28
 suid 133,0
 )
@@ -5693,7 +5646,6 @@
 font "Courier New,8,0"
 )
-xt "39000,24600,54000,25400"
-st "EE_CS           : std_logic
-"
+xt "39000,27000,54000,27800"
+st "EE_CS           : std_logic"
 )
 )
@@ -5704,5 +5656,5 @@
 t "std_logic_vector"
 b "( 2 DOWNTO 0 )"
-o 28
+o 29
 suid 134,0
 i "(others => '1')"
@@ -5713,7 +5665,6 @@
 font "Courier New,8,0"
 )
-xt "39000,25400,74500,26200"
-st "LED             : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')
-"
+xt "39000,27800,74500,28600"
+st "LED             : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')"
 )
 )
@@ -5948,5 +5899,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 25
+o 26
 suid 141,0
 i "(OTHERS => '0')"
@@ -5957,7 +5908,6 @@
 font "Courier New,8,0"
 )
-xt "39000,23000,74500,23800"
-st "D_T             : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
-"
+xt "39000,25400,74500,26200"
+st "D_T             : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
 )
 )
@@ -6022,6 +5972,5 @@
 )
 xt "39000,11000,64000,11800"
-st "D_PLLLCK        : std_logic_vector(3 DOWNTO 0)
-"
+st "D_PLLLCK        : std_logic_vector(3 DOWNTO 0)"
 )
 )
@@ -6076,5 +6025,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 26
+o 27
 suid 154,0
 i "(others => '0')"
@@ -6085,7 +6034,6 @@
 font "Courier New,8,0"
 )
-xt "39000,23800,74500,24600"
-st "D_T2            : std_logic_vector(3 DOWNTO 0)   := (others => '0')
-"
+xt "39000,26200,74500,27000"
+st "D_T2            : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
 )
 )
@@ -6316,5 +6264,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 15
+o 16
 suid 155,0
 i "(OTHERS => '0')"
@@ -6325,7 +6273,6 @@
 font "Courier New,8,0"
 )
-xt "39000,15000,74500,15800"
-st "A1_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
-"
+xt "39000,17400,74500,18200"
+st "A1_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
 )
 )
@@ -6335,5 +6282,5 @@
 n "dummy"
 t "std_logic"
-o 58
+o 72
 suid 157,0
 )
@@ -6343,7 +6290,6 @@
 font "Courier New,8,0"
 )
-xt "39000,60000,57500,60800"
-st "SIGNAL dummy           : std_logic
-"
+xt "39000,64000,57500,64800"
+st "SIGNAL dummy           : std_logic"
 )
 )
@@ -6408,5 +6354,5 @@
 n "s"
 t "std_logic"
-o 58
+o 72
 suid 1,0
 )
@@ -6473,5 +6419,5 @@
 n "t"
 t "std_logic"
-o 21
+o 22
 suid 2,0
 )
@@ -6671,5 +6617,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 57
+o 71
 suid 159,0
 i "(others => '0')"
@@ -6680,7 +6626,6 @@
 font "Courier New,8,0"
 )
-xt "39000,59200,78000,60000"
-st "SIGNAL drs_channel_id  : std_logic_vector(3 downto 0)   := (others => '0')
-"
+xt "39000,63200,78000,64000"
+st "SIGNAL drs_channel_id  : std_logic_vector(3 downto 0)   := (others => '0')"
 )
 )
@@ -6690,5 +6635,5 @@
 n "CLK_50"
 t "std_logic"
-o 51
+o 57
 suid 163,0
 )
@@ -6698,7 +6643,6 @@
 font "Courier New,8,0"
 )
-xt "39000,48000,57500,48800"
-st "SIGNAL CLK_50          : std_logic
-"
+xt "39000,52000,57500,52800"
+st "SIGNAL CLK_50          : std_logic"
 )
 )
@@ -6761,5 +6705,5 @@
 n "dout"
 t "std_logic"
-o 50
+o 55
 suid 1,0
 )
@@ -6815,5 +6759,5 @@
 n "din0"
 t "std_logic"
-o 59
+o 67
 suid 2,0
 i "'0'"
@@ -6870,5 +6814,5 @@
 n "din1"
 t "std_logic"
-o 58
+o 56
 suid 3,0
 )
@@ -7075,5 +7019,5 @@
 n "CLK_25_PS1"
 t "std_logic"
-o 58
+o 56
 suid 164,0
 )
@@ -7083,7 +7027,6 @@
 font "Courier New,8,0"
 )
-xt "39000,47200,57500,48000"
-st "SIGNAL CLK_25_PS1      : std_logic
-"
+xt "39000,51200,57500,52000"
+st "SIGNAL CLK_25_PS1      : std_logic"
 )
 )
@@ -7093,5 +7036,5 @@
 n "adc_clk_en"
 t "std_logic"
-o 59
+o 67
 suid 165,0
 i "'0'"
@@ -7102,7 +7045,6 @@
 font "Courier New,8,0"
 )
-xt "39000,56000,72000,56800"
-st "SIGNAL adc_clk_en      : std_logic                      := '0'
-"
+xt "39000,60000,72000,60800"
+st "SIGNAL adc_clk_en      : std_logic                      := '0'"
 )
 )
@@ -7157,5 +7099,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 60
+o 15
 suid 166,0
 i "(others => '0')"
@@ -7166,7 +7108,6 @@
 font "Courier New,8,0"
 )
-xt "39000,14200,74500,15000"
-st "A0_T            : std_logic_vector(7 DOWNTO 0)   := (others => '0')
-"
+xt "39000,16600,74500,17400"
+st "A0_T            : std_logic_vector(7 DOWNTO 0)   := (others => '0')"
 )
 )
@@ -7281,5 +7222,5 @@
 n "CLK50_OUT"
 t "std_logic"
-o 61
+o 54
 suid 184,0
 )
@@ -7289,7 +7230,6 @@
 font "Courier New,8,0"
 )
-xt "39000,45600,57500,46400"
-st "SIGNAL CLK50_OUT       : std_logic
-"
+xt "39000,49600,57500,50400"
+st "SIGNAL CLK50_OUT       : std_logic"
 )
 )
@@ -7299,5 +7239,5 @@
 n "CLK25_OUT"
 t "std_logic"
-o 62
+o 52
 suid 185,0
 )
@@ -7307,7 +7247,6 @@
 font "Courier New,8,0"
 )
-xt "39000,44000,57500,44800"
-st "SIGNAL CLK25_OUT       : std_logic
-"
+xt "39000,48000,57500,48800"
+st "SIGNAL CLK25_OUT       : std_logic"
 )
 )
@@ -7317,5 +7256,5 @@
 n "CLK25_PSOUT"
 t "std_logic"
-o 63
+o 53
 suid 186,0
 )
@@ -7325,7 +7264,6 @@
 font "Courier New,8,0"
 )
-xt "39000,44800,57500,45600"
-st "SIGNAL CLK25_PSOUT     : std_logic
-"
+xt "39000,48800,57500,49600"
+st "SIGNAL CLK25_PSOUT     : std_logic"
 )
 )
@@ -7343,7 +7281,6 @@
 font "Courier New,8,0"
 )
-xt "39000,53600,57500,54400"
-st "SIGNAL PS_DIR_IN       : std_logic
-"
+xt "39000,57600,57500,58400"
+st "SIGNAL PS_DIR_IN       : std_logic"
 )
 )
@@ -7361,7 +7298,6 @@
 font "Courier New,8,0"
 )
-xt "39000,54400,57500,55200"
-st "SIGNAL PS_DO_IN        : std_logic
-"
+xt "39000,58400,57500,59200"
+st "SIGNAL PS_DO_IN        : std_logic"
 )
 )
@@ -7371,5 +7307,5 @@
 n "PSEN_OUT"
 t "std_logic"
-o 66
+o 62
 suid 189,0
 )
@@ -7379,7 +7315,6 @@
 font "Courier New,8,0"
 )
-xt "39000,52000,57500,52800"
-st "SIGNAL PSEN_OUT        : std_logic
-"
+xt "39000,56000,57500,56800"
+st "SIGNAL PSEN_OUT        : std_logic"
 )
 )
@@ -7389,5 +7324,5 @@
 n "PSINCDEC_OUT"
 t "std_logic"
-o 67
+o 63
 suid 190,0
 )
@@ -7397,7 +7332,6 @@
 font "Courier New,8,0"
 )
-xt "39000,52800,57500,53600"
-st "SIGNAL PSINCDEC_OUT    : std_logic
-"
+xt "39000,56800,57500,57600"
+st "SIGNAL PSINCDEC_OUT    : std_logic"
 )
 )
@@ -7409,5 +7343,5 @@
 preAdd 0
 posAdd 0
-o 68
+o 58
 suid 191,0
 )
@@ -7417,7 +7351,6 @@
 font "Courier New,8,0"
 )
-xt "39000,48800,57500,49600"
-st "SIGNAL DCM_locked      : std_logic
-"
+xt "39000,52800,57500,53600"
+st "SIGNAL DCM_locked      : std_logic"
 )
 )
@@ -7429,5 +7362,5 @@
 preAdd 0
 posAdd 0
-o 69
+o 73
 suid 192,0
 i "'0'"
@@ -7438,7 +7371,6 @@
 font "Courier New,8,0"
 )
-xt "39000,60800,72000,61600"
-st "SIGNAL ready           : std_logic                      := '0'
-"
+xt "39000,64800,72000,65600"
+st "SIGNAL ready           : std_logic                      := '0'"
 )
 )
@@ -7451,5 +7383,5 @@
 preAdd 0
 posAdd 0
-o 70
+o 75
 suid 193,0
 i "'0'"
@@ -7460,8 +7392,7 @@
 font "Courier New,8,0"
 )
-xt "39000,62400,72000,64000"
+xt "39000,66400,72000,68000"
 st "-- status:
-SIGNAL shifting        : std_logic                      := '0'
-"
+SIGNAL shifting        : std_logic                      := '0'"
 )
 )
@@ -7471,5 +7402,5 @@
 n "PSDONE_extraOUT"
 t "std_logic"
-o 71
+o 61
 suid 194,0
 )
@@ -7479,7 +7410,6 @@
 font "Courier New,8,0"
 )
-xt "39000,51200,57500,52000"
-st "SIGNAL PSDONE_extraOUT : std_logic
-"
+xt "39000,55200,57500,56000"
+st "SIGNAL PSDONE_extraOUT : std_logic"
 )
 )
@@ -7489,5 +7419,5 @@
 n "PSCLK_OUT"
 t "std_logic"
-o 72
+o 60
 suid 195,0
 )
@@ -7497,7 +7427,6 @@
 font "Courier New,8,0"
 )
-xt "39000,50400,57500,51200"
-st "SIGNAL PSCLK_OUT       : std_logic
-"
+xt "39000,54400,57500,55200"
+st "SIGNAL PSCLK_OUT       : std_logic"
 )
 )
@@ -7507,5 +7436,5 @@
 n "LOCKED_extraOUT"
 t "std_logic"
-o 73
+o 59
 suid 196,0
 )
@@ -7515,10 +7444,317 @@
 font "Courier New,8,0"
 )
-xt "39000,49600,57500,50400"
-st "SIGNAL LOCKED_extraOUT : std_logic
-"
-)
-)
-*252 (Wire
+xt "39000,53600,57500,54400"
+st "SIGNAL LOCKED_extraOUT : std_logic"
+)
+)
+*252 (PortIoIn
+uid 11090,0
+shape (CompositeShape
+uid 11091,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11092,0
+sl 0
+ro 270
+xt "94000,102625,95500,103375"
+)
+(Line
+uid 11093,0
+sl 0
+ro 270
+xt "95500,103000,96000,103000"
+pts [
+"95500,103000"
+"96000,103000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 11094,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11095,0
+va (VaSet
+)
+xt "87700,102500,93000,103500"
+st "RS485_C_DI"
+ju 2
+blo "93000,103300"
+tm "WireNameMgr"
+)
+)
+)
+*253 (Net
+uid 11102,0
+decl (Decl
+n "RS485_C_DI"
+t "std_logic"
+o 74
+suid 197,0
+)
+declText (MLText
+uid 11103,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "39000,11800,54000,12600"
+st "RS485_C_DI      : std_logic"
+)
+)
+*254 (PortIoOut
+uid 11104,0
+shape (CompositeShape
+uid 11105,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11106,0
+sl 0
+ro 270
+xt "111500,111625,113000,112375"
+)
+(Line
+uid 11107,0
+sl 0
+ro 270
+xt "111000,112000,111500,112000"
+pts [
+"111000,112000"
+"111500,112000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 11108,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11109,0
+va (VaSet
+)
+xt "114000,111500,119700,112500"
+st "RS485_C_DO"
+blo "114000,112300"
+tm "WireNameMgr"
+)
+)
+)
+*255 (Net
+uid 11116,0
+decl (Decl
+n "RS485_C_DO"
+t "std_logic"
+o 75
+suid 198,0
+)
+declText (MLText
+uid 11117,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "39000,31000,54000,31800"
+st "RS485_C_DO      : std_logic"
+)
+)
+*256 (PortIoIn
+uid 11508,0
+shape (CompositeShape
+uid 11509,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11510,0
+sl 0
+ro 270
+xt "121000,115625,122500,116375"
+)
+(Line
+uid 11511,0
+sl 0
+ro 270
+xt "122500,116000,123000,116000"
+pts [
+"122500,116000"
+"123000,116000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 11512,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11513,0
+va (VaSet
+)
+xt "114800,115500,120000,116500"
+st "RS485_E_DI"
+ju 2
+blo "120000,116300"
+tm "WireNameMgr"
+)
+)
+)
+*257 (Net
+uid 11520,0
+decl (Decl
+n "RS485_E_DI"
+t "std_logic"
+o 76
+suid 200,0
+)
+declText (MLText
+uid 11521,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "39000,12600,54000,13400"
+st "RS485_E_DI      : std_logic"
+)
+)
+*258 (Net
+uid 11534,0
+decl (Decl
+n "RS485_E_DO"
+t "std_logic"
+o 77
+suid 201,0
+)
+declText (MLText
+uid 11535,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "39000,13400,54000,14200"
+st "RS485_E_DO      : std_logic"
+)
+)
+*259 (PortIoIn
+uid 11922,0
+shape (CompositeShape
+uid 11923,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11924,0
+sl 0
+ro 90
+xt "126500,113625,128000,114375"
+)
+(Line
+uid 11925,0
+sl 0
+ro 90
+xt "126000,114000,126500,114000"
+pts [
+"126500,114000"
+"126000,114000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 11926,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11927,0
+va (VaSet
+)
+xt "129000,113500,134600,114500"
+st "RS485_E_DO"
+blo "129000,114300"
+tm "WireNameMgr"
+)
+)
+)
+*260 (Net
+uid 12318,0
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 78
+suid 202,0
+i "'0'"
+)
+declText (MLText
+uid 12319,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "39000,35800,68500,36600"
+st "SRIN_out        : std_logic                      := '0'"
+)
+)
+*261 (PortIoOut
+uid 12326,0
+shape (CompositeShape
+uid 12327,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 12328,0
+sl 0
+ro 270
+xt "87500,139625,89000,140375"
+)
+(Line
+uid 12329,0
+sl 0
+ro 270
+xt "87000,140000,87500,140000"
+pts [
+"87000,140000"
+"87500,140000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 12330,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 12331,0
+va (VaSet
+)
+xt "90000,139500,93700,140500"
+st "SRIN_out"
+blo "90000,140300"
+tm "WireNameMgr"
+)
+)
+)
+*262 (Wire
 uid 245,0
 shape (OrthoPolyLine
@@ -7559,5 +7795,5 @@
 on &85
 )
-*253 (Wire
+*263 (Wire
 uid 277,0
 shape (OrthoPolyLine
@@ -7597,5 +7833,5 @@
 on &69
 )
-*254 (Wire
+*264 (Wire
 uid 285,0
 shape (OrthoPolyLine
@@ -7635,5 +7871,5 @@
 on &70
 )
-*255 (Wire
+*265 (Wire
 uid 362,0
 shape (OrthoPolyLine
@@ -7673,5 +7909,5 @@
 on &94
 )
-*256 (Wire
+*266 (Wire
 uid 418,0
 shape (OrthoPolyLine
@@ -7711,5 +7947,5 @@
 on &146
 )
-*257 (Wire
+*267 (Wire
 uid 426,0
 shape (OrthoPolyLine
@@ -7751,5 +7987,5 @@
 on &144
 )
-*258 (Wire
+*268 (Wire
 uid 434,0
 shape (OrthoPolyLine
@@ -7789,5 +8025,5 @@
 on &150
 )
-*259 (Wire
+*269 (Wire
 uid 442,0
 shape (OrthoPolyLine
@@ -7829,5 +8065,5 @@
 on &145
 )
-*260 (Wire
+*270 (Wire
 uid 450,0
 shape (OrthoPolyLine
@@ -7867,5 +8103,5 @@
 on &149
 )
-*261 (Wire
+*271 (Wire
 uid 458,0
 shape (OrthoPolyLine
@@ -7905,5 +8141,5 @@
 on &147
 )
-*262 (Wire
+*272 (Wire
 uid 466,0
 shape (OrthoPolyLine
@@ -7943,5 +8179,5 @@
 on &148
 )
-*263 (Wire
+*273 (Wire
 uid 1467,0
 shape (OrthoPolyLine
@@ -7979,5 +8215,5 @@
 on &78
 )
-*264 (Wire
+*274 (Wire
 uid 1730,0
 shape (OrthoPolyLine
@@ -8019,5 +8255,5 @@
 on &96
 )
-*265 (Wire
+*275 (Wire
 uid 1833,0
 shape (OrthoPolyLine
@@ -8059,5 +8295,5 @@
 on &126
 )
-*266 (Wire
+*276 (Wire
 uid 1841,0
 shape (OrthoPolyLine
@@ -8097,5 +8333,5 @@
 on &128
 )
-*267 (Wire
+*277 (Wire
 uid 1865,0
 shape (OrthoPolyLine
@@ -8135,5 +8371,5 @@
 on &121
 )
-*268 (Wire
+*278 (Wire
 uid 1873,0
 shape (OrthoPolyLine
@@ -8173,5 +8409,5 @@
 on &122
 )
-*269 (Wire
+*279 (Wire
 uid 1881,0
 shape (OrthoPolyLine
@@ -8211,5 +8447,5 @@
 on &123
 )
-*270 (Wire
+*280 (Wire
 uid 1889,0
 shape (OrthoPolyLine
@@ -8249,5 +8485,5 @@
 on &124
 )
-*271 (Wire
+*281 (Wire
 uid 2409,0
 shape (OrthoPolyLine
@@ -8287,5 +8523,5 @@
 on &79
 )
-*272 (Wire
+*282 (Wire
 uid 2423,0
 shape (OrthoPolyLine
@@ -8325,5 +8561,5 @@
 on &81
 )
-*273 (Wire
+*283 (Wire
 uid 3009,0
 shape (OrthoPolyLine
@@ -8363,5 +8599,5 @@
 on &143
 )
-*274 (Wire
+*284 (Wire
 uid 3015,0
 shape (OrthoPolyLine
@@ -8401,5 +8637,5 @@
 on &154
 )
-*275 (Wire
+*285 (Wire
 uid 3021,0
 shape (OrthoPolyLine
@@ -8439,5 +8675,5 @@
 on &82
 )
-*276 (Wire
+*286 (Wire
 uid 3027,0
 shape (OrthoPolyLine
@@ -8478,5 +8714,5 @@
 on &83
 )
-*277 (Wire
+*287 (Wire
 uid 3218,0
 shape (OrthoPolyLine
@@ -8516,5 +8752,5 @@
 on &86
 )
-*278 (Wire
+*288 (Wire
 uid 3260,0
 shape (OrthoPolyLine
@@ -8556,5 +8792,5 @@
 on &91
 )
-*279 (Wire
+*289 (Wire
 uid 3270,0
 shape (OrthoPolyLine
@@ -8594,5 +8830,5 @@
 on &92
 )
-*280 (Wire
+*290 (Wire
 uid 3318,0
 shape (OrthoPolyLine
@@ -8634,5 +8870,5 @@
 on &105
 )
-*281 (Wire
+*291 (Wire
 uid 3352,0
 shape (OrthoPolyLine
@@ -8674,5 +8910,5 @@
 on &106
 )
-*282 (Wire
+*292 (Wire
 uid 3360,0
 shape (OrthoPolyLine
@@ -8714,5 +8950,5 @@
 on &107
 )
-*283 (Wire
+*293 (Wire
 uid 3368,0
 shape (OrthoPolyLine
@@ -8754,5 +8990,5 @@
 on &108
 )
-*284 (Wire
+*294 (Wire
 uid 3430,0
 shape (OrthoPolyLine
@@ -8792,5 +9028,5 @@
 on &113
 )
-*285 (Wire
+*295 (Wire
 uid 3438,0
 shape (OrthoPolyLine
@@ -8830,5 +9066,5 @@
 on &114
 )
-*286 (Wire
+*296 (Wire
 uid 3446,0
 shape (OrthoPolyLine
@@ -8868,5 +9104,5 @@
 on &115
 )
-*287 (Wire
+*297 (Wire
 uid 3454,0
 shape (OrthoPolyLine
@@ -8906,5 +9142,5 @@
 on &116
 )
-*288 (Wire
+*298 (Wire
 uid 3574,0
 shape (OrthoPolyLine
@@ -8944,5 +9180,5 @@
 on &138
 )
-*289 (Wire
+*299 (Wire
 uid 3582,0
 shape (OrthoPolyLine
@@ -8982,5 +9218,5 @@
 on &139
 )
-*290 (Wire
+*300 (Wire
 uid 3590,0
 shape (OrthoPolyLine
@@ -9020,5 +9256,5 @@
 on &140
 )
-*291 (Wire
+*301 (Wire
 uid 3598,0
 shape (OrthoPolyLine
@@ -9058,5 +9294,5 @@
 on &141
 )
-*292 (Wire
+*302 (Wire
 uid 3682,0
 shape (OrthoPolyLine
@@ -9096,5 +9332,5 @@
 on &152
 )
-*293 (Wire
+*303 (Wire
 uid 3778,0
 shape (OrthoPolyLine
@@ -9134,5 +9370,5 @@
 on &168
 )
-*294 (Wire
+*304 (Wire
 uid 3786,0
 shape (OrthoPolyLine
@@ -9172,5 +9408,5 @@
 on &169
 )
-*295 (Wire
+*305 (Wire
 uid 3794,0
 shape (OrthoPolyLine
@@ -9210,5 +9446,5 @@
 on &170
 )
-*296 (Wire
+*306 (Wire
 uid 3802,0
 shape (OrthoPolyLine
@@ -9248,5 +9484,5 @@
 on &171
 )
-*297 (Wire
+*307 (Wire
 uid 3810,0
 shape (OrthoPolyLine
@@ -9286,5 +9522,5 @@
 on &172
 )
-*298 (Wire
+*308 (Wire
 uid 3826,0
 shape (OrthoPolyLine
@@ -9324,5 +9560,5 @@
 on &174
 )
-*299 (Wire
+*309 (Wire
 uid 3834,0
 shape (OrthoPolyLine
@@ -9362,5 +9598,5 @@
 on &175
 )
-*300 (Wire
+*310 (Wire
 uid 3842,0
 shape (OrthoPolyLine
@@ -9402,5 +9638,5 @@
 on &176
 )
-*301 (Wire
+*311 (Wire
 uid 4942,0
 shape (OrthoPolyLine
@@ -9442,5 +9678,5 @@
 on &182
 )
-*302 (Wire
+*312 (Wire
 uid 6431,0
 shape (OrthoPolyLine
@@ -9480,5 +9716,5 @@
 on &173
 )
-*303 (Wire
+*313 (Wire
 uid 6787,0
 shape (OrthoPolyLine
@@ -9519,5 +9755,5 @@
 on &184
 )
-*304 (Wire
+*314 (Wire
 uid 6880,0
 shape (OrthoPolyLine
@@ -9558,5 +9794,5 @@
 on &186
 )
-*305 (Wire
+*315 (Wire
 uid 7144,0
 shape (OrthoPolyLine
@@ -9596,5 +9832,5 @@
 on &196
 )
-*306 (Wire
+*316 (Wire
 uid 7477,0
 shape (OrthoPolyLine
@@ -9633,5 +9869,5 @@
 on &197
 )
-*307 (Wire
+*317 (Wire
 uid 8853,0
 shape (OrthoPolyLine
@@ -9673,5 +9909,5 @@
 on &211
 )
-*308 (Wire
+*318 (Wire
 uid 9502,0
 shape (OrthoPolyLine
@@ -9708,5 +9944,5 @@
 on &212
 )
-*309 (Wire
+*319 (Wire
 uid 10034,0
 shape (OrthoPolyLine
@@ -9746,5 +9982,5 @@
 on &231
 )
-*310 (Wire
+*320 (Wire
 uid 10052,0
 shape (OrthoPolyLine
@@ -9783,5 +10019,5 @@
 on &232
 )
-*311 (Wire
+*321 (Wire
 uid 10302,0
 shape (OrthoPolyLine
@@ -9821,5 +10057,5 @@
 on &234
 )
-*312 (Wire
+*322 (Wire
 uid 10452,0
 shape (OrthoPolyLine
@@ -9827,4 +10063,5 @@
 va (VaSet
 vasetType 3
+lineWidth 2
 )
 xt "112000,126000,122000,126000"
@@ -9837,4 +10074,5 @@
 sat 2
 eat 16
+sty 1
 st 0
 sf 1
@@ -9856,5 +10094,5 @@
 on &234
 )
-*313 (Wire
+*323 (Wire
 uid 10460,0
 shape (OrthoPolyLine
@@ -9862,4 +10100,5 @@
 va (VaSet
 vasetType 3
+lineWidth 2
 )
 xt "112000,127000,122000,127000"
@@ -9872,4 +10111,5 @@
 sat 2
 eat 16
+sty 1
 st 0
 sf 1
@@ -9891,5 +10131,5 @@
 on &196
 )
-*314 (Wire
+*324 (Wire
 uid 10498,0
 shape (OrthoPolyLine
@@ -9904,5 +10144,5 @@
 ]
 )
-start &59
+start &58
 sat 32
 eat 16
@@ -9926,5 +10166,5 @@
 on &239
 )
-*315 (Wire
+*325 (Wire
 uid 10506,0
 shape (OrthoPolyLine
@@ -9937,4 +10177,39 @@
 "80750,124000"
 "88000,124000"
+]
+)
+start &56
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10510,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10511,0
+va (VaSet
+)
+xt "82000,123000,86800,124000"
+st "CLK25_OUT"
+blo "82000,123800"
+tm "WireNameMgr"
+)
+)
+on &240
+)
+*326 (Wire
+uid 10514,0
+shape (OrthoPolyLine
+uid 10515,0
+va (VaSet
+vasetType 3
+)
+xt "80750,125000,89000,125000"
+pts [
+"80750,125000"
+"89000,125000"
 ]
 )
@@ -9946,33 +10221,33 @@
 si 0
 tg (WTG
-uid 10510,0
+uid 10518,0
 ps "ConnStartEndStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 10511,0
-va (VaSet
-)
-xt "82000,123000,86800,124000"
-st "CLK25_OUT"
-blo "82000,123800"
-tm "WireNameMgr"
-)
-)
-on &240
-)
-*316 (Wire
-uid 10514,0
+uid 10519,0
+va (VaSet
+)
+xt "82000,124000,88200,125000"
+st "CLK25_PSOUT"
+blo "82000,124800"
+tm "WireNameMgr"
+)
+)
+on &241
+)
+*327 (Wire
+uid 10522,0
 shape (OrthoPolyLine
-uid 10515,0
+uid 10523,0
 va (VaSet
 vasetType 3
 )
-xt "80750,125000,89000,125000"
-pts [
-"80750,125000"
-"89000,125000"
-]
-)
-start &58
+xt "80750,126000,87000,126000"
+pts [
+"80750,126000"
+"87000,126000"
+]
+)
+start &48
 sat 32
 eat 16
@@ -9981,30 +10256,30 @@
 si 0
 tg (WTG
-uid 10518,0
+uid 10526,0
 ps "ConnStartEndStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 10519,0
-va (VaSet
-)
-xt "82000,124000,88200,125000"
-st "CLK25_PSOUT"
-blo "82000,124800"
-tm "WireNameMgr"
-)
-)
-on &241
-)
-*317 (Wire
-uid 10522,0
+uid 10527,0
+va (VaSet
+)
+xt "82000,125000,86400,126000"
+st "PS_DIR_IN"
+blo "82000,125800"
+tm "WireNameMgr"
+)
+)
+on &242
+)
+*328 (Wire
+uid 10530,0
 shape (OrthoPolyLine
-uid 10523,0
+uid 10531,0
 va (VaSet
 vasetType 3
 )
-xt "80750,126000,87000,126000"
-pts [
-"80750,126000"
-"87000,126000"
+xt "80750,127000,87000,127000"
+pts [
+"80750,127000"
+"87000,127000"
 ]
 )
@@ -10016,30 +10291,240 @@
 si 0
 tg (WTG
-uid 10526,0
+uid 10534,0
 ps "ConnStartEndStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 10527,0
-va (VaSet
-)
-xt "82000,125000,86400,126000"
-st "PS_DIR_IN"
-blo "82000,125800"
-tm "WireNameMgr"
-)
-)
-on &242
-)
-*318 (Wire
-uid 10530,0
+uid 10535,0
+va (VaSet
+)
+xt "82000,126000,86200,127000"
+st "PS_DO_IN"
+blo "82000,126800"
+tm "WireNameMgr"
+)
+)
+on &243
+)
+*329 (Wire
+uid 10538,0
 shape (OrthoPolyLine
-uid 10531,0
+uid 10539,0
 va (VaSet
 vasetType 3
 )
-xt "80750,127000,87000,127000"
-pts [
-"80750,127000"
-"87000,127000"
+xt "80750,129000,88000,129000"
+pts [
+"80750,129000"
+"88000,129000"
+]
+)
+start &52
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10542,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10543,0
+va (VaSet
+)
+xt "82000,128000,86600,129000"
+st "PSEN_OUT"
+blo "82000,128800"
+tm "WireNameMgr"
+)
+)
+on &244
+)
+*330 (Wire
+uid 10546,0
+shape (OrthoPolyLine
+uid 10547,0
+va (VaSet
+vasetType 3
+)
+xt "80750,128000,90000,128000"
+pts [
+"80750,128000"
+"90000,128000"
+]
+)
+start &53
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10550,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10551,0
+va (VaSet
+)
+xt "82000,127000,89000,128000"
+st "PSINCDEC_OUT"
+blo "82000,127800"
+tm "WireNameMgr"
+)
+)
+on &245
+)
+*331 (Wire
+uid 10554,0
+shape (OrthoPolyLine
+uid 10555,0
+va (VaSet
+vasetType 3
+)
+xt "80750,130000,88000,130000"
+pts [
+"80750,130000"
+"88000,130000"
+]
+)
+start &45
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10558,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10559,0
+va (VaSet
+)
+xt "82000,129000,87200,130000"
+st "DCM_locked"
+blo "82000,129800"
+tm "WireNameMgr"
+)
+)
+on &246
+)
+*332 (Wire
+uid 10562,0
+shape (OrthoPolyLine
+uid 10563,0
+va (VaSet
+vasetType 3
+)
+xt "80750,132000,85000,132000"
+pts [
+"80750,132000"
+"85000,132000"
+]
+)
+start &54
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10566,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10567,0
+va (VaSet
+)
+xt "82000,131000,84200,132000"
+st "ready"
+blo "82000,131800"
+tm "WireNameMgr"
+)
+)
+on &247
+)
+*333 (Wire
+uid 10570,0
+shape (OrthoPolyLine
+uid 10571,0
+va (VaSet
+vasetType 3
+)
+xt "80750,133000,86000,133000"
+pts [
+"80750,133000"
+"86000,133000"
+]
+)
+start &55
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10574,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10575,0
+va (VaSet
+)
+xt "82000,132000,84900,133000"
+st "shifting"
+blo "82000,132800"
+tm "WireNameMgr"
+)
+)
+on &248
+)
+*334 (Wire
+uid 10578,0
+shape (OrthoPolyLine
+uid 10579,0
+va (VaSet
+vasetType 3
+)
+xt "80750,134000,91000,134000"
+pts [
+"80750,134000"
+"91000,134000"
+]
+)
+start &51
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10582,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10583,0
+va (VaSet
+)
+xt "82000,133000,89800,134000"
+st "PSDONE_extraOUT"
+blo "82000,133800"
+tm "WireNameMgr"
+)
+)
+on &249
+)
+*335 (Wire
+uid 10586,0
+shape (OrthoPolyLine
+uid 10587,0
+va (VaSet
+vasetType 3
+)
+xt "80750,135000,88000,135000"
+pts [
+"80750,135000"
+"88000,135000"
 ]
 )
@@ -10051,33 +10536,33 @@
 si 0
 tg (WTG
-uid 10534,0
+uid 10590,0
 ps "ConnStartEndStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 10535,0
-va (VaSet
-)
-xt "82000,126000,86200,127000"
-st "PS_DO_IN"
-blo "82000,126800"
-tm "WireNameMgr"
-)
-)
-on &243
-)
-*319 (Wire
-uid 10538,0
+uid 10591,0
+va (VaSet
+)
+xt "82000,134000,87000,135000"
+st "PSCLK_OUT"
+blo "82000,134800"
+tm "WireNameMgr"
+)
+)
+on &250
+)
+*336 (Wire
+uid 10594,0
 shape (OrthoPolyLine
-uid 10539,0
+uid 10595,0
 va (VaSet
 vasetType 3
 )
-xt "80750,129000,88000,129000"
-pts [
-"80750,129000"
-"88000,129000"
-]
-)
-start &53
+xt "80750,136000,91000,136000"
+pts [
+"80750,136000"
+"91000,136000"
+]
+)
+start &46
 sat 32
 eat 16
@@ -10086,249 +10571,4 @@
 si 0
 tg (WTG
-uid 10542,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10543,0
-va (VaSet
-)
-xt "82000,128000,86600,129000"
-st "PSEN_OUT"
-blo "82000,128800"
-tm "WireNameMgr"
-)
-)
-on &244
-)
-*320 (Wire
-uid 10546,0
-shape (OrthoPolyLine
-uid 10547,0
-va (VaSet
-vasetType 3
-)
-xt "80750,128000,90000,128000"
-pts [
-"80750,128000"
-"90000,128000"
-]
-)
-start &54
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10550,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10551,0
-va (VaSet
-)
-xt "82000,127000,89000,128000"
-st "PSINCDEC_OUT"
-blo "82000,127800"
-tm "WireNameMgr"
-)
-)
-on &245
-)
-*321 (Wire
-uid 10554,0
-shape (OrthoPolyLine
-uid 10555,0
-va (VaSet
-vasetType 3
-)
-xt "80750,130000,88000,130000"
-pts [
-"80750,130000"
-"88000,130000"
-]
-)
-start &45
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10558,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10559,0
-va (VaSet
-)
-xt "82000,129000,87200,130000"
-st "DCM_locked"
-blo "82000,129800"
-tm "WireNameMgr"
-)
-)
-on &246
-)
-*322 (Wire
-uid 10562,0
-shape (OrthoPolyLine
-uid 10563,0
-va (VaSet
-vasetType 3
-)
-xt "80750,132000,85000,132000"
-pts [
-"80750,132000"
-"85000,132000"
-]
-)
-start &55
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10566,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10567,0
-va (VaSet
-)
-xt "82000,131000,84200,132000"
-st "ready"
-blo "82000,131800"
-tm "WireNameMgr"
-)
-)
-on &247
-)
-*323 (Wire
-uid 10570,0
-shape (OrthoPolyLine
-uid 10571,0
-va (VaSet
-vasetType 3
-)
-xt "80750,133000,86000,133000"
-pts [
-"80750,133000"
-"86000,133000"
-]
-)
-start &56
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10574,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10575,0
-va (VaSet
-)
-xt "82000,132000,84900,133000"
-st "shifting"
-blo "82000,132800"
-tm "WireNameMgr"
-)
-)
-on &248
-)
-*324 (Wire
-uid 10578,0
-shape (OrthoPolyLine
-uid 10579,0
-va (VaSet
-vasetType 3
-)
-xt "80750,134000,91000,134000"
-pts [
-"80750,134000"
-"91000,134000"
-]
-)
-start &52
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10582,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10583,0
-va (VaSet
-)
-xt "82000,133000,89800,134000"
-st "PSDONE_extraOUT"
-blo "82000,133800"
-tm "WireNameMgr"
-)
-)
-on &249
-)
-*325 (Wire
-uid 10586,0
-shape (OrthoPolyLine
-uid 10587,0
-va (VaSet
-vasetType 3
-)
-xt "80750,135000,88000,135000"
-pts [
-"80750,135000"
-"88000,135000"
-]
-)
-start &51
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10590,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10591,0
-va (VaSet
-)
-xt "82000,134000,87000,135000"
-st "PSCLK_OUT"
-blo "82000,134800"
-tm "WireNameMgr"
-)
-)
-on &250
-)
-*326 (Wire
-uid 10594,0
-shape (OrthoPolyLine
-uid 10595,0
-va (VaSet
-vasetType 3
-)
-xt "80750,136000,91000,136000"
-pts [
-"80750,136000"
-"91000,136000"
-]
-)
-start &47
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
 uid 10598,0
 ps "ConnStartEndStrategy"
@@ -10346,5 +10586,5 @@
 on &251
 )
-*327 (Wire
+*337 (Wire
 uid 10600,0
 shape (OrthoPolyLine
@@ -10381,5 +10621,5 @@
 on &240
 )
-*328 (Wire
+*338 (Wire
 uid 10608,0
 shape (OrthoPolyLine
@@ -10416,5 +10656,5 @@
 on &241
 )
-*329 (Wire
+*339 (Wire
 uid 10616,0
 shape (OrthoPolyLine
@@ -10451,5 +10691,5 @@
 on &239
 )
-*330 (Wire
+*340 (Wire
 uid 10624,0
 shape (OrthoPolyLine
@@ -10486,5 +10726,5 @@
 on &246
 )
-*331 (Wire
+*341 (Wire
 uid 10632,0
 shape (OrthoPolyLine
@@ -10521,5 +10761,5 @@
 on &251
 )
-*332 (Wire
+*342 (Wire
 uid 10640,0
 shape (OrthoPolyLine
@@ -10556,5 +10796,5 @@
 on &250
 )
-*333 (Wire
+*343 (Wire
 uid 10648,0
 shape (OrthoPolyLine
@@ -10591,5 +10831,5 @@
 on &249
 )
-*334 (Wire
+*344 (Wire
 uid 10656,0
 shape (OrthoPolyLine
@@ -10626,5 +10866,5 @@
 on &244
 )
-*335 (Wire
+*345 (Wire
 uid 10664,0
 shape (OrthoPolyLine
@@ -10661,5 +10901,5 @@
 on &245
 )
-*336 (Wire
+*346 (Wire
 uid 10672,0
 shape (OrthoPolyLine
@@ -10696,5 +10936,5 @@
 on &242
 )
-*337 (Wire
+*347 (Wire
 uid 10680,0
 shape (OrthoPolyLine
@@ -10731,5 +10971,5 @@
 on &243
 )
-*338 (Wire
+*348 (Wire
 uid 10688,0
 shape (OrthoPolyLine
@@ -10766,5 +11006,5 @@
 on &247
 )
-*339 (Wire
+*349 (Wire
 uid 10696,0
 shape (OrthoPolyLine
@@ -10800,4 +11040,188 @@
 )
 on &248
+)
+*350 (Wire
+uid 11096,0
+shape (OrthoPolyLine
+uid 11097,0
+va (VaSet
+vasetType 3
+)
+xt "96000,103000,100000,103000"
+pts [
+"96000,103000"
+"100000,103000"
+]
+)
+start &252
+end &155
+sat 32
+eat 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 11100,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11101,0
+va (VaSet
+isHidden 1
+)
+xt "126000,96000,131300,97000"
+st "RS485_C_DI"
+blo "126000,96800"
+tm "WireNameMgr"
+)
+)
+on &253
+)
+*351 (Wire
+uid 11110,0
+shape (OrthoPolyLine
+uid 11111,0
+va (VaSet
+vasetType 3
+)
+xt "108000,112000,111000,112000"
+pts [
+"108000,112000"
+"111000,112000"
+]
+)
+start &155
+end &254
+sat 2
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 11114,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11115,0
+va (VaSet
+isHidden 1
+)
+xt "110000,111000,115700,112000"
+st "RS485_C_DO"
+blo "110000,111800"
+tm "WireNameMgr"
+)
+)
+on &255
+)
+*352 (Wire
+uid 11514,0
+shape (OrthoPolyLine
+uid 11515,0
+va (VaSet
+vasetType 3
+)
+xt "123000,116000,127000,116000"
+pts [
+"123000,116000"
+"127000,116000"
+]
+)
+start &256
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 11518,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11519,0
+va (VaSet
+isHidden 1
+)
+xt "125000,115000,130200,116000"
+st "RS485_E_DI"
+blo "125000,115800"
+tm "WireNameMgr"
+)
+)
+on &257
+)
+*353 (Wire
+uid 11528,0
+shape (OrthoPolyLine
+uid 11529,0
+va (VaSet
+vasetType 3
+)
+xt "123000,114000,126000,114000"
+pts [
+"123000,114000"
+"126000,114000"
+]
+)
+end &259
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 11532,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11533,0
+va (VaSet
+isHidden 1
+)
+xt "125000,113000,130600,114000"
+st "RS485_E_DO"
+blo "125000,113800"
+tm "WireNameMgr"
+)
+)
+on &258
+)
+*354 (Wire
+uid 12320,0
+shape (OrthoPolyLine
+uid 12321,0
+va (VaSet
+vasetType 3
+)
+xt "80750,140000,87000,140000"
+pts [
+"80750,140000"
+"87000,140000"
+]
+)
+start &59
+end &261
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 12324,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 12325,0
+va (VaSet
+isHidden 1
+)
+xt "82000,139000,85700,140000"
+st "SRIN_out"
+blo "82000,139800"
+tm "WireNameMgr"
+)
+)
+on &260
 )
 ]
@@ -10813,9 +11237,9 @@
 color "26368,26368,26368"
 )
-packageList *340 (PackageList
+packageList *355 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*341 (Text
+*356 (Text
 uid 42,0
 va (VaSet
@@ -10826,5 +11250,5 @@
 blo "0,800"
 )
-*342 (MLText
+*357 (MLText
 uid 43,0
 va (VaSet
@@ -10847,5 +11271,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*343 (Text
+*358 (Text
 uid 45,0
 va (VaSet
@@ -10857,5 +11281,5 @@
 blo "20000,800"
 )
-*344 (Text
+*359 (Text
 uid 46,0
 va (VaSet
@@ -10867,5 +11291,5 @@
 blo "20000,1800"
 )
-*345 (MLText
+*360 (MLText
 uid 47,0
 va (VaSet
@@ -10877,5 +11301,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*346 (Text
+*361 (Text
 uid 48,0
 va (VaSet
@@ -10887,5 +11311,5 @@
 blo "20000,4800"
 )
-*347 (MLText
+*362 (MLText
 uid 49,0
 va (VaSet
@@ -10895,5 +11319,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*348 (Text
+*363 (Text
 uid 50,0
 va (VaSet
@@ -10905,5 +11329,5 @@
 blo "20000,5800"
 )
-*349 (MLText
+*364 (MLText
 uid 51,0
 va (VaSet
@@ -10916,6 +11340,6 @@
 associable 1
 )
-windowSize "1276,-4,2564,1028"
-viewArea "50354,105045,134172,174344"
+windowSize "0,0,1281,1002"
+viewArea "16140,87720,101020,155960"
 cachedDiagramExtent "0,0,699000,450107"
 pageSetupInfo (PageSetupInfo
@@ -10930,5 +11354,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "0,0"
-lastUid 10729,0
+lastUid 12333,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -10992,5 +11416,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*350 (Text
+*365 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11001,5 +11425,5 @@
 tm "BdLibraryNameMgr"
 )
-*351 (Text
+*366 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11010,5 +11434,5 @@
 tm "BlkNameMgr"
 )
-*352 (Text
+*367 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11061,5 +11485,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*353 (Text
+*368 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11069,5 +11493,5 @@
 blo "550,4300"
 )
-*354 (Text
+*369 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11077,5 +11501,5 @@
 blo "550,5300"
 )
-*355 (Text
+*370 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11126,5 +11550,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*356 (Text
+*371 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11135,5 +11559,5 @@
 tm "BdLibraryNameMgr"
 )
-*357 (Text
+*372 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11144,5 +11568,5 @@
 tm "CptNameMgr"
 )
-*358 (Text
+*373 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11198,5 +11622,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*359 (Text
+*374 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11206,5 +11630,5 @@
 blo "500,4300"
 )
-*360 (Text
+*375 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11214,5 +11638,5 @@
 blo "500,5300"
 )
-*361 (Text
+*376 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11259,5 +11683,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*362 (Text
+*377 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11267,5 +11691,5 @@
 blo "50,4300"
 )
-*363 (Text
+*378 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11275,5 +11699,5 @@
 blo "50,5300"
 )
-*364 (Text
+*379 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11316,5 +11740,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*365 (Text
+*380 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11325,5 +11749,5 @@
 tm "HdlTextNameMgr"
 )
-*366 (Text
+*381 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11728,5 +12152,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*367 (Text
+*382 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11736,5 +12160,5 @@
 blo "14100,20800"
 )
-*368 (MLText
+*383 (MLText
 va (VaSet
 )
@@ -11788,5 +12212,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*369 (Text
+*384 (Text
 va (VaSet
 font "Arial,8,1"
@@ -11796,5 +12220,5 @@
 blo "14100,20800"
 )
-*370 (MLText
+*385 (MLText
 va (VaSet
 )
@@ -11914,7 +12338,7 @@
 font "Arial,8,1"
 )
-xt "37000,43000,44100,44000"
+xt "37000,47000,44100,48000"
 st "Diagram Signals:"
-blo "37000,43800"
+blo "37000,47800"
 )
 postUserLabel (Text
@@ -11940,44 +12364,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 196,0
+suid 202,0
 usingSuid 1
-emptyRow *371 (LEmptyRow
+emptyRow *386 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*372 (RefLabelRowHdr
-)
-*373 (TitleRowHdr
-)
-*374 (FilterRowHdr
-)
-*375 (RefLabelColHdr
+*387 (RefLabelRowHdr
+)
+*388 (TitleRowHdr
+)
+*389 (FilterRowHdr
+)
+*390 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*376 (RowExpandColHdr
+*391 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*377 (GroupColHdr
+*392 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*378 (NameColHdr
+*393 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*379 (ModeColHdr
+*394 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*380 (TypeColHdr
+*395 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*381 (BoundsColHdr
+*396 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*382 (InitColHdr
+*397 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*383 (EolColHdr
+*398 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*384 (LeafLogPort
+*399 (LeafLogPort
 port (LogicalPort
 m 4
@@ -11988,5 +12412,5 @@
 preAdd 0
 posAdd 0
-o 55
+o 69
 suid 5,0
 )
@@ -11994,5 +12418,5 @@
 uid 327,0
 )
-*385 (LeafLogPort
+*400 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12001,5 +12425,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 56
+o 70
 suid 6,0
 )
@@ -12007,5 +12431,5 @@
 uid 329,0
 )
-*386 (LeafLogPort
+*401 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12013,5 +12437,5 @@
 n "adc_data_array"
 t "adc_data_array_type"
-o 54
+o 68
 suid 29,0
 )
@@ -12019,5 +12443,5 @@
 uid 1491,0
 )
-*387 (LeafLogPort
+*402 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12025,5 +12449,5 @@
 n "RSRLOAD"
 t "std_logic"
-o 35
+o 37
 suid 57,0
 i "'0'"
@@ -12032,5 +12456,5 @@
 uid 2435,0
 )
-*388 (LeafLogPort
+*403 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12038,5 +12462,5 @@
 n "SRCLK"
 t "std_logic"
-o 52
+o 66
 suid 58,0
 i "'0'"
@@ -12045,5 +12469,5 @@
 uid 2437,0
 )
-*389 (LeafLogPort
+*404 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12052,5 +12476,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 59
+o 74
 suid 65,0
 )
@@ -12058,5 +12482,5 @@
 uid 3037,0
 )
-*390 (LeafLogPort
+*405 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12064,5 +12488,5 @@
 n "DAC_CS"
 t "std_logic"
-o 21
+o 22
 suid 66,0
 )
@@ -12070,5 +12494,5 @@
 uid 3039,0
 )
-*391 (LeafLogPort
+*406 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12083,5 +12507,5 @@
 uid 3276,0
 )
-*392 (LeafLogPort
+*407 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12094,5 +12518,5 @@
 uid 3278,0
 )
-*393 (LeafLogPort
+*408 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12101,5 +12525,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 16
+o 17
 suid 71,0
 )
@@ -12107,5 +12531,5 @@
 uid 3280,0
 )
-*394 (LeafLogPort
+*409 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12113,5 +12537,5 @@
 n "CLK_25_PS"
 t "std_logic"
-o 50
+o 55
 suid 72,0
 )
@@ -12119,5 +12543,5 @@
 uid 3282,0
 )
-*395 (LeafLogPort
+*410 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12127,5 +12551,5 @@
 preAdd 0
 posAdd 0
-o 30
+o 31
 suid 73,0
 )
@@ -12133,5 +12557,5 @@
 uid 3382,0
 )
-*396 (LeafLogPort
+*411 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12145,5 +12569,5 @@
 uid 3384,0
 )
-*397 (LeafLogPort
+*412 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12157,5 +12581,5 @@
 uid 3386,0
 )
-*398 (LeafLogPort
+*413 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12169,5 +12593,5 @@
 uid 3388,0
 )
-*399 (LeafLogPort
+*414 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12181,5 +12605,5 @@
 uid 3390,0
 )
-*400 (LeafLogPort
+*415 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12193,5 +12617,5 @@
 uid 3392,0
 )
-*401 (LeafLogPort
+*416 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12199,5 +12623,5 @@
 n "D0_SRCLK"
 t "STD_LOGIC"
-o 17
+o 18
 suid 87,0
 )
@@ -12205,5 +12629,5 @@
 uid 3468,0
 )
-*402 (LeafLogPort
+*417 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12211,5 +12635,5 @@
 n "D1_SRCLK"
 t "STD_LOGIC"
-o 18
+o 19
 suid 88,0
 )
@@ -12217,5 +12641,5 @@
 uid 3470,0
 )
-*403 (LeafLogPort
+*418 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12223,5 +12647,5 @@
 n "D2_SRCLK"
 t "STD_LOGIC"
-o 19
+o 20
 suid 89,0
 )
@@ -12229,5 +12653,5 @@
 uid 3472,0
 )
-*404 (LeafLogPort
+*419 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12235,5 +12659,5 @@
 n "D3_SRCLK"
 t "STD_LOGIC"
-o 20
+o 21
 suid 90,0
 )
@@ -12241,5 +12665,5 @@
 uid 3474,0
 )
-*405 (LeafLogPort
+*420 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12252,5 +12676,5 @@
 uid 3524,0
 )
-*406 (LeafLogPort
+*421 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12263,5 +12687,5 @@
 uid 3526,0
 )
-*407 (LeafLogPort
+*422 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12274,5 +12698,5 @@
 uid 3528,0
 )
-*408 (LeafLogPort
+*423 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12285,5 +12709,5 @@
 uid 3530,0
 )
-*409 (LeafLogPort
+*424 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12292,5 +12716,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 24
+o 25
 suid 95,0
 i "(others => '0')"
@@ -12299,5 +12723,5 @@
 uid 3532,0
 )
-*410 (LeafLogPort
+*425 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12305,5 +12729,5 @@
 n "DWRITE"
 t "std_logic"
-o 23
+o 24
 suid 96,0
 i "'0'"
@@ -12312,5 +12736,5 @@
 uid 3534,0
 )
-*411 (LeafLogPort
+*426 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12318,5 +12742,5 @@
 n "T0_CS"
 t "std_logic"
-o 38
+o 40
 suid 101,0
 )
@@ -12324,5 +12748,5 @@
 uid 3646,0
 )
-*412 (LeafLogPort
+*427 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12330,5 +12754,5 @@
 n "T1_CS"
 t "std_logic"
-o 39
+o 41
 suid 102,0
 )
@@ -12336,5 +12760,5 @@
 uid 3648,0
 )
-*413 (LeafLogPort
+*428 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12342,5 +12766,5 @@
 n "T2_CS"
 t "std_logic"
-o 40
+o 42
 suid 103,0
 )
@@ -12348,5 +12772,5 @@
 uid 3650,0
 )
-*414 (LeafLogPort
+*429 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12354,5 +12778,5 @@
 n "T3_CS"
 t "std_logic"
-o 41
+o 43
 suid 104,0
 )
@@ -12360,5 +12784,5 @@
 uid 3652,0
 )
-*415 (LeafLogPort
+*430 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12366,5 +12790,5 @@
 n "S_CLK"
 t "std_logic"
-o 37
+o 39
 suid 105,0
 )
@@ -12372,5 +12796,5 @@
 uid 3654,0
 )
-*416 (LeafLogPort
+*431 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12379,5 +12803,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 43
+o 45
 suid 106,0
 )
@@ -12385,5 +12809,5 @@
 uid 3656,0
 )
-*417 (LeafLogPort
+*432 (LeafLogPort
 port (LogicalPort
 m 2
@@ -12392,196 +12816,9 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 49
+o 51
 suid 107,0
 )
 )
 uid 3658,0
-)
-*418 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_RES"
-t "std_logic"
-o 46
-suid 108,0
-i "'1'"
-)
-)
-uid 3660,0
-)
-*419 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_RD"
-t "std_logic"
-o 45
-suid 109,0
-i "'1'"
-)
-)
-uid 3662,0
-)
-*420 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_WR"
-t "std_logic"
-o 47
-suid 110,0
-i "'1'"
-)
-)
-uid 3664,0
-)
-*421 (LeafLogPort
-port (LogicalPort
-decl (Decl
-n "W_INT"
-t "std_logic"
-o 13
-suid 111,0
-)
-)
-uid 3666,0
-)
-*422 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "W_CS"
-t "std_logic"
-o 44
-suid 112,0
-i "'1'"
-)
-)
-uid 3668,0
-)
-*423 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "MOSI"
-t "std_logic"
-o 29
-suid 113,0
-i "'0'"
-)
-)
-uid 3696,0
-)
-*424 (LeafLogPort
-port (LogicalPort
-m 2
-decl (Decl
-n "MISO"
-t "std_logic"
-preAdd 0
-posAdd 0
-o 48
-suid 114,0
-)
-)
-uid 3698,0
-)
-*425 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "TRG_V"
-t "std_logic"
-o 42
-suid 126,0
-)
-)
-uid 3886,0
-)
-*426 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_C_RE"
-t "std_logic"
-o 32
-suid 127,0
-)
-)
-uid 3888,0
-)
-*427 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_C_DE"
-t "std_logic"
-o 31
-suid 128,0
-)
-)
-uid 3890,0
-)
-*428 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_E_RE"
-t "std_logic"
-o 34
-suid 129,0
-)
-)
-uid 3892,0
-)
-*429 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "RS485_E_DE"
-t "std_logic"
-o 33
-suid 130,0
-)
-)
-uid 3894,0
-)
-*430 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "DENABLE"
-t "std_logic"
-o 22
-suid 131,0
-i "'0'"
-)
-)
-uid 3896,0
-)
-*431 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "SRIN"
-t "std_logic"
-o 36
-suid 132,0
-)
-)
-uid 3898,0
-)
-*432 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "EE_CS"
-t "std_logic"
-o 27
-suid 133,0
-)
-)
-uid 3900,0
 )
 *433 (LeafLogPort
@@ -12589,8 +12826,195 @@
 m 1
 decl (Decl
+n "W_RES"
+t "std_logic"
+o 48
+suid 108,0
+i "'1'"
+)
+)
+uid 3660,0
+)
+*434 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "W_RD"
+t "std_logic"
+o 47
+suid 109,0
+i "'1'"
+)
+)
+uid 3662,0
+)
+*435 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "W_WR"
+t "std_logic"
+o 49
+suid 110,0
+i "'1'"
+)
+)
+uid 3664,0
+)
+*436 (LeafLogPort
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+decl (Decl
+n "W_INT"
+t "std_logic"
+o 13
+suid 111,0
+)
+)
+uid 3666,0
+)
+*437 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "W_CS"
+t "std_logic"
+o 46
+suid 112,0
+i "'1'"
+)
+)
+uid 3668,0
+)
+*438 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "MOSI"
+t "std_logic"
+o 30
+suid 113,0
+i "'0'"
+)
+)
+uid 3696,0
+)
+*439 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "MISO"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 50
+suid 114,0
+)
+)
+uid 3698,0
+)
+*440 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "TRG_V"
+t "std_logic"
+o 44
+suid 126,0
+)
+)
+uid 3886,0
+)
+*441 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_RE"
+t "std_logic"
+o 34
+suid 127,0
+)
+)
+uid 3888,0
+)
+*442 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_DE"
+t "std_logic"
+o 32
+suid 128,0
+)
+)
+uid 3890,0
+)
+*443 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_E_RE"
+t "std_logic"
+o 36
+suid 129,0
+)
+)
+uid 3892,0
+)
+*444 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_E_DE"
+t "std_logic"
+o 35
+suid 130,0
+)
+)
+uid 3894,0
+)
+*445 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "DENABLE"
+t "std_logic"
+o 23
+suid 131,0
+i "'0'"
+)
+)
+uid 3896,0
+)
+*446 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "SRIN"
+t "std_logic"
+o 38
+suid 132,0
+)
+)
+uid 3898,0
+)
+*447 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "EE_CS"
+t "std_logic"
+o 28
+suid 133,0
+)
+)
+uid 3900,0
+)
+*448 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
 n "LED"
 t "std_logic_vector"
 b "( 2 DOWNTO 0 )"
-o 28
+o 29
 suid 134,0
 i "(others => '1')"
@@ -12599,5 +13023,5 @@
 uid 3902,0
 )
-*434 (LeafLogPort
+*449 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12606,5 +13030,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 25
+o 26
 suid 141,0
 i "(OTHERS => '0')"
@@ -12613,5 +13037,5 @@
 uid 5322,0
 )
-*435 (LeafLogPort
+*450 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -12626,5 +13050,5 @@
 scheme 0
 )
-*436 (LeafLogPort
+*451 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12633,5 +13057,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 26
+o 27
 suid 154,0
 i "(others => '0')"
@@ -12641,5 +13065,5 @@
 scheme 0
 )
-*437 (LeafLogPort
+*452 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12648,5 +13072,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 15
+o 16
 suid 155,0
 i "(OTHERS => '0')"
@@ -12656,5 +13080,5 @@
 scheme 0
 )
-*438 (LeafLogPort
+*453 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12662,5 +13086,5 @@
 n "dummy"
 t "std_logic"
-o 58
+o 72
 suid 157,0
 )
@@ -12669,5 +13093,5 @@
 scheme 0
 )
-*439 (LeafLogPort
+*454 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12676,5 +13100,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 57
+o 71
 suid 159,0
 i "(others => '0')"
@@ -12683,5 +13107,5 @@
 uid 8875,0
 )
-*440 (LeafLogPort
+*455 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12689,5 +13113,5 @@
 n "CLK_50"
 t "std_logic"
-o 51
+o 57
 suid 163,0
 )
@@ -12695,5 +13119,5 @@
 uid 9516,0
 )
-*441 (LeafLogPort
+*456 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12701,5 +13125,5 @@
 n "CLK_25_PS1"
 t "std_logic"
-o 58
+o 56
 suid 164,0
 )
@@ -12707,5 +13131,5 @@
 uid 10056,0
 )
-*442 (LeafLogPort
+*457 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12713,5 +13137,5 @@
 n "adc_clk_en"
 t "std_logic"
-o 59
+o 67
 suid 165,0
 i "'0'"
@@ -12720,5 +13144,5 @@
 uid 10058,0
 )
-*443 (LeafLogPort
+*458 (LeafLogPort
 port (LogicalPort
 m 1
@@ -12727,5 +13151,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 60
+o 15
 suid 166,0
 i "(others => '0')"
@@ -12735,5 +13159,5 @@
 scheme 0
 )
-*444 (LeafLogPort
+*459 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12741,5 +13165,5 @@
 n "CLK50_OUT"
 t "std_logic"
-o 61
+o 54
 suid 184,0
 )
@@ -12747,5 +13171,5 @@
 uid 10704,0
 )
-*445 (LeafLogPort
+*460 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12753,5 +13177,5 @@
 n "CLK25_OUT"
 t "std_logic"
-o 62
+o 52
 suid 185,0
 )
@@ -12759,5 +13183,5 @@
 uid 10706,0
 )
-*446 (LeafLogPort
+*461 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12765,5 +13189,5 @@
 n "CLK25_PSOUT"
 t "std_logic"
-o 63
+o 53
 suid 186,0
 )
@@ -12771,5 +13195,5 @@
 uid 10708,0
 )
-*447 (LeafLogPort
+*462 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12783,5 +13207,5 @@
 uid 10710,0
 )
-*448 (LeafLogPort
+*463 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12795,5 +13219,5 @@
 uid 10712,0
 )
-*449 (LeafLogPort
+*464 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12801,5 +13225,5 @@
 n "PSEN_OUT"
 t "std_logic"
-o 66
+o 62
 suid 189,0
 )
@@ -12807,5 +13231,5 @@
 uid 10714,0
 )
-*450 (LeafLogPort
+*465 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12813,5 +13237,5 @@
 n "PSINCDEC_OUT"
 t "std_logic"
-o 67
+o 63
 suid 190,0
 )
@@ -12819,5 +13243,5 @@
 uid 10716,0
 )
-*451 (LeafLogPort
+*466 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12827,5 +13251,5 @@
 preAdd 0
 posAdd 0
-o 68
+o 58
 suid 191,0
 )
@@ -12833,5 +13257,5 @@
 uid 10718,0
 )
-*452 (LeafLogPort
+*467 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12841,5 +13265,5 @@
 preAdd 0
 posAdd 0
-o 69
+o 73
 suid 192,0
 i "'0'"
@@ -12848,5 +13272,5 @@
 uid 10720,0
 )
-*453 (LeafLogPort
+*468 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12857,5 +13281,5 @@
 preAdd 0
 posAdd 0
-o 70
+o 75
 suid 193,0
 i "'0'"
@@ -12864,5 +13288,5 @@
 uid 10722,0
 )
-*454 (LeafLogPort
+*469 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12870,5 +13294,5 @@
 n "PSDONE_extraOUT"
 t "std_logic"
-o 71
+o 61
 suid 194,0
 )
@@ -12876,5 +13300,5 @@
 uid 10724,0
 )
-*455 (LeafLogPort
+*470 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12882,5 +13306,5 @@
 n "PSCLK_OUT"
 t "std_logic"
-o 72
+o 60
 suid 195,0
 )
@@ -12888,5 +13312,5 @@
 uid 10726,0
 )
-*456 (LeafLogPort
+*471 (LeafLogPort
 port (LogicalPort
 m 4
@@ -12894,9 +13318,71 @@
 n "LOCKED_extraOUT"
 t "std_logic"
-o 73
+o 59
 suid 196,0
 )
 )
 uid 10728,0
+)
+*472 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "RS485_C_DI"
+t "std_logic"
+o 74
+suid 197,0
+)
+)
+uid 11084,0
+scheme 0
+)
+*473 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_DO"
+t "std_logic"
+o 75
+suid 198,0
+)
+)
+uid 11086,0
+scheme 0
+)
+*474 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "RS485_E_DI"
+t "std_logic"
+o 76
+suid 200,0
+)
+)
+uid 11504,0
+scheme 0
+)
+*475 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "RS485_E_DO"
+t "std_logic"
+o 77
+suid 201,0
+)
+)
+uid 11506,0
+scheme 0
+)
+*476 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 78
+suid 202,0
+i "'0'"
+)
+)
+uid 12332,0
 )
 ]
@@ -12907,5 +13393,5 @@
 uid 67,0
 optionalChildren [
-*457 (Sheet
+*477 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -12924,25 +13410,25 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *458 (MRCItem
-litem &371
-pos 73
+emptyMRCItem *478 (MRCItem
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+pos 78
 dimension 20
 )
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 optionalChildren [
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 pos 0
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 pos 1
 dimension 23
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 pos 2
 hidden 1
@@ -12950,441 +13436,471 @@
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 pos 48
 dimension 20
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 )
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 dimension 20
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 dimension 20
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 )
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 pos 26
 dimension 20
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 dimension 20
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 dimension 20
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 )
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 dimension 20
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 pos 31
 dimension 20
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 dimension 20
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 pos 33
 dimension 20
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 )
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 pos 34
 dimension 20
 uid 3699,0
 )
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 pos 35
 dimension 20
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 )
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 dimension 20
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 )
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 )
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 dimension 20
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 )
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 dimension 20
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 )
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 dimension 20
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 dimension 20
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 )
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 )
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+uid 11507,0
+)
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+uid 12333,0
 )
 ]
@@ -13399,48 +13915,48 @@
 uid 73,0
 optionalChildren [
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 pos 0
 dimension 20
 uid 74,0
 )
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 dimension 50
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 pos 2
 dimension 100
 uid 76,0
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 dimension 50
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 pos 4
 dimension 100
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 pos 5
 dimension 100
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-*541 (MRCItem
-litem &382
+*566 (MRCItem
+litem &397
 pos 6
 dimension 92
 uid 80,0
 )
-*542 (MRCItem
-litem &383
+*567 (MRCItem
+litem &398
 pos 7
 dimension 80
@@ -13462,36 +13978,36 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *543 (LEmptyRow
+emptyRow *568 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*544 (RefLabelRowHdr
-)
-*545 (TitleRowHdr
-)
-*546 (FilterRowHdr
-)
-*547 (RefLabelColHdr
+*569 (RefLabelRowHdr
+)
+*570 (TitleRowHdr
+)
+*571 (FilterRowHdr
+)
+*572 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*548 (RowExpandColHdr
+*573 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*549 (GroupColHdr
+*574 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*550 (NameColHdr
+*575 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*551 (TypeColHdr
+*576 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*552 (InitColHdr
+*577 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*553 (PragmaColHdr
+*578 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*554 (EolColHdr
+*579 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
@@ -13503,5 +14019,5 @@
 uid 95,0
 optionalChildren [
-*555 (Sheet
+*580 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -13520,6 +14036,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *556 (MRCItem
-litem &543
+emptyMRCItem *581 (MRCItem
+litem &568
 pos 0
 dimension 20
@@ -13527,18 +14043,18 @@
 uid 97,0
 optionalChildren [
-*557 (MRCItem
-litem &544
+*582 (MRCItem
+litem &569
 pos 0
 dimension 20
 uid 98,0
 )
-*558 (MRCItem
-litem &545
+*583 (MRCItem
+litem &570
 pos 1
 dimension 23
 uid 99,0
 )
-*559 (MRCItem
-litem &546
+*584 (MRCItem
+litem &571
 pos 2
 hidden 1
@@ -13557,42 +14073,42 @@
 uid 101,0
 optionalChildren [
-*560 (MRCItem
-litem &547
+*585 (MRCItem
+litem &572
 pos 0
 dimension 20
 uid 102,0
 )
-*561 (MRCItem
-litem &549
+*586 (MRCItem
+litem &574
 pos 1
 dimension 50
 uid 103,0
 )
-*562 (MRCItem
-litem &550
+*587 (MRCItem
+litem &575
 pos 2
 dimension 100
 uid 104,0
 )
-*563 (MRCItem
-litem &551
+*588 (MRCItem
+litem &576
 pos 3
 dimension 100
 uid 105,0
 )
-*564 (MRCItem
-litem &552
+*589 (MRCItem
+litem &577
 pos 4
 dimension 50
 uid 106,0
 )
-*565 (MRCItem
-litem &553
+*590 (MRCItem
+litem &578
 pos 5
 dimension 50
 uid 107,0
 )
-*566 (MRCItem
-litem &554
+*591 (MRCItem
+litem &579
 pos 6
 dimension 80
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb	(revision 10073)
@@ -21,5 +21,5 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 68,0
+suid 73,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -66,5 +66,5 @@
 n "RSRLOAD"
 t "std_logic"
-o 35
+o 39
 suid 11,0
 i "'0'"
@@ -80,5 +80,5 @@
 preAdd 0
 posAdd 0
-o 13
+o 16
 suid 15,0
 )
@@ -91,5 +91,5 @@
 n "TRG"
 t "STD_LOGIC"
-o 11
+o 14
 suid 16,0
 )
@@ -104,5 +104,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 16
+o 19
 suid 17,0
 )
@@ -118,5 +118,5 @@
 preAdd 0
 posAdd 0
-o 30
+o 33
 suid 18,0
 )
@@ -190,5 +190,5 @@
 n "D0_SRCLK"
 t "STD_LOGIC"
-o 17
+o 20
 suid 24,0
 )
@@ -202,5 +202,5 @@
 n "D1_SRCLK"
 t "STD_LOGIC"
-o 18
+o 21
 suid 25,0
 )
@@ -214,5 +214,5 @@
 n "D2_SRCLK"
 t "STD_LOGIC"
-o 19
+o 22
 suid 26,0
 )
@@ -226,5 +226,5 @@
 n "D3_SRCLK"
 t "STD_LOGIC"
-o 20
+o 23
 suid 27,0
 )
@@ -283,5 +283,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 24
+o 27
 suid 32,0
 i "(others => '0')"
@@ -296,5 +296,5 @@
 n "DWRITE"
 t "std_logic"
-o 23
+o 26
 suid 33,0
 i "'0'"
@@ -309,5 +309,5 @@
 n "DAC_CS"
 t "std_logic"
-o 21
+o 24
 suid 34,0
 )
@@ -321,5 +321,5 @@
 n "T0_CS"
 t "std_logic"
-o 38
+o 42
 suid 35,0
 )
@@ -333,5 +333,5 @@
 n "T1_CS"
 t "std_logic"
-o 39
+o 43
 suid 36,0
 )
@@ -345,5 +345,5 @@
 n "T2_CS"
 t "std_logic"
-o 40
+o 44
 suid 37,0
 )
@@ -357,17 +357,17 @@
 n "T3_CS"
 t "std_logic"
+o 45
+suid 38,0
+)
+)
+uid 1346,0
+)
+*39 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "S_CLK"
+t "std_logic"
 o 41
-suid 38,0
-)
-)
-uid 1346,0
-)
-*39 (LogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "S_CLK"
-t "std_logic"
-o 37
 suid 39,0
 )
@@ -382,5 +382,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 43
+o 47
 suid 40,0
 )
@@ -395,5 +395,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 49
+o 53
 suid 41,0
 )
@@ -407,5 +407,5 @@
 n "W_RES"
 t "std_logic"
-o 46
+o 50
 suid 42,0
 i "'1'"
@@ -420,5 +420,5 @@
 n "W_RD"
 t "std_logic"
-o 45
+o 49
 suid 43,0
 i "'1'"
@@ -433,5 +433,5 @@
 n "W_WR"
 t "std_logic"
-o 47
+o 51
 suid 44,0
 i "'1'"
@@ -445,5 +445,5 @@
 n "W_INT"
 t "std_logic"
-o 12
+o 15
 suid 45,0
 )
@@ -457,5 +457,5 @@
 n "W_CS"
 t "std_logic"
-o 44
+o 48
 suid 46,0
 i "'1'"
@@ -470,5 +470,5 @@
 n "MOSI"
 t "std_logic"
-o 29
+o 32
 suid 47,0
 i "'0'"
@@ -485,5 +485,5 @@
 preAdd 0
 posAdd 0
-o 48
+o 52
 suid 48,0
 )
@@ -497,5 +497,5 @@
 n "TRG_V"
 t "std_logic"
-o 42
+o 46
 suid 49,0
 )
@@ -509,5 +509,5 @@
 n "RS485_C_RE"
 t "std_logic"
-o 32
+o 36
 suid 50,0
 )
@@ -521,5 +521,5 @@
 n "RS485_C_DE"
 t "std_logic"
-o 31
+o 34
 suid 51,0
 )
@@ -533,5 +533,5 @@
 n "RS485_E_RE"
 t "std_logic"
-o 34
+o 38
 suid 52,0
 )
@@ -545,5 +545,5 @@
 n "RS485_E_DE"
 t "std_logic"
-o 33
+o 37
 suid 53,0
 )
@@ -557,5 +557,5 @@
 n "DENABLE"
 t "std_logic"
-o 22
+o 25
 suid 54,0
 i "'0'"
@@ -570,6 +570,7 @@
 n "SRIN"
 t "std_logic"
-o 36
+o 40
 suid 55,0
+i "'0'"
 )
 )
@@ -582,5 +583,5 @@
 n "EE_CS"
 t "std_logic"
-o 27
+o 30
 suid 56,0
 )
@@ -595,5 +596,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 25
+o 28
 suid 61,0
 i "(OTHERS => '0')"
@@ -609,5 +610,5 @@
 t "std_logic_vector"
 b "( 2 DOWNTO 0 )"
-o 28
+o 31
 suid 62,0
 i "(others => '1')"
@@ -635,5 +636,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 26
+o 29
 suid 65,0
 i "(others => '0')"
@@ -649,5 +650,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 15
+o 18
 suid 66,0
 i "(OTHERS => '0')"
@@ -663,5 +664,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 14
+o 17
 suid 68,0
 i "(others => '0')"
@@ -669,4 +670,49 @@
 )
 uid 3455,0
+)
+*63 (LogPort
+port (LogicalPort
+decl (Decl
+n "RS485_C_DI"
+t "std_logic"
+o 11
+suid 69,0
+)
+)
+uid 3578,0
+)
+*64 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_DO"
+t "std_logic"
+o 35
+suid 70,0
+)
+)
+uid 3580,0
+)
+*65 (LogPort
+port (LogicalPort
+decl (Decl
+n "RS485_E_DI"
+t "std_logic"
+o 12
+suid 71,0
+)
+)
+uid 3684,0
+)
+*66 (LogPort
+port (LogicalPort
+decl (Decl
+n "RS485_E_DO"
+t "std_logic"
+o 13
+suid 72,0
+)
+)
+uid 3686,0
 )
 ]
@@ -677,5 +723,5 @@
 uid 66,0
 optionalChildren [
-*63 (Sheet
+*67 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -694,5 +740,5 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *64 (MRCItem
+emptyMRCItem *68 (MRCItem
 litem &1
 pos 3
@@ -701,5 +747,5 @@
 uid 68,0
 optionalChildren [
-*65 (MRCItem
+*69 (MRCItem
 litem &2
 pos 0
@@ -707,5 +753,5 @@
 uid 69,0
 )
-*66 (MRCItem
+*70 (MRCItem
 litem &3
 pos 1
@@ -713,5 +759,5 @@
 uid 70,0
 )
-*67 (MRCItem
+*71 (MRCItem
 litem &4
 pos 2
@@ -720,5 +766,5 @@
 uid 71,0
 )
-*68 (MRCItem
+*72 (MRCItem
 litem &14
 pos 0
@@ -726,5 +772,5 @@
 uid 689,0
 )
-*69 (MRCItem
+*73 (MRCItem
 litem &15
 pos 2
@@ -732,5 +778,5 @@
 uid 1110,0
 )
-*70 (MRCItem
+*74 (MRCItem
 litem &16
 pos 3
@@ -738,5 +784,5 @@
 uid 1112,0
 )
-*71 (MRCItem
+*75 (MRCItem
 litem &17
 pos 4
@@ -744,5 +790,5 @@
 uid 1114,0
 )
-*72 (MRCItem
+*76 (MRCItem
 litem &18
 pos 5
@@ -750,5 +796,5 @@
 uid 1154,0
 )
-*73 (MRCItem
+*77 (MRCItem
 litem &19
 pos 6
@@ -756,5 +802,5 @@
 uid 1156,0
 )
-*74 (MRCItem
+*78 (MRCItem
 litem &20
 pos 7
@@ -762,5 +808,5 @@
 uid 1158,0
 )
-*75 (MRCItem
+*79 (MRCItem
 litem &21
 pos 8
@@ -768,5 +814,5 @@
 uid 1160,0
 )
-*76 (MRCItem
+*80 (MRCItem
 litem &22
 pos 9
@@ -774,5 +820,5 @@
 uid 1162,0
 )
-*77 (MRCItem
+*81 (MRCItem
 litem &23
 pos 10
@@ -780,5 +826,5 @@
 uid 1164,0
 )
-*78 (MRCItem
+*82 (MRCItem
 litem &24
 pos 11
@@ -786,5 +832,5 @@
 uid 1219,0
 )
-*79 (MRCItem
+*83 (MRCItem
 litem &25
 pos 12
@@ -792,5 +838,5 @@
 uid 1221,0
 )
-*80 (MRCItem
+*84 (MRCItem
 litem &26
 pos 13
@@ -798,5 +844,5 @@
 uid 1223,0
 )
-*81 (MRCItem
+*85 (MRCItem
 litem &27
 pos 14
@@ -804,5 +850,5 @@
 uid 1225,0
 )
-*82 (MRCItem
+*86 (MRCItem
 litem &28
 pos 15
@@ -810,5 +856,5 @@
 uid 1270,0
 )
-*83 (MRCItem
+*87 (MRCItem
 litem &29
 pos 16
@@ -816,5 +862,5 @@
 uid 1272,0
 )
-*84 (MRCItem
+*88 (MRCItem
 litem &30
 pos 17
@@ -822,5 +868,5 @@
 uid 1274,0
 )
-*85 (MRCItem
+*89 (MRCItem
 litem &31
 pos 18
@@ -828,5 +874,5 @@
 uid 1276,0
 )
-*86 (MRCItem
+*90 (MRCItem
 litem &32
 pos 19
@@ -834,5 +880,5 @@
 uid 1278,0
 )
-*87 (MRCItem
+*91 (MRCItem
 litem &33
 pos 20
@@ -840,5 +886,5 @@
 uid 1280,0
 )
-*88 (MRCItem
+*92 (MRCItem
 litem &34
 pos 1
@@ -846,5 +892,5 @@
 uid 1337,0
 )
-*89 (MRCItem
+*93 (MRCItem
 litem &35
 pos 21
@@ -852,5 +898,5 @@
 uid 1339,0
 )
-*90 (MRCItem
+*94 (MRCItem
 litem &36
 pos 22
@@ -858,5 +904,5 @@
 uid 1341,0
 )
-*91 (MRCItem
+*95 (MRCItem
 litem &37
 pos 23
@@ -864,5 +910,5 @@
 uid 1343,0
 )
-*92 (MRCItem
+*96 (MRCItem
 litem &38
 pos 24
@@ -870,5 +916,5 @@
 uid 1345,0
 )
-*93 (MRCItem
+*97 (MRCItem
 litem &39
 pos 25
@@ -876,5 +922,5 @@
 uid 1347,0
 )
-*94 (MRCItem
+*98 (MRCItem
 litem &40
 pos 26
@@ -882,5 +928,5 @@
 uid 1349,0
 )
-*95 (MRCItem
+*99 (MRCItem
 litem &41
 pos 27
@@ -888,5 +934,5 @@
 uid 1351,0
 )
-*96 (MRCItem
+*100 (MRCItem
 litem &42
 pos 28
@@ -894,5 +940,5 @@
 uid 1353,0
 )
-*97 (MRCItem
+*101 (MRCItem
 litem &43
 pos 29
@@ -900,5 +946,5 @@
 uid 1355,0
 )
-*98 (MRCItem
+*102 (MRCItem
 litem &44
 pos 30
@@ -906,5 +952,5 @@
 uid 1357,0
 )
-*99 (MRCItem
+*103 (MRCItem
 litem &45
 pos 31
@@ -912,5 +958,5 @@
 uid 1359,0
 )
-*100 (MRCItem
+*104 (MRCItem
 litem &46
 pos 32
@@ -918,5 +964,5 @@
 uid 1361,0
 )
-*101 (MRCItem
+*105 (MRCItem
 litem &47
 pos 33
@@ -924,5 +970,5 @@
 uid 1616,0
 )
-*102 (MRCItem
+*106 (MRCItem
 litem &48
 pos 34
@@ -930,5 +976,5 @@
 uid 1618,0
 )
-*103 (MRCItem
+*107 (MRCItem
 litem &49
 pos 35
@@ -936,5 +982,5 @@
 uid 1654,0
 )
-*104 (MRCItem
+*108 (MRCItem
 litem &50
 pos 36
@@ -942,5 +988,5 @@
 uid 1656,0
 )
-*105 (MRCItem
+*109 (MRCItem
 litem &51
 pos 37
@@ -948,5 +994,5 @@
 uid 1658,0
 )
-*106 (MRCItem
+*110 (MRCItem
 litem &52
 pos 38
@@ -954,5 +1000,5 @@
 uid 1660,0
 )
-*107 (MRCItem
+*111 (MRCItem
 litem &53
 pos 39
@@ -960,5 +1006,5 @@
 uid 1662,0
 )
-*108 (MRCItem
+*112 (MRCItem
 litem &54
 pos 40
@@ -966,51 +1012,75 @@
 uid 1664,0
 )
-*109 (MRCItem
+*113 (MRCItem
 litem &55
+pos 52
+dimension 20
+uid 1666,0
+)
+*114 (MRCItem
+litem &56
 pos 41
 dimension 20
-uid 1666,0
-)
-*110 (MRCItem
-litem &56
+uid 1668,0
+)
+*115 (MRCItem
+litem &57
+pos 43
+dimension 20
+uid 2066,0
+)
+*116 (MRCItem
+litem &58
 pos 42
 dimension 20
-uid 1668,0
-)
-*111 (MRCItem
-litem &57
+uid 2373,0
+)
+*117 (MRCItem
+litem &59
 pos 44
 dimension 20
-uid 2066,0
-)
-*112 (MRCItem
-litem &58
-pos 43
-dimension 20
-uid 2373,0
-)
-*113 (MRCItem
-litem &59
+uid 2917,0
+)
+*118 (MRCItem
+litem &60
 pos 45
 dimension 20
-uid 2917,0
-)
-*114 (MRCItem
-litem &60
+uid 2947,0
+)
+*119 (MRCItem
+litem &61
 pos 46
 dimension 20
-uid 2947,0
-)
-*115 (MRCItem
-litem &61
+uid 3024,0
+)
+*120 (MRCItem
+litem &62
 pos 47
 dimension 20
-uid 3024,0
-)
-*116 (MRCItem
-litem &62
+uid 3454,0
+)
+*121 (MRCItem
+litem &63
 pos 48
 dimension 20
-uid 3454,0
+uid 3577,0
+)
+*122 (MRCItem
+litem &64
+pos 49
+dimension 20
+uid 3579,0
+)
+*123 (MRCItem
+litem &65
+pos 50
+dimension 20
+uid 3683,0
+)
+*124 (MRCItem
+litem &66
+pos 51
+dimension 20
+uid 3685,0
 )
 ]
@@ -1025,5 +1095,5 @@
 uid 72,0
 optionalChildren [
-*117 (MRCItem
+*125 (MRCItem
 litem &5
 pos 0
@@ -1031,5 +1101,5 @@
 uid 73,0
 )
-*118 (MRCItem
+*126 (MRCItem
 litem &7
 pos 1
@@ -1037,5 +1107,5 @@
 uid 74,0
 )
-*119 (MRCItem
+*127 (MRCItem
 litem &8
 pos 2
@@ -1043,5 +1113,5 @@
 uid 75,0
 )
-*120 (MRCItem
+*128 (MRCItem
 litem &9
 pos 3
@@ -1049,5 +1119,5 @@
 uid 76,0
 )
-*121 (MRCItem
+*129 (MRCItem
 litem &10
 pos 4
@@ -1055,5 +1125,5 @@
 uid 77,0
 )
-*122 (MRCItem
+*130 (MRCItem
 litem &11
 pos 5
@@ -1061,5 +1131,5 @@
 uid 78,0
 )
-*123 (MRCItem
+*131 (MRCItem
 litem &12
 pos 6
@@ -1067,5 +1137,5 @@
 uid 79,0
 )
-*124 (MRCItem
+*132 (MRCItem
 litem &13
 pos 7
@@ -1088,36 +1158,36 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *125 (LEmptyRow
+emptyRow *133 (LEmptyRow
 )
 uid 82,0
 optionalChildren [
-*126 (RefLabelRowHdr
-)
-*127 (TitleRowHdr
-)
-*128 (FilterRowHdr
-)
-*129 (RefLabelColHdr
+*134 (RefLabelRowHdr
+)
+*135 (TitleRowHdr
+)
+*136 (FilterRowHdr
+)
+*137 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*130 (RowExpandColHdr
+*138 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*131 (GroupColHdr
+*139 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*132 (NameColHdr
+*140 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*133 (TypeColHdr
+*141 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*134 (InitColHdr
+*142 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*135 (PragmaColHdr
+*143 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*136 (EolColHdr
+*144 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
@@ -1129,5 +1199,5 @@
 uid 94,0
 optionalChildren [
-*137 (Sheet
+*145 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -1146,6 +1216,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *138 (MRCItem
-litem &125
+emptyMRCItem *146 (MRCItem
+litem &133
 pos 3
 dimension 20
@@ -1153,18 +1223,18 @@
 uid 96,0
 optionalChildren [
-*139 (MRCItem
-litem &126
+*147 (MRCItem
+litem &134
 pos 0
 dimension 20
 uid 97,0
 )
-*140 (MRCItem
-litem &127
+*148 (MRCItem
+litem &135
 pos 1
 dimension 23
 uid 98,0
 )
-*141 (MRCItem
-litem &128
+*149 (MRCItem
+litem &136
 pos 2
 hidden 1
@@ -1183,42 +1253,42 @@
 uid 100,0
 optionalChildren [
-*142 (MRCItem
-litem &129
+*150 (MRCItem
+litem &137
 pos 0
 dimension 20
 uid 101,0
 )
-*143 (MRCItem
-litem &131
+*151 (MRCItem
+litem &139
 pos 1
 dimension 50
 uid 102,0
 )
-*144 (MRCItem
-litem &132
+*152 (MRCItem
+litem &140
 pos 2
 dimension 100
 uid 103,0
 )
-*145 (MRCItem
-litem &133
+*153 (MRCItem
+litem &141
 pos 3
 dimension 100
 uid 104,0
 )
-*146 (MRCItem
-litem &134
+*154 (MRCItem
+litem &142
 pos 4
 dimension 50
 uid 105,0
 )
-*147 (MRCItem
-litem &135
+*155 (MRCItem
+litem &143
 pos 5
 dimension 50
 uid 106,0
 )
-*148 (MRCItem
-litem &136
+*156 (MRCItem
+litem &144
 pos 6
 dimension 80
@@ -1243,21 +1313,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -1275,25 +1345,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
 )
 (vvPair
 variable "date"
-value "27.08.2010"
+value "03.01.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Mo"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Montag"
 )
 (vvPair
 variable "dd"
-value "27"
+value "03"
 )
 (vvPair
@@ -1355,5 +1425,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -1363,17 +1433,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
 )
 (vvPair
@@ -1431,5 +1501,5 @@
 (vvPair
 variable "time"
-value "17:10:56"
+value "16:58:24"
 )
 (vvPair
@@ -1451,9 +1521,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -1462,8 +1532,8 @@
 uid 51,0
 optionalChildren [
-*149 (SymbolBody
+*157 (SymbolBody
 uid 8,0
 optionalChildren [
-*150 (CptPort
+*158 (CptPort
 uid 693,0
 ps "OnEdgeStrategy"
@@ -1507,6 +1577,7 @@
 font "Courier New,8,0"
 )
-xt "44000,29200,76000,30000"
-st "RSRLOAD    : OUT    std_logic                       := '0' ;"
+xt "44000,32400,76000,33200"
+st "RSRLOAD    : OUT    std_logic                       := '0' ;
+"
 )
 thePort (LogicalPort
@@ -1515,5 +1586,5 @@
 n "RSRLOAD"
 t "std_logic"
-o 35
+o 39
 suid 11,0
 i "'0'"
@@ -1521,5 +1592,5 @@
 )
 )
-*151 (CptPort
+*159 (CptPort
 uid 1116,0
 ps "OnEdgeStrategy"
@@ -1552,6 +1623,7 @@
 font "Courier New,8,0"
 )
-xt "44000,11600,61500,12400"
-st "X_50M      : IN     STD_LOGIC  ;"
+xt "44000,14000,61500,14800"
+st "X_50M      : IN     STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -1561,10 +1633,10 @@
 preAdd 0
 posAdd 0
-o 13
+o 16
 suid 15,0
 )
 )
 )
-*152 (CptPort
+*160 (CptPort
 uid 1121,0
 ps "OnEdgeStrategy"
@@ -1597,6 +1669,7 @@
 font "Courier New,8,0"
 )
-xt "44000,10000,61500,10800"
-st "TRG        : IN     STD_LOGIC  ;"
+xt "44000,12400,61500,13200"
+st "TRG        : IN     STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -1604,10 +1677,10 @@
 n "TRG"
 t "STD_LOGIC"
-o 11
+o 14
 suid 16,0
 )
 )
 )
-*153 (CptPort
+*161 (CptPort
 uid 1126,0
 ps "OnEdgeStrategy"
@@ -1641,6 +1714,7 @@
 font "Courier New,8,0"
 )
-xt "44000,14000,71500,14800"
-st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;"
+xt "44000,16400,71500,17200"
+st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;
+"
 )
 thePort (LogicalPort
@@ -1650,10 +1724,10 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 16
+o 19
 suid 17,0
 )
 )
 )
-*154 (CptPort
+*162 (CptPort
 uid 1166,0
 ps "OnEdgeStrategy"
@@ -1687,6 +1761,7 @@
 font "Courier New,8,0"
 )
-xt "44000,25200,61500,26000"
-st "OE_ADC     : OUT    STD_LOGIC  ;"
+xt "44000,27600,61500,28400"
+st "OE_ADC     : OUT    STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -1697,10 +1772,10 @@
 preAdd 0
 posAdd 0
-o 30
+o 33
 suid 18,0
 )
 )
 )
-*155 (CptPort
+*163 (CptPort
 uid 1171,0
 ps "OnEdgeStrategy"
@@ -1734,5 +1809,6 @@
 )
 xt "44000,5200,71500,6000"
-st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;"
+st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -1746,5 +1822,5 @@
 )
 )
-*156 (CptPort
+*164 (CptPort
 uid 1176,0
 ps "OnEdgeStrategy"
@@ -1778,5 +1854,6 @@
 )
 xt "44000,2000,72000,2800"
-st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
+st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -1790,5 +1867,5 @@
 )
 )
-*157 (CptPort
+*165 (CptPort
 uid 1181,0
 ps "OnEdgeStrategy"
@@ -1822,5 +1899,6 @@
 )
 xt "44000,2800,72000,3600"
-st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
+st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -1834,5 +1912,5 @@
 )
 )
-*158 (CptPort
+*166 (CptPort
 uid 1186,0
 ps "OnEdgeStrategy"
@@ -1866,5 +1944,6 @@
 )
 xt "44000,3600,72000,4400"
-st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
+st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -1878,5 +1957,5 @@
 )
 )
-*159 (CptPort
+*167 (CptPort
 uid 1191,0
 ps "OnEdgeStrategy"
@@ -1910,5 +1989,6 @@
 )
 xt "44000,4400,72000,5200"
-st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
+st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -1922,5 +2002,5 @@
 )
 )
-*160 (CptPort
+*168 (CptPort
 uid 1227,0
 ps "OnEdgeStrategy"
@@ -1954,6 +2034,7 @@
 font "Courier New,8,0"
 )
-xt "44000,14800,61500,15600"
-st "D0_SRCLK   : OUT    STD_LOGIC  ;"
+xt "44000,17200,61500,18000"
+st "D0_SRCLK   : OUT    STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -1962,10 +2043,10 @@
 n "D0_SRCLK"
 t "STD_LOGIC"
-o 17
+o 20
 suid 24,0
 )
 )
 )
-*161 (CptPort
+*169 (CptPort
 uid 1232,0
 ps "OnEdgeStrategy"
@@ -1999,6 +2080,7 @@
 font "Courier New,8,0"
 )
-xt "44000,15600,61500,16400"
-st "D1_SRCLK   : OUT    STD_LOGIC  ;"
+xt "44000,18000,61500,18800"
+st "D1_SRCLK   : OUT    STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -2007,10 +2089,10 @@
 n "D1_SRCLK"
 t "STD_LOGIC"
-o 18
+o 21
 suid 25,0
 )
 )
 )
-*162 (CptPort
+*170 (CptPort
 uid 1237,0
 ps "OnEdgeStrategy"
@@ -2044,6 +2126,7 @@
 font "Courier New,8,0"
 )
-xt "44000,16400,61500,17200"
-st "D2_SRCLK   : OUT    STD_LOGIC  ;"
+xt "44000,18800,61500,19600"
+st "D2_SRCLK   : OUT    STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -2052,10 +2135,10 @@
 n "D2_SRCLK"
 t "STD_LOGIC"
-o 19
+o 22
 suid 26,0
 )
 )
 )
-*163 (CptPort
+*171 (CptPort
 uid 1242,0
 ps "OnEdgeStrategy"
@@ -2089,6 +2172,7 @@
 font "Courier New,8,0"
 )
-xt "44000,17200,61500,18000"
-st "D3_SRCLK   : OUT    STD_LOGIC  ;"
+xt "44000,19600,61500,20400"
+st "D3_SRCLK   : OUT    STD_LOGIC  ;
+"
 )
 thePort (LogicalPort
@@ -2097,10 +2181,10 @@
 n "D3_SRCLK"
 t "STD_LOGIC"
-o 20
+o 23
 suid 27,0
 )
 )
 )
-*164 (CptPort
+*172 (CptPort
 uid 1282,0
 ps "OnEdgeStrategy"
@@ -2134,5 +2218,6 @@
 )
 xt "44000,6000,61500,6800"
-st "D0_SROUT   : IN     std_logic  ;"
+st "D0_SROUT   : IN     std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2145,5 +2230,5 @@
 )
 )
-*165 (CptPort
+*173 (CptPort
 uid 1287,0
 ps "OnEdgeStrategy"
@@ -2177,5 +2262,6 @@
 )
 xt "44000,6800,61500,7600"
-st "D1_SROUT   : IN     std_logic  ;"
+st "D1_SROUT   : IN     std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2188,5 +2274,5 @@
 )
 )
-*166 (CptPort
+*174 (CptPort
 uid 1292,0
 ps "OnEdgeStrategy"
@@ -2220,5 +2306,6 @@
 )
 xt "44000,7600,61500,8400"
-st "D2_SROUT   : IN     std_logic  ;"
+st "D2_SROUT   : IN     std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2231,5 +2318,5 @@
 )
 )
-*167 (CptPort
+*175 (CptPort
 uid 1297,0
 ps "OnEdgeStrategy"
@@ -2263,5 +2350,6 @@
 )
 xt "44000,8400,61500,9200"
-st "D3_SROUT   : IN     std_logic  ;"
+st "D3_SROUT   : IN     std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2274,5 +2362,5 @@
 )
 )
-*168 (CptPort
+*176 (CptPort
 uid 1302,0
 ps "OnEdgeStrategy"
@@ -2316,6 +2404,7 @@
 font "Courier New,8,0"
 )
-xt "44000,20400,82000,21200"
-st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
+xt "44000,22800,82000,23600"
+st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;
+"
 )
 thePort (LogicalPort
@@ -2325,5 +2414,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 24
+o 27
 suid 32,0
 i "(others => '0')"
@@ -2331,5 +2420,5 @@
 )
 )
-*169 (CptPort
+*177 (CptPort
 uid 1308,0
 ps "OnEdgeStrategy"
@@ -2373,6 +2462,7 @@
 font "Courier New,8,0"
 )
-xt "44000,19600,76000,20400"
-st "DWRITE     : OUT    std_logic                       := '0' ;"
+xt "44000,22000,76000,22800"
+st "DWRITE     : OUT    std_logic                       := '0' ;
+"
 )
 thePort (LogicalPort
@@ -2381,5 +2471,5 @@
 n "DWRITE"
 t "std_logic"
-o 23
+o 26
 suid 33,0
 i "'0'"
@@ -2387,5 +2477,5 @@
 )
 )
-*170 (CptPort
+*178 (CptPort
 uid 1363,0
 ps "OnEdgeStrategy"
@@ -2419,6 +2509,7 @@
 font "Courier New,8,0"
 )
-xt "44000,18000,61500,18800"
-st "DAC_CS     : OUT    std_logic  ;"
+xt "44000,20400,61500,21200"
+st "DAC_CS     : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2427,10 +2518,10 @@
 n "DAC_CS"
 t "std_logic"
-o 21
+o 24
 suid 34,0
 )
 )
 )
-*171 (CptPort
+*179 (CptPort
 uid 1368,0
 ps "OnEdgeStrategy"
@@ -2464,6 +2555,7 @@
 font "Courier New,8,0"
 )
-xt "44000,31600,61500,32400"
-st "T0_CS      : OUT    std_logic  ;"
+xt "44000,34800,61500,35600"
+st "T0_CS      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2472,10 +2564,10 @@
 n "T0_CS"
 t "std_logic"
-o 38
+o 42
 suid 35,0
 )
 )
 )
-*172 (CptPort
+*180 (CptPort
 uid 1373,0
 ps "OnEdgeStrategy"
@@ -2509,6 +2601,7 @@
 font "Courier New,8,0"
 )
-xt "44000,32400,61500,33200"
-st "T1_CS      : OUT    std_logic  ;"
+xt "44000,35600,61500,36400"
+st "T1_CS      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2517,10 +2610,10 @@
 n "T1_CS"
 t "std_logic"
-o 39
+o 43
 suid 36,0
 )
 )
 )
-*173 (CptPort
+*181 (CptPort
 uid 1378,0
 ps "OnEdgeStrategy"
@@ -2554,6 +2647,7 @@
 font "Courier New,8,0"
 )
-xt "44000,33200,61500,34000"
-st "T2_CS      : OUT    std_logic  ;"
+xt "44000,36400,61500,37200"
+st "T2_CS      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2562,10 +2656,10 @@
 n "T2_CS"
 t "std_logic"
-o 40
+o 44
 suid 37,0
 )
 )
 )
-*174 (CptPort
+*182 (CptPort
 uid 1383,0
 ps "OnEdgeStrategy"
@@ -2599,6 +2693,7 @@
 font "Courier New,8,0"
 )
-xt "44000,34000,61500,34800"
-st "T3_CS      : OUT    std_logic  ;"
+xt "44000,37200,61500,38000"
+st "T3_CS      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2607,10 +2702,10 @@
 n "T3_CS"
 t "std_logic"
-o 41
+o 45
 suid 38,0
 )
 )
 )
-*175 (CptPort
+*183 (CptPort
 uid 1388,0
 ps "OnEdgeStrategy"
@@ -2644,6 +2739,7 @@
 font "Courier New,8,0"
 )
-xt "44000,30800,61500,31600"
-st "S_CLK      : OUT    std_logic  ;"
+xt "44000,34000,61500,34800"
+st "S_CLK      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2652,10 +2748,10 @@
 n "S_CLK"
 t "std_logic"
-o 37
+o 41
 suid 39,0
 )
 )
 )
-*176 (CptPort
+*184 (CptPort
 uid 1393,0
 ps "OnEdgeStrategy"
@@ -2689,6 +2785,7 @@
 font "Courier New,8,0"
 )
-xt "44000,35600,71500,36400"
-st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;"
+xt "44000,38800,71500,39600"
+st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -2698,10 +2795,10 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 43
+o 47
 suid 40,0
 )
 )
 )
-*177 (CptPort
+*185 (CptPort
 uid 1398,0
 ps "OnEdgeStrategy"
@@ -2735,6 +2832,7 @@
 font "Courier New,8,0"
 )
-xt "44000,40400,71000,41200"
-st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)"
+xt "44000,43600,71000,44400"
+st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
+"
 )
 thePort (LogicalPort
@@ -2744,10 +2842,10 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 49
+o 53
 suid 41,0
 )
 )
 )
-*178 (CptPort
+*186 (CptPort
 uid 1403,0
 ps "OnEdgeStrategy"
@@ -2791,6 +2889,7 @@
 font "Courier New,8,0"
 )
-xt "44000,38000,76000,38800"
-st "W_RES      : OUT    std_logic                       := '1' ;"
+xt "44000,41200,76000,42000"
+st "W_RES      : OUT    std_logic                       := '1' ;
+"
 )
 thePort (LogicalPort
@@ -2799,5 +2898,5 @@
 n "W_RES"
 t "std_logic"
-o 46
+o 50
 suid 42,0
 i "'1'"
@@ -2805,5 +2904,5 @@
 )
 )
-*179 (CptPort
+*187 (CptPort
 uid 1409,0
 ps "OnEdgeStrategy"
@@ -2847,6 +2946,7 @@
 font "Courier New,8,0"
 )
-xt "44000,37200,76000,38000"
-st "W_RD       : OUT    std_logic                       := '1' ;"
+xt "44000,40400,76000,41200"
+st "W_RD       : OUT    std_logic                       := '1' ;
+"
 )
 thePort (LogicalPort
@@ -2855,5 +2955,5 @@
 n "W_RD"
 t "std_logic"
-o 45
+o 49
 suid 43,0
 i "'1'"
@@ -2861,5 +2961,5 @@
 )
 )
-*180 (CptPort
+*188 (CptPort
 uid 1415,0
 ps "OnEdgeStrategy"
@@ -2903,6 +3003,7 @@
 font "Courier New,8,0"
 )
-xt "44000,38800,76000,39600"
-st "W_WR       : OUT    std_logic                       := '1' ;"
+xt "44000,42000,76000,42800"
+st "W_WR       : OUT    std_logic                       := '1' ;
+"
 )
 thePort (LogicalPort
@@ -2911,5 +3012,5 @@
 n "W_WR"
 t "std_logic"
-o 47
+o 51
 suid 44,0
 i "'1'"
@@ -2917,5 +3018,5 @@
 )
 )
-*181 (CptPort
+*189 (CptPort
 uid 1421,0
 ps "OnEdgeStrategy"
@@ -2948,6 +3049,7 @@
 font "Courier New,8,0"
 )
-xt "44000,10800,61500,11600"
-st "W_INT      : IN     std_logic  ;"
+xt "44000,13200,61500,14000"
+st "W_INT      : IN     std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -2955,10 +3057,10 @@
 n "W_INT"
 t "std_logic"
-o 12
+o 15
 suid 45,0
 )
 )
 )
-*182 (CptPort
+*190 (CptPort
 uid 1426,0
 ps "OnEdgeStrategy"
@@ -3002,6 +3104,7 @@
 font "Courier New,8,0"
 )
-xt "44000,36400,76000,37200"
-st "W_CS       : OUT    std_logic                       := '1' ;"
+xt "44000,39600,76000,40400"
+st "W_CS       : OUT    std_logic                       := '1' ;
+"
 )
 thePort (LogicalPort
@@ -3010,5 +3113,5 @@
 n "W_CS"
 t "std_logic"
-o 44
+o 48
 suid 46,0
 i "'1'"
@@ -3016,5 +3119,5 @@
 )
 )
-*183 (CptPort
+*191 (CptPort
 uid 1620,0
 ps "OnEdgeStrategy"
@@ -3058,6 +3161,7 @@
 font "Courier New,8,0"
 )
-xt "44000,24400,76000,25200"
-st "MOSI       : OUT    std_logic                       := '0' ;"
+xt "44000,26800,76000,27600"
+st "MOSI       : OUT    std_logic                       := '0' ;
+"
 )
 thePort (LogicalPort
@@ -3066,5 +3170,5 @@
 n "MOSI"
 t "std_logic"
-o 29
+o 32
 suid 47,0
 i "'0'"
@@ -3072,5 +3176,5 @@
 )
 )
-*184 (CptPort
+*192 (CptPort
 uid 1626,0
 ps "OnEdgeStrategy"
@@ -3104,6 +3208,7 @@
 font "Courier New,8,0"
 )
-xt "44000,39600,61500,40400"
-st "MISO       : INOUT  std_logic  ;"
+xt "44000,42800,61500,43600"
+st "MISO       : INOUT  std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3114,10 +3219,10 @@
 preAdd 0
 posAdd 0
-o 48
+o 52
 suid 48,0
 )
 )
 )
-*185 (CptPort
+*193 (CptPort
 uid 1676,0
 ps "OnEdgeStrategy"
@@ -3151,6 +3256,7 @@
 font "Courier New,8,0"
 )
-xt "44000,34800,61500,35600"
-st "TRG_V      : OUT    std_logic  ;"
+xt "44000,38000,61500,38800"
+st "TRG_V      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3159,10 +3265,10 @@
 n "TRG_V"
 t "std_logic"
-o 42
+o 46
 suid 49,0
 )
 )
 )
-*186 (CptPort
+*194 (CptPort
 uid 1681,0
 ps "OnEdgeStrategy"
@@ -3196,6 +3302,7 @@
 font "Courier New,8,0"
 )
-xt "44000,26800,61500,27600"
-st "RS485_C_RE : OUT    std_logic  ;"
+xt "44000,30000,61500,30800"
+st "RS485_C_RE : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3204,10 +3311,10 @@
 n "RS485_C_RE"
 t "std_logic"
-o 32
+o 36
 suid 50,0
 )
 )
 )
-*187 (CptPort
+*195 (CptPort
 uid 1686,0
 ps "OnEdgeStrategy"
@@ -3241,6 +3348,7 @@
 font "Courier New,8,0"
 )
-xt "44000,26000,61500,26800"
-st "RS485_C_DE : OUT    std_logic  ;"
+xt "44000,28400,61500,29200"
+st "RS485_C_DE : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3249,10 +3357,10 @@
 n "RS485_C_DE"
 t "std_logic"
-o 31
+o 34
 suid 51,0
 )
 )
 )
-*188 (CptPort
+*196 (CptPort
 uid 1691,0
 ps "OnEdgeStrategy"
@@ -3286,6 +3394,7 @@
 font "Courier New,8,0"
 )
-xt "44000,28400,61500,29200"
-st "RS485_E_RE : OUT    std_logic  ;"
+xt "44000,31600,61500,32400"
+st "RS485_E_RE : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3294,10 +3403,10 @@
 n "RS485_E_RE"
 t "std_logic"
-o 34
+o 38
 suid 52,0
 )
 )
 )
-*189 (CptPort
+*197 (CptPort
 uid 1696,0
 ps "OnEdgeStrategy"
@@ -3331,6 +3440,7 @@
 font "Courier New,8,0"
 )
-xt "44000,27600,61500,28400"
-st "RS485_E_DE : OUT    std_logic  ;"
+xt "44000,30800,61500,31600"
+st "RS485_E_DE : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3339,10 +3449,10 @@
 n "RS485_E_DE"
 t "std_logic"
-o 33
+o 37
 suid 53,0
 )
 )
 )
-*190 (CptPort
+*198 (CptPort
 uid 1701,0
 ps "OnEdgeStrategy"
@@ -3386,6 +3496,7 @@
 font "Courier New,8,0"
 )
-xt "44000,18800,76000,19600"
-st "DENABLE    : OUT    std_logic                       := '0' ;"
+xt "44000,21200,76000,22000"
+st "DENABLE    : OUT    std_logic                       := '0' ;
+"
 )
 thePort (LogicalPort
@@ -3394,5 +3505,5 @@
 n "DENABLE"
 t "std_logic"
-o 22
+o 25
 suid 54,0
 i "'0'"
@@ -3400,5 +3511,5 @@
 )
 )
-*191 (CptPort
+*199 (CptPort
 uid 1706,0
 ps "OnEdgeStrategy"
@@ -3426,4 +3537,13 @@
 tm "CptPortNameMgr"
 )
+t (Text
+va (VaSet
+)
+xt "30800,74500,32000,75500"
+st "'0'"
+ju 2
+blo "32000,75300"
+tm "InitValueDelayMgr"
+)
 )
 dt (MLText
@@ -3432,6 +3552,7 @@
 font "Courier New,8,0"
 )
-xt "44000,30000,61500,30800"
-st "SRIN       : OUT    std_logic  ;"
+xt "44000,33200,76000,34000"
+st "SRIN       : OUT    std_logic                       := '0' ;
+"
 )
 thePort (LogicalPort
@@ -3440,10 +3561,11 @@
 n "SRIN"
 t "std_logic"
-o 36
+o 40
 suid 55,0
-)
-)
-)
-*192 (CptPort
+i "'0'"
+)
+)
+)
+*200 (CptPort
 uid 1711,0
 ps "OnEdgeStrategy"
@@ -3477,6 +3599,7 @@
 font "Courier New,8,0"
 )
-xt "44000,22800,61500,23600"
-st "EE_CS      : OUT    std_logic  ;"
+xt "44000,25200,61500,26000"
+st "EE_CS      : OUT    std_logic  ;
+"
 )
 thePort (LogicalPort
@@ -3485,10 +3608,10 @@
 n "EE_CS"
 t "std_logic"
-o 27
+o 30
 suid 56,0
 )
 )
 )
-*193 (CptPort
+*201 (CptPort
 uid 2068,0
 ps "OnEdgeStrategy"
@@ -3532,6 +3655,7 @@
 font "Courier New,8,0"
 )
-xt "44000,21200,82000,22000"
-st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;"
+xt "44000,23600,82000,24400"
+st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;
+"
 )
 thePort (LogicalPort
@@ -3541,5 +3665,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 25
+o 28
 suid 61,0
 i "(OTHERS => '0')"
@@ -3547,5 +3671,5 @@
 )
 )
-*194 (CptPort
+*202 (CptPort
 uid 2375,0
 ps "OnEdgeStrategy"
@@ -3589,6 +3713,7 @@
 font "Courier New,8,0"
 )
-xt "44000,23600,82000,24400"
-st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;"
+xt "44000,26000,82000,26800"
+st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;
+"
 )
 thePort (LogicalPort
@@ -3598,5 +3723,5 @@
 t "std_logic_vector"
 b "( 2 DOWNTO 0 )"
-o 28
+o 31
 suid 62,0
 i "(others => '1')"
@@ -3604,5 +3729,5 @@
 )
 )
-*195 (CptPort
+*203 (CptPort
 uid 2919,0
 ps "OnEdgeStrategy"
@@ -3636,5 +3761,6 @@
 )
 xt "44000,9200,71500,10000"
-st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;"
+st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;
+"
 )
 thePort (LogicalPort
@@ -3648,5 +3774,5 @@
 )
 )
-*196 (CptPort
+*204 (CptPort
 uid 2949,0
 ps "OnEdgeStrategy"
@@ -3690,6 +3816,7 @@
 font "Courier New,8,0"
 )
-xt "44000,22000,82000,22800"
-st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
+xt "44000,24400,82000,25200"
+st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;
+"
 )
 thePort (LogicalPort
@@ -3699,5 +3826,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 26
+o 29
 suid 65,0
 i "(others => '0')"
@@ -3705,5 +3832,5 @@
 )
 )
-*197 (CptPort
+*205 (CptPort
 uid 3026,0
 ps "OnEdgeStrategy"
@@ -3747,6 +3874,7 @@
 font "Courier New,8,0"
 )
-xt "44000,13200,82000,14000"
-st "A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;"
+xt "44000,15600,82000,16400"
+st "A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;
+"
 )
 thePort (LogicalPort
@@ -3756,5 +3884,5 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 15
+o 18
 suid 66,0
 i "(OTHERS => '0')"
@@ -3762,5 +3890,5 @@
 )
 )
-*198 (CptPort
+*206 (CptPort
 uid 3456,0
 ps "OnEdgeStrategy"
@@ -3804,6 +3932,7 @@
 font "Courier New,8,0"
 )
-xt "44000,12400,82000,13200"
-st "A0_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (others => '0') ;"
+xt "44000,14800,82000,15600"
+st "A0_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (others => '0') ;
+"
 )
 thePort (LogicalPort
@@ -3813,7 +3942,185 @@
 t "std_logic_vector"
 b "(7 DOWNTO 0)"
-o 14
+o 17
 suid 68,0
 i "(others => '0')"
+)
+)
+)
+*207 (CptPort
+uid 3581,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3582,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,47625,15000,48375"
+)
+tg (CPTG
+uid 3583,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3584,0
+va (VaSet
+)
+xt "16000,47500,21300,48500"
+st "RS485_C_DI"
+blo "16000,48300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 3585,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,10000,61500,10800"
+st "RS485_C_DI : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "RS485_C_DI"
+t "std_logic"
+o 11
+suid 69,0
+)
+)
+)
+*208 (CptPort
+uid 3586,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3587,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "33000,101625,33750,102375"
+)
+tg (CPTG
+uid 3588,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3589,0
+va (VaSet
+)
+xt "26300,101500,32000,102500"
+st "RS485_C_DO"
+ju 2
+blo "32000,102300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 3590,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,29200,61500,30000"
+st "RS485_C_DO : OUT    std_logic  ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "RS485_C_DO"
+t "std_logic"
+o 35
+suid 70,0
+)
+)
+)
+*209 (CptPort
+uid 3687,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3688,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,49625,15000,50375"
+)
+tg (CPTG
+uid 3689,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3690,0
+va (VaSet
+)
+xt "16000,49500,21200,50500"
+st "RS485_E_DI"
+blo "16000,50300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 3691,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,10800,61500,11600"
+st "RS485_E_DI : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "RS485_E_DI"
+t "std_logic"
+o 12
+suid 71,0
+)
+)
+)
+*210 (CptPort
+uid 3692,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3789,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,51625,15000,52375"
+)
+tg (CPTG
+uid 3694,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3695,0
+va (VaSet
+)
+xt "16000,51500,21600,52500"
+st "RS485_E_DO"
+blo "16000,52300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 3696,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,11600,61500,12400"
+st "RS485_E_DO : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "RS485_E_DO"
+t "std_logic"
+o 13
+suid 72,0
 )
 )
@@ -3828,5 +4135,5 @@
 lineWidth 2
 )
-xt "15000,6000,33000,101000"
+xt "15000,6000,33000,105000"
 )
 oxt "15000,6000,33000,26000"
@@ -3854,5 +4161,5 @@
 )
 )
-gi *199 (GenericInterface
+gi *211 (GenericInterface
 uid 13,0
 ps "CenterOffsetStrategy"
@@ -3881,8 +4188,8 @@
 )
 )
-*200 (Grouping
+*212 (Grouping
 uid 16,0
 optionalChildren [
-*201 (CommentText
+*213 (CommentText
 uid 18,0
 shape (Rectangle
@@ -3902,5 +4209,5 @@
 bg "0,0,32768"
 )
-xt "36200,48000,45900,49000"
+xt "36200,48000,45700,49000"
 st "
 by %user on %dd %month %year
@@ -3915,5 +4222,5 @@
 titleBlock 1
 )
-*202 (CommentText
+*214 (CommentText
 uid 21,0
 shape (Rectangle
@@ -3946,5 +4253,5 @@
 titleBlock 1
 )
-*203 (CommentText
+*215 (CommentText
 uid 24,0
 shape (Rectangle
@@ -3977,5 +4284,5 @@
 titleBlock 1
 )
-*204 (CommentText
+*216 (CommentText
 uid 27,0
 shape (Rectangle
@@ -4008,5 +4315,5 @@
 titleBlock 1
 )
-*205 (CommentText
+*217 (CommentText
 uid 30,0
 shape (Rectangle
@@ -4038,5 +4345,5 @@
 titleBlock 1
 )
-*206 (CommentText
+*218 (CommentText
 uid 33,0
 shape (Rectangle
@@ -4069,5 +4376,5 @@
 titleBlock 1
 )
-*207 (CommentText
+*219 (CommentText
 uid 36,0
 shape (Rectangle
@@ -4101,5 +4408,5 @@
 titleBlock 1
 )
-*208 (CommentText
+*220 (CommentText
 uid 39,0
 shape (Rectangle
@@ -4132,5 +4439,5 @@
 titleBlock 1
 )
-*209 (CommentText
+*221 (CommentText
 uid 42,0
 shape (Rectangle
@@ -4163,5 +4470,5 @@
 titleBlock 1
 )
-*210 (CommentText
+*222 (CommentText
 uid 45,0
 shape (Rectangle
@@ -4219,9 +4526,9 @@
 color "26368,26368,26368"
 )
-packageList *211 (PackageList
+packageList *223 (PackageList
 uid 48,0
 stg "VerticalLayoutStrategy"
 textVec [
-*212 (Text
+*224 (Text
 uid 49,0
 va (VaSet
@@ -4232,5 +4539,5 @@
 blo "0,800"
 )
-*213 (MLText
+*225 (MLText
 uid 50,0
 va (VaSet
@@ -4330,5 +4637,5 @@
 )
 )
-gi *214 (GenericInterface
+gi *226 (GenericInterface
 ps "CenterOffsetStrategy"
 matrix (Matrix
@@ -4427,5 +4734,5 @@
 )
 )
-DeclarativeBlock *215 (SymDeclBlock
+DeclarativeBlock *227 (SymDeclBlock
 uid 1,0
 stg "SymDeclLayoutStrategy"
@@ -4453,7 +4760,7 @@
 font "Arial,8,1"
 )
-xt "42000,41200,44400,42200"
+xt "42000,44400,44400,45400"
 st "User:"
-blo "42000,42000"
+blo "42000,45200"
 )
 internalLabel (Text
@@ -4472,5 +4779,5 @@
 font "Courier New,8,0"
 )
-xt "44000,42200,44000,42200"
+xt "44000,45400,44000,45400"
 tm "SyDeclarativeTextMgr"
 )
@@ -4485,5 +4792,5 @@
 )
 )
-lastUid 3530,0
+lastUid 3958,0
 activeModelName "Symbol:CDM"
 )
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd	(revision 10073)
@@ -224,4 +224,13 @@
 uid 9957,0
 )
+(Instance
+name "U_9"
+duLibraryName "moduleware"
+duName "or"
+elements [
+]
+mwi 1
+uid 10380,0
+)
 ]
 libraryRefs [
@@ -239,21 +248,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -271,25 +280,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main"
 )
 (vvPair
 variable "date"
-value "30.08.2010"
+value "04.01.2011"
 )
 (vvPair
 variable "day"
-value "Mo"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Montag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "30"
+value "04"
 )
 (vvPair
@@ -355,5 +364,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -363,17 +372,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
 )
 (vvPair
@@ -431,5 +440,5 @@
 (vvPair
 variable "time"
-value "10:49:09"
+value "11:02:29"
 )
 (vvPair
@@ -451,9 +460,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -522,7 +531,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,105000,-59500,105800"
-st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
-"
+xt "-103000,114600,-59500,115400"
+st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
 )
 )
@@ -541,7 +549,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,61000,-63000,61800"
-st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
-"
+xt "-103000,61800,-63000,62600"
+st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
 )
 )
@@ -560,7 +567,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,75400,-70500,76200"
-st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
-"
+xt "-103000,79400,-70500,80200"
+st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
 )
 )
@@ -579,7 +585,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,87400,-63000,88200"
-st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
-"
+xt "-103000,92200,-63000,93000"
+st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
 )
 )
@@ -598,7 +603,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,88200,-70500,89000"
-st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
-"
+xt "-103000,93000,-70500,93800"
+st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
 )
 )
@@ -617,7 +621,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,52600,-63000,53400"
-st "wiz_reset              : std_logic                                    := '1'
-"
+xt "-103000,53400,-63000,54200"
+st "wiz_reset              : std_logic                                    := '1'"
 )
 )
@@ -636,7 +639,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,50200,-74500,51000"
-st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
-"
+xt "-103000,51000,-74500,51800"
+st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
 )
 )
@@ -655,7 +657,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,55000,-74000,55800"
-st "wiz_data               : std_logic_vector(15 DOWNTO 0)
-"
+xt "-103000,55800,-74000,56600"
+st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
 )
 )
@@ -674,7 +675,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,51000,-63000,51800"
-st "wiz_cs                 : std_logic                                    := '1'
-"
+xt "-103000,51800,-63000,52600"
+st "wiz_cs                 : std_logic                                    := '1'"
 )
 )
@@ -693,7 +693,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,53400,-63000,54200"
-st "wiz_wr                 : std_logic                                    := '1'
-"
+xt "-103000,54200,-63000,55000"
+st "wiz_wr                 : std_logic                                    := '1'"
 )
 )
@@ -712,7 +711,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,51800,-63000,52600"
-st "wiz_rd                 : std_logic                                    := '1'
-"
+xt "-103000,52600,-63000,53400"
+st "wiz_rd                 : std_logic                                    := '1'"
 )
 )
@@ -731,6 +729,5 @@
 )
 xt "-103000,26200,-84500,27000"
-st "wiz_int                : std_logic
-"
+st "wiz_int                : std_logic"
 )
 )
@@ -748,5 +745,5 @@
 sl 0
 ro 270
-xt "153500,51625,155000,52375"
+xt "154500,51625,156000,52375"
 )
 (Line
@@ -754,8 +751,8 @@
 sl 0
 ro 270
-xt "153000,52000,153500,52000"
-pts [
-"153000,52000"
-"153500,52000"
+xt "154000,52000,154500,52000"
+pts [
+"154000,52000"
+"154500,52000"
 ]
 )
@@ -771,7 +768,7 @@
 va (VaSet
 )
-xt "156000,51500,159600,52500"
+xt "157000,51500,160600,52500"
 st "wiz_reset"
-blo "156000,52300"
+blo "157000,52300"
 tm "WireNameMgr"
 )
@@ -791,5 +788,5 @@
 sl 0
 ro 270
-xt "153500,59625,155000,60375"
+xt "154500,59625,156000,60375"
 )
 (Line
@@ -797,8 +794,8 @@
 sl 0
 ro 270
-xt "153000,60000,153500,60000"
-pts [
-"153000,60000"
-"153500,60000"
+xt "154000,60000,154500,60000"
+pts [
+"154000,60000"
+"154500,60000"
 ]
 )
@@ -814,7 +811,7 @@
 va (VaSet
 )
-xt "156000,59500,162000,60500"
+xt "157000,59500,163000,60500"
 st "wiz_addr : (9:0)"
-blo "156000,60300"
+blo "157000,60300"
 tm "WireNameMgr"
 )
@@ -833,13 +830,13 @@
 uid 468,0
 sl 0
-xt "153500,60625,155000,61375"
+xt "154500,60625,156000,61375"
 )
 (Line
 uid 469,0
 sl 0
-xt "153000,61000,153500,61000"
-pts [
-"153000,61000"
-"153500,61000"
+xt "154000,61000,154500,61000"
+pts [
+"154000,61000"
+"154500,61000"
 ]
 )
@@ -855,7 +852,7 @@
 va (VaSet
 )
-xt "156000,60500,162300,61500"
+xt "157000,60500,163300,61500"
 st "wiz_data : (15:0)"
-blo "156000,61300"
+blo "157000,61300"
 tm "WireNameMgr"
 )
@@ -875,5 +872,5 @@
 sl 0
 ro 270
-xt "153500,52625,155000,53375"
+xt "154500,52625,156000,53375"
 )
 (Line
@@ -881,8 +878,8 @@
 sl 0
 ro 270
-xt "153000,53000,153500,53000"
-pts [
-"153000,53000"
-"153500,53000"
+xt "154000,53000,154500,53000"
+pts [
+"154000,53000"
+"154500,53000"
 ]
 )
@@ -899,7 +896,7 @@
 va (VaSet
 )
-xt "156000,52500,158700,53500"
+xt "157000,52500,159700,53500"
 st "wiz_cs"
-blo "156000,53300"
+blo "157000,53300"
 tm "WireNameMgr"
 )
@@ -919,5 +916,5 @@
 sl 0
 ro 270
-xt "153500,53625,155000,54375"
+xt "154500,53625,156000,54375"
 )
 (Line
@@ -925,8 +922,8 @@
 sl 0
 ro 270
-xt "153000,54000,153500,54000"
-pts [
-"153000,54000"
-"153500,54000"
+xt "154000,54000,154500,54000"
+pts [
+"154000,54000"
+"154500,54000"
 ]
 )
@@ -943,7 +940,7 @@
 va (VaSet
 )
-xt "156000,53500,158700,54500"
+xt "157000,53500,159700,54500"
 st "wiz_wr"
-blo "156000,54300"
+blo "157000,54300"
 tm "WireNameMgr"
 )
@@ -963,5 +960,5 @@
 sl 0
 ro 270
-xt "153500,70625,155000,71375"
+xt "154500,70625,156000,71375"
 )
 (Line
@@ -969,8 +966,8 @@
 sl 0
 ro 270
-xt "153000,71000,153500,71000"
-pts [
-"153000,71000"
-"153500,71000"
+xt "154000,71000,154500,71000"
+pts [
+"154000,71000"
+"154500,71000"
 ]
 )
@@ -986,7 +983,7 @@
 va (VaSet
 )
-xt "156000,70500,160000,71500"
+xt "157000,70500,161000,71500"
 st "led : (7:0)"
-blo "156000,71300"
+blo "157000,71300"
 tm "WireNameMgr"
 )
@@ -1006,5 +1003,5 @@
 sl 0
 ro 270
-xt "153500,54625,155000,55375"
+xt "154500,54625,156000,55375"
 )
 (Line
@@ -1012,8 +1009,8 @@
 sl 0
 ro 270
-xt "153000,55000,153500,55000"
-pts [
-"153000,55000"
-"153500,55000"
+xt "154000,55000,154500,55000"
+pts [
+"154000,55000"
+"154500,55000"
 ]
 )
@@ -1030,7 +1027,7 @@
 va (VaSet
 )
-xt "156000,54500,158600,55500"
+xt "157000,54500,159600,55500"
 st "wiz_rd"
-blo "156000,55300"
+blo "157000,55300"
 tm "WireNameMgr"
 )
@@ -1050,5 +1047,5 @@
 sl 0
 ro 90
-xt "153500,55625,155000,56375"
+xt "154500,55625,156000,56375"
 )
 (Line
@@ -1056,8 +1053,8 @@
 sl 0
 ro 90
-xt "153000,56000,153500,56000"
-pts [
-"153500,56000"
-"153000,56000"
+xt "154000,56000,154500,56000"
+pts [
+"154500,56000"
+"154000,56000"
 ]
 )
@@ -1074,7 +1071,7 @@
 va (VaSet
 )
-xt "156000,55500,158700,56500"
+xt "157000,55500,159700,56500"
 st "wiz_int"
-blo "156000,56300"
+blo "157000,56300"
 tm "WireNameMgr"
 )
@@ -1113,4 +1110,5 @@
 n "clk"
 t "std_logic"
+prec "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');"
 preAdd 0
 posAdd 0
@@ -1308,5 +1306,5 @@
 preAdd 0
 posAdd 0
-o 23
+o 24
 suid 9,0
 )
@@ -1345,5 +1343,5 @@
 preAdd 0
 posAdd 0
-o 25
+o 26
 suid 10,0
 )
@@ -1381,5 +1379,5 @@
 preAdd 0
 posAdd 0
-o 26
+o 27
 suid 11,0
 )
@@ -1416,5 +1414,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 24
+o 25
 suid 12,0
 )
@@ -1487,4 +1485,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 7
 suid 17,0
@@ -1523,5 +1522,5 @@
 n "roi_max"
 t "roi_max_type"
-o 18
+o 19
 suid 18,0
 )
@@ -1558,5 +1557,5 @@
 n "roi_array"
 t "roi_array_type"
-o 17
+o 18
 suid 19,0
 )
@@ -1594,5 +1593,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 22
+o 23
 suid 20,0
 )
@@ -1680,5 +1679,5 @@
 fg "0,65535,0"
 )
-xt "18250,56625,19000,57375"
+xt "18250,63625,19000,64375"
 )
 tg (CPTG
@@ -1690,7 +1689,7 @@
 va (VaSet
 )
-xt "20000,56500,28500,57500"
+xt "20000,63500,28500,64500"
 st "drs_channel_id : (3:0)"
-blo "20000,57300"
+blo "20000,64300"
 )
 )
@@ -1844,5 +1843,5 @@
 n "drs_read_s_cell_ready"
 t "std_logic"
-o 38
+o 42
 suid 34,0
 )
@@ -1878,5 +1877,5 @@
 n "drs_s_cell_array"
 t "drs_s_cell_array_type"
-o 39
+o 43
 suid 35,0
 )
@@ -1947,5 +1946,5 @@
 n "config_ready_cm"
 t "std_logic"
-o 12
+o 13
 suid 39,0
 )
@@ -1983,5 +1982,8 @@
 n "config_start_cm"
 t "std_logic"
-o 9
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
 suid 40,0
 i "'0'"
@@ -1990,39 +1992,4 @@
 )
 *48 (CptPort
-uid 5271,0
-ps "OnEdgeStrategy"
-shape (Triangle
-uid 5272,0
-ro 270
-va (VaSet
-vasetType 1
-fg "0,65535,0"
-)
-xt "40000,52625,40750,53375"
-)
-tg (CPTG
-uid 5273,0
-ps "CptPortTextPlaceStrategy"
-stg "RightVerticalLayoutStrategy"
-f (Text
-uid 5274,0
-va (VaSet
-)
-xt "35400,52500,39000,53500"
-st "s_trigger"
-ju 2
-blo "39000,53300"
-)
-)
-thePort (LogicalPort
-decl (Decl
-n "s_trigger"
-t "std_logic"
-o 27
-suid 41,0
-)
-)
-)
-*49 (CptPort
 uid 5392,0
 ps "OnEdgeStrategy"
@@ -2054,10 +2021,10 @@
 n "config_ready_mm"
 t "std_logic"
-o 11
+o 12
 suid 42,0
 )
 )
 )
-*50 (CptPort
+*49 (CptPort
 uid 5396,0
 ps "OnEdgeStrategy"
@@ -2089,10 +2056,10 @@
 n "config_ready_spi"
 t "std_logic"
-o 13
+o 14
 suid 43,0
 )
 )
 )
-*51 (CptPort
+*50 (CptPort
 uid 5464,0
 ps "OnEdgeStrategy"
@@ -2124,10 +2091,10 @@
 n "sensor_array"
 t "sensor_array_type"
-o 19
+o 20
 suid 44,0
 )
 )
 )
-*52 (CptPort
+*51 (CptPort
 uid 5468,0
 ps "OnEdgeStrategy"
@@ -2159,10 +2126,10 @@
 n "sensor_ready"
 t "std_logic"
-o 20
+o 21
 suid 45,0
 )
 )
 )
-*53 (CptPort
+*52 (CptPort
 uid 5735,0
 ps "OnEdgeStrategy"
@@ -2195,5 +2162,8 @@
 n "config_start_mm"
 t "std_logic"
-o 8
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
 suid 46,0
 i "'0'"
@@ -2201,5 +2171,5 @@
 )
 )
-*54 (CptPort
+*53 (CptPort
 uid 5739,0
 ps "OnEdgeStrategy"
@@ -2232,5 +2202,7 @@
 n "config_start_spi"
 t "std_logic"
-o 10
+prec "-- --"
+preAdd 0
+o 11
 suid 47,0
 i "'0'"
@@ -2238,5 +2210,5 @@
 )
 )
-*55 (CptPort
+*54 (CptPort
 uid 5916,0
 ps "OnEdgeStrategy"
@@ -2275,5 +2247,5 @@
 )
 )
-*56 (CptPort
+*55 (CptPort
 uid 5920,0
 ps "OnEdgeStrategy"
@@ -2305,4 +2277,6 @@
 n "new_config"
 t "std_logic"
+prec "--      s_trigger      : in std_logic;"
+preAdd 0
 o 28
 suid 49,0
@@ -2310,5 +2284,5 @@
 )
 )
-*57 (CptPort
+*56 (CptPort
 uid 5974,0
 ps "OnEdgeStrategy"
@@ -2340,10 +2314,10 @@
 n "config_started_cm"
 t "std_logic"
-o 15
+o 16
 suid 50,0
 )
 )
 )
-*58 (CptPort
+*57 (CptPort
 uid 5978,0
 ps "OnEdgeStrategy"
@@ -2375,10 +2349,10 @@
 n "config_started_mm"
 t "std_logic"
-o 14
+o 15
 suid 51,0
 )
 )
 )
-*59 (CptPort
+*58 (CptPort
 uid 5982,0
 ps "OnEdgeStrategy"
@@ -2410,10 +2384,10 @@
 n "config_started_spi"
 t "std_logic"
-o 16
+o 17
 suid 52,0
 )
 )
 )
-*60 (CptPort
+*59 (CptPort
 uid 6060,0
 ps "OnEdgeStrategy"
@@ -2445,10 +2419,10 @@
 n "dac_array"
 t "dac_array_type"
-o 21
+o 22
 suid 53,0
 )
 )
 )
-*61 (CptPort
+*60 (CptPort
 uid 9000,0
 ps "OnEdgeStrategy"
@@ -2483,4 +2457,183 @@
 suid 54,0
 i "'0'"
+)
+)
+)
+*61 (CptPort
+uid 10244,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10245,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,56625,19000,57375"
+)
+tg (CPTG
+uid 10246,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10247,0
+va (VaSet
+)
+xt "20000,56500,28000,57500"
+st "drs_srin_data : (7:0)"
+blo "20000,57300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_data"
+t "std_logic_vector"
+b "(7 downto 0)"
+o 40
+suid 56,0
+i "(others => '0')"
+)
+)
+)
+*62 (CptPort
+uid 10248,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10249,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,53625,19000,54375"
+)
+tg (CPTG
+uid 10250,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10251,0
+va (VaSet
+)
+xt "20000,53500,26800,54500"
+st "drs_srin_write_8b"
+blo "20000,54300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_write_8b"
+t "std_logic"
+o 38
+suid 57,0
+i "'0'"
+)
+)
+)
+*63 (CptPort
+uid 10252,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10253,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,54625,19000,55375"
+)
+tg (CPTG
+uid 10254,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10255,0
+va (VaSet
+)
+xt "20000,54500,27100,55500"
+st "drs_srin_write_ack"
+blo "20000,55300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_srin_write_ack"
+t "std_logic"
+o 39
+suid 58,0
+)
+)
+)
+*64 (CptPort
+uid 10256,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10257,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,55625,19000,56375"
+)
+tg (CPTG
+uid 10258,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10259,0
+va (VaSet
+)
+xt "20000,55500,28200,56500"
+st "drs_srin_write_ready"
+blo "20000,56300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_srin_write_ready"
+t "std_logic"
+o 41
+suid 59,0
+)
+)
+)
+*65 (CptPort
+uid 10260,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10261,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "40000,65625,40750,66375"
+)
+tg (CPTG
+uid 10262,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10263,0
+va (VaSet
+)
+xt "31200,65500,39000,66500"
+st "ram_write_ready_ack"
+ju 2
+blo "39000,66300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 8
+suid 60,0
 )
 )
@@ -2503,5 +2656,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*62 (Text
+*66 (Text
 uid 1402,0
 va (VaSet
@@ -2513,5 +2666,5 @@
 tm "BdLibraryNameMgr"
 )
-*63 (Text
+*67 (Text
 uid 1403,0
 va (VaSet
@@ -2523,5 +2676,5 @@
 tm "CptNameMgr"
 )
-*64 (Text
+*68 (Text
 uid 1404,0
 va (VaSet
@@ -2576,5 +2729,5 @@
 archFileType "UNKNOWN"
 )
-*65 (Net
+*69 (Net
 uid 1409,0
 decl (Decl
@@ -2593,9 +2746,8 @@
 )
 xt "-103000,23800,-74500,24600"
-st "board_id               : std_logic_vector(3 downto 0)
-"
-)
-)
-*66 (Net
+st "board_id               : std_logic_vector(3 downto 0)"
+)
+)
+*70 (Net
 uid 1423,0
 decl (Decl
@@ -2613,9 +2765,8 @@
 )
 xt "-103000,25400,-84500,26200"
-st "trigger                : std_logic
-"
-)
-)
-*67 (PortIoIn
+st "trigger                : std_logic"
+)
+)
+*71 (PortIoIn
 uid 1443,0
 shape (CompositeShape
@@ -2630,5 +2781,5 @@
 sl 0
 ro 270
-xt "-28000,68625,-26500,69375"
+xt "-34000,69625,-32500,70375"
 )
 (Line
@@ -2636,8 +2787,8 @@
 sl 0
 ro 270
-xt "-26500,69000,-26000,69000"
-pts [
-"-26500,69000"
-"-26000,69000"
+xt "-32500,70000,-32000,70000"
+pts [
+"-32500,70000"
+"-32000,70000"
 ]
 )
@@ -2654,16 +2805,16 @@
 va (VaSet
 )
-xt "-31800,68500,-29000,69500"
+xt "-36800,69500,-34000,70500"
 st "trigger"
 ju 2
-blo "-29000,69300"
+blo "-34000,70300"
 tm "WireNameMgr"
 )
 )
 )
-*68 (SaComponent
+*72 (SaComponent
 uid 1606,0
 optionalChildren [
-*69 (CptPort
+*73 (CptPort
 uid 1542,0
 ps "OnEdgeStrategy"
@@ -2675,5 +2826,5 @@
 fg "0,65535,0"
 )
-xt "126250,51625,127000,52375"
+xt "127250,51625,128000,52375"
 )
 tg (CPTG
@@ -2685,7 +2836,7 @@
 va (VaSet
 )
-xt "128000,51500,129300,52500"
+xt "129000,51500,130300,52500"
 st "clk"
-blo "128000,52300"
+blo "129000,52300"
 )
 )
@@ -2701,5 +2852,5 @@
 )
 )
-*70 (CptPort
+*74 (CptPort
 uid 1546,0
 ps "OnEdgeStrategy"
@@ -2711,5 +2862,5 @@
 fg "0,65535,0"
 )
-xt "148000,51625,148750,52375"
+xt "149000,51625,149750,52375"
 )
 tg (CPTG
@@ -2721,8 +2872,8 @@
 va (VaSet
 )
-xt "143400,51500,147000,52500"
+xt "144400,51500,148000,52500"
 st "wiz_reset"
 ju 2
-blo "147000,52300"
+blo "148000,52300"
 )
 )
@@ -2740,5 +2891,5 @@
 )
 )
-*71 (CptPort
+*75 (CptPort
 uid 1550,0
 ps "OnEdgeStrategy"
@@ -2750,5 +2901,5 @@
 fg "0,65535,0"
 )
-xt "148000,59625,148750,60375"
+xt "149000,59625,149750,60375"
 )
 tg (CPTG
@@ -2760,8 +2911,8 @@
 va (VaSet
 )
-xt "142500,59500,147000,60500"
+xt "143500,59500,148000,60500"
 st "addr : (9:0)"
 ju 2
-blo "147000,60300"
+blo "148000,60300"
 )
 )
@@ -2779,5 +2930,5 @@
 )
 )
-*72 (CptPort
+*76 (CptPort
 uid 1554,0
 ps "OnEdgeStrategy"
@@ -2789,5 +2940,5 @@
 fg "0,65535,0"
 )
-xt "148000,60625,148750,61375"
+xt "149000,60625,149750,61375"
 )
 tg (CPTG
@@ -2799,8 +2950,8 @@
 va (VaSet
 )
-xt "142200,60500,147000,61500"
+xt "143200,60500,148000,61500"
 st "data : (15:0)"
 ju 2
-blo "147000,61300"
+blo "148000,61300"
 )
 )
@@ -2818,5 +2969,5 @@
 )
 )
-*73 (CptPort
+*77 (CptPort
 uid 1558,0
 ps "OnEdgeStrategy"
@@ -2828,5 +2979,5 @@
 fg "0,65535,0"
 )
-xt "148000,52625,148750,53375"
+xt "149000,52625,149750,53375"
 )
 tg (CPTG
@@ -2838,8 +2989,8 @@
 va (VaSet
 )
-xt "145800,52500,147000,53500"
+xt "146800,52500,148000,53500"
 st "cs"
 ju 2
-blo "147000,53300"
+blo "148000,53300"
 )
 )
@@ -2857,5 +3008,5 @@
 )
 )
-*74 (CptPort
+*78 (CptPort
 uid 1562,0
 ps "OnEdgeStrategy"
@@ -2867,5 +3018,5 @@
 fg "0,65535,0"
 )
-xt "148000,53625,148750,54375"
+xt "149000,53625,149750,54375"
 )
 tg (CPTG
@@ -2877,8 +3028,8 @@
 va (VaSet
 )
-xt "145800,53500,147000,54500"
+xt "146800,53500,148000,54500"
 st "wr"
 ju 2
-blo "147000,54300"
+blo "148000,54300"
 )
 )
@@ -2896,5 +3047,5 @@
 )
 )
-*75 (CptPort
+*79 (CptPort
 uid 1570,0
 ps "OnEdgeStrategy"
@@ -2906,5 +3057,5 @@
 fg "0,65535,0"
 )
-xt "148000,54625,148750,55375"
+xt "149000,54625,149750,55375"
 )
 tg (CPTG
@@ -2916,8 +3067,8 @@
 va (VaSet
 )
-xt "145900,54500,147000,55500"
+xt "146900,54500,148000,55500"
 st "rd"
 ju 2
-blo "147000,55300"
+blo "148000,55300"
 )
 )
@@ -2935,5 +3086,5 @@
 )
 )
-*76 (CptPort
+*80 (CptPort
 uid 1574,0
 ps "OnEdgeStrategy"
@@ -2945,5 +3096,5 @@
 fg "0,65535,0"
 )
-xt "148000,55625,148750,56375"
+xt "149000,55625,149750,56375"
 )
 tg (CPTG
@@ -2955,8 +3106,8 @@
 va (VaSet
 )
-xt "145800,55500,147000,56500"
+xt "146800,55500,148000,56500"
 st "int"
 ju 2
-blo "147000,56300"
+blo "148000,56300"
 )
 )
@@ -2972,5 +3123,5 @@
 )
 )
-*77 (CptPort
+*81 (CptPort
 uid 1578,0
 ps "OnEdgeStrategy"
@@ -2982,5 +3133,5 @@
 fg "0,65535,0"
 )
-xt "126250,69625,127000,70375"
+xt "127250,69625,128000,70375"
 )
 tg (CPTG
@@ -2992,7 +3143,7 @@
 va (VaSet
 )
-xt "128000,69500,135900,70500"
+xt "129000,69500,136900,70500"
 st "write_length : (16:0)"
-blo "128000,70300"
+blo "129000,70300"
 )
 )
@@ -3009,5 +3160,5 @@
 )
 )
-*78 (CptPort
+*82 (CptPort
 uid 1582,0
 ps "OnEdgeStrategy"
@@ -3019,5 +3170,5 @@
 fg "0,65535,0"
 )
-xt "126250,70625,127000,71375"
+xt "127250,70625,128000,71375"
 )
 tg (CPTG
@@ -3029,7 +3180,7 @@
 va (VaSet
 )
-xt "128000,70500,144300,71500"
+xt "129000,70500,145300,71500"
 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
-blo "128000,71300"
+blo "129000,71300"
 )
 )
@@ -3046,5 +3197,5 @@
 )
 )
-*79 (CptPort
+*83 (CptPort
 uid 1586,0
 ps "OnEdgeStrategy"
@@ -3056,5 +3207,5 @@
 fg "0,65535,0"
 )
-xt "126250,54625,127000,55375"
+xt "127250,54625,128000,55375"
 )
 tg (CPTG
@@ -3066,7 +3217,7 @@
 va (VaSet
 )
-xt "128000,54500,134500,55500"
+xt "129000,54500,135500,55500"
 st "ram_data : (15:0)"
-blo "128000,55300"
+blo "129000,55300"
 )
 )
@@ -3083,5 +3234,5 @@
 )
 )
-*80 (CptPort
+*84 (CptPort
 uid 1590,0
 ps "OnEdgeStrategy"
@@ -3093,5 +3244,5 @@
 fg "0,65535,0"
 )
-xt "126250,53625,127000,54375"
+xt "127250,53625,128000,54375"
 )
 tg (CPTG
@@ -3103,7 +3254,7 @@
 va (VaSet
 )
-xt "128000,53500,142400,54500"
+xt "129000,53500,143400,54500"
 st "ram_addr : (RAM_ADDR_WIDTH-1:0)"
-blo "128000,54300"
+blo "129000,54300"
 )
 )
@@ -3121,5 +3272,5 @@
 )
 )
-*81 (CptPort
+*85 (CptPort
 uid 1594,0
 ps "OnEdgeStrategy"
@@ -3131,5 +3282,5 @@
 fg "0,65535,0"
 )
-xt "126250,68625,127000,69375"
+xt "127250,68625,128000,69375"
 )
 tg (CPTG
@@ -3141,7 +3292,7 @@
 va (VaSet
 )
-xt "128000,68500,132100,69500"
+xt "129000,68500,133100,69500"
 st "data_valid"
-blo "128000,69300"
+blo "129000,69300"
 )
 )
@@ -3157,5 +3308,5 @@
 )
 )
-*82 (CptPort
+*86 (CptPort
 uid 1598,0
 ps "OnEdgeStrategy"
@@ -3167,5 +3318,5 @@
 fg "0,65535,0"
 )
-xt "126250,67625,127000,68375"
+xt "127250,67625,128000,68375"
 )
 tg (CPTG
@@ -3177,7 +3328,7 @@
 va (VaSet
 )
-xt "128000,67500,129900,68500"
+xt "129000,67500,130900,68500"
 st "busy"
-blo "128000,68300"
+blo "129000,68300"
 )
 )
@@ -3195,5 +3346,5 @@
 )
 )
-*83 (CptPort
+*87 (CptPort
 uid 2218,0
 ps "OnEdgeStrategy"
@@ -3205,5 +3356,5 @@
 fg "0,65535,0"
 )
-xt "126250,71625,127000,72375"
+xt "127250,71625,128000,72375"
 )
 tg (CPTG
@@ -3215,7 +3366,7 @@
 va (VaSet
 )
-xt "128000,71500,135800,72500"
+xt "129000,71500,136800,72500"
 st "fifo_channels : (3:0)"
-blo "128000,72300"
+blo "129000,72300"
 )
 )
@@ -3230,5 +3381,5 @@
 )
 )
-*84 (CptPort
+*88 (CptPort
 uid 2222,0
 ps "OnEdgeStrategy"
@@ -3240,5 +3391,5 @@
 fg "0,65535,0"
 )
-xt "126250,72625,127000,73375"
+xt "127250,72625,128000,73375"
 )
 tg (CPTG
@@ -3250,7 +3401,7 @@
 va (VaSet
 )
-xt "128000,72500,133700,73500"
+xt "129000,72500,134700,73500"
 st "write_end_flag"
-blo "128000,73300"
+blo "129000,73300"
 )
 )
@@ -3264,5 +3415,5 @@
 )
 )
-*85 (CptPort
+*89 (CptPort
 uid 2226,0
 ps "OnEdgeStrategy"
@@ -3274,5 +3425,5 @@
 fg "0,65535,0"
 )
-xt "126250,73625,127000,74375"
+xt "127250,73625,128000,74375"
 )
 tg (CPTG
@@ -3284,7 +3435,7 @@
 va (VaSet
 )
-xt "128000,73500,134800,74500"
+xt "129000,73500,135800,74500"
 st "write_header_flag"
-blo "128000,74300"
+blo "129000,74300"
 )
 )
@@ -3298,5 +3449,5 @@
 )
 )
-*86 (CptPort
+*90 (CptPort
 uid 5216,0
 ps "OnEdgeStrategy"
@@ -3308,5 +3459,5 @@
 fg "0,65535,0"
 )
-xt "148000,70625,148750,71375"
+xt "149000,70625,149750,71375"
 )
 tg (CPTG
@@ -3318,8 +3469,8 @@
 va (VaSet
 )
-xt "143000,70500,147000,71500"
+xt "144000,70500,148000,71500"
 st "led : (7:0)"
 ju 2
-blo "147000,71300"
+blo "148000,71300"
 )
 )
@@ -3337,5 +3488,5 @@
 )
 )
-*87 (CptPort
+*91 (CptPort
 uid 5275,0
 ps "OnEdgeStrategy"
@@ -3347,5 +3498,5 @@
 fg "0,65535,0"
 )
-xt "126250,58625,127000,59375"
+xt "127250,63625,128000,64375"
 )
 tg (CPTG
@@ -3357,7 +3508,7 @@
 va (VaSet
 )
-xt "128000,58500,131600,59500"
+xt "129000,63500,132600,64500"
 st "s_trigger"
-blo "128000,59300"
+blo "129000,64300"
 )
 )
@@ -3373,5 +3524,5 @@
 )
 )
-*88 (CptPort
+*92 (CptPort
 uid 5924,0
 ps "OnEdgeStrategy"
@@ -3383,5 +3534,5 @@
 fg "0,65535,0"
 )
-xt "126250,78625,127000,79375"
+xt "127250,78625,128000,79375"
 )
 tg (CPTG
@@ -3393,7 +3544,7 @@
 va (VaSet
 )
-xt "128000,78500,135000,79500"
+xt "129000,78500,136000,79500"
 st "config_addr : (7:0)"
-blo "128000,79300"
+blo "129000,79300"
 )
 )
@@ -3409,5 +3560,5 @@
 )
 )
-*89 (CptPort
+*93 (CptPort
 uid 5928,0
 ps "OnEdgeStrategy"
@@ -3419,5 +3570,5 @@
 fg "0,65535,0"
 )
-xt "126250,83625,127000,84375"
+xt "127250,83625,128000,84375"
 )
 tg (CPTG
@@ -3429,7 +3580,7 @@
 va (VaSet
 )
-xt "128000,83500,132800,84500"
+xt "129000,83500,133800,84500"
 st "config_busy"
-blo "128000,84300"
+blo "129000,84300"
 )
 )
@@ -3438,10 +3589,12 @@
 n "config_busy"
 t "std_logic"
-o 27
+prec "-- --"
+preAdd 0
+o 29
 suid 25,0
 )
 )
 )
-*90 (CptPort
+*94 (CptPort
 uid 5932,0
 ps "OnEdgeStrategy"
@@ -3453,5 +3606,5 @@
 fg "0,65535,0"
 )
-xt "126250,79625,127000,80375"
+xt "127250,79625,128000,80375"
 )
 tg (CPTG
@@ -3463,7 +3616,7 @@
 va (VaSet
 )
-xt "128000,79500,135700,80500"
+xt "129000,79500,136700,80500"
 st "config_data : (15:0)"
-blo "128000,80300"
+blo "129000,80300"
 )
 )
@@ -3480,5 +3633,5 @@
 )
 )
-*91 (CptPort
+*95 (CptPort
 uid 5936,0
 ps "OnEdgeStrategy"
@@ -3490,5 +3643,5 @@
 fg "0,65535,0"
 )
-xt "126250,60625,127000,61375"
+xt "127250,60625,128000,61375"
 )
 tg (CPTG
@@ -3500,7 +3653,7 @@
 va (VaSet
 )
-xt "128000,60500,133600,61500"
+xt "129000,60500,134600,61500"
 st "config_started"
-blo "128000,61300"
+blo "129000,61300"
 )
 )
@@ -3514,5 +3667,5 @@
 )
 )
-*92 (CptPort
+*96 (CptPort
 uid 5940,0
 ps "OnEdgeStrategy"
@@ -3524,5 +3677,5 @@
 fg "0,65535,0"
 )
-xt "126250,81625,127000,82375"
+xt "127250,81625,128000,82375"
 )
 tg (CPTG
@@ -3534,7 +3687,7 @@
 va (VaSet
 )
-xt "128000,81500,133300,82500"
+xt "129000,81500,134300,82500"
 st "config_wr_en"
-blo "128000,82300"
+blo "129000,82300"
 )
 )
@@ -3550,5 +3703,5 @@
 )
 )
-*93 (CptPort
+*97 (CptPort
 uid 5944,0
 ps "OnEdgeStrategy"
@@ -3560,5 +3713,5 @@
 fg "0,65535,0"
 )
-xt "126250,59625,127000,60375"
+xt "127250,59625,128000,60375"
 )
 tg (CPTG
@@ -3570,7 +3723,7 @@
 va (VaSet
 )
-xt "128000,59500,132600,60500"
+xt "129000,59500,133600,60500"
 st "new_config"
-blo "128000,60300"
+blo "129000,60300"
 )
 )
@@ -3586,5 +3739,5 @@
 )
 )
-*94 (CptPort
+*98 (CptPort
 uid 5970,0
 ps "OnEdgeStrategy"
@@ -3596,5 +3749,5 @@
 fg "0,65535,0"
 )
-xt "126250,82625,127000,83375"
+xt "127250,82625,128000,83375"
 )
 tg (CPTG
@@ -3606,7 +3759,7 @@
 va (VaSet
 )
-xt "128000,82500,133200,83500"
+xt "129000,82500,134200,83500"
 st "config_rd_en"
-blo "128000,83300"
+blo "129000,83300"
 )
 )
@@ -3616,4 +3769,5 @@
 n "config_rd_en"
 t "std_logic"
+posAdd 0
 o 26
 suid 30,0
@@ -3622,5 +3776,5 @@
 )
 )
-*95 (CptPort
+*99 (CptPort
 uid 6356,0
 ps "OnEdgeStrategy"
@@ -3632,5 +3786,5 @@
 fg "0,65535,0"
 )
-xt "148000,74625,148750,75375"
+xt "149000,74625,149750,75375"
 )
 tg (CPTG
@@ -3642,8 +3796,8 @@
 va (VaSet
 )
-xt "144000,74500,147000,75500"
+xt "145000,74500,148000,75500"
 st "denable"
 ju 2
-blo "147000,75300"
+blo "148000,75300"
 )
 )
@@ -3655,5 +3809,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 28
+o 30
 suid 31,0
 i "'0'"
@@ -3661,5 +3815,5 @@
 )
 )
-*96 (CptPort
+*100 (CptPort
 uid 6446,0
 ps "OnEdgeStrategy"
@@ -3671,5 +3825,5 @@
 fg "0,65535,0"
 )
-xt "148000,75625,148750,76375"
+xt "149000,75625,149750,76375"
 )
 tg (CPTG
@@ -3681,8 +3835,8 @@
 va (VaSet
 )
-xt "141600,75500,147000,76500"
+xt "142600,75500,148000,76500"
 st "dwrite_enable"
 ju 2
-blo "147000,76300"
+blo "148000,76300"
 )
 )
@@ -3695,5 +3849,5 @@
 preAdd 0
 posAdd 0
-o 29
+o 31
 suid 32,0
 i "'0'"
@@ -3701,5 +3855,5 @@
 )
 )
-*97 (CptPort
+*101 (CptPort
 uid 8406,0
 ps "OnEdgeStrategy"
@@ -3711,5 +3865,5 @@
 fg "0,65535,0"
 )
-xt "126250,74625,127000,75375"
+xt "127250,74625,128000,75375"
 )
 tg (CPTG
@@ -3721,7 +3875,7 @@
 va (VaSet
 )
-xt "128000,74500,133600,75500"
+xt "129000,74500,134600,75500"
 st "data_valid_ack"
-blo "128000,75300"
+blo "129000,75300"
 )
 )
@@ -3737,5 +3891,5 @@
 )
 )
-*98 (CptPort
+*102 (CptPort
 uid 8748,0
 ps "OnEdgeStrategy"
@@ -3747,5 +3901,5 @@
 fg "0,65535,0"
 )
-xt "148000,76625,148750,77375"
+xt "149000,76625,149750,77375"
 )
 tg (CPTG
@@ -3757,8 +3911,8 @@
 va (VaSet
 )
-xt "142300,76500,147000,77500"
+xt "143300,76500,148000,77500"
 st "sclk_enable"
 ju 2
-blo "147000,77300"
+blo "148000,77300"
 )
 )
@@ -3770,5 +3924,5 @@
 eolc "-- default DWRITE HIGH."
 posAdd 0
-o 30
+o 32
 suid 35,0
 i "'1'"
@@ -3776,5 +3930,5 @@
 )
 )
-*99 (CptPort
+*103 (CptPort
 uid 9223,0
 ps "OnEdgeStrategy"
@@ -3786,5 +3940,5 @@
 fg "0,65535,0"
 )
-xt "148000,80625,148750,81375"
+xt "149000,80625,149750,81375"
 )
 tg (CPTG
@@ -3796,8 +3950,8 @@
 va (VaSet
 )
-xt "142100,80500,147000,81500"
+xt "143100,80500,148000,81500"
 st "ps_direction"
 ju 2
-blo "147000,81300"
+blo "148000,81300"
 )
 )
@@ -3809,5 +3963,5 @@
 eolc "-- default phase shift upwards"
 posAdd 0
-o 31
+o 33
 suid 36,0
 i "'1'"
@@ -3815,5 +3969,5 @@
 )
 )
-*100 (CptPort
+*104 (CptPort
 uid 9227,0
 ps "OnEdgeStrategy"
@@ -3825,5 +3979,5 @@
 fg "0,65535,0"
 )
-xt "148000,81625,148750,82375"
+xt "149000,81625,149750,82375"
 )
 tg (CPTG
@@ -3835,8 +3989,8 @@
 va (VaSet
 )
-xt "140000,81500,147000,82500"
+xt "141000,81500,148000,82500"
 st "ps_do_phase_shift"
 ju 2
-blo "147000,82300"
+blo "148000,82300"
 )
 )
@@ -3849,5 +4003,5 @@
 preAdd 0
 posAdd 0
-o 32
+o 34
 suid 37,0
 i "'0'"
@@ -3855,5 +4009,5 @@
 )
 )
-*101 (CptPort
+*105 (CptPort
 uid 9933,0
 ps "OnEdgeStrategy"
@@ -3865,5 +4019,5 @@
 fg "0,65535,0"
 )
-xt "148000,82625,148750,83375"
+xt "149000,82625,149750,83375"
 )
 tg (CPTG
@@ -3875,8 +4029,8 @@
 va (VaSet
 )
-xt "143700,82500,147000,83500"
+xt "144700,82500,148000,83500"
 st "ps_reset"
 ju 2
-blo "147000,83300"
+blo "148000,83300"
 )
 )
@@ -3888,5 +4042,5 @@
 eolc "-- pulse this to reset the variable phase shift"
 posAdd 0
-o 33
+o 35
 suid 38,0
 i "'0'"
@@ -3894,5 +4048,5 @@
 )
 )
-*102 (CptPort
+*106 (CptPort
 uid 9937,0
 ps "OnEdgeStrategy"
@@ -3904,5 +4058,5 @@
 fg "0,65535,0"
 )
-xt "148000,84625,148750,85375"
+xt "149000,84625,149750,85375"
 )
 tg (CPTG
@@ -3914,8 +4068,8 @@
 va (VaSet
 )
-xt "142000,84500,147000,85500"
+xt "143000,84500,148000,85500"
 st "srclk_enable"
 ju 2
-blo "147000,85300"
+blo "148000,85300"
 )
 )
@@ -3927,7 +4081,81 @@
 eolc "-- default SRCLK on."
 posAdd 0
-o 34
+o 36
 suid 39,0
 i "'1'"
+)
+)
+)
+*107 (CptPort
+uid 10212,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10213,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "127250,84625,128000,85375"
+)
+tg (CPTG
+uid 10214,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10215,0
+va (VaSet
+)
+xt "129000,84500,134600,85500"
+st "config_rw_ack"
+blo "129000,85300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 27
+suid 40,0
+)
+)
+)
+*108 (CptPort
+uid 10216,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10217,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "127250,85625,128000,86375"
+)
+tg (CPTG
+uid 10218,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10219,0
+va (VaSet
+)
+xt "129000,85500,135300,86500"
+st "config_rw_ready"
+blo "129000,86300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 28
+suid 41,0
 )
 )
@@ -3942,5 +4170,5 @@
 lineWidth 2
 )
-xt "127000,51000,148000,89000"
+xt "128000,51000,149000,89000"
 )
 oxt "43000,2000,56000,22000"
@@ -3950,32 +4178,32 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*103 (Text
+*109 (Text
 uid 1609,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "126700,87000,132900,88000"
+xt "127700,87000,133900,88000"
 st "FACT_FAD_lib"
-blo "126700,87800"
+blo "127700,87800"
 tm "BdLibraryNameMgr"
 )
-*104 (Text
+*110 (Text
 uid 1610,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "126700,88000,132400,89000"
+xt "127700,88000,133400,89000"
 st "w5300_modul"
-blo "126700,88800"
+blo "127700,88800"
 tm "CptNameMgr"
 )
-*105 (Text
+*111 (Text
 uid 1611,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "126700,89000,133400,90000"
+xt "127700,89000,134400,90000"
 st "I_main_ethernet"
-blo "126700,89800"
+blo "127700,89800"
 tm "InstanceNameMgr"
 )
@@ -3992,5 +4220,5 @@
 font "Courier New,8,0"
 )
-xt "127000,50200,154500,51000"
+xt "128000,50200,155500,51000"
 st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2    ( integer )  "
 )
@@ -4012,5 +4240,5 @@
 fg "49152,49152,49152"
 )
-xt "127250,87250,128750,88750"
+xt "128250,87250,129750,88750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -4023,5 +4251,5 @@
 archFileType "UNKNOWN"
 )
-*106 (Net
+*112 (Net
 uid 1680,0
 decl (Decl
@@ -4038,12 +4266,11 @@
 )
 xt "-103000,24600,-74500,25400"
-st "crate_id               : std_logic_vector(1 downto 0)
-"
-)
-)
-*107 (SaComponent
+st "crate_id               : std_logic_vector(1 downto 0)"
+)
+)
+*113 (SaComponent
 uid 1768,0
 optionalChildren [
-*108 (CptPort
+*114 (CptPort
 uid 1760,0
 ps "OnEdgeStrategy"
@@ -4085,5 +4312,5 @@
 )
 )
-*109 (CptPort
+*115 (CptPort
 uid 1764,0
 ps "OnEdgeStrategy"
@@ -4122,5 +4349,5 @@
 )
 )
-*110 (CptPort
+*116 (CptPort
 uid 6207,0
 ps "OnEdgeStrategy"
@@ -4174,5 +4401,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*111 (Text
+*117 (Text
 uid 1771,0
 va (VaSet
@@ -4184,5 +4411,5 @@
 tm "BdLibraryNameMgr"
 )
-*112 (Text
+*118 (Text
 uid 1772,0
 va (VaSet
@@ -4194,5 +4421,5 @@
 tm "CptNameMgr"
 )
-*113 (Text
+*119 (Text
 uid 1773,0
 va (VaSet
@@ -4242,5 +4469,5 @@
 archFileType "UNKNOWN"
 )
-*114 (Net
+*120 (Net
 uid 1981,0
 lang 2
@@ -4259,10 +4486,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,97800,-70500,98600"
-st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
-"
-)
-)
-*115 (Net
+xt "-103000,106600,-70500,107400"
+st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
+)
+)
+*121 (Net
 uid 2297,0
 decl (Decl
@@ -4280,13 +4506,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,89000,-63000,89800"
-st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
-"
-)
-)
-*116 (SaComponent
+xt "-103000,93800,-63000,94600"
+st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+)
+)
+*122 (SaComponent
 uid 2311,0
 optionalChildren [
-*117 (CptPort
+*123 (CptPort
 uid 2307,0
 ps "OnEdgeStrategy"
@@ -4323,5 +4548,5 @@
 preAdd 0
 posAdd 0
-o 18
+o 19
 suid 1,0
 i "(others => '0')"
@@ -4329,5 +4554,5 @@
 )
 )
-*118 (CptPort
+*124 (CptPort
 uid 2351,0
 ps "OnEdgeStrategy"
@@ -4365,5 +4590,5 @@
 )
 )
-*119 (CptPort
+*125 (CptPort
 uid 2361,0
 ps "OnEdgeStrategy"
@@ -4397,5 +4622,5 @@
 n "config_ready"
 t "std_logic"
-o 6
+o 7
 suid 5,0
 i "'0'"
@@ -4403,5 +4628,5 @@
 )
 )
-*120 (CptPort
+*126 (CptPort
 uid 2365,0
 ps "OnEdgeStrategy"
@@ -4439,5 +4664,5 @@
 )
 )
-*121 (CptPort
+*127 (CptPort
 uid 2369,0
 ps "OnEdgeStrategy"
@@ -4471,5 +4696,5 @@
 n "ram_write_ea"
 t "std_logic"
-o 5
+o 6
 suid 4,0
 i "'0'"
@@ -4477,5 +4702,5 @@
 )
 )
-*122 (CptPort
+*128 (CptPort
 uid 2373,0
 ps "OnEdgeStrategy"
@@ -4508,4 +4733,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 3
 suid 12,0
@@ -4513,5 +4739,5 @@
 )
 )
-*123 (CptPort
+*129 (CptPort
 uid 2377,0
 ps "OnEdgeStrategy"
@@ -4546,5 +4772,5 @@
 t "roi_max_type"
 posAdd 0
-o 8
+o 9
 suid 14,0
 i "(others => conv_std_logic_vector (0, 11))"
@@ -4552,5 +4778,5 @@
 )
 )
-*124 (CptPort
+*130 (CptPort
 uid 2381,0
 ps "OnEdgeStrategy"
@@ -4584,10 +4810,10 @@
 n "wiz_busy"
 t "std_logic"
-o 16
+o 17
 suid 13,0
 )
 )
 )
-*125 (CptPort
+*131 (CptPort
 uid 2385,0
 ps "OnEdgeStrategy"
@@ -4623,5 +4849,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 12
+o 13
 suid 6,0
 i "(others => '0')"
@@ -4629,5 +4855,5 @@
 )
 )
-*126 (CptPort
+*132 (CptPort
 uid 2389,0
 ps "OnEdgeStrategy"
@@ -4664,5 +4890,5 @@
 b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
 preAdd 0
-o 10
+o 11
 suid 7,0
 i "(others => '0')"
@@ -4670,5 +4896,5 @@
 )
 )
-*127 (CptPort
+*133 (CptPort
 uid 2393,0
 ps "OnEdgeStrategy"
@@ -4703,5 +4929,5 @@
 n "wiz_write_ea"
 t "std_logic"
-o 13
+o 14
 suid 8,0
 i "'0'"
@@ -4709,5 +4935,5 @@
 )
 )
-*128 (CptPort
+*134 (CptPort
 uid 2397,0
 ps "OnEdgeStrategy"
@@ -4742,5 +4968,5 @@
 n "wiz_write_end"
 t "std_logic"
-o 15
+o 16
 suid 9,0
 i "'0'"
@@ -4748,5 +4974,5 @@
 )
 )
-*129 (CptPort
+*135 (CptPort
 uid 2401,0
 ps "OnEdgeStrategy"
@@ -4781,5 +5007,5 @@
 n "wiz_write_header"
 t "std_logic"
-o 14
+o 15
 suid 10,0
 i "'0'"
@@ -4787,5 +5013,5 @@
 )
 )
-*130 (CptPort
+*136 (CptPort
 uid 2405,0
 ps "OnEdgeStrategy"
@@ -4821,5 +5047,5 @@
 t "std_logic_vector"
 b "(16 downto 0)"
-o 11
+o 12
 suid 11,0
 i "(others => '0')"
@@ -4827,5 +5053,5 @@
 )
 )
-*131 (CptPort
+*137 (CptPort
 uid 2454,0
 ps "OnEdgeStrategy"
@@ -4858,10 +5084,12 @@
 n "roi_array"
 t "roi_array_type"
-o 4
+prec "-- --"
+preAdd 0
+o 5
 suid 15,0
 )
 )
 )
-*132 (CptPort
+*138 (CptPort
 uid 2628,0
 ps "OnEdgeStrategy"
@@ -4896,5 +5124,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 9
+o 10
 suid 18,0
 i "(others => '0')"
@@ -4902,5 +5130,5 @@
 )
 )
-*133 (CptPort
+*139 (CptPort
 uid 5991,0
 ps "OnEdgeStrategy"
@@ -4934,5 +5162,5 @@
 n "config_started"
 t "std_logic"
-o 7
+o 8
 suid 21,0
 i "'0'"
@@ -4940,5 +5168,5 @@
 )
 )
-*134 (CptPort
+*140 (CptPort
 uid 8410,0
 ps "OnEdgeStrategy"
@@ -4972,6 +5200,47 @@
 n "wiz_ack"
 t "std_logic"
-o 17
+o 18
 suid 22,0
+)
+)
+)
+*141 (CptPort
+uid 10232,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10233,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "71250,72625,72000,73375"
+)
+tg (CPTG
+uid 10234,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10235,0
+va (VaSet
+font "arial,8,0"
+)
+xt "73000,72500,80800,73500"
+st "ram_write_ready_ack"
+blo "73000,73300"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 4
+suid 23,0
+i "'0'"
 )
 )
@@ -4994,5 +5263,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*135 (Text
+*142 (Text
 uid 2314,0
 va (VaSet
@@ -5004,5 +5273,5 @@
 tm "BdLibraryNameMgr"
 )
-*136 (Text
+*143 (Text
 uid 2315,0
 va (VaSet
@@ -5014,5 +5283,5 @@
 tm "CptNameMgr"
 )
-*137 (Text
+*144 (Text
 uid 2316,0
 va (VaSet
@@ -5073,5 +5342,5 @@
 archFileType "UNKNOWN"
 )
-*138 (Net
+*145 (Net
 uid 2468,0
 lang 2
@@ -5087,10 +5356,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,99400,-80500,100200"
-st "SIGNAL wiz_busy               : std_logic
-"
-)
-)
-*139 (Net
+xt "-103000,109000,-80500,109800"
+st "SIGNAL wiz_busy               : std_logic"
+)
+)
+*146 (Net
 uid 2474,0
 lang 2
@@ -5107,10 +5375,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,101800,-59500,102600"
-st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
-"
-)
-)
-*140 (Net
+xt "-103000,111400,-59500,112200"
+st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
+)
+)
+*147 (Net
 uid 2480,0
 lang 2
@@ -5128,10 +5395,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,104200,-53500,105000"
-st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
-"
-)
-)
-*141 (Net
+xt "-103000,113800,-53500,114600"
+st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
+)
+)
+*148 (Net
 uid 2486,0
 lang 2
@@ -5150,10 +5416,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,101000,-53500,101800"
-st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
-"
-)
-)
-*142 (Net
+xt "-103000,110600,-53500,111400"
+st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
+)
+)
+*149 (Net
 uid 2492,0
 lang 2
@@ -5171,10 +5436,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,100200,-53500,101000"
-st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
-"
-)
-)
-*143 (Net
+xt "-103000,109800,-53500,110600"
+st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
+)
+)
+*150 (Net
 uid 2498,0
 lang 2
@@ -5191,10 +5455,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,102600,-59500,103400"
-st "SIGNAL wiz_write_end          : std_logic                                    := '0'
-"
-)
-)
-*144 (Net
+xt "-103000,112200,-59500,113000"
+st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
+)
+)
+*151 (Net
 uid 2504,0
 lang 2
@@ -5211,10 +5474,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,103400,-59500,104200"
-st "SIGNAL wiz_write_header       : std_logic                                    := '0'
-"
-)
-)
-*145 (Net
+xt "-103000,113000,-59500,113800"
+st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
+)
+)
+*152 (Net
 uid 2574,0
 decl (Decl
@@ -5229,10 +5491,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,89800,-80500,90600"
-st "SIGNAL ram_write_ea           : std_logic
-"
-)
-)
-*146 (Net
+xt "-103000,94600,-80500,95400"
+st "SIGNAL ram_write_ea           : std_logic"
+)
+)
+*153 (Net
 uid 2580,0
 decl (Decl
@@ -5248,10 +5509,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,90600,-59500,91400"
-st "SIGNAL ram_write_ready        : std_logic                                    := '0'
-"
-)
-)
-*147 (Net
+xt "-103000,95400,-59500,96200"
+st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
+)
+)
+*154 (Net
 uid 2586,0
 decl (Decl
@@ -5267,10 +5527,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,68200,-59500,69000"
-st "SIGNAL config_start           : std_logic                                    := '0'
-"
-)
-)
-*148 (Net
+xt "-103000,72200,-59500,73000"
+st "SIGNAL config_start           : std_logic                                    := '0'"
+)
+)
+*155 (Net
 uid 2592,0
 decl (Decl
@@ -5285,10 +5544,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,65800,-80500,66600"
-st "SIGNAL config_ready           : std_logic
-"
-)
-)
-*149 (Net
+xt "-103000,66600,-80500,67400"
+st "SIGNAL config_ready           : std_logic"
+)
+)
+*156 (Net
 uid 2598,0
 decl (Decl
@@ -5303,10 +5561,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,92200,-79000,93000"
-st "SIGNAL roi_max                : roi_max_type
-"
-)
-)
-*150 (Net
+xt "-103000,98600,-79000,99400"
+st "SIGNAL roi_max                : roi_max_type"
+)
+)
+*157 (Net
 uid 2640,0
 decl (Decl
@@ -5322,10 +5579,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,84200,-70500,85000"
-st "SIGNAL package_length         : std_logic_vector(15 downto 0)
-"
-)
-)
-*151 (Net
+xt "-103000,89000,-70500,89800"
+st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
+)
+)
+*158 (Net
 uid 2776,0
 decl (Decl
@@ -5341,10 +5597,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,39800,-63000,40600"
-st "adc_oeb                : std_logic                                    := '1'
-"
-)
-)
-*152 (PortIoOut
+xt "-103000,40600,-63000,41400"
+st "adc_oeb                : std_logic                                    := '1'"
+)
+)
+*159 (PortIoOut
 uid 2798,0
 shape (CompositeShape
@@ -5391,5 +5646,5 @@
 )
 )
-*153 (PortIoIn
+*160 (PortIoIn
 uid 2804,0
 shape (CompositeShape
@@ -5436,5 +5691,5 @@
 )
 )
-*154 (Net
+*161 (Net
 uid 2924,0
 decl (Decl
@@ -5449,10 +5704,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,91400,-78000,92200"
-st "SIGNAL roi_array              : roi_array_type
-"
-)
-)
-*155 (PortIoIn
+xt "-103000,97800,-78000,98600"
+st "SIGNAL roi_array              : roi_array_type"
+)
+)
+*162 (PortIoIn
 uid 2950,0
 shape (CompositeShape
@@ -5499,5 +5753,5 @@
 )
 )
-*156 (PortIoIn
+*163 (PortIoIn
 uid 2956,0
 shape (CompositeShape
@@ -5544,8 +5798,8 @@
 )
 )
-*157 (Grouping
+*164 (Grouping
 uid 3137,0
 optionalChildren [
-*158 (CommentText
+*165 (CommentText
 uid 3139,0
 shape (Rectangle
@@ -5565,5 +5819,5 @@
 bg "0,0,32768"
 )
-xt "125200,175000,134900,176000"
+xt "125200,175000,134700,176000"
 st "
 by %user on %dd %month %year
@@ -5578,5 +5832,5 @@
 titleBlock 1
 )
-*159 (CommentText
+*166 (CommentText
 uid 3142,0
 shape (Rectangle
@@ -5609,5 +5863,5 @@
 titleBlock 1
 )
-*160 (CommentText
+*167 (CommentText
 uid 3145,0
 shape (Rectangle
@@ -5640,5 +5894,5 @@
 titleBlock 1
 )
-*161 (CommentText
+*168 (CommentText
 uid 3148,0
 shape (Rectangle
@@ -5671,5 +5925,5 @@
 titleBlock 1
 )
-*162 (CommentText
+*169 (CommentText
 uid 3151,0
 shape (Rectangle
@@ -5701,5 +5955,5 @@
 titleBlock 1
 )
-*163 (CommentText
+*170 (CommentText
 uid 3154,0
 shape (Rectangle
@@ -5732,5 +5986,5 @@
 titleBlock 1
 )
-*164 (CommentText
+*171 (CommentText
 uid 3157,0
 shape (Rectangle
@@ -5764,5 +6018,5 @@
 titleBlock 1
 )
-*165 (CommentText
+*172 (CommentText
 uid 3160,0
 shape (Rectangle
@@ -5795,5 +6049,5 @@
 titleBlock 1
 )
-*166 (CommentText
+*173 (CommentText
 uid 3163,0
 shape (Rectangle
@@ -5826,5 +6080,5 @@
 titleBlock 1
 )
-*167 (CommentText
+*174 (CommentText
 uid 3166,0
 shape (Rectangle
@@ -5870,5 +6124,5 @@
 oxt "14000,66000,55000,71000"
 )
-*168 (Net
+*175 (Net
 uid 3894,0
 decl (Decl
@@ -5884,9 +6138,8 @@
 )
 xt "-103000,29400,-84500,30200"
-st "CLK_25_PS              : std_logic
-"
-)
-)
-*169 (PortIoOut
+st "CLK_25_PS              : std_logic"
+)
+)
+*176 (PortIoOut
 uid 3978,0
 shape (CompositeShape
@@ -5933,5 +6186,5 @@
 )
 )
-*170 (Net
+*177 (Net
 uid 4068,0
 decl (Decl
@@ -5947,9 +6200,8 @@
 )
 xt "-103000,30200,-84500,31000"
-st "CLK_50                 : std_logic
-"
-)
-)
-*171 (Net
+st "CLK_50                 : std_logic"
+)
+)
+*178 (Net
 uid 4204,0
 decl (Decl
@@ -5964,10 +6216,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,57800,-80500,58600"
-st "SIGNAL CLK_25                 : std_logic
-"
-)
-)
-*172 (PortIoOut
+xt "-103000,58600,-80500,59400"
+st "SIGNAL CLK_25                 : std_logic"
+)
+)
+*179 (PortIoOut
 uid 4220,0
 shape (CompositeShape
@@ -6014,5 +6265,5 @@
 )
 )
-*173 (Net
+*180 (Net
 uid 4232,0
 decl (Decl
@@ -6028,9 +6279,8 @@
 )
 xt "-103000,18200,-84500,19000"
-st "CLK                    : std_logic
-"
-)
-)
-*174 (Net
+st "CLK                    : std_logic"
+)
+)
+*181 (Net
 uid 4260,0
 decl (Decl
@@ -6047,9 +6297,8 @@
 )
 xt "-103000,23000,-74500,23800"
-st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*175 (Net
+st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*182 (Net
 uid 4270,0
 decl (Decl
@@ -6065,9 +6314,8 @@
 )
 xt "-103000,22200,-79000,23000"
-st "adc_data_array         : adc_data_array_type
-"
-)
-)
-*176 (PortIoIn
+st "adc_data_array         : adc_data_array_type"
+)
+)
+*183 (PortIoIn
 uid 4307,0
 shape (CompositeShape
@@ -6114,5 +6362,5 @@
 )
 )
-*177 (Net
+*184 (Net
 uid 4399,0
 decl (Decl
@@ -6128,10 +6376,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,78600,-59500,79400"
-st "SIGNAL drs_clk_en             : std_logic                                    := '0'
-"
-)
-)
-*178 (Net
+xt "-103000,82600,-59500,83400"
+st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
+)
+)
+*185 (Net
 uid 4405,0
 decl (Decl
@@ -6146,10 +6393,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,81000,-74500,81800"
-st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
-"
-)
-)
-*179 (Net
+xt "-103000,85000,-74500,85800"
+st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
+)
+)
+*186 (Net
 uid 4417,0
 decl (Decl
@@ -6165,10 +6411,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,79400,-59500,80200"
-st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
-"
-)
-)
-*180 (Net
+xt "-103000,83400,-59500,84200"
+st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
+)
+)
+*187 (Net
 uid 4535,0
 decl (Decl
@@ -6185,10 +6430,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,42200,-57000,43000"
-st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
-"
-)
-)
-*181 (Net
+xt "-103000,43000,-57000,43800"
+st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
+)
+)
+*188 (Net
 uid 4543,0
 decl (Decl
@@ -6204,10 +6448,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,43000,-63000,43800"
-st "drs_dwrite             : std_logic                                    := '1'
-"
-)
-)
-*182 (PortIoOut
+xt "-103000,43800,-63000,44600"
+st "drs_dwrite             : std_logic                                    := '1'"
+)
+)
+*189 (PortIoOut
 uid 4551,0
 shape (CompositeShape
@@ -6254,5 +6497,5 @@
 )
 )
-*183 (PortIoOut
+*190 (PortIoOut
 uid 4557,0
 shape (CompositeShape
@@ -6299,5 +6542,5 @@
 )
 )
-*184 (Net
+*191 (Net
 uid 4669,0
 decl (Decl
@@ -6313,9 +6556,8 @@
 )
 xt "-103000,19000,-84500,19800"
-st "SROUT_in_0             : std_logic
-"
-)
-)
-*185 (Net
+st "SROUT_in_0             : std_logic"
+)
+)
+*192 (Net
 uid 4677,0
 decl (Decl
@@ -6331,9 +6573,8 @@
 )
 xt "-103000,19800,-84500,20600"
-st "SROUT_in_1             : std_logic
-"
-)
-)
-*186 (Net
+st "SROUT_in_1             : std_logic"
+)
+)
+*193 (Net
 uid 4685,0
 decl (Decl
@@ -6349,9 +6590,8 @@
 )
 xt "-103000,20600,-84500,21400"
-st "SROUT_in_2             : std_logic
-"
-)
-)
-*187 (Net
+st "SROUT_in_2             : std_logic"
+)
+)
+*194 (Net
 uid 4693,0
 decl (Decl
@@ -6367,9 +6607,8 @@
 )
 xt "-103000,21400,-84500,22200"
-st "SROUT_in_3             : std_logic
-"
-)
-)
-*188 (PortIoIn
+st "SROUT_in_3             : std_logic"
+)
+)
+*195 (PortIoIn
 uid 4701,0
 shape (CompositeShape
@@ -6416,5 +6655,5 @@
 )
 )
-*189 (PortIoIn
+*196 (PortIoIn
 uid 4707,0
 shape (CompositeShape
@@ -6461,5 +6700,5 @@
 )
 )
-*190 (PortIoIn
+*197 (PortIoIn
 uid 4713,0
 shape (CompositeShape
@@ -6506,5 +6745,5 @@
 )
 )
-*191 (PortIoIn
+*198 (PortIoIn
 uid 4719,0
 shape (CompositeShape
@@ -6551,5 +6790,5 @@
 )
 )
-*192 (Net
+*199 (Net
 uid 4741,0
 decl (Decl
@@ -6564,13 +6803,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,80200,-80500,81000"
-st "SIGNAL drs_read_s_cell_ready  : std_logic
-"
-)
-)
-*193 (SaComponent
+xt "-103000,84200,-80500,85000"
+st "SIGNAL drs_read_s_cell_ready  : std_logic"
+)
+)
+*200 (SaComponent
 uid 4903,0
 optionalChildren [
-*194 (CptPort
+*201 (CptPort
 uid 4867,0
 ps "OnEdgeStrategy"
@@ -6605,5 +6843,5 @@
 )
 )
-*195 (CptPort
+*202 (CptPort
 uid 4871,0
 ps "OnEdgeStrategy"
@@ -6615,5 +6853,5 @@
 fg "0,65535,0"
 )
-xt "1000,52625,1750,53375"
+xt "1000,48625,1750,49375"
 )
 tg (CPTG
@@ -6625,8 +6863,8 @@
 va (VaSet
 )
-xt "-7500,52500,0,53500"
+xt "-7500,48500,0,49500"
 st "start_endless_mode"
 ju 2
-blo "0,53300"
+blo "0,49300"
 )
 )
@@ -6639,5 +6877,5 @@
 )
 )
-*196 (CptPort
+*203 (CptPort
 uid 4875,0
 ps "OnEdgeStrategy"
@@ -6649,5 +6887,5 @@
 fg "0,65535,0"
 )
-xt "1000,49625,1750,50375"
+xt "1000,45625,1750,46375"
 )
 tg (CPTG
@@ -6659,8 +6897,8 @@
 va (VaSet
 )
-xt "-10200,49500,0,50500"
+xt "-10200,45500,0,46500"
 st "start_read_stop_pos_mode"
 ju 2
-blo "0,50300"
+blo "0,46300"
 )
 )
@@ -6673,5 +6911,5 @@
 )
 )
-*197 (CptPort
+*204 (CptPort
 uid 4879,0
 ps "OnEdgeStrategy"
@@ -6706,5 +6944,5 @@
 )
 )
-*198 (CptPort
+*205 (CptPort
 uid 4883,0
 ps "OnEdgeStrategy"
@@ -6739,5 +6977,5 @@
 )
 )
-*199 (CptPort
+*206 (CptPort
 uid 4887,0
 ps "OnEdgeStrategy"
@@ -6772,5 +7010,5 @@
 )
 )
-*200 (CptPort
+*207 (CptPort
 uid 4891,0
 ps "OnEdgeStrategy"
@@ -6805,5 +7043,5 @@
 )
 )
-*201 (CptPort
+*208 (CptPort
 uid 4895,0
 ps "OnEdgeStrategy"
@@ -6815,5 +7053,5 @@
 fg "0,65535,0"
 )
-xt "1000,51625,1750,52375"
+xt "1000,47625,1750,48375"
 )
 tg (CPTG
@@ -6825,8 +7063,8 @@
 va (VaSet
 )
-xt "-3400,51500,0,52500"
+xt "-3400,47500,0,48500"
 st "stop_pos"
 ju 2
-blo "0,52300"
+blo "0,48300"
 )
 )
@@ -6840,5 +7078,5 @@
 )
 )
-*202 (CptPort
+*209 (CptPort
 uid 4899,0
 ps "OnEdgeStrategy"
@@ -6850,5 +7088,5 @@
 fg "0,65535,0"
 )
-xt "1000,50625,1750,51375"
+xt "1000,46625,1750,47375"
 )
 tg (CPTG
@@ -6860,8 +7098,8 @@
 va (VaSet
 )
-xt "-5700,50500,0,51500"
+xt "-5700,46500,0,47500"
 st "stop_pos_valid"
 ju 2
-blo "0,51300"
+blo "0,47300"
 )
 )
@@ -6876,5 +7114,5 @@
 )
 )
-*203 (CptPort
+*210 (CptPort
 uid 4938,0
 ps "OnEdgeStrategy"
@@ -6906,10 +7144,10 @@
 n "RSRLOAD"
 t "std_logic"
-o 10
+o 15
 i "'0'"
 )
 )
 )
-*204 (CptPort
+*211 (CptPort
 uid 4942,0
 ps "OnEdgeStrategy"
@@ -6941,6 +7179,182 @@
 n "SRCLK"
 t "std_logic"
+o 16
+i "'0'"
+)
+)
+)
+*212 (CptPort
+uid 10272,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10273,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,56625,1750,57375"
+)
+tg (CPTG
+uid 10274,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10275,0
+va (VaSet
+)
+xt "-6100,56500,0,57500"
+st "srin_data : (7:0)"
+ju 2
+blo "0,57300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "srin_data"
+t "std_logic_vector"
+b "(7 downto 0)"
+o 13
+)
+)
+)
+*213 (CptPort
+uid 10276,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10277,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-18750,56625,-18000,57375"
+)
+tg (CPTG
+uid 10278,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10279,0
+va (VaSet
+)
+xt "-17000,56500,-13300,57500"
+st "SRIN_out"
+blo "-17000,57300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 14
+i "'0'"
+)
+)
+)
+*214 (CptPort
+uid 10280,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10281,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,54625,1750,55375"
+)
+tg (CPTG
+uid 10282,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10283,0
+va (VaSet
+)
+xt "-5600,54500,0,55500"
+st "srin_write_ack"
+ju 2
+blo "0,55300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "srin_write_ack"
+t "std_logic"
+o 12
+i "'0'"
+)
+)
+)
+*215 (CptPort
+uid 10284,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10285,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,55625,1750,56375"
+)
+tg (CPTG
+uid 10286,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10287,0
+va (VaSet
+)
+xt "-6300,55500,0,56500"
+st "srin_write_ready"
+ju 2
+blo "0,56300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "srin_write_ready"
+t "std_logic"
 o 11
 i "'0'"
+)
+)
+)
+*216 (CptPort
+uid 10288,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10289,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,53625,1750,54375"
+)
+tg (CPTG
+uid 10290,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10291,0
+va (VaSet
+)
+xt "-7200,53500,0,54500"
+st "start_srin_write_8b"
+ju 2
+blo "0,54300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "start_srin_write_8b"
+t "std_logic"
+o 10
 )
 )
@@ -6955,5 +7369,5 @@
 lineWidth 2
 )
-xt "-18000,44000,1000,54000"
+xt "-18000,44000,1000,59000"
 )
 oxt "0,0,8000,10000"
@@ -6963,32 +7377,32 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*205 (Text
+*217 (Text
 uid 4906,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "-17400,54000,-10800,55000"
+xt "-12400,41000,-5800,42000"
 st "FACT_FAD_LIB"
-blo "-17400,54800"
+blo "-12400,41800"
 tm "BdLibraryNameMgr"
 )
-*206 (Text
+*218 (Text
 uid 4907,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "-17400,55000,-12700,56000"
+xt "-12400,42000,-7700,43000"
 st "drs_pulser"
-blo "-17400,55800"
+blo "-12400,42800"
 tm "CptNameMgr"
 )
-*207 (Text
+*219 (Text
 uid 4908,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "-17400,56000,-9900,57000"
+xt "-12400,43000,-4900,44000"
 st "I_main_drs_pulser"
-blo "-17400,56800"
+blo "-12400,43800"
 tm "InstanceNameMgr"
 )
@@ -7019,5 +7433,5 @@
 fg "49152,49152,49152"
 )
-xt "-17750,52250,-16250,53750"
+xt "-17750,57250,-16250,58750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -7030,5 +7444,5 @@
 archFileType "UNKNOWN"
 )
-*208 (Net
+*220 (Net
 uid 4946,0
 decl (Decl
@@ -7045,9 +7459,8 @@
 )
 xt "-103000,37400,-63000,38200"
-st "RSRLOAD                : std_logic                                    := '0'
-"
-)
-)
-*209 (PortIoOut
+st "RSRLOAD                : std_logic                                    := '0'"
+)
+)
+*221 (PortIoOut
 uid 4954,0
 shape (CompositeShape
@@ -7094,5 +7507,5 @@
 )
 )
-*210 (Net
+*222 (Net
 uid 4960,0
 decl (Decl
@@ -7109,9 +7522,8 @@
 )
 xt "-103000,38200,-63000,39000"
-st "SRCLK                  : std_logic                                    := '0'
-"
-)
-)
-*211 (PortIoOut
+st "SRCLK                  : std_logic                                    := '0'"
+)
+)
+*223 (PortIoOut
 uid 4968,0
 shape (CompositeShape
@@ -7158,8 +7570,8 @@
 )
 )
-*212 (SaComponent
+*224 (SaComponent
 uid 5072,0
 optionalChildren [
-*213 (CptPort
+*225 (CptPort
 uid 5028,0
 ps "OnEdgeStrategy"
@@ -7195,5 +7607,5 @@
 )
 )
-*214 (CptPort
+*226 (CptPort
 uid 5032,0
 ps "OnEdgeStrategy"
@@ -7231,5 +7643,5 @@
 )
 )
-*215 (CptPort
+*227 (CptPort
 uid 5036,0
 ps "OnEdgeStrategy"
@@ -7267,5 +7679,5 @@
 )
 )
-*216 (CptPort
+*228 (CptPort
 uid 5040,0
 ps "OnEdgeStrategy"
@@ -7303,5 +7715,5 @@
 )
 )
-*217 (CptPort
+*229 (CptPort
 uid 5044,0
 ps "OnEdgeStrategy"
@@ -7340,5 +7752,5 @@
 )
 )
-*218 (CptPort
+*230 (CptPort
 uid 5048,0
 ps "OnEdgeStrategy"
@@ -7375,5 +7787,5 @@
 )
 )
-*219 (CptPort
+*231 (CptPort
 uid 5052,0
 ps "OnEdgeStrategy"
@@ -7410,5 +7822,5 @@
 )
 )
-*220 (CptPort
+*232 (CptPort
 uid 5056,0
 ps "OnEdgeStrategy"
@@ -7440,10 +7852,10 @@
 n "dac_array"
 t "dac_array_type"
-o 10
+o 12
 suid 8,0
 )
 )
 )
-*221 (CptPort
+*233 (CptPort
 uid 5060,0
 ps "OnEdgeStrategy"
@@ -7480,5 +7892,5 @@
 )
 )
-*222 (CptPort
+*234 (CptPort
 uid 5064,0
 ps "OnEdgeStrategy"
@@ -7514,5 +7926,5 @@
 )
 )
-*223 (CptPort
+*235 (CptPort
 uid 5068,0
 ps "OnEdgeStrategy"
@@ -7549,5 +7961,5 @@
 )
 )
-*224 (CptPort
+*236 (CptPort
 uid 5995,0
 ps "OnEdgeStrategy"
@@ -7579,5 +7991,5 @@
 n "config_started"
 t "std_logic"
-o 9
+o 11
 suid 12,0
 i "'0'"
@@ -7585,9 +7997,9 @@
 )
 )
-*225 (CptPort
-uid 8500,0
+*237 (CptPort
+uid 10184,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 8501,0
+uid 10185,0
 ro 90
 va (VaSet
@@ -7598,13 +8010,13 @@
 )
 tg (CPTG
-uid 8502,0
+uid 10186,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 8503,0
-va (VaSet
-)
-xt "83800,109500,91000,110500"
-st "drs_address : (3:0)"
+uid 10187,0
+va (VaSet
+)
+xt "85400,109500,91000,110500"
+st "config_rw_ack"
 ju 2
 blo "91000,110300"
@@ -7614,17 +8026,20 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 11
-suid 13,0
-)
-)
-)
-*226 (CptPort
-uid 8504,0
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
+suid 15,0
+i "'0'"
+)
+)
+)
+*238 (CptPort
+uid 10188,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 8505,0
+uid 10189,0
 ro 90
 va (VaSet
@@ -7635,13 +8050,13 @@
 )
 tg (CPTG
-uid 8506,0
+uid 10190,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 8507,0
-va (VaSet
-)
-xt "83800,110500,91000,111500"
-st "drs_address_mode"
+uid 10191,0
+va (VaSet
+)
+xt "84700,110500,91000,111500"
+st "config_rw_ready"
 ju 2
 blo "91000,111300"
@@ -7651,8 +8066,12 @@
 m 1
 decl (Decl
-n "drs_address_mode"
-t "std_logic"
-o 12
-suid 14,0
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
+suid 16,0
+i "'0'"
 )
 )
@@ -7675,5 +8094,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*227 (Text
+*239 (Text
 uid 5075,0
 va (VaSet
@@ -7685,5 +8104,5 @@
 tm "BdLibraryNameMgr"
 )
-*228 (Text
+*240 (Text
 uid 5076,0
 va (VaSet
@@ -7695,5 +8114,5 @@
 tm "CptNameMgr"
 )
-*229 (Text
+*241 (Text
 uid 5077,0
 va (VaSet
@@ -7741,5 +8160,5 @@
 archFileType "UNKNOWN"
 )
-*230 (Net
+*242 (Net
 uid 5088,0
 decl (Decl
@@ -7755,10 +8174,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,61800,-71000,62600"
-st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
-"
-)
-)
-*231 (Net
+xt "-103000,62600,-71000,63400"
+st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
+)
+)
+*243 (Net
 uid 5096,0
 decl (Decl
@@ -7773,10 +8191,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,64200,-80500,65000"
-st "SIGNAL config_data_valid      : std_logic
-"
-)
-)
-*232 (Net
+xt "-103000,65000,-80500,65800"
+st "SIGNAL config_data_valid      : std_logic"
+)
+)
+*244 (Net
 uid 5104,0
 decl (Decl
@@ -7791,10 +8208,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,62600,-80500,63400"
-st "SIGNAL config_busy            : std_logic
-"
-)
-)
-*233 (Net
+xt "-103000,63400,-80500,64200"
+st "SIGNAL config_busy            : std_logic"
+)
+)
+*245 (Net
 uid 5112,0
 decl (Decl
@@ -7810,10 +8226,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,63400,-70500,64200"
-st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
-"
-)
-)
-*234 (Net
+xt "-103000,64200,-70500,65000"
+st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
+)
+)
+*246 (Net
 uid 5120,0
 decl (Decl
@@ -7828,10 +8243,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,73800,-80500,74600"
-st "SIGNAL config_wr_en           : std_logic
-"
-)
-)
-*235 (Net
+xt "-103000,77800,-80500,78600"
+st "SIGNAL config_wr_en           : std_logic"
+)
+)
+*247 (Net
 uid 5128,0
 decl (Decl
@@ -7846,10 +8260,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,65000,-80500,65800"
-st "SIGNAL config_rd_en           : std_logic
-"
-)
-)
-*236 (Net
+xt "-103000,65800,-80500,66600"
+st "SIGNAL config_rd_en           : std_logic"
+)
+)
+*248 (Net
 uid 5144,0
 decl (Decl
@@ -7864,10 +8277,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,74600,-78000,75400"
-st "SIGNAL dac_array              : dac_array_type
-"
-)
-)
-*237 (Net
+xt "-103000,78600,-78000,79400"
+st "SIGNAL dac_array              : dac_array_type"
+)
+)
+*249 (Net
 uid 5194,0
 decl (Decl
@@ -7882,10 +8294,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,69000,-80500,69800"
-st "SIGNAL config_start_cm        : std_logic
-"
-)
-)
-*238 (Net
+xt "-103000,73000,-80500,73800"
+st "SIGNAL config_start_cm        : std_logic"
+)
+)
+*250 (Net
 uid 5196,0
 decl (Decl
@@ -7900,10 +8311,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,66600,-80500,67400"
-st "SIGNAL config_ready_cm        : std_logic
-"
-)
-)
-*239 (Net
+xt "-103000,67400,-80500,68200"
+st "SIGNAL config_ready_cm        : std_logic"
+)
+)
+*251 (Net
 uid 5220,0
 decl (Decl
@@ -7921,29 +8331,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,43800,-57000,44600"
-st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
-"
-)
-)
-*240 (Net
-uid 5279,0
-decl (Decl
-n "s_trigger"
-t "std_logic"
-o 69
-suid 134,0
-i "'0'"
-)
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 font "Courier New,8,0"
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-)
-)
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+st "SIGNAL config_started_spi     : std_logic                                    := '0'"
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 font "Courier New,8,0"
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-)
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 va (VaSet
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-)
-)
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 va (VaSet
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 va (VaSet
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-"
-)
-)
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 decl (Decl
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-)
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 shape (CompositeShape
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 decl (Decl
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 xt "-103000,33400,-84500,34200"
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-)
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 uid 9295,0
 decl (Decl
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 )
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-"
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-)
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 decl (Decl
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 )
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-)
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 decl (Decl
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 )
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 shape (CompositeShape
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 font "Courier New,8,0"
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-)
-)
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 font "Courier New,8,0"
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+xt "-103000,49400,-63000,51000"
 st "-- status:
-shifting               : std_logic                                    := '0'
-"
-)
-)
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 shape (CompositeShape
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-"
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-)
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-)
-)
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 decl (Decl
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-)
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+)
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@@ -15203,11 +16240,11 @@
 vasetType 3
 )
-xt "148750,55000,153000,55000"
-pts [
-"148750,55000"
-"153000,55000"
-]
-)
-start &75
+xt "149750,55000,154000,55000"
+pts [
+"149750,55000"
+"154000,55000"
+]
+)
+start &79
 end &20
 sat 32
@@ -15226,7 +16263,7 @@
 isHidden 1
 )
-xt "150000,54000,152600,55000"
+xt "151000,54000,153600,55000"
 st "wiz_rd"
-blo "150000,54800"
+blo "151000,54800"
 tm "WireNameMgr"
 )
@@ -15234,5 +16271,5 @@
 on &12
 )
-*514 (Wire
+*559 (Wire
 uid 432,0
 shape (OrthoPolyLine
@@ -15241,12 +16278,12 @@
 vasetType 3
 )
-xt "148750,56000,153000,56000"
-pts [
-"153000,56000"
-"148750,56000"
+xt "149750,56000,154000,56000"
+pts [
+"154000,56000"
+"149750,56000"
 ]
 )
 start &21
-end &76
+end &80
 sat 32
 eat 32
@@ -15264,7 +16301,7 @@
 isHidden 1
 )
-xt "150000,55000,152700,56000"
+xt "151000,55000,153700,56000"
 st "wiz_int"
-blo "150000,55800"
+blo "151000,55800"
 tm "WireNameMgr"
 )
@@ -15272,5 +16309,5 @@
 on &13
 )
-*515 (Wire
+*560 (Wire
 uid 1411,0
 shape (OrthoPolyLine
@@ -15286,5 +16323,5 @@
 ]
 )
-start &155
+start &162
 end &28
 sat 32
@@ -15309,22 +16346,8 @@
 )
 )
-on &65
-)
-*516 (Wire
+on &69
+)
+*561 (Wire
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-optionalChildren [
-*517 (BdJunction
-uid 4391,0
-ps "OnConnectorStrategy"
-shape (Circle
-uid 4392,0
-va (VaSet
-vasetType 1
-)
-xt "-22400,68600,-21600,69400"
-radius 400
-)
-)
-]
 shape (OrthoPolyLine
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@@ -15332,12 +16355,12 @@
 vasetType 3
 )
-xt "-26000,69000,18250,69000"
-pts [
-"-26000,69000"
-"18250,69000"
-]
-)
-start &67
-end &30
+xt "-32000,70000,-30000,70000"
+pts [
+"-32000,70000"
+"-30000,70000"
+]
+)
+start &71
+end &524
 es 0
 sat 32
@@ -15356,13 +16379,13 @@
 isHidden 1
 )
-xt "5000,63000,7800,64000"
+xt "-38000,69000,-35200,70000"
 st "trigger"
-blo "5000,63800"
+blo "-38000,69800"
 tm "WireNameMgr"
 )
 )
-on &66
-)
-*518 (Wire
+on &70
+)
+*562 (Wire
 uid 1682,0
 shape (OrthoPolyLine
@@ -15378,5 +16401,5 @@
 ]
 )
-start &156
+start &163
 end &31
 sat 32
@@ -15401,7 +16424,7 @@
 )
 )
-on &106
-)
-*519 (Wire
+on &112
+)
+*563 (Wire
 uid 1983,0
 shape (OrthoPolyLine
@@ -15419,5 +16442,5 @@
 ]
 )
-start &108
+start &114
 end &29
 sat 32
@@ -15440,7 +16463,7 @@
 )
 )
-on &114
-)
-*520 (Wire
+on &120
+)
+*564 (Wire
 uid 2299,0
 shape (OrthoPolyLine
@@ -15458,5 +16481,5 @@
 ]
 )
-start &117
+start &123
 end &27
 sat 32
@@ -15480,7 +16503,7 @@
 )
 )
-on &115
-)
-*521 (Wire
+on &121
+)
+*565 (Wire
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 shape (OrthoPolyLine
@@ -15489,13 +16512,12 @@
 vasetType 3
 )
-xt "103750,68000,126250,68000"
+xt "103750,68000,127250,68000"
 pts [
 "103750,68000"
-"115000,68000"
-"126250,68000"
-]
-)
-start &124
-end &82
+"127250,68000"
+]
+)
+start &130
+end &86
 sat 32
 eat 32
@@ -15517,7 +16539,7 @@
 )
 )
-on &138
-)
-*522 (Wire
+on &145
+)
+*566 (Wire
 uid 2476,0
 shape (OrthoPolyLine
@@ -15526,13 +16548,12 @@
 vasetType 3
 )
-xt "103750,69000,126250,69000"
+xt "103750,69000,127250,69000"
 pts [
 "103750,69000"
-"115000,69000"
-"126250,69000"
-]
-)
-start &127
-end &81
+"127250,69000"
+]
+)
+start &133
+end &85
 sat 32
 eat 32
@@ -15554,7 +16575,7 @@
 )
 )
-on &139
-)
-*523 (Wire
+on &146
+)
+*567 (Wire
 uid 2482,0
 shape (OrthoPolyLine
@@ -15564,13 +16585,12 @@
 lineWidth 2
 )
-xt "103750,70000,126250,70000"
+xt "103750,70000,127250,70000"
 pts [
 "103750,70000"
-"115000,70000"
-"126250,70000"
-]
-)
-start &130
-end &77
+"127250,70000"
+]
+)
+start &136
+end &81
 sat 32
 eat 32
@@ -15593,7 +16613,7 @@
 )
 )
-on &140
-)
-*524 (Wire
+on &147
+)
+*568 (Wire
 uid 2488,0
 shape (OrthoPolyLine
@@ -15603,13 +16623,12 @@
 lineWidth 2
 )
-xt "103750,71000,126250,71000"
+xt "103750,71000,127250,71000"
 pts [
 "103750,71000"
-"115000,71000"
-"126250,71000"
-]
-)
-start &126
-end &78
+"127250,71000"
+]
+)
+start &132
+end &82
 sat 32
 eat 32
@@ -15632,7 +16651,7 @@
 )
 )
-on &141
-)
-*525 (Wire
+on &148
+)
+*569 (Wire
 uid 2494,0
 shape (OrthoPolyLine
@@ -15642,13 +16661,12 @@
 lineWidth 2
 )
-xt "103750,72000,126250,72000"
+xt "103750,72000,127250,72000"
 pts [
 "103750,72000"
-"115000,72000"
-"126250,72000"
-]
-)
-start &125
-end &83
+"127250,72000"
+]
+)
+start &131
+end &87
 sat 32
 eat 32
@@ -15671,7 +16689,7 @@
 )
 )
-on &142
-)
-*526 (Wire
+on &149
+)
+*570 (Wire
 uid 2500,0
 shape (OrthoPolyLine
@@ -15680,13 +16698,12 @@
 vasetType 3
 )
-xt "103750,73000,126250,73000"
+xt "103750,73000,127250,73000"
 pts [
 "103750,73000"
-"115000,73000"
-"126250,73000"
-]
-)
-start &128
-end &84
+"127250,73000"
+]
+)
+start &134
+end &88
 sat 32
 eat 32
@@ -15708,7 +16725,7 @@
 )
 )
-on &143
-)
-*527 (Wire
+on &150
+)
+*571 (Wire
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 shape (OrthoPolyLine
@@ -15717,13 +16734,12 @@
 vasetType 3
 )
-xt "103750,74000,126250,74000"
+xt "103750,74000,127250,74000"
 pts [
 "103750,74000"
-"115000,74000"
-"126250,74000"
-]
-)
-start &129
-end &85
+"127250,74000"
+]
+)
+start &135
+end &89
 sat 32
 eat 32
@@ -15745,7 +16761,7 @@
 )
 )
-on &144
-)
-*528 (Wire
+on &151
+)
+*572 (Wire
 uid 2576,0
 shape (OrthoPolyLine
@@ -15763,5 +16779,5 @@
 )
 start &32
-end &121
+end &127
 sat 32
 eat 32
@@ -15783,7 +16799,7 @@
 )
 )
-on &145
-)
-*529 (Wire
+on &152
+)
+*573 (Wire
 uid 2582,0
 shape (OrthoPolyLine
@@ -15801,5 +16817,5 @@
 )
 start &33
-end &122
+end &128
 sat 32
 eat 32
@@ -15821,7 +16837,7 @@
 )
 )
-on &146
-)
-*530 (Wire
+on &153
+)
+*574 (Wire
 uid 2588,0
 shape (OrthoPolyLine
@@ -15833,11 +16849,11 @@
 pts [
 "40750,70000"
-"64000,70000"
-"64000,75000"
+"63000,70000"
+"63000,75000"
 "71250,75000"
 ]
 )
-start &53
-end &120
+start &52
+end &126
 ss 0
 sat 32
@@ -15860,7 +16876,7 @@
 )
 )
-on &147
-)
-*531 (Wire
+on &154
+)
+*575 (Wire
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 shape (OrthoPolyLine
@@ -15872,11 +16888,11 @@
 pts [
 "40750,72000"
-"62000,72000"
-"62000,77000"
+"61000,72000"
+"61000,77000"
 "71250,77000"
 ]
 )
-start &49
-end &119
+start &48
+end &125
 sat 32
 eat 32
@@ -15898,7 +16914,7 @@
 )
 )
-on &148
-)
-*532 (Wire
+on &155
+)
+*576 (Wire
 uid 2600,0
 shape (OrthoPolyLine
@@ -15910,11 +16926,11 @@
 pts [
 "40750,74000"
-"61000,74000"
-"61000,78000"
+"60000,74000"
+"60000,78000"
 "71250,78000"
 ]
 )
 start &34
-end &123
+end &129
 sat 32
 eat 32
@@ -15936,7 +16952,7 @@
 )
 )
-on &149
-)
-*533 (Wire
+on &156
+)
+*577 (Wire
 uid 2642,0
 shape (OrthoPolyLine
@@ -15949,11 +16965,11 @@
 pts [
 "40750,75000"
-"60000,75000"
-"60000,79000"
+"59000,75000"
+"59000,79000"
 "71250,79000"
 ]
 )
 start &36
-end &132
+end &138
 sat 32
 eat 32
@@ -15976,7 +16992,7 @@
 )
 )
-on &150
-)
-*534 (Wire
+on &157
+)
+*578 (Wire
 uid 2778,0
 shape (OrthoPolyLine
@@ -15992,5 +17008,5 @@
 )
 start &37
-end &152
+end &159
 sat 32
 eat 32
@@ -16014,7 +17030,7 @@
 )
 )
-on &151
-)
-*535 (Wire
+on &158
+)
+*579 (Wire
 uid 2786,0
 shape (OrthoPolyLine
@@ -16030,6 +17046,6 @@
 ]
 )
-start &153
-end &250
+start &160
+end &261
 sat 32
 eat 32
@@ -16054,48 +17070,10 @@
 )
 )
-on &174
-)
-*536 (Wire
-uid 2876,0
-shape (OrthoPolyLine
-uid 2877,0
-va (VaSet
-vasetType 3
-)
-xt "-22000,64000,-18750,69000"
-pts [
-"-22000,69000"
-"-22000,64000"
-"-18750,64000"
-]
-)
-start &517
-end &109
-es 0
-sat 32
-eat 32
-st 0
-sf 1
-tg (WTG
-uid 2880,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 2881,0
-ro 270
-va (VaSet
-)
-xt "-23000,64200,-22000,67000"
-st "trigger"
-blo "-22200,67000"
-tm "WireNameMgr"
-)
-)
-on &66
-)
-*537 (Wire
+on &181
+)
+*580 (Wire
 uid 3888,0
 optionalChildren [
-*538 (BdJunction
+*581 (BdJunction
 uid 4230,0
 ps "OnConnectorStrategy"
@@ -16109,5 +17087,5 @@
 )
 )
-*539 (BdJunction
+*582 (BdJunction
 uid 4244,0
 ps "OnConnectorStrategy"
@@ -16117,9 +17095,9 @@
 vasetType 1
 )
-xt "108600,18600,109400,19400"
+xt "108600,51600,109400,52400"
 radius 400
 )
 )
-*540 (BdJunction
+*583 (BdJunction
 uid 9677,0
 ps "OnConnectorStrategy"
@@ -16140,14 +17118,14 @@
 lineColor "0,0,65535"
 )
-xt "-1250,19000,126250,52000"
+xt "-1250,19000,127250,52000"
 pts [
 "-1250,19000"
-"123000,19000"
-"123000,52000"
-"126250,52000"
-]
-)
-start &368
-end &69
+"106000,19000"
+"106000,52000"
+"127250,52000"
+]
+)
+start &379
+end &73
 sat 32
 eat 32
@@ -16170,10 +17148,10 @@
 )
 )
-on &170
-)
-*541 (Wire
+on &177
+)
+*584 (Wire
 uid 3984,0
 optionalChildren [
-*542 (BdJunction
+*585 (BdJunction
 uid 9751,0
 ps "OnConnectorStrategy"
@@ -16202,6 +17180,6 @@
 ]
 )
-start &169
-end &380
+start &176
+end &391
 sat 32
 eat 32
@@ -16225,7 +17203,7 @@
 )
 )
-on &168
-)
-*543 (Wire
+on &175
+)
+*586 (Wire
 uid 4042,0
 shape (OrthoPolyLine
@@ -16241,5 +17219,5 @@
 )
 start &1
-end &370
+end &381
 sat 32
 eat 32
@@ -16263,7 +17241,7 @@
 )
 )
-on &173
-)
-*544 (Wire
+on &180
+)
+*587 (Wire
 uid 4226,0
 shape (OrthoPolyLine
@@ -16280,6 +17258,6 @@
 ]
 )
-start &172
-end &538
+start &179
+end &581
 sat 32
 eat 32
@@ -16303,7 +17281,7 @@
 )
 )
-on &170
-)
-*545 (Wire
+on &177
+)
+*588 (Wire
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 shape (OrthoPolyLine
@@ -16313,13 +17291,13 @@
 lineColor "0,0,65535"
 )
-xt "91750,19000,109000,44000"
+xt "91750,44000,109000,52000"
 pts [
 "91750,44000"
 "109000,44000"
-"109000,19000"
-]
-)
-start &314
-end &539
+"109000,52000"
+]
+)
+start &325
+end &582
 sat 32
 eat 32
@@ -16342,7 +17320,7 @@
 )
 )
-on &170
-)
-*546 (Wire
+on &177
+)
+*589 (Wire
 uid 4272,0
 shape (OrthoPolyLine
@@ -16357,6 +17335,6 @@
 ]
 )
-start &176
-end &247
+start &183
+end &258
 sat 32
 eat 32
@@ -16380,7 +17358,7 @@
 )
 )
-on &175
-)
-*547 (Wire
+on &182
+)
+*590 (Wire
 uid 4401,0
 shape (OrthoPolyLine
@@ -16389,12 +17367,14 @@
 vasetType 3
 )
-xt "1750,53000,18250,53000"
+xt "1750,49000,18250,53000"
 pts [
 "18250,53000"
-"1750,53000"
+"7000,53000"
+"7000,49000"
+"1750,49000"
 ]
 )
 start &40
-end &195
+end &202
 sat 32
 eat 32
@@ -16416,7 +17396,7 @@
 )
 )
-on &177
-)
-*548 (Wire
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+)
+*591 (Wire
 uid 4407,0
 shape (OrthoPolyLine
@@ -16425,12 +17405,14 @@
 vasetType 3
 )
-xt "1750,52000,18250,52000"
+xt "1750,48000,18250,52000"
 pts [
 "18250,52000"
-"1750,52000"
+"8000,52000"
+"8000,48000"
+"1750,48000"
 ]
 )
 start &44
-end &201
+end &208
 sat 32
 eat 32
@@ -16452,7 +17434,7 @@
 )
 )
-on &178
-)
-*549 (Wire
+on &185
+)
+*592 (Wire
 uid 4419,0
 shape (OrthoPolyLine
@@ -16461,12 +17443,14 @@
 vasetType 3
 )
-xt "1750,50000,18250,50000"
+xt "1750,46000,18250,50000"
 pts [
 "18250,50000"
-"1750,50000"
+"10000,50000"
+"10000,46000"
+"1750,46000"
 ]
 )
 start &42
-end &196
+end &203
 sat 32
 eat 32
@@ -16488,7 +17472,7 @@
 )
 )
-on &179
-)
-*550 (Wire
+on &186
+)
+*593 (Wire
 uid 4537,0
 shape (OrthoPolyLine
@@ -16504,6 +17488,6 @@
 ]
 )
-start &326
-end &182
+start &337
+end &189
 sat 32
 eat 32
@@ -16528,7 +17512,7 @@
 )
 )
-on &180
-)
-*551 (Wire
+on &187
+)
+*594 (Wire
 uid 4545,0
 shape (OrthoPolyLine
@@ -16543,6 +17527,6 @@
 ]
 )
-start &291
-end &183
+start &302
+end &190
 sat 32
 eat 32
@@ -16565,7 +17549,7 @@
 )
 )
-on &181
-)
-*552 (Wire
+on &188
+)
+*595 (Wire
 uid 4671,0
 shape (OrthoPolyLine
@@ -16580,6 +17564,6 @@
 ]
 )
-start &188
-end &197
+start &195
+end &204
 sat 32
 eat 32
@@ -16603,7 +17587,7 @@
 )
 )
-on &184
-)
-*553 (Wire
+on &191
+)
+*596 (Wire
 uid 4679,0
 shape (OrthoPolyLine
@@ -16618,6 +17602,6 @@
 ]
 )
-start &189
-end &198
+start &196
+end &205
 sat 32
 eat 32
@@ -16641,7 +17625,7 @@
 )
 )
-on &185
-)
-*554 (Wire
+on &192
+)
+*597 (Wire
 uid 4687,0
 shape (OrthoPolyLine
@@ -16656,6 +17640,6 @@
 ]
 )
-start &190
-end &199
+start &197
+end &206
 sat 32
 eat 32
@@ -16679,7 +17663,7 @@
 )
 )
-on &186
-)
-*555 (Wire
+on &193
+)
+*598 (Wire
 uid 4695,0
 shape (OrthoPolyLine
@@ -16694,6 +17678,6 @@
 ]
 )
-start &191
-end &200
+start &198
+end &207
 sat 32
 eat 32
@@ -16717,7 +17701,7 @@
 )
 )
-on &187
-)
-*556 (Wire
+on &194
+)
+*599 (Wire
 uid 4743,0
 shape (OrthoPolyLine
@@ -16726,11 +17710,13 @@
 vasetType 3
 )
-xt "1750,51000,18250,51000"
-pts [
-"1750,51000"
+xt "1750,47000,18250,51000"
+pts [
+"1750,47000"
+"9000,47000"
+"9000,51000"
 "18250,51000"
 ]
 )
-start &202
+start &209
 end &43
 sat 32
@@ -16753,10 +17739,10 @@
 )
 )
-on &192
-)
-*557 (Wire
+on &199
+)
+*600 (Wire
 uid 4757,0
 optionalChildren [
-*558 (BdJunction
+*601 (BdJunction
 uid 6076,0
 ps "OnConnectorStrategy"
@@ -16785,6 +17771,6 @@
 ]
 )
-start &194
-end *559 (BdJunction
+start &201
+end *602 (BdJunction
 uid 6080,0
 ps "OnConnectorStrategy"
@@ -16818,7 +17804,7 @@
 )
 )
-on &171
-)
-*560 (Wire
+on &178
+)
+*603 (Wire
 uid 4948,0
 shape (OrthoPolyLine
@@ -16833,6 +17819,6 @@
 ]
 )
-start &203
-end &209
+start &210
+end &221
 sat 32
 eat 32
@@ -16856,7 +17842,7 @@
 )
 )
-on &208
-)
-*561 (Wire
+on &220
+)
+*604 (Wire
 uid 4962,0
 shape (OrthoPolyLine
@@ -16871,6 +17857,6 @@
 ]
 )
-start &485
-end &211
+start &496
+end &223
 sat 32
 eat 32
@@ -16894,7 +17880,7 @@
 )
 )
-on &210
-)
-*562 (Wire
+on &222
+)
+*605 (Wire
 uid 5090,0
 shape (OrthoPolyLine
@@ -16904,14 +17890,14 @@
 lineWidth 2
 )
-xt "92750,79000,126250,100000"
-pts [
-"126250,79000"
-"116000,79000"
-"116000,100000"
+xt "92750,79000,127250,100000"
+pts [
+"127250,79000"
+"120000,79000"
+"120000,100000"
 "92750,100000"
 ]
 )
-start &88
-end &214
+start &92
+end &226
 sat 32
 eat 32
@@ -16927,13 +17913,13 @@
 va (VaSet
 )
-xt "119000,78000,126000,79000"
+xt "120000,78000,127000,79000"
 st "config_addr : (7:0)"
-blo "119000,78800"
+blo "120000,78800"
 tm "WireNameMgr"
 )
 )
-on &230
-)
-*563 (Wire
+on &242
+)
+*606 (Wire
 uid 5098,0
 shape (OrthoPolyLine
@@ -16948,5 +17934,5 @@
 ]
 )
-start &215
+start &227
 sat 32
 eat 16
@@ -16967,7 +17953,7 @@
 )
 )
-on &231
-)
-*564 (Wire
+on &243
+)
+*607 (Wire
 uid 5106,0
 shape (OrthoPolyLine
@@ -16976,14 +17962,14 @@
 vasetType 3
 )
-xt "92750,84000,126250,106000"
+xt "92750,84000,127250,106000"
 pts [
 "92750,106000"
-"121000,106000"
-"121000,84000"
-"126250,84000"
-]
-)
-start &216
-end &89
+"124000,106000"
+"124000,84000"
+"127250,84000"
+]
+)
+start &228
+end &93
 sat 32
 eat 32
@@ -17004,7 +17990,7 @@
 )
 )
-on &232
-)
-*565 (Wire
+on &244
+)
+*608 (Wire
 uid 5114,0
 shape (OrthoPolyLine
@@ -17014,14 +18000,14 @@
 lineWidth 2
 )
-xt "92750,80000,126250,101000"
+xt "92750,80000,127250,101000"
 pts [
 "92750,101000"
-"117000,101000"
-"117000,80000"
-"126250,80000"
-]
-)
-start &217
-end &90
+"121000,101000"
+"121000,80000"
+"127250,80000"
+]
+)
+start &229
+end &94
 sat 32
 eat 32
@@ -17043,7 +18029,7 @@
 )
 )
-on &233
-)
-*566 (Wire
+on &245
+)
+*609 (Wire
 uid 5122,0
 shape (OrthoPolyLine
@@ -17052,14 +18038,14 @@
 vasetType 3
 )
-xt "92750,82000,126250,104000"
-pts [
-"126250,82000"
-"119000,82000"
-"119000,104000"
+xt "92750,82000,127250,104000"
+pts [
+"127250,82000"
+"122000,82000"
+"122000,104000"
 "92750,104000"
 ]
 )
-start &92
-end &219
+start &96
+end &231
 sat 32
 eat 32
@@ -17074,13 +18060,13 @@
 va (VaSet
 )
-xt "121000,81000,126300,82000"
+xt "122000,81000,127300,82000"
 st "config_wr_en"
-blo "121000,81800"
+blo "122000,81800"
 tm "WireNameMgr"
 )
 )
-on &234
-)
-*567 (Wire
+on &246
+)
+*610 (Wire
 uid 5130,0
 shape (OrthoPolyLine
@@ -17089,14 +18075,14 @@
 vasetType 3
 )
-xt "92750,83000,126250,105000"
-pts [
-"126250,83000"
-"120000,83000"
-"120000,105000"
+xt "92750,83000,127250,105000"
+pts [
+"127250,83000"
+"123000,83000"
+"123000,105000"
 "92750,105000"
 ]
 )
-start &94
-end &221
+start &98
+end &233
 sat 32
 eat 32
@@ -17111,16 +18097,16 @@
 va (VaSet
 )
-xt "121000,82000,126200,83000"
+xt "122000,82000,127200,83000"
 st "config_rd_en"
-blo "121000,82800"
+blo "122000,82800"
 tm "WireNameMgr"
 )
 )
-on &235
-)
-*568 (Wire
+on &247
+)
+*611 (Wire
 uid 5138,0
 optionalChildren [
-*569 (BdJunction
+*612 (BdJunction
 uid 5400,0
 ps "OnConnectorStrategy"
@@ -17148,5 +18134,5 @@
 ]
 )
-start &218
+start &230
 end &35
 ss 0
@@ -17170,7 +18156,7 @@
 )
 )
-on &154
-)
-*570 (Wire
+on &161
+)
+*613 (Wire
 uid 5146,0
 shape (OrthoPolyLine
@@ -17185,6 +18171,6 @@
 ]
 )
-start &220
-end &258
+start &232
+end &269
 es 0
 sat 32
@@ -17206,7 +18192,7 @@
 )
 )
-on &236
-)
-*571 (Wire
+on &248
+)
+*614 (Wire
 uid 5168,0
 shape (OrthoPolyLine
@@ -17221,6 +18207,6 @@
 ]
 )
-start &569
-end &131
+start &612
+end &137
 sat 32
 eat 32
@@ -17242,7 +18228,7 @@
 )
 )
-on &154
-)
-*572 (Wire
+on &161
+)
+*615 (Wire
 uid 5184,0
 shape (OrthoPolyLine
@@ -17259,5 +18245,5 @@
 ]
 )
-start &222
+start &234
 end &47
 sat 32
@@ -17279,7 +18265,7 @@
 )
 )
-on &237
-)
-*573 (Wire
+on &249
+)
+*616 (Wire
 uid 5190,0
 shape (OrthoPolyLine
@@ -17296,5 +18282,5 @@
 ]
 )
-start &223
+start &235
 end &46
 sat 32
@@ -17316,7 +18302,7 @@
 )
 )
-on &238
-)
-*574 (Wire
+on &250
+)
+*617 (Wire
 uid 5222,0
 shape (OrthoPolyLine
@@ -17326,11 +18312,11 @@
 lineWidth 2
 )
-xt "148750,71000,153000,71000"
-pts [
-"148750,71000"
-"153000,71000"
-]
-)
-start &86
+xt "149750,71000,154000,71000"
+pts [
+"149750,71000"
+"154000,71000"
+]
+)
+start &90
 end &19
 sat 32
@@ -17350,51 +18336,13 @@
 isHidden 1
 )
-xt "150750,70000,152150,71000"
+xt "151750,70000,153150,71000"
 st "led"
-blo "150750,70800"
+blo "151750,70800"
 tm "WireNameMgr"
 )
 )
-on &239
-)
-*575 (Wire
-uid 5281,0
-shape (OrthoPolyLine
-uid 5282,0
-va (VaSet
-vasetType 3
-)
-xt "40750,53000,126250,59000"
-pts [
-"126250,59000"
-"73000,59000"
-"73000,53000"
-"40750,53000"
-]
-)
-start &87
-end &48
-sat 32
-eat 32
-st 0
-sf 1
-si 0
-tg (WTG
-uid 5283,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 5284,0
-va (VaSet
-)
-xt "121250,58000,124850,59000"
-st "s_trigger"
-blo "121250,58800"
-tm "WireNameMgr"
-)
-)
-on &240
-)
-*576 (Wire
+on &251
+)
+*618 (Wire
 uid 5404,0
 shape (OrthoPolyLine
@@ -17411,6 +18359,6 @@
 ]
 )
-start &259
-end &50
+start &270
+end &49
 sat 32
 eat 32
@@ -17431,7 +18379,7 @@
 )
 )
-on &243
-)
-*577 (Wire
+on &254
+)
+*619 (Wire
 uid 5474,0
 shape (OrthoPolyLine
@@ -17448,6 +18396,6 @@
 ]
 )
-start &262
-end &52
+start &273
+end &51
 sat 32
 eat 32
@@ -17468,7 +18416,7 @@
 )
 )
-on &241
-)
-*578 (Wire
+on &252
+)
+*620 (Wire
 uid 5480,0
 shape (OrthoPolyLine
@@ -17485,6 +18433,6 @@
 ]
 )
-start &261
-end &51
+start &272
+end &50
 sat 32
 eat 32
@@ -17505,7 +18453,7 @@
 )
 )
-on &242
-)
-*579 (Wire
+on &253
+)
+*621 (Wire
 uid 5582,0
 shape (OrthoPolyLine
@@ -17521,5 +18469,5 @@
 ]
 )
-end &213
+end &225
 sat 16
 eat 32
@@ -17540,11 +18488,11 @@
 )
 )
-on &170
-)
-*580 (Wire
+on &177
+)
+*622 (Wire
 uid 5602,0
 optionalChildren [
-&559
-*581 (BdJunction
+&602
+*623 (BdJunction
 uid 6086,0
 ps "OnConnectorStrategy"
@@ -17576,5 +18524,5 @@
 )
 start &23
-end &310
+end &321
 sat 32
 eat 32
@@ -17597,7 +18545,7 @@
 )
 )
-on &171
-)
-*582 (Wire
+on &178
+)
+*624 (Wire
 uid 5626,0
 shape (OrthoPolyLine
@@ -17613,5 +18561,5 @@
 )
 start &45
-end &248
+end &259
 sat 32
 eat 32
@@ -17633,7 +18581,7 @@
 )
 )
-on &245
-)
-*583 (Wire
+on &256
+)
+*625 (Wire
 uid 5634,0
 shape (OrthoPolyLine
@@ -17650,5 +18598,5 @@
 )
 start &38
-end &249
+end &260
 sat 32
 eat 32
@@ -17671,7 +18619,7 @@
 )
 )
-on &244
-)
-*584 (Wire
+on &255
+)
+*626 (Wire
 uid 5646,0
 shape (OrthoPolyLine
@@ -17687,5 +18635,5 @@
 ]
 )
-end &251
+end &262
 sat 16
 eat 32
@@ -17707,7 +18655,7 @@
 )
 )
-on &168
-)
-*585 (Wire
+on &175
+)
+*627 (Wire
 uid 5745,0
 shape (OrthoPolyLine
@@ -17724,6 +18672,6 @@
 ]
 )
-start &54
-end &260
+start &53
+end &271
 sat 32
 eat 32
@@ -17745,7 +18693,7 @@
 )
 )
-on &255
-)
-*586 (Wire
+on &266
+)
+*628 (Wire
 uid 5805,0
 shape (OrthoPolyLine
@@ -17760,5 +18708,5 @@
 ]
 )
-end &265
+end &276
 sat 16
 eat 32
@@ -17779,7 +18727,7 @@
 )
 )
-on &170
-)
-*587 (Wire
+on &177
+)
+*629 (Wire
 uid 5813,0
 shape (OrthoPolyLine
@@ -17794,6 +18742,6 @@
 ]
 )
-start &346
-end &276
+start &357
+end &287
 sat 32
 eat 32
@@ -17817,7 +18765,7 @@
 )
 )
-on &272
-)
-*588 (Wire
+on &283
+)
+*630 (Wire
 uid 5821,0
 shape (OrthoPolyLine
@@ -17832,6 +18780,6 @@
 ]
 )
-start &268
-end &277
+start &279
+end &288
 sat 32
 eat 32
@@ -17855,7 +18803,7 @@
 )
 )
-on &273
-)
-*589 (Wire
+on &284
+)
+*631 (Wire
 uid 5829,0
 shape (OrthoPolyLine
@@ -17870,6 +18818,6 @@
 ]
 )
-start &263
-end &278
+start &274
+end &289
 sat 32
 eat 32
@@ -17893,7 +18841,7 @@
 )
 )
-on &274
-)
-*590 (Wire
+on &285
+)
+*632 (Wire
 uid 5837,0
 shape (OrthoPolyLine
@@ -17909,6 +18857,6 @@
 ]
 )
-start &264
-end &279
+start &275
+end &290
 sat 32
 eat 32
@@ -17933,7 +18881,7 @@
 )
 )
-on &275
-)
-*591 (Wire
+on &286
+)
+*633 (Wire
 uid 5950,0
 shape (OrthoPolyLine
@@ -17942,14 +18890,14 @@
 vasetType 3
 )
-xt "40750,54000,126250,60000"
-pts [
-"126250,60000"
-"72000,60000"
-"72000,54000"
+xt "40750,54000,127250,60000"
+pts [
+"127250,60000"
+"110000,60000"
+"110000,54000"
 "40750,54000"
 ]
 )
-start &93
-end &56
+start &97
+end &55
 sat 32
 eat 32
@@ -17965,13 +18913,13 @@
 va (VaSet
 )
-xt "120250,59000,124850,60000"
+xt "121250,59000,125850,60000"
 st "new_config"
-blo "120250,59800"
+blo "121250,59800"
 tm "WireNameMgr"
 )
 )
-on &280
-)
-*592 (Wire
+on &291
+)
+*634 (Wire
 uid 5962,0
 shape (OrthoPolyLine
@@ -17980,14 +18928,14 @@
 vasetType 3
 )
-xt "40750,55000,126250,61000"
-pts [
-"126250,61000"
-"71000,61000"
-"71000,55000"
+xt "40750,55000,127250,61000"
+pts [
+"127250,61000"
+"111000,61000"
+"111000,55000"
 "40750,55000"
 ]
 )
-start &91
-end &55
+start &95
+end &54
 sat 32
 eat 32
@@ -18003,13 +18951,13 @@
 va (VaSet
 )
-xt "119250,60000,124850,61000"
+xt "120250,60000,125850,61000"
 st "config_started"
-blo "119250,60800"
+blo "120250,60800"
 tm "WireNameMgr"
 )
 )
-on &281
-)
-*593 (Wire
+on &292
+)
+*635 (Wire
 uid 6002,0
 shape (OrthoPolyLine
@@ -18026,6 +18974,6 @@
 ]
 )
-start &224
-end &57
+start &236
+end &56
 sat 32
 eat 32
@@ -18047,7 +18995,7 @@
 )
 )
-on &283
-)
-*594 (Wire
+on &294
+)
+*636 (Wire
 uid 6008,0
 shape (OrthoPolyLine
@@ -18064,6 +19012,6 @@
 ]
 )
-start &266
-end &59
+start &277
+end &58
 sat 32
 eat 32
@@ -18085,7 +19033,7 @@
 )
 )
-on &282
-)
-*595 (Wire
+on &293
+)
+*637 (Wire
 uid 6018,0
 shape (OrthoPolyLine
@@ -18097,11 +19045,11 @@
 pts [
 "40750,71000"
-"63000,71000"
-"63000,76000"
+"62000,71000"
+"62000,76000"
 "71250,76000"
 ]
 )
-start &58
-end &133
+start &57
+end &139
 sat 32
 eat 32
@@ -18123,7 +19071,7 @@
 )
 )
-on &284
-)
-*596 (Wire
+on &295
+)
+*638 (Wire
 uid 6064,0
 shape (OrthoPolyLine
@@ -18138,5 +19086,5 @@
 ]
 )
-end &60
+end &59
 sat 16
 eat 32
@@ -18158,10 +19106,10 @@
 )
 )
-on &236
-)
-*597 (Wire
+on &248
+)
+*639 (Wire
 uid 6072,0
 optionalChildren [
-*598 (BdJunction
+*640 (BdJunction
 uid 9745,0
 ps "OnConnectorStrategy"
@@ -18189,6 +19137,6 @@
 ]
 )
-start &369
-end &558
+start &380
+end &601
 sat 32
 eat 32
@@ -18211,7 +19159,7 @@
 )
 )
-on &171
-)
-*599 (Wire
+on &178
+)
+*641 (Wire
 uid 6082,0
 shape (OrthoPolyLine
@@ -18228,6 +19176,6 @@
 ]
 )
-start &118
-end &581
+start &124
+end &623
 sat 32
 eat 32
@@ -18250,7 +19198,7 @@
 )
 )
-on &171
-)
-*600 (Wire
+on &178
+)
+*642 (Wire
 uid 6160,0
 shape (OrthoPolyLine
@@ -18265,6 +19213,6 @@
 ]
 )
-start &267
-end &286
+start &278
+end &297
 sat 32
 eat 32
@@ -18288,7 +19236,7 @@
 )
 )
-on &285
-)
-*601 (Wire
+on &296
+)
+*643 (Wire
 uid 6276,0
 shape (OrthoPolyLine
@@ -18303,5 +19251,5 @@
 ]
 )
-end &110
+end &116
 sat 16
 eat 32
@@ -18322,7 +19270,7 @@
 )
 )
-on &168
-)
-*602 (Wire
+on &175
+)
+*644 (Wire
 uid 6362,0
 shape (OrthoPolyLine
@@ -18331,12 +19279,12 @@
 vasetType 3
 )
-xt "148750,75000,153000,75000"
-pts [
-"148750,75000"
-"153000,75000"
-]
-)
-start &95
-end &288
+xt "149750,75000,154000,75000"
+pts [
+"149750,75000"
+"154000,75000"
+]
+)
+start &99
+end &299
 sat 32
 eat 32
@@ -18354,13 +19302,13 @@
 isHidden 1
 )
-xt "150000,74000,153000,75000"
+xt "151000,74000,154000,75000"
 st "denable"
-blo "150000,74800"
+blo "151000,74800"
 tm "WireNameMgr"
 )
 )
-on &287
-)
-*603 (Wire
+on &298
+)
+*645 (Wire
 uid 6452,0
 shape (OrthoPolyLine
@@ -18369,11 +19317,11 @@
 vasetType 3
 )
-xt "148750,76000,154000,76000"
-pts [
-"148750,76000"
-"154000,76000"
-]
-)
-start &96
+xt "149750,76000,155000,76000"
+pts [
+"149750,76000"
+"155000,76000"
+]
+)
+start &100
 sat 32
 eat 16
@@ -18390,13 +19338,13 @@
 va (VaSet
 )
-xt "155000,76000,160400,77000"
+xt "156000,76000,161400,77000"
 st "dwrite_enable"
-blo "155000,76800"
+blo "156000,76800"
 tm "WireNameMgr"
 )
 )
-on &289
-)
-*604 (Wire
+on &300
+)
+*646 (Wire
 uid 6540,0
 shape (OrthoPolyLine
@@ -18411,5 +19359,5 @@
 ]
 )
-start &294
+start &305
 end &41
 sat 32
@@ -18433,7 +19381,7 @@
 )
 )
-on &308
-)
-*605 (Wire
+on &319
+)
+*647 (Wire
 uid 6548,0
 shape (OrthoPolyLine
@@ -18444,11 +19392,13 @@
 xt "7000,61000,15000,61000"
 pts [
+"15000,61000"
 "7000,61000"
-"15000,61000"
-]
-)
-start &296
-sat 32
-eat 16
+]
+)
+end &307
+ss 0
+es 0
+sat 16
+eat 32
 stc 0
 st 0
@@ -18463,13 +19413,13 @@
 va (VaSet
 )
-xt "7000,60000,12400,61000"
+xt "15000,60000,20400,61000"
 st "dwrite_enable"
-blo "7000,60800"
+blo "15000,60800"
 tm "WireNameMgr"
 )
 )
-on &289
-)
-*606 (Wire
+on &300
+)
+*648 (Wire
 uid 8416,0
 shape (OrthoPolyLine
@@ -18478,12 +19428,12 @@
 vasetType 3
 )
-xt "103750,75000,126250,75000"
+xt "103750,75000,127250,75000"
 pts [
 "103750,75000"
-"126250,75000"
-]
-)
-start &134
-end &97
+"127250,75000"
+]
+)
+start &140
+end &101
 sat 32
 eat 32
@@ -18505,79 +19455,7 @@
 )
 )
-on &320
-)
-*607 (Wire
-uid 8510,0
-shape (OrthoPolyLine
-uid 8511,0
-va (VaSet
-vasetType 3
-lineWidth 2
-)
-xt "92750,110000,102000,110000"
-pts [
-"92750,110000"
-"102000,110000"
-]
-)
-start &225
-sat 32
-eat 16
-sty 1
-st 0
-sf 1
-si 0
-tg (WTG
-uid 8514,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 8515,0
-va (VaSet
-)
-xt "94000,109000,101200,110000"
-st "drs_address : (3:0)"
-blo "94000,109800"
-tm "WireNameMgr"
-)
-)
-on &321
-)
-*608 (Wire
-uid 8518,0
-shape (OrthoPolyLine
-uid 8519,0
-va (VaSet
-vasetType 3
-)
-xt "92750,111000,102000,111000"
-pts [
-"92750,111000"
-"102000,111000"
-]
-)
-start &226
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 8522,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 8523,0
-va (VaSet
-)
-xt "94000,110000,101200,111000"
-st "drs_address_mode"
-blo "94000,110800"
-tm "WireNameMgr"
-)
-)
-on &322
-)
-*609 (Wire
+on &331
+)
+*649 (Wire
 uid 8577,0
 shape (OrthoPolyLine
@@ -18587,8 +19465,9 @@
 lineWidth 2
 )
-xt "7000,57000,18250,57000"
-pts [
-"18250,57000"
-"7000,57000"
+xt "13000,64000,18250,64000"
+pts [
+"18250,64000"
+"13000,64000"
+"13000,64000"
 ]
 )
@@ -18608,13 +19487,13 @@
 va (VaSet
 )
-xt "8000,56000,18400,57000"
+xt "8000,62000,18400,63000"
 st "drs_channel_internal : (3:0)"
-blo "8000,56800"
+blo "8000,62800"
 tm "WireNameMgr"
 )
 )
-on &344
-)
-*610 (Wire
+on &355
+)
+*650 (Wire
 uid 8587,0
 shape (OrthoPolyLine
@@ -18630,5 +19509,5 @@
 ]
 )
-end &324
+end &335
 sat 16
 eat 32
@@ -18652,7 +19531,7 @@
 )
 )
-on &344
-)
-*611 (Wire
+on &355
+)
+*651 (Wire
 uid 8595,0
 shape (OrthoPolyLine
@@ -18668,5 +19547,5 @@
 ]
 )
-end &329
+end &340
 sat 16
 eat 32
@@ -18690,7 +19569,7 @@
 )
 )
-on &321
-)
-*612 (Wire
+on &332
+)
+*652 (Wire
 uid 8603,0
 shape (OrthoPolyLine
@@ -18706,5 +19585,5 @@
 ]
 )
-end &331
+end &342
 sat 16
 eat 32
@@ -18727,7 +19606,7 @@
 )
 )
-on &322
-)
-*613 (Wire
+on &333
+)
+*653 (Wire
 uid 8732,0
 shape (OrthoPolyLine
@@ -18744,6 +19623,6 @@
 ]
 )
-start &257
-end &351
+start &268
+end &362
 sat 32
 eat 32
@@ -18765,7 +19644,7 @@
 )
 )
-on &363
-)
-*614 (Wire
+on &374
+)
+*654 (Wire
 uid 8738,0
 shape (OrthoPolyLine
@@ -18780,5 +19659,5 @@
 ]
 )
-end &349
+end &360
 sat 16
 eat 32
@@ -18801,7 +19680,7 @@
 )
 )
-on &364
-)
-*615 (Wire
+on &375
+)
+*655 (Wire
 uid 8752,0
 shape (OrthoPolyLine
@@ -18810,11 +19689,11 @@
 vasetType 3
 )
-xt "148750,77000,154000,77000"
-pts [
-"148750,77000"
-"154000,77000"
-]
-)
-start &98
+xt "149750,77000,155000,77000"
+pts [
+"149750,77000"
+"155000,77000"
+]
+)
+start &102
 sat 32
 eat 16
@@ -18830,13 +19709,13 @@
 va (VaSet
 )
-xt "155000,77000,159700,78000"
+xt "156000,77000,160700,78000"
 st "sclk_enable"
-blo "155000,77800"
+blo "156000,77800"
 tm "WireNameMgr"
 )
 )
-on &364
-)
-*616 (Wire
+on &375
+)
+*656 (Wire
 uid 9006,0
 shape (OrthoPolyLine
@@ -18851,6 +19730,6 @@
 ]
 )
-start &61
-end &366
+start &60
+end &377
 sat 32
 eat 32
@@ -18874,7 +19753,7 @@
 )
 )
-on &365
-)
-*617 (Wire
+on &376
+)
+*657 (Wire
 uid 9233,0
 shape (OrthoPolyLine
@@ -18883,11 +19762,11 @@
 vasetType 3
 )
-xt "148750,81000,154000,81000"
-pts [
-"148750,81000"
-"154000,81000"
-]
-)
-start &99
+xt "149750,81000,155000,81000"
+pts [
+"149750,81000"
+"155000,81000"
+]
+)
+start &103
 sat 32
 eat 16
@@ -18903,13 +19782,13 @@
 va (VaSet
 )
-xt "155000,81000,159900,82000"
+xt "156000,81000,160900,82000"
 st "ps_direction"
-blo "155000,81800"
+blo "156000,81800"
 tm "WireNameMgr"
 )
 )
-on &387
-)
-*618 (Wire
+on &398
+)
+*658 (Wire
 uid 9241,0
 shape (OrthoPolyLine
@@ -18918,11 +19797,11 @@
 vasetType 3
 )
-xt "148750,82000,154000,82000"
-pts [
-"148750,82000"
-"154000,82000"
-]
-)
-start &100
+xt "149750,82000,155000,82000"
+pts [
+"149750,82000"
+"155000,82000"
+]
+)
+start &104
 sat 32
 eat 16
@@ -18938,16 +19817,16 @@
 va (VaSet
 )
-xt "155000,82000,162000,83000"
+xt "156000,82000,163000,83000"
 st "ps_do_phase_shift"
-blo "155000,82800"
+blo "156000,82800"
 tm "WireNameMgr"
 )
 )
-on &388
-)
-*619 (Wire
+on &399
+)
+*659 (Wire
 uid 9253,0
 optionalChildren [
-*620 (BdJunction
+*660 (BdJunction
 uid 9507,0
 ps "OnConnectorStrategy"
@@ -18973,5 +19852,5 @@
 ]
 )
-end &381
+end &392
 sat 16
 eat 32
@@ -18992,10 +19871,10 @@
 )
 )
-on &387
-)
-*621 (Wire
+on &398
+)
+*661 (Wire
 uid 9261,0
 optionalChildren [
-*622 (BdJunction
+*662 (BdJunction
 uid 9513,0
 ps "OnConnectorStrategy"
@@ -19021,5 +19900,5 @@
 ]
 )
-end &382
+end &393
 sat 16
 eat 32
@@ -19040,7 +19919,7 @@
 )
 )
-on &388
-)
-*623 (Wire
+on &399
+)
+*663 (Wire
 uid 9269,0
 shape (OrthoPolyLine
@@ -19055,6 +19934,6 @@
 ]
 )
-start &379
-end &390
+start &390
+end &401
 sat 32
 eat 32
@@ -19078,7 +19957,7 @@
 )
 )
-on &389
-)
-*624 (Wire
+on &400
+)
+*664 (Wire
 uid 9283,0
 shape (OrthoPolyLine
@@ -19093,6 +19972,6 @@
 ]
 )
-start &378
-end &392
+start &389
+end &403
 sat 32
 eat 32
@@ -19116,7 +19995,7 @@
 )
 )
-on &391
-)
-*625 (Wire
+on &402
+)
+*665 (Wire
 uid 9297,0
 shape (OrthoPolyLine
@@ -19131,6 +20010,6 @@
 ]
 )
-start &377
-end &394
+start &388
+end &405
 sat 32
 eat 32
@@ -19154,7 +20033,7 @@
 )
 )
-on &393
-)
-*626 (Wire
+on &404
+)
+*666 (Wire
 uid 9311,0
 shape (OrthoPolyLine
@@ -19169,6 +20048,6 @@
 ]
 )
-start &376
-end &396
+start &387
+end &407
 sat 32
 eat 32
@@ -19192,7 +20071,7 @@
 )
 )
-on &395
-)
-*627 (Wire
+on &406
+)
+*667 (Wire
 uid 9325,0
 shape (OrthoPolyLine
@@ -19207,6 +20086,6 @@
 ]
 )
-start &375
-end &398
+start &386
+end &409
 sat 32
 eat 32
@@ -19230,7 +20109,7 @@
 )
 )
-on &397
-)
-*628 (Wire
+on &408
+)
+*668 (Wire
 uid 9353,0
 shape (OrthoPolyLine
@@ -19245,6 +20124,6 @@
 ]
 )
-start &374
-end &400
+start &385
+end &411
 sat 32
 eat 32
@@ -19268,7 +20147,7 @@
 )
 )
-on &399
-)
-*629 (Wire
+on &410
+)
+*669 (Wire
 uid 9367,0
 shape (OrthoPolyLine
@@ -19284,6 +20163,6 @@
 ]
 )
-start &373
-end &402
+start &384
+end &413
 sat 32
 eat 32
@@ -19308,7 +20187,7 @@
 )
 )
-on &401
-)
-*630 (Wire
+on &412
+)
+*670 (Wire
 uid 9382,0
 shape (OrthoPolyLine
@@ -19323,6 +20202,6 @@
 ]
 )
-start &372
-end &404
+start &383
+end &415
 sat 32
 eat 32
@@ -19346,7 +20225,7 @@
 )
 )
-on &403
-)
-*631 (Wire
+on &414
+)
+*671 (Wire
 uid 9397,0
 shape (OrthoPolyLine
@@ -19361,6 +20240,6 @@
 ]
 )
-start &371
-end &406
+start &382
+end &417
 sat 32
 eat 32
@@ -19384,7 +20263,7 @@
 )
 )
-on &405
-)
-*632 (Wire
+on &416
+)
+*672 (Wire
 uid 9503,0
 shape (OrthoPolyLine
@@ -19400,6 +20279,6 @@
 ]
 )
-start &620
-end &421
+start &660
+end &432
 sat 32
 eat 32
@@ -19422,7 +20301,7 @@
 )
 )
-on &387
-)
-*633 (Wire
+on &398
+)
+*673 (Wire
 uid 9509,0
 shape (OrthoPolyLine
@@ -19438,6 +20317,6 @@
 ]
 )
-start &622
-end &408
+start &662
+end &419
 sat 32
 eat 32
@@ -19460,7 +20339,7 @@
 )
 )
-on &388
-)
-*634 (Wire
+on &399
+)
+*674 (Wire
 uid 9517,0
 shape (OrthoPolyLine
@@ -19477,6 +20356,6 @@
 ]
 )
-start &410
-end &433
+start &421
+end &444
 sat 32
 eat 32
@@ -19500,7 +20379,7 @@
 )
 )
-on &436
-)
-*635 (Wire
+on &447
+)
+*675 (Wire
 uid 9539,0
 shape (OrthoPolyLine
@@ -19517,6 +20396,6 @@
 ]
 )
-start &423
-end &434
+start &434
+end &445
 sat 32
 eat 32
@@ -19540,7 +20419,7 @@
 )
 )
-on &435
-)
-*636 (Wire
+on &446
+)
+*676 (Wire
 uid 9673,0
 shape (OrthoPolyLine
@@ -19556,6 +20435,6 @@
 ]
 )
-start &540
-end &438
+start &583
+end &449
 sat 32
 eat 32
@@ -19578,7 +20457,7 @@
 )
 )
-on &170
-)
-*637 (Wire
+on &177
+)
+*677 (Wire
 uid 9741,0
 shape (OrthoPolyLine
@@ -19595,6 +20474,6 @@
 ]
 )
-start &598
-end &451
+start &640
+end &462
 sat 32
 eat 32
@@ -19617,7 +20496,7 @@
 )
 )
-on &171
-)
-*638 (Wire
+on &178
+)
+*678 (Wire
 uid 9747,0
 shape (OrthoPolyLine
@@ -19634,6 +20513,6 @@
 ]
 )
-start &542
-end &464
+start &585
+end &475
 sat 32
 eat 32
@@ -19656,7 +20535,7 @@
 )
 )
-on &168
-)
-*639 (Wire
+on &175
+)
+*679 (Wire
 uid 9755,0
 shape (OrthoPolyLine
@@ -19671,6 +20550,6 @@
 ]
 )
-start &440
-end &476
+start &451
+end &487
 sat 32
 eat 32
@@ -19694,7 +20573,7 @@
 )
 )
-on &477
-)
-*640 (Wire
+on &488
+)
+*680 (Wire
 uid 9771,0
 shape (OrthoPolyLine
@@ -19709,6 +20588,6 @@
 ]
 )
-start &453
-end &478
+start &464
+end &489
 sat 32
 eat 32
@@ -19732,7 +20611,7 @@
 )
 )
-on &479
-)
-*641 (Wire
+on &490
+)
+*681 (Wire
 uid 9787,0
 shape (OrthoPolyLine
@@ -19747,6 +20626,6 @@
 ]
 )
-start &466
-end &480
+start &477
+end &491
 sat 32
 eat 32
@@ -19770,7 +20649,7 @@
 )
 )
-on &481
-)
-*642 (Wire
+on &492
+)
+*682 (Wire
 uid 9943,0
 shape (OrthoPolyLine
@@ -19779,11 +20658,11 @@
 vasetType 3
 )
-xt "148750,83000,154000,83000"
-pts [
-"148750,83000"
-"154000,83000"
-]
-)
-start &101
+xt "149750,83000,155000,83000"
+pts [
+"149750,83000"
+"155000,83000"
+]
+)
+start &105
 sat 32
 eat 16
@@ -19799,13 +20678,13 @@
 va (VaSet
 )
-xt "155000,83000,158300,84000"
+xt "156000,83000,159300,84000"
 st "ps_reset"
-blo "155000,83800"
+blo "156000,83800"
 tm "WireNameMgr"
 )
 )
-on &482
-)
-*643 (Wire
+on &493
+)
+*683 (Wire
 uid 9951,0
 shape (OrthoPolyLine
@@ -19814,11 +20693,11 @@
 vasetType 3
 )
-xt "148750,85000,154000,85000"
-pts [
-"148750,85000"
-"154000,85000"
-]
-)
-start &102
+xt "149750,85000,155000,85000"
+pts [
+"149750,85000"
+"155000,85000"
+]
+)
+start &106
 sat 32
 eat 16
@@ -19834,13 +20713,13 @@
 va (VaSet
 )
-xt "155000,85000,160000,86000"
+xt "156000,85000,161000,86000"
 st "srclk_enable"
-blo "155000,85800"
+blo "156000,85800"
 tm "WireNameMgr"
 )
 )
-on &483
-)
-*644 (Wire
+on &494
+)
+*684 (Wire
 uid 10010,0
 shape (OrthoPolyLine
@@ -19857,6 +20736,6 @@
 ]
 )
-start &204
-end &488
+start &211
+end &499
 sat 32
 eat 32
@@ -19878,7 +20757,7 @@
 )
 )
-on &502
-)
-*645 (Wire
+on &513
+)
+*685 (Wire
 uid 10018,0
 shape (OrthoPolyLine
@@ -19893,5 +20772,5 @@
 ]
 )
-end &490
+end &501
 sat 16
 eat 32
@@ -19914,7 +20793,7 @@
 )
 )
-on &483
-)
-*646 (Wire
+on &494
+)
+*686 (Wire
 uid 10036,0
 shape (OrthoPolyLine
@@ -19929,5 +20808,5 @@
 ]
 )
-end &383
+end &394
 sat 16
 eat 32
@@ -19948,5 +20827,466 @@
 )
 )
-on &482
+on &493
+)
+*687 (Wire
+uid 10194,0
+shape (OrthoPolyLine
+uid 10195,0
+va (VaSet
+vasetType 3
+)
+xt "92750,85000,127250,110000"
+pts [
+"92750,110000"
+"125000,110000"
+"125000,85000"
+"127250,85000"
+]
+)
+start &237
+end &107
+ss 0
+es 0
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10198,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10199,0
+va (VaSet
+)
+xt "94750,109000,100350,110000"
+st "config_rw_ack"
+blo "94750,109800"
+tm "WireNameMgr"
+)
+)
+on &514
+)
+*688 (Wire
+uid 10202,0
+shape (OrthoPolyLine
+uid 10203,0
+va (VaSet
+vasetType 3
+)
+xt "92750,86000,127250,111000"
+pts [
+"92750,111000"
+"126000,111000"
+"126000,86000"
+"127250,86000"
+]
+)
+start &238
+end &108
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10206,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10207,0
+va (VaSet
+)
+xt "94750,110000,101050,111000"
+st "config_rw_ready"
+blo "94750,110800"
+tm "WireNameMgr"
+)
+)
+on &515
+)
+*689 (Wire
+uid 10266,0
+shape (OrthoPolyLine
+uid 10267,0
+va (VaSet
+vasetType 3
+)
+xt "121000,64000,127250,64000"
+pts [
+"127250,64000"
+"124000,64000"
+"121000,64000"
+]
+)
+start &91
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10270,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10271,0
+va (VaSet
+)
+xt "122000,63000,125600,64000"
+st "s_trigger"
+blo "122000,63800"
+tm "WireNameMgr"
+)
+)
+on &516
+)
+*690 (Wire
+uid 10298,0
+shape (OrthoPolyLine
+uid 10299,0
+va (VaSet
+vasetType 3
+)
+xt "1750,54000,18250,54000"
+pts [
+"1750,54000"
+"18250,54000"
+]
+)
+start &216
+end &62
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10300,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10301,0
+va (VaSet
+)
+xt "3750,53000,10950,54000"
+st "start_srin_write_8b"
+blo "3750,53800"
+tm "WireNameMgr"
+)
+)
+on &517
+)
+*691 (Wire
+uid 10304,0
+shape (OrthoPolyLine
+uid 10305,0
+va (VaSet
+vasetType 3
+)
+xt "1750,55000,18250,55000"
+pts [
+"1750,55000"
+"18250,55000"
+]
+)
+start &214
+end &63
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10306,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10307,0
+va (VaSet
+)
+xt "3750,54000,9350,55000"
+st "srin_write_ack"
+blo "3750,54800"
+tm "WireNameMgr"
+)
+)
+on &518
+)
+*692 (Wire
+uid 10310,0
+shape (OrthoPolyLine
+uid 10311,0
+va (VaSet
+vasetType 3
+)
+xt "1750,56000,18250,56000"
+pts [
+"1750,56000"
+"18250,56000"
+]
+)
+start &215
+end &64
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10312,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10313,0
+va (VaSet
+)
+xt "3750,55000,10050,56000"
+st "srin_write_ready"
+blo "3750,55800"
+tm "WireNameMgr"
+)
+)
+on &519
+)
+*693 (Wire
+uid 10316,0
+shape (OrthoPolyLine
+uid 10317,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "1750,57000,18250,57000"
+pts [
+"18250,57000"
+"1750,57000"
+]
+)
+start &61
+end &212
+sat 32
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10318,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10319,0
+va (VaSet
+)
+xt "4000,56000,12000,57000"
+st "drs_srin_data : (7:0)"
+blo "4000,56800"
+tm "WireNameMgr"
+)
+)
+on &520
+)
+*694 (Wire
+uid 10322,0
+shape (OrthoPolyLine
+uid 10323,0
+va (VaSet
+vasetType 3
+)
+xt "-34000,57000,-18750,57000"
+pts [
+"-18750,57000"
+"-34000,57000"
+]
+)
+start &213
+end &522
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10326,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10327,0
+va (VaSet
+isHidden 1
+)
+xt "-24000,56000,-20300,57000"
+st "SRIN_out"
+blo "-24000,56800"
+tm "WireNameMgr"
+)
+)
+on &521
+)
+*695 (Wire
+uid 10431,0
+shape (OrthoPolyLine
+uid 10432,0
+va (VaSet
+vasetType 3
+)
+xt "-34000,68000,-30000,68000"
+pts [
+"-34000,68000"
+"-30000,68000"
+]
+)
+end &529
+sat 16
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10435,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10436,0
+va (VaSet
+)
+xt "-33000,67000,-29400,68000"
+st "s_trigger"
+blo "-33000,67800"
+tm "WireNameMgr"
+)
+)
+on &516
+)
+*696 (Wire
+uid 10439,0
+optionalChildren [
+*697 (BdJunction
+uid 10447,0
+ps "OnConnectorStrategy"
+shape (Circle
+uid 10448,0
+va (VaSet
+vasetType 1
+)
+xt "-21400,68600,-20600,69400"
+radius 400
+)
+)
+]
+shape (OrthoPolyLine
+uid 10440,0
+va (VaSet
+vasetType 3
+)
+xt "-24000,69000,18250,69000"
+pts [
+"18250,69000"
+"-24000,69000"
+]
+)
+start &30
+end &526
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10441,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10442,0
+va (VaSet
+)
+xt "14250,68000,18850,69000"
+st "trigger_out"
+blo "14250,68800"
+tm "WireNameMgr"
+)
+)
+on &546
+)
+*698 (Wire
+uid 10443,0
+shape (OrthoPolyLine
+uid 10444,0
+va (VaSet
+vasetType 3
+)
+xt "-21000,64000,-18750,69000"
+pts [
+"-18750,64000"
+"-21000,64000"
+"-21000,69000"
+]
+)
+start &115
+end &697
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10445,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10446,0
+va (VaSet
+)
+xt "-20000,68000,-15400,69000"
+st "trigger_out"
+blo "-20000,68800"
+tm "WireNameMgr"
+)
+)
+on &546
+)
+*699 (Wire
+uid 10467,0
+shape (OrthoPolyLine
+uid 10468,0
+va (VaSet
+vasetType 3
+)
+xt "40750,66000,71250,73000"
+pts [
+"71250,73000"
+"64000,73000"
+"64000,66000"
+"40750,66000"
+]
+)
+start &141
+end &65
+es 0
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10471,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10472,0
+va (VaSet
+)
+xt "42000,65000,49800,66000"
+st "ram_write_ready_ack"
+blo "42000,65800"
+tm "WireNameMgr"
+)
+)
+on &547
 )
 ]
@@ -19962,9 +21302,9 @@
 color "26368,26368,26368"
 )
-packageList *647 (PackageList
+packageList *700 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*648 (Text
+*701 (Text
 uid 42,0
 va (VaSet
@@ -19975,5 +21315,5 @@
 blo "-87000,1800"
 )
-*649 (MLText
+*702 (MLText
 uid 43,0
 va (VaSet
@@ -20000,5 +21340,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*650 (Text
+*703 (Text
 uid 45,0
 va (VaSet
@@ -20010,5 +21350,5 @@
 blo "20000,800"
 )
-*651 (Text
+*704 (Text
 uid 46,0
 va (VaSet
@@ -20020,5 +21360,5 @@
 blo "20000,1800"
 )
-*652 (MLText
+*705 (MLText
 uid 47,0
 va (VaSet
@@ -20030,5 +21370,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*653 (Text
+*706 (Text
 uid 48,0
 va (VaSet
@@ -20040,5 +21380,5 @@
 blo "20000,4800"
 )
-*654 (MLText
+*707 (MLText
 uid 49,0
 va (VaSet
@@ -20048,5 +21388,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*655 (Text
+*708 (Text
 uid 50,0
 va (VaSet
@@ -20058,5 +21398,5 @@
 blo "20000,5800"
 )
-*656 (MLText
+*709 (MLText
 uid 51,0
 va (VaSet
@@ -20070,6 +21410,6 @@
 )
 windowSize "1280,0,2561,1024"
-viewArea "-71804,-21787,15728,50400"
-cachedDiagramExtent "-105000,-60500,162300,343294"
+viewArea "1300,44100,167081,180819"
+cachedDiagramExtent "-105000,-60500,163300,343294"
 pageSetupInfo (PageSetupInfo
 ptrCmd "eDocPrintPro,winspool,"
@@ -20096,5 +21436,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
-lastUid 10041,0
+lastUid 10547,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -20158,5 +21498,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*657 (Text
+*710 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20167,5 +21507,5 @@
 tm "BdLibraryNameMgr"
 )
-*658 (Text
+*711 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20176,5 +21516,5 @@
 tm "BlkNameMgr"
 )
-*659 (Text
+*712 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20227,5 +21567,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*660 (Text
+*713 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20235,5 +21575,5 @@
 blo "550,4300"
 )
-*661 (Text
+*714 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20243,5 +21583,5 @@
 blo "550,5300"
 )
-*662 (Text
+*715 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20292,5 +21632,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*663 (Text
+*716 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20301,5 +21641,5 @@
 tm "BdLibraryNameMgr"
 )
-*664 (Text
+*717 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20310,5 +21650,5 @@
 tm "CptNameMgr"
 )
-*665 (Text
+*718 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20364,5 +21704,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*666 (Text
+*719 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20372,5 +21712,5 @@
 blo "500,4300"
 )
-*667 (Text
+*720 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20380,5 +21720,5 @@
 blo "500,5300"
 )
-*668 (Text
+*721 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20425,5 +21765,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*669 (Text
+*722 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20433,5 +21773,5 @@
 blo "50,4300"
 )
-*670 (Text
+*723 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20441,5 +21781,5 @@
 blo "50,5300"
 )
-*671 (Text
+*724 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20482,5 +21822,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*672 (Text
+*725 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20491,5 +21831,5 @@
 tm "HdlTextNameMgr"
 )
-*673 (Text
+*726 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20894,5 +22234,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*674 (Text
+*727 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20902,5 +22242,5 @@
 blo "14100,20800"
 )
-*675 (MLText
+*728 (MLText
 va (VaSet
 )
@@ -20954,5 +22294,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*676 (Text
+*729 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20962,5 +22302,5 @@
 blo "14100,20800"
 )
-*677 (MLText
+*730 (MLText
 va (VaSet
 )
@@ -21061,7 +22401,7 @@
 font "Arial,8,1"
 )
-xt "-105000,55800,-101200,56800"
+xt "-105000,56600,-101200,57600"
 st "Pre User:"
-blo "-105000,56600"
+blo "-105000,57400"
 )
 preUserText (MLText
@@ -21078,7 +22418,7 @@
 font "Arial,8,1"
 )
-xt "-105000,56800,-97900,57800"
+xt "-105000,57600,-97900,58600"
 st "Diagram Signals:"
-blo "-105000,57600"
+blo "-105000,58400"
 )
 postUserLabel (Text
@@ -21087,7 +22427,7 @@
 font "Arial,8,1"
 )
-xt "-105000,105800,-100300,106800"
+xt "-105000,115400,-100300,116400"
 st "Post User:"
-blo "-105000,106600"
+blo "-105000,116200"
 )
 postUserText (MLText
@@ -21102,44 +22442,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 226,0
+suid 242,0
 usingSuid 1
-emptyRow *678 (LEmptyRow
+emptyRow *731 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*679 (RefLabelRowHdr
-)
-*680 (TitleRowHdr
-)
-*681 (FilterRowHdr
-)
-*682 (RefLabelColHdr
+*732 (RefLabelRowHdr
+)
+*733 (TitleRowHdr
+)
+*734 (FilterRowHdr
+)
+*735 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*683 (RowExpandColHdr
+*736 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*684 (GroupColHdr
+*737 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*685 (NameColHdr
+*738 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*686 (ModeColHdr
+*739 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*687 (TypeColHdr
+*740 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*688 (BoundsColHdr
+*741 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*689 (InitColHdr
+*742 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*690 (EolColHdr
+*743 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*691 (LeafLogPort
+*744 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21155,5 +22495,5 @@
 uid 516,0
 )
-*692 (LeafLogPort
+*745 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21168,5 +22508,5 @@
 uid 518,0
 )
-*693 (LeafLogPort
+*746 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21181,5 +22521,5 @@
 uid 520,0
 )
-*694 (LeafLogPort
+*747 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21194,5 +22534,5 @@
 uid 530,0
 )
-*695 (LeafLogPort
+*748 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21207,5 +22547,5 @@
 uid 532,0
 )
-*696 (LeafLogPort
+*749 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21220,5 +22560,5 @@
 uid 534,0
 )
-*697 (LeafLogPort
+*750 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21233,5 +22573,5 @@
 uid 536,0
 )
-*698 (LeafLogPort
+*751 (LeafLogPort
 port (LogicalPort
 m 2
@@ -21246,5 +22586,5 @@
 uid 538,0
 )
-*699 (LeafLogPort
+*752 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21259,5 +22599,5 @@
 uid 540,0
 )
-*700 (LeafLogPort
+*753 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21272,5 +22612,5 @@
 uid 542,0
 )
-*701 (LeafLogPort
+*754 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21285,5 +22625,5 @@
 uid 546,0
 )
-*702 (LeafLogPort
+*755 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21296,5 +22636,5 @@
 uid 548,0
 )
-*703 (LeafLogPort
+*756 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21310,5 +22650,5 @@
 uid 1455,0
 )
-*704 (LeafLogPort
+*757 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21323,5 +22663,5 @@
 uid 1457,0
 )
-*705 (LeafLogPort
+*758 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21335,5 +22675,5 @@
 uid 1694,0
 )
-*706 (LeafLogPort
+*759 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21351,5 +22691,5 @@
 uid 1993,0
 )
-*707 (LeafLogPort
+*760 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21366,5 +22706,5 @@
 uid 2305,0
 )
-*708 (LeafLogPort
+*761 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21379,5 +22719,5 @@
 uid 2510,0
 )
-*709 (LeafLogPort
+*762 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21393,5 +22733,5 @@
 uid 2512,0
 )
-*710 (LeafLogPort
+*763 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21408,5 +22748,5 @@
 uid 2514,0
 )
-*711 (LeafLogPort
+*764 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21424,5 +22764,5 @@
 uid 2516,0
 )
-*712 (LeafLogPort
+*765 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21439,5 +22779,5 @@
 uid 2518,0
 )
-*713 (LeafLogPort
+*766 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21453,5 +22793,5 @@
 uid 2520,0
 )
-*714 (LeafLogPort
+*767 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21467,5 +22807,5 @@
 uid 2522,0
 )
-*715 (LeafLogPort
+*768 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21479,5 +22819,5 @@
 uid 2604,0
 )
-*716 (LeafLogPort
+*769 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21492,5 +22832,5 @@
 uid 2606,0
 )
-*717 (LeafLogPort
+*770 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21505,5 +22845,5 @@
 uid 2608,0
 )
-*718 (LeafLogPort
+*771 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21517,5 +22857,5 @@
 uid 2610,0
 )
-*719 (LeafLogPort
+*772 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21529,5 +22869,5 @@
 uid 2612,0
 )
-*720 (LeafLogPort
+*773 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21542,5 +22882,5 @@
 uid 2646,0
 )
-*721 (LeafLogPort
+*774 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21555,5 +22895,5 @@
 uid 2812,0
 )
-*722 (LeafLogPort
+*775 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21567,5 +22907,5 @@
 uid 2962,0
 )
-*723 (LeafLogPort
+*776 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21579,5 +22919,5 @@
 uid 3902,0
 )
-*724 (LeafLogPort
+*777 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21591,5 +22931,5 @@
 uid 4070,0
 )
-*725 (LeafLogPort
+*778 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21603,5 +22943,5 @@
 uid 4212,0
 )
-*726 (LeafLogPort
+*779 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21614,5 +22954,5 @@
 uid 4234,0
 )
-*727 (LeafLogPort
+*780 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21626,5 +22966,5 @@
 uid 4262,0
 )
-*728 (LeafLogPort
+*781 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21637,5 +22977,5 @@
 uid 4276,0
 )
-*729 (LeafLogPort
+*782 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21650,5 +22990,5 @@
 uid 4563,0
 )
-*730 (LeafLogPort
+*783 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21662,5 +23002,5 @@
 uid 4565,0
 )
-*731 (LeafLogPort
+*784 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21675,5 +23015,5 @@
 uid 4569,0
 )
-*732 (LeafLogPort
+*785 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21689,5 +23029,5 @@
 uid 4585,0
 )
-*733 (LeafLogPort
+*786 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21702,5 +23042,5 @@
 uid 4587,0
 )
-*734 (LeafLogPort
+*787 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21713,5 +23053,5 @@
 uid 4733,0
 )
-*735 (LeafLogPort
+*788 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21724,5 +23064,5 @@
 uid 4735,0
 )
-*736 (LeafLogPort
+*789 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21735,5 +23075,5 @@
 uid 4737,0
 )
-*737 (LeafLogPort
+*790 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21746,5 +23086,5 @@
 uid 4739,0
 )
-*738 (LeafLogPort
+*791 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21758,5 +23098,5 @@
 uid 4749,0
 )
-*739 (LeafLogPort
+*792 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21771,5 +23111,5 @@
 uid 4974,0
 )
-*740 (LeafLogPort
+*793 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21784,5 +23124,5 @@
 uid 4976,0
 )
-*741 (LeafLogPort
+*794 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21797,5 +23137,5 @@
 uid 5198,0
 )
-*742 (LeafLogPort
+*795 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21809,5 +23149,5 @@
 uid 5200,0
 )
-*743 (LeafLogPort
+*796 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21821,5 +23161,5 @@
 uid 5202,0
 )
-*744 (LeafLogPort
+*797 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21834,5 +23174,5 @@
 uid 5204,0
 )
-*745 (LeafLogPort
+*798 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21846,5 +23186,5 @@
 uid 5206,0
 )
-*746 (LeafLogPort
+*799 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21858,5 +23198,5 @@
 uid 5208,0
 )
-*747 (LeafLogPort
+*800 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21870,5 +23210,5 @@
 uid 5210,0
 )
-*748 (LeafLogPort
+*801 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21882,5 +23222,5 @@
 uid 5212,0
 )
-*749 (LeafLogPort
+*802 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21894,5 +23234,5 @@
 uid 5214,0
 )
-*750 (LeafLogPort
+*803 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21909,21 +23249,8 @@
 uid 5226,0
 )
-*751 (LeafLogPort
+*804 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "s_trigger"
-t "std_logic"
-o 69
-suid 134,0
-i "'0'"
-)
-)
-uid 5285,0
-)
-*752 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "sensor_ready"
 t "std_logic"
@@ -21934,5 +23261,5 @@
 uid 5502,0
 )
-*753 (LeafLogPort
+*805 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21946,5 +23273,5 @@
 uid 5504,0
 )
-*754 (LeafLogPort
+*806 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21958,5 +23285,5 @@
 uid 5600,0
 )
-*755 (LeafLogPort
+*807 (LeafLogPort
 port (LogicalPort
 lang 10
@@ -21972,5 +23299,5 @@
 uid 5642,0
 )
-*756 (LeafLogPort
+*808 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21984,5 +23311,5 @@
 uid 5644,0
 )
-*757 (LeafLogPort
+*809 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21997,5 +23324,5 @@
 uid 5751,0
 )
-*758 (LeafLogPort
+*810 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22009,5 +23336,5 @@
 uid 5867,0
 )
-*759 (LeafLogPort
+*811 (LeafLogPort
 port (LogicalPort
 m 2
@@ -22023,5 +23350,5 @@
 uid 5869,0
 )
-*760 (LeafLogPort
+*812 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22035,5 +23362,5 @@
 uid 5871,0
 )
-*761 (LeafLogPort
+*813 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22048,5 +23375,5 @@
 uid 5873,0
 )
-*762 (LeafLogPort
+*814 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22061,5 +23388,5 @@
 uid 5966,0
 )
-*763 (LeafLogPort
+*815 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22073,5 +23400,5 @@
 uid 5968,0
 )
-*764 (LeafLogPort
+*816 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22086,5 +23413,5 @@
 uid 6022,0
 )
-*765 (LeafLogPort
+*817 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22099,5 +23426,5 @@
 uid 6024,0
 )
-*766 (LeafLogPort
+*818 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22111,5 +23438,5 @@
 uid 6026,0
 )
-*767 (LeafLogPort
+*819 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22124,5 +23451,5 @@
 uid 6172,0
 )
-*768 (LeafLogPort
+*820 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22139,5 +23466,5 @@
 uid 6374,0
 )
-*769 (LeafLogPort
+*821 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22152,5 +23479,5 @@
 uid 6464,0
 )
-*770 (LeafLogPort
+*822 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22165,5 +23492,5 @@
 uid 6554,0
 )
-*771 (LeafLogPort
+*823 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -22178,5 +23505,5 @@
 uid 8420,0
 )
-*772 (LeafLogPort
+*824 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22192,5 +23519,5 @@
 uid 8609,0
 )
-*773 (LeafLogPort
+*825 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22204,5 +23531,5 @@
 uid 8611,0
 )
-*774 (LeafLogPort
+*826 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22218,5 +23545,5 @@
 uid 8613,0
 )
-*775 (LeafLogPort
+*827 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22230,5 +23557,5 @@
 uid 8758,0
 )
-*776 (LeafLogPort
+*828 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22242,5 +23569,5 @@
 uid 8760,0
 )
-*777 (LeafLogPort
+*829 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22255,5 +23582,5 @@
 uid 9018,0
 )
-*778 (LeafLogPort
+*830 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22270,5 +23597,5 @@
 uid 9247,0
 )
-*779 (LeafLogPort
+*831 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22286,5 +23613,5 @@
 uid 9249,0
 )
-*780 (LeafLogPort
+*832 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22298,5 +23625,5 @@
 uid 9555,0
 )
-*781 (LeafLogPort
+*833 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22310,5 +23637,5 @@
 uid 9557,0
 )
-*782 (LeafLogPort
+*834 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22322,5 +23649,5 @@
 uid 9559,0
 )
-*783 (LeafLogPort
+*835 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22334,5 +23661,5 @@
 uid 9561,0
 )
-*784 (LeafLogPort
+*836 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22346,5 +23673,5 @@
 uid 9563,0
 )
-*785 (LeafLogPort
+*837 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22360,5 +23687,5 @@
 uid 9567,0
 )
-*786 (LeafLogPort
+*838 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22376,5 +23703,5 @@
 uid 9569,0
 )
-*787 (LeafLogPort
+*839 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22392,5 +23719,5 @@
 uid 9571,0
 )
-*788 (LeafLogPort
+*840 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22407,5 +23734,5 @@
 uid 9573,0
 )
-*789 (LeafLogPort
+*841 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22419,5 +23746,5 @@
 uid 9575,0
 )
-*790 (LeafLogPort
+*842 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22431,5 +23758,5 @@
 uid 9577,0
 )
-*791 (LeafLogPort
+*843 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22443,5 +23770,5 @@
 uid 9801,0
 )
-*792 (LeafLogPort
+*844 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22455,5 +23782,5 @@
 uid 9803,0
 )
-*793 (LeafLogPort
+*845 (LeafLogPort
 port (LogicalPort
 m 1
@@ -22467,5 +23794,5 @@
 uid 9805,0
 )
-*794 (LeafLogPort
+*846 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22482,5 +23809,5 @@
 uid 10024,0
 )
-*795 (LeafLogPort
+*847 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22495,5 +23822,5 @@
 uid 10026,0
 )
-*796 (LeafLogPort
+*848 (LeafLogPort
 port (LogicalPort
 m 4
@@ -22507,4 +23834,144 @@
 )
 uid 10028,0
+)
+*849 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 107
+suid 227,0
+i "'0'"
+)
+)
+uid 10208,0
+)
+*850 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 108
+suid 228,0
+i "'0'"
+)
+)
+uid 10210,0
+)
+*851 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "s_trigger"
+t "std_logic"
+o 109
+suid 230,0
+)
+)
+uid 10294,0
+)
+*852 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "start_srin_write_8b"
+t "std_logic"
+o 110
+suid 231,0
+)
+)
+uid 10334,0
+)
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+i "'0'"
+)
+)
+uid 10336,0
+)
+*854 (LeafLogPort
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+i "'0'"
+)
+)
+uid 10338,0
+)
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+decl (Decl
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+suid 234,0
+i "(others => '0')"
+)
+)
+uid 10340,0
+)
+*856 (LeafLogPort
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+i "'0'"
+)
+)
+uid 10342,0
+)
+*857 (LeafLogPort
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+suid 240,0
+)
+)
+uid 10473,0
+)
+*858 (LeafLogPort
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+lang 2
+m 4
+decl (Decl
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+posAdd 0
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+i "'0'"
+)
+)
+uid 10475,0
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 ]
@@ -22515,5 +23982,5 @@
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@@ -22532,25 +23999,25 @@
 font "Tahoma,10,0"
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@@ -22558,639 +24025,693 @@
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@@ -23205,48 +24726,48 @@
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 uid 99,0
 )
-*933 (MRCItem
-litem &919
+*1004 (MRCItem
+litem &990
 pos 2
 hidden 1
@@ -23360,6 +24881,6 @@
 uid 100,0
 )
-*934 (MRCItem
-litem &928
+*1005 (MRCItem
+litem &999
 pos 0
 dimension 20
@@ -23377,42 +24898,42 @@
 uid 101,0
 optionalChildren [
-*935 (MRCItem
-litem &920
+*1006 (MRCItem
+litem &991
 pos 0
 dimension 20
 uid 102,0
 )
-*936 (MRCItem
-litem &922
+*1007 (MRCItem
+litem &993
 pos 1
 dimension 50
 uid 103,0
 )
-*937 (MRCItem
-litem &923
+*1008 (MRCItem
+litem &994
 pos 2
 dimension 186
 uid 104,0
 )
-*938 (MRCItem
-litem &924
+*1009 (MRCItem
+litem &995
 pos 3
 dimension 96
 uid 105,0
 )
-*939 (MRCItem
-litem &925
+*1010 (MRCItem
+litem &996
 pos 4
 dimension 50
 uid 106,0
 )
-*940 (MRCItem
-litem &926
+*1011 (MRCItem
+litem &997
 pos 5
 dimension 50
 uid 107,0
 )
-*941 (MRCItem
-litem &927
+*1012 (MRCItem
+litem &998
 pos 6
 dimension 80
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak	(revision 10073)
@@ -224,4 +224,13 @@
 uid 9957,0
 )
+(Instance
+name "U_9"
+duLibraryName "moduleware"
+duName "or"
+elements [
+]
+mwi 1
+uid 10380,0
+)
 ]
 libraryRefs [
@@ -239,21 +248,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -271,25 +280,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main"
 )
 (vvPair
 variable "date"
-value "30.08.2010"
+value "04.01.2011"
 )
 (vvPair
 variable "day"
-value "Mo"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Montag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "30"
+value "04"
 )
 (vvPair
@@ -355,5 +364,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -363,17 +372,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
 )
 (vvPair
@@ -431,5 +440,5 @@
 (vvPair
 variable "time"
-value "10:42:05"
+value "11:02:28"
 )
 (vvPair
@@ -451,9 +460,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -522,7 +531,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,105000,-59500,105800"
-st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
-"
+xt "-103000,114600,-59500,115400"
+st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
 )
 )
@@ -541,7 +549,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,61000,-63000,61800"
-st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
-"
+xt "-103000,61800,-63000,62600"
+st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
 )
 )
@@ -560,7 +567,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,75400,-70500,76200"
-st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
-"
+xt "-103000,79400,-70500,80200"
+st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
 )
 )
@@ -579,7 +585,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,87400,-63000,88200"
-st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
-"
+xt "-103000,92200,-63000,93000"
+st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
 )
 )
@@ -598,7 +603,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,88200,-70500,89000"
-st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
-"
+xt "-103000,93000,-70500,93800"
+st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
 )
 )
@@ -617,7 +621,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,52600,-63000,53400"
-st "wiz_reset              : std_logic                                    := '1'
-"
+xt "-103000,53400,-63000,54200"
+st "wiz_reset              : std_logic                                    := '1'"
 )
 )
@@ -636,7 +639,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,50200,-74500,51000"
-st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
-"
+xt "-103000,51000,-74500,51800"
+st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
 )
 )
@@ -655,7 +657,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,55000,-74000,55800"
-st "wiz_data               : std_logic_vector(15 DOWNTO 0)
-"
+xt "-103000,55800,-74000,56600"
+st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
 )
 )
@@ -674,7 +675,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,51000,-63000,51800"
-st "wiz_cs                 : std_logic                                    := '1'
-"
+xt "-103000,51800,-63000,52600"
+st "wiz_cs                 : std_logic                                    := '1'"
 )
 )
@@ -693,7 +693,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,53400,-63000,54200"
-st "wiz_wr                 : std_logic                                    := '1'
-"
+xt "-103000,54200,-63000,55000"
+st "wiz_wr                 : std_logic                                    := '1'"
 )
 )
@@ -712,7 +711,6 @@
 font "Courier New,8,0"
 )
-xt "-103000,51800,-63000,52600"
-st "wiz_rd                 : std_logic                                    := '1'
-"
+xt "-103000,52600,-63000,53400"
+st "wiz_rd                 : std_logic                                    := '1'"
 )
 )
@@ -731,6 +729,5 @@
 )
 xt "-103000,26200,-84500,27000"
-st "wiz_int                : std_logic
-"
+st "wiz_int                : std_logic"
 )
 )
@@ -748,5 +745,5 @@
 sl 0
 ro 270
-xt "153500,51625,155000,52375"
+xt "154500,51625,156000,52375"
 )
 (Line
@@ -754,8 +751,8 @@
 sl 0
 ro 270
-xt "153000,52000,153500,52000"
-pts [
-"153000,52000"
-"153500,52000"
+xt "154000,52000,154500,52000"
+pts [
+"154000,52000"
+"154500,52000"
 ]
 )
@@ -771,7 +768,7 @@
 va (VaSet
 )
-xt "156000,51500,159600,52500"
+xt "157000,51500,160600,52500"
 st "wiz_reset"
-blo "156000,52300"
+blo "157000,52300"
 tm "WireNameMgr"
 )
@@ -791,5 +788,5 @@
 sl 0
 ro 270
-xt "153500,59625,155000,60375"
+xt "154500,59625,156000,60375"
 )
 (Line
@@ -797,8 +794,8 @@
 sl 0
 ro 270
-xt "153000,60000,153500,60000"
-pts [
-"153000,60000"
-"153500,60000"
+xt "154000,60000,154500,60000"
+pts [
+"154000,60000"
+"154500,60000"
 ]
 )
@@ -814,7 +811,7 @@
 va (VaSet
 )
-xt "156000,59500,162000,60500"
+xt "157000,59500,163000,60500"
 st "wiz_addr : (9:0)"
-blo "156000,60300"
+blo "157000,60300"
 tm "WireNameMgr"
 )
@@ -833,13 +830,13 @@
 uid 468,0
 sl 0
-xt "153500,60625,155000,61375"
+xt "154500,60625,156000,61375"
 )
 (Line
 uid 469,0
 sl 0
-xt "153000,61000,153500,61000"
-pts [
-"153000,61000"
-"153500,61000"
+xt "154000,61000,154500,61000"
+pts [
+"154000,61000"
+"154500,61000"
 ]
 )
@@ -855,7 +852,7 @@
 va (VaSet
 )
-xt "156000,60500,162300,61500"
+xt "157000,60500,163300,61500"
 st "wiz_data : (15:0)"
-blo "156000,61300"
+blo "157000,61300"
 tm "WireNameMgr"
 )
@@ -875,5 +872,5 @@
 sl 0
 ro 270
-xt "153500,52625,155000,53375"
+xt "154500,52625,156000,53375"
 )
 (Line
@@ -881,8 +878,8 @@
 sl 0
 ro 270
-xt "153000,53000,153500,53000"
-pts [
-"153000,53000"
-"153500,53000"
+xt "154000,53000,154500,53000"
+pts [
+"154000,53000"
+"154500,53000"
 ]
 )
@@ -899,7 +896,7 @@
 va (VaSet
 )
-xt "156000,52500,158700,53500"
+xt "157000,52500,159700,53500"
 st "wiz_cs"
-blo "156000,53300"
+blo "157000,53300"
 tm "WireNameMgr"
 )
@@ -919,5 +916,5 @@
 sl 0
 ro 270
-xt "153500,53625,155000,54375"
+xt "154500,53625,156000,54375"
 )
 (Line
@@ -925,8 +922,8 @@
 sl 0
 ro 270
-xt "153000,54000,153500,54000"
-pts [
-"153000,54000"
-"153500,54000"
+xt "154000,54000,154500,54000"
+pts [
+"154000,54000"
+"154500,54000"
 ]
 )
@@ -943,7 +940,7 @@
 va (VaSet
 )
-xt "156000,53500,158700,54500"
+xt "157000,53500,159700,54500"
 st "wiz_wr"
-blo "156000,54300"
+blo "157000,54300"
 tm "WireNameMgr"
 )
@@ -963,5 +960,5 @@
 sl 0
 ro 270
-xt "153500,70625,155000,71375"
+xt "154500,70625,156000,71375"
 )
 (Line
@@ -969,8 +966,8 @@
 sl 0
 ro 270
-xt "153000,71000,153500,71000"
-pts [
-"153000,71000"
-"153500,71000"
+xt "154000,71000,154500,71000"
+pts [
+"154000,71000"
+"154500,71000"
 ]
 )
@@ -986,7 +983,7 @@
 va (VaSet
 )
-xt "156000,70500,160000,71500"
+xt "157000,70500,161000,71500"
 st "led : (7:0)"
-blo "156000,71300"
+blo "157000,71300"
 tm "WireNameMgr"
 )
@@ -1006,5 +1003,5 @@
 sl 0
 ro 270
-xt "153500,54625,155000,55375"
+xt "154500,54625,156000,55375"
 )
 (Line
@@ -1012,8 +1009,8 @@
 sl 0
 ro 270
-xt "153000,55000,153500,55000"
-pts [
-"153000,55000"
-"153500,55000"
+xt "154000,55000,154500,55000"
+pts [
+"154000,55000"
+"154500,55000"
 ]
 )
@@ -1030,7 +1027,7 @@
 va (VaSet
 )
-xt "156000,54500,158600,55500"
+xt "157000,54500,159600,55500"
 st "wiz_rd"
-blo "156000,55300"
+blo "157000,55300"
 tm "WireNameMgr"
 )
@@ -1050,5 +1047,5 @@
 sl 0
 ro 90
-xt "153500,55625,155000,56375"
+xt "154500,55625,156000,56375"
 )
 (Line
@@ -1056,8 +1053,8 @@
 sl 0
 ro 90
-xt "153000,56000,153500,56000"
-pts [
-"153500,56000"
-"153000,56000"
+xt "154000,56000,154500,56000"
+pts [
+"154500,56000"
+"154000,56000"
 ]
 )
@@ -1074,7 +1071,7 @@
 va (VaSet
 )
-xt "156000,55500,158700,56500"
+xt "157000,55500,159700,56500"
 st "wiz_int"
-blo "156000,56300"
+blo "157000,56300"
 tm "WireNameMgr"
 )
@@ -1113,4 +1110,5 @@
 n "clk"
 t "std_logic"
+prec "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');"
 preAdd 0
 posAdd 0
@@ -1308,5 +1306,5 @@
 preAdd 0
 posAdd 0
-o 23
+o 24
 suid 9,0
 )
@@ -1345,5 +1343,5 @@
 preAdd 0
 posAdd 0
-o 25
+o 26
 suid 10,0
 )
@@ -1381,5 +1379,5 @@
 preAdd 0
 posAdd 0
-o 26
+o 27
 suid 11,0
 )
@@ -1416,5 +1414,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 24
+o 25
 suid 12,0
 )
@@ -1487,4 +1485,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 7
 suid 17,0
@@ -1523,5 +1522,5 @@
 n "roi_max"
 t "roi_max_type"
-o 18
+o 19
 suid 18,0
 )
@@ -1558,5 +1557,5 @@
 n "roi_array"
 t "roi_array_type"
-o 17
+o 18
 suid 19,0
 )
@@ -1594,5 +1593,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 22
+o 23
 suid 20,0
 )
@@ -1680,5 +1679,5 @@
 fg "0,65535,0"
 )
-xt "18250,56625,19000,57375"
+xt "18250,63625,19000,64375"
 )
 tg (CPTG
@@ -1690,7 +1689,7 @@
 va (VaSet
 )
-xt "20000,56500,28500,57500"
+xt "20000,63500,28500,64500"
 st "drs_channel_id : (3:0)"
-blo "20000,57300"
+blo "20000,64300"
 )
 )
@@ -1844,5 +1843,5 @@
 n "drs_read_s_cell_ready"
 t "std_logic"
-o 38
+o 42
 suid 34,0
 )
@@ -1878,5 +1877,5 @@
 n "drs_s_cell_array"
 t "drs_s_cell_array_type"
-o 39
+o 43
 suid 35,0
 )
@@ -1947,5 +1946,5 @@
 n "config_ready_cm"
 t "std_logic"
-o 12
+o 13
 suid 39,0
 )
@@ -1983,5 +1982,8 @@
 n "config_start_cm"
 t "std_logic"
-o 9
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
 suid 40,0
 i "'0'"
@@ -1990,39 +1992,4 @@
 )
 *48 (CptPort
-uid 5271,0
-ps "OnEdgeStrategy"
-shape (Triangle
-uid 5272,0
-ro 270
-va (VaSet
-vasetType 1
-fg "0,65535,0"
-)
-xt "40000,52625,40750,53375"
-)
-tg (CPTG
-uid 5273,0
-ps "CptPortTextPlaceStrategy"
-stg "RightVerticalLayoutStrategy"
-f (Text
-uid 5274,0
-va (VaSet
-)
-xt "35400,52500,39000,53500"
-st "s_trigger"
-ju 2
-blo "39000,53300"
-)
-)
-thePort (LogicalPort
-decl (Decl
-n "s_trigger"
-t "std_logic"
-o 27
-suid 41,0
-)
-)
-)
-*49 (CptPort
 uid 5392,0
 ps "OnEdgeStrategy"
@@ -2054,10 +2021,10 @@
 n "config_ready_mm"
 t "std_logic"
-o 11
+o 12
 suid 42,0
 )
 )
 )
-*50 (CptPort
+*49 (CptPort
 uid 5396,0
 ps "OnEdgeStrategy"
@@ -2089,10 +2056,10 @@
 n "config_ready_spi"
 t "std_logic"
-o 13
+o 14
 suid 43,0
 )
 )
 )
-*51 (CptPort
+*50 (CptPort
 uid 5464,0
 ps "OnEdgeStrategy"
@@ -2124,10 +2091,10 @@
 n "sensor_array"
 t "sensor_array_type"
-o 19
+o 20
 suid 44,0
 )
 )
 )
-*52 (CptPort
+*51 (CptPort
 uid 5468,0
 ps "OnEdgeStrategy"
@@ -2159,10 +2126,10 @@
 n "sensor_ready"
 t "std_logic"
-o 20
+o 21
 suid 45,0
 )
 )
 )
-*53 (CptPort
+*52 (CptPort
 uid 5735,0
 ps "OnEdgeStrategy"
@@ -2195,5 +2162,8 @@
 n "config_start_mm"
 t "std_logic"
-o 8
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
 suid 46,0
 i "'0'"
@@ -2201,5 +2171,5 @@
 )
 )
-*54 (CptPort
+*53 (CptPort
 uid 5739,0
 ps "OnEdgeStrategy"
@@ -2232,5 +2202,7 @@
 n "config_start_spi"
 t "std_logic"
-o 10
+prec "-- --"
+preAdd 0
+o 11
 suid 47,0
 i "'0'"
@@ -2238,5 +2210,5 @@
 )
 )
-*55 (CptPort
+*54 (CptPort
 uid 5916,0
 ps "OnEdgeStrategy"
@@ -2275,5 +2247,5 @@
 )
 )
-*56 (CptPort
+*55 (CptPort
 uid 5920,0
 ps "OnEdgeStrategy"
@@ -2305,4 +2277,6 @@
 n "new_config"
 t "std_logic"
+prec "--      s_trigger      : in std_logic;"
+preAdd 0
 o 28
 suid 49,0
@@ -2310,5 +2284,5 @@
 )
 )
-*57 (CptPort
+*56 (CptPort
 uid 5974,0
 ps "OnEdgeStrategy"
@@ -2340,10 +2314,10 @@
 n "config_started_cm"
 t "std_logic"
-o 15
+o 16
 suid 50,0
 )
 )
 )
-*58 (CptPort
+*57 (CptPort
 uid 5978,0
 ps "OnEdgeStrategy"
@@ -2375,10 +2349,10 @@
 n "config_started_mm"
 t "std_logic"
-o 14
+o 15
 suid 51,0
 )
 )
 )
-*59 (CptPort
+*58 (CptPort
 uid 5982,0
 ps "OnEdgeStrategy"
@@ -2410,10 +2384,10 @@
 n "config_started_spi"
 t "std_logic"
-o 16
+o 17
 suid 52,0
 )
 )
 )
-*60 (CptPort
+*59 (CptPort
 uid 6060,0
 ps "OnEdgeStrategy"
@@ -2445,10 +2419,10 @@
 n "dac_array"
 t "dac_array_type"
-o 21
+o 22
 suid 53,0
 )
 )
 )
-*61 (CptPort
+*60 (CptPort
 uid 9000,0
 ps "OnEdgeStrategy"
@@ -2483,4 +2457,183 @@
 suid 54,0
 i "'0'"
+)
+)
+)
+*61 (CptPort
+uid 10244,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10245,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,56625,19000,57375"
+)
+tg (CPTG
+uid 10246,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10247,0
+va (VaSet
+)
+xt "20000,56500,28000,57500"
+st "drs_srin_data : (7:0)"
+blo "20000,57300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_data"
+t "std_logic_vector"
+b "(7 downto 0)"
+o 40
+suid 56,0
+i "(others => '0')"
+)
+)
+)
+*62 (CptPort
+uid 10248,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10249,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,53625,19000,54375"
+)
+tg (CPTG
+uid 10250,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10251,0
+va (VaSet
+)
+xt "20000,53500,26800,54500"
+st "drs_srin_write_8b"
+blo "20000,54300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_write_8b"
+t "std_logic"
+o 38
+suid 57,0
+i "'0'"
+)
+)
+)
+*63 (CptPort
+uid 10252,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10253,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,54625,19000,55375"
+)
+tg (CPTG
+uid 10254,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10255,0
+va (VaSet
+)
+xt "20000,54500,27100,55500"
+st "drs_srin_write_ack"
+blo "20000,55300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_srin_write_ack"
+t "std_logic"
+o 39
+suid 58,0
+)
+)
+)
+*64 (CptPort
+uid 10256,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10257,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "18250,55625,19000,56375"
+)
+tg (CPTG
+uid 10258,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10259,0
+va (VaSet
+)
+xt "20000,55500,28200,56500"
+st "drs_srin_write_ready"
+blo "20000,56300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_srin_write_ready"
+t "std_logic"
+o 41
+suid 59,0
+)
+)
+)
+*65 (CptPort
+uid 10260,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10261,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "40000,65625,40750,66375"
+)
+tg (CPTG
+uid 10262,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10263,0
+va (VaSet
+)
+xt "31200,65500,39000,66500"
+st "ram_write_ready_ack"
+ju 2
+blo "39000,66300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 8
+suid 60,0
 )
 )
@@ -2503,5 +2656,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*62 (Text
+*66 (Text
 uid 1402,0
 va (VaSet
@@ -2513,5 +2666,5 @@
 tm "BdLibraryNameMgr"
 )
-*63 (Text
+*67 (Text
 uid 1403,0
 va (VaSet
@@ -2523,5 +2676,5 @@
 tm "CptNameMgr"
 )
-*64 (Text
+*68 (Text
 uid 1404,0
 va (VaSet
@@ -2576,5 +2729,5 @@
 archFileType "UNKNOWN"
 )
-*65 (Net
+*69 (Net
 uid 1409,0
 decl (Decl
@@ -2593,9 +2746,8 @@
 )
 xt "-103000,23800,-74500,24600"
-st "board_id               : std_logic_vector(3 downto 0)
-"
-)
-)
-*66 (Net
+st "board_id               : std_logic_vector(3 downto 0)"
+)
+)
+*70 (Net
 uid 1423,0
 decl (Decl
@@ -2613,9 +2765,8 @@
 )
 xt "-103000,25400,-84500,26200"
-st "trigger                : std_logic
-"
-)
-)
-*67 (PortIoIn
+st "trigger                : std_logic"
+)
+)
+*71 (PortIoIn
 uid 1443,0
 shape (CompositeShape
@@ -2630,5 +2781,5 @@
 sl 0
 ro 270
-xt "-28000,68625,-26500,69375"
+xt "-34000,69625,-32500,70375"
 )
 (Line
@@ -2636,8 +2787,8 @@
 sl 0
 ro 270
-xt "-26500,69000,-26000,69000"
-pts [
-"-26500,69000"
-"-26000,69000"
+xt "-32500,70000,-32000,70000"
+pts [
+"-32500,70000"
+"-32000,70000"
 ]
 )
@@ -2654,16 +2805,16 @@
 va (VaSet
 )
-xt "-31800,68500,-29000,69500"
+xt "-36800,69500,-34000,70500"
 st "trigger"
 ju 2
-blo "-29000,69300"
+blo "-34000,70300"
 tm "WireNameMgr"
 )
 )
 )
-*68 (SaComponent
+*72 (SaComponent
 uid 1606,0
 optionalChildren [
-*69 (CptPort
+*73 (CptPort
 uid 1542,0
 ps "OnEdgeStrategy"
@@ -2675,5 +2826,5 @@
 fg "0,65535,0"
 )
-xt "126250,51625,127000,52375"
+xt "127250,51625,128000,52375"
 )
 tg (CPTG
@@ -2685,7 +2836,7 @@
 va (VaSet
 )
-xt "128000,51500,129300,52500"
+xt "129000,51500,130300,52500"
 st "clk"
-blo "128000,52300"
+blo "129000,52300"
 )
 )
@@ -2701,5 +2852,5 @@
 )
 )
-*70 (CptPort
+*74 (CptPort
 uid 1546,0
 ps "OnEdgeStrategy"
@@ -2711,5 +2862,5 @@
 fg "0,65535,0"
 )
-xt "148000,51625,148750,52375"
+xt "149000,51625,149750,52375"
 )
 tg (CPTG
@@ -2721,8 +2872,8 @@
 va (VaSet
 )
-xt "143400,51500,147000,52500"
+xt "144400,51500,148000,52500"
 st "wiz_reset"
 ju 2
-blo "147000,52300"
+blo "148000,52300"
 )
 )
@@ -2740,5 +2891,5 @@
 )
 )
-*71 (CptPort
+*75 (CptPort
 uid 1550,0
 ps "OnEdgeStrategy"
@@ -2750,5 +2901,5 @@
 fg "0,65535,0"
 )
-xt "148000,59625,148750,60375"
+xt "149000,59625,149750,60375"
 )
 tg (CPTG
@@ -2760,8 +2911,8 @@
 va (VaSet
 )
-xt "142500,59500,147000,60500"
+xt "143500,59500,148000,60500"
 st "addr : (9:0)"
 ju 2
-blo "147000,60300"
+blo "148000,60300"
 )
 )
@@ -2779,5 +2930,5 @@
 )
 )
-*72 (CptPort
+*76 (CptPort
 uid 1554,0
 ps "OnEdgeStrategy"
@@ -2789,5 +2940,5 @@
 fg "0,65535,0"
 )
-xt "148000,60625,148750,61375"
+xt "149000,60625,149750,61375"
 )
 tg (CPTG
@@ -2799,8 +2950,8 @@
 va (VaSet
 )
-xt "142200,60500,147000,61500"
+xt "143200,60500,148000,61500"
 st "data : (15:0)"
 ju 2
-blo "147000,61300"
+blo "148000,61300"
 )
 )
@@ -2818,5 +2969,5 @@
 )
 )
-*73 (CptPort
+*77 (CptPort
 uid 1558,0
 ps "OnEdgeStrategy"
@@ -2828,5 +2979,5 @@
 fg "0,65535,0"
 )
-xt "148000,52625,148750,53375"
+xt "149000,52625,149750,53375"
 )
 tg (CPTG
@@ -2838,8 +2989,8 @@
 va (VaSet
 )
-xt "145800,52500,147000,53500"
+xt "146800,52500,148000,53500"
 st "cs"
 ju 2
-blo "147000,53300"
+blo "148000,53300"
 )
 )
@@ -2857,5 +3008,5 @@
 )
 )
-*74 (CptPort
+*78 (CptPort
 uid 1562,0
 ps "OnEdgeStrategy"
@@ -2867,5 +3018,5 @@
 fg "0,65535,0"
 )
-xt "148000,53625,148750,54375"
+xt "149000,53625,149750,54375"
 )
 tg (CPTG
@@ -2877,8 +3028,8 @@
 va (VaSet
 )
-xt "145800,53500,147000,54500"
+xt "146800,53500,148000,54500"
 st "wr"
 ju 2
-blo "147000,54300"
+blo "148000,54300"
 )
 )
@@ -2896,5 +3047,5 @@
 )
 )
-*75 (CptPort
+*79 (CptPort
 uid 1570,0
 ps "OnEdgeStrategy"
@@ -2906,5 +3057,5 @@
 fg "0,65535,0"
 )
-xt "148000,54625,148750,55375"
+xt "149000,54625,149750,55375"
 )
 tg (CPTG
@@ -2916,8 +3067,8 @@
 va (VaSet
 )
-xt "145900,54500,147000,55500"
+xt "146900,54500,148000,55500"
 st "rd"
 ju 2
-blo "147000,55300"
+blo "148000,55300"
 )
 )
@@ -2935,5 +3086,5 @@
 )
 )
-*76 (CptPort
+*80 (CptPort
 uid 1574,0
 ps "OnEdgeStrategy"
@@ -2945,5 +3096,5 @@
 fg "0,65535,0"
 )
-xt "148000,55625,148750,56375"
+xt "149000,55625,149750,56375"
 )
 tg (CPTG
@@ -2955,8 +3106,8 @@
 va (VaSet
 )
-xt "145800,55500,147000,56500"
+xt "146800,55500,148000,56500"
 st "int"
 ju 2
-blo "147000,56300"
+blo "148000,56300"
 )
 )
@@ -2972,5 +3123,5 @@
 )
 )
-*77 (CptPort
+*81 (CptPort
 uid 1578,0
 ps "OnEdgeStrategy"
@@ -2982,5 +3133,5 @@
 fg "0,65535,0"
 )
-xt "126250,69625,127000,70375"
+xt "127250,69625,128000,70375"
 )
 tg (CPTG
@@ -2992,7 +3143,7 @@
 va (VaSet
 )
-xt "128000,69500,135900,70500"
+xt "129000,69500,136900,70500"
 st "write_length : (16:0)"
-blo "128000,70300"
+blo "129000,70300"
 )
 )
@@ -3009,5 +3160,5 @@
 )
 )
-*78 (CptPort
+*82 (CptPort
 uid 1582,0
 ps "OnEdgeStrategy"
@@ -3019,5 +3170,5 @@
 fg "0,65535,0"
 )
-xt "126250,70625,127000,71375"
+xt "127250,70625,128000,71375"
 )
 tg (CPTG
@@ -3029,7 +3180,7 @@
 va (VaSet
 )
-xt "128000,70500,144300,71500"
+xt "129000,70500,145300,71500"
 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
-blo "128000,71300"
+blo "129000,71300"
 )
 )
@@ -3046,5 +3197,5 @@
 )
 )
-*79 (CptPort
+*83 (CptPort
 uid 1586,0
 ps "OnEdgeStrategy"
@@ -3056,5 +3207,5 @@
 fg "0,65535,0"
 )
-xt "126250,54625,127000,55375"
+xt "127250,54625,128000,55375"
 )
 tg (CPTG
@@ -3066,7 +3217,7 @@
 va (VaSet
 )
-xt "128000,54500,134500,55500"
+xt "129000,54500,135500,55500"
 st "ram_data : (15:0)"
-blo "128000,55300"
+blo "129000,55300"
 )
 )
@@ -3083,5 +3234,5 @@
 )
 )
-*80 (CptPort
+*84 (CptPort
 uid 1590,0
 ps "OnEdgeStrategy"
@@ -3093,5 +3244,5 @@
 fg "0,65535,0"
 )
-xt "126250,53625,127000,54375"
+xt "127250,53625,128000,54375"
 )
 tg (CPTG
@@ -3103,7 +3254,7 @@
 va (VaSet
 )
-xt "128000,53500,142400,54500"
+xt "129000,53500,143400,54500"
 st "ram_addr : (RAM_ADDR_WIDTH-1:0)"
-blo "128000,54300"
+blo "129000,54300"
 )
 )
@@ -3121,5 +3272,5 @@
 )
 )
-*81 (CptPort
+*85 (CptPort
 uid 1594,0
 ps "OnEdgeStrategy"
@@ -3131,5 +3282,5 @@
 fg "0,65535,0"
 )
-xt "126250,68625,127000,69375"
+xt "127250,68625,128000,69375"
 )
 tg (CPTG
@@ -3141,7 +3292,7 @@
 va (VaSet
 )
-xt "128000,68500,132100,69500"
+xt "129000,68500,133100,69500"
 st "data_valid"
-blo "128000,69300"
+blo "129000,69300"
 )
 )
@@ -3157,5 +3308,5 @@
 )
 )
-*82 (CptPort
+*86 (CptPort
 uid 1598,0
 ps "OnEdgeStrategy"
@@ -3167,5 +3318,5 @@
 fg "0,65535,0"
 )
-xt "126250,67625,127000,68375"
+xt "127250,67625,128000,68375"
 )
 tg (CPTG
@@ -3177,7 +3328,7 @@
 va (VaSet
 )
-xt "128000,67500,129900,68500"
+xt "129000,67500,130900,68500"
 st "busy"
-blo "128000,68300"
+blo "129000,68300"
 )
 )
@@ -3195,5 +3346,5 @@
 )
 )
-*83 (CptPort
+*87 (CptPort
 uid 2218,0
 ps "OnEdgeStrategy"
@@ -3205,5 +3356,5 @@
 fg "0,65535,0"
 )
-xt "126250,71625,127000,72375"
+xt "127250,71625,128000,72375"
 )
 tg (CPTG
@@ -3215,7 +3366,7 @@
 va (VaSet
 )
-xt "128000,71500,135800,72500"
+xt "129000,71500,136800,72500"
 st "fifo_channels : (3:0)"
-blo "128000,72300"
+blo "129000,72300"
 )
 )
@@ -3230,5 +3381,5 @@
 )
 )
-*84 (CptPort
+*88 (CptPort
 uid 2222,0
 ps "OnEdgeStrategy"
@@ -3240,5 +3391,5 @@
 fg "0,65535,0"
 )
-xt "126250,72625,127000,73375"
+xt "127250,72625,128000,73375"
 )
 tg (CPTG
@@ -3250,7 +3401,7 @@
 va (VaSet
 )
-xt "128000,72500,133700,73500"
+xt "129000,72500,134700,73500"
 st "write_end_flag"
-blo "128000,73300"
+blo "129000,73300"
 )
 )
@@ -3264,5 +3415,5 @@
 )
 )
-*85 (CptPort
+*89 (CptPort
 uid 2226,0
 ps "OnEdgeStrategy"
@@ -3274,5 +3425,5 @@
 fg "0,65535,0"
 )
-xt "126250,73625,127000,74375"
+xt "127250,73625,128000,74375"
 )
 tg (CPTG
@@ -3284,7 +3435,7 @@
 va (VaSet
 )
-xt "128000,73500,134800,74500"
+xt "129000,73500,135800,74500"
 st "write_header_flag"
-blo "128000,74300"
+blo "129000,74300"
 )
 )
@@ -3298,5 +3449,5 @@
 )
 )
-*86 (CptPort
+*90 (CptPort
 uid 5216,0
 ps "OnEdgeStrategy"
@@ -3308,5 +3459,5 @@
 fg "0,65535,0"
 )
-xt "148000,70625,148750,71375"
+xt "149000,70625,149750,71375"
 )
 tg (CPTG
@@ -3318,8 +3469,8 @@
 va (VaSet
 )
-xt "143000,70500,147000,71500"
+xt "144000,70500,148000,71500"
 st "led : (7:0)"
 ju 2
-blo "147000,71300"
+blo "148000,71300"
 )
 )
@@ -3337,5 +3488,5 @@
 )
 )
-*87 (CptPort
+*91 (CptPort
 uid 5275,0
 ps "OnEdgeStrategy"
@@ -3347,5 +3498,5 @@
 fg "0,65535,0"
 )
-xt "126250,58625,127000,59375"
+xt "127250,63625,128000,64375"
 )
 tg (CPTG
@@ -3357,7 +3508,7 @@
 va (VaSet
 )
-xt "128000,58500,131600,59500"
+xt "129000,63500,132600,64500"
 st "s_trigger"
-blo "128000,59300"
+blo "129000,64300"
 )
 )
@@ -3373,5 +3524,5 @@
 )
 )
-*88 (CptPort
+*92 (CptPort
 uid 5924,0
 ps "OnEdgeStrategy"
@@ -3383,5 +3534,5 @@
 fg "0,65535,0"
 )
-xt "126250,78625,127000,79375"
+xt "127250,78625,128000,79375"
 )
 tg (CPTG
@@ -3393,7 +3544,7 @@
 va (VaSet
 )
-xt "128000,78500,135000,79500"
+xt "129000,78500,136000,79500"
 st "config_addr : (7:0)"
-blo "128000,79300"
+blo "129000,79300"
 )
 )
@@ -3409,5 +3560,5 @@
 )
 )
-*89 (CptPort
+*93 (CptPort
 uid 5928,0
 ps "OnEdgeStrategy"
@@ -3419,5 +3570,5 @@
 fg "0,65535,0"
 )
-xt "126250,83625,127000,84375"
+xt "127250,83625,128000,84375"
 )
 tg (CPTG
@@ -3429,7 +3580,7 @@
 va (VaSet
 )
-xt "128000,83500,132800,84500"
+xt "129000,83500,133800,84500"
 st "config_busy"
-blo "128000,84300"
+blo "129000,84300"
 )
 )
@@ -3438,10 +3589,12 @@
 n "config_busy"
 t "std_logic"
-o 27
+prec "-- --"
+preAdd 0
+o 29
 suid 25,0
 )
 )
 )
-*90 (CptPort
+*94 (CptPort
 uid 5932,0
 ps "OnEdgeStrategy"
@@ -3453,5 +3606,5 @@
 fg "0,65535,0"
 )
-xt "126250,79625,127000,80375"
+xt "127250,79625,128000,80375"
 )
 tg (CPTG
@@ -3463,7 +3616,7 @@
 va (VaSet
 )
-xt "128000,79500,135700,80500"
+xt "129000,79500,136700,80500"
 st "config_data : (15:0)"
-blo "128000,80300"
+blo "129000,80300"
 )
 )
@@ -3480,5 +3633,5 @@
 )
 )
-*91 (CptPort
+*95 (CptPort
 uid 5936,0
 ps "OnEdgeStrategy"
@@ -3490,5 +3643,5 @@
 fg "0,65535,0"
 )
-xt "126250,60625,127000,61375"
+xt "127250,60625,128000,61375"
 )
 tg (CPTG
@@ -3500,7 +3653,7 @@
 va (VaSet
 )
-xt "128000,60500,133600,61500"
+xt "129000,60500,134600,61500"
 st "config_started"
-blo "128000,61300"
+blo "129000,61300"
 )
 )
@@ -3514,5 +3667,5 @@
 )
 )
-*92 (CptPort
+*96 (CptPort
 uid 5940,0
 ps "OnEdgeStrategy"
@@ -3524,5 +3677,5 @@
 fg "0,65535,0"
 )
-xt "126250,81625,127000,82375"
+xt "127250,81625,128000,82375"
 )
 tg (CPTG
@@ -3534,7 +3687,7 @@
 va (VaSet
 )
-xt "128000,81500,133300,82500"
+xt "129000,81500,134300,82500"
 st "config_wr_en"
-blo "128000,82300"
+blo "129000,82300"
 )
 )
@@ -3550,5 +3703,5 @@
 )
 )
-*93 (CptPort
+*97 (CptPort
 uid 5944,0
 ps "OnEdgeStrategy"
@@ -3560,5 +3713,5 @@
 fg "0,65535,0"
 )
-xt "126250,59625,127000,60375"
+xt "127250,59625,128000,60375"
 )
 tg (CPTG
@@ -3570,7 +3723,7 @@
 va (VaSet
 )
-xt "128000,59500,132600,60500"
+xt "129000,59500,133600,60500"
 st "new_config"
-blo "128000,60300"
+blo "129000,60300"
 )
 )
@@ -3586,5 +3739,5 @@
 )
 )
-*94 (CptPort
+*98 (CptPort
 uid 5970,0
 ps "OnEdgeStrategy"
@@ -3596,5 +3749,5 @@
 fg "0,65535,0"
 )
-xt "126250,82625,127000,83375"
+xt "127250,82625,128000,83375"
 )
 tg (CPTG
@@ -3606,7 +3759,7 @@
 va (VaSet
 )
-xt "128000,82500,133200,83500"
+xt "129000,82500,134200,83500"
 st "config_rd_en"
-blo "128000,83300"
+blo "129000,83300"
 )
 )
@@ -3616,4 +3769,5 @@
 n "config_rd_en"
 t "std_logic"
+posAdd 0
 o 26
 suid 30,0
@@ -3622,5 +3776,5 @@
 )
 )
-*95 (CptPort
+*99 (CptPort
 uid 6356,0
 ps "OnEdgeStrategy"
@@ -3632,5 +3786,5 @@
 fg "0,65535,0"
 )
-xt "148000,74625,148750,75375"
+xt "149000,74625,149750,75375"
 )
 tg (CPTG
@@ -3642,8 +3796,8 @@
 va (VaSet
 )
-xt "144000,74500,147000,75500"
+xt "145000,74500,148000,75500"
 st "denable"
 ju 2
-blo "147000,75300"
+blo "148000,75300"
 )
 )
@@ -3655,5 +3809,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 28
+o 30
 suid 31,0
 i "'0'"
@@ -3661,5 +3815,5 @@
 )
 )
-*96 (CptPort
+*100 (CptPort
 uid 6446,0
 ps "OnEdgeStrategy"
@@ -3671,5 +3825,5 @@
 fg "0,65535,0"
 )
-xt "148000,75625,148750,76375"
+xt "149000,75625,149750,76375"
 )
 tg (CPTG
@@ -3681,8 +3835,8 @@
 va (VaSet
 )
-xt "141600,75500,147000,76500"
+xt "142600,75500,148000,76500"
 st "dwrite_enable"
 ju 2
-blo "147000,76300"
+blo "148000,76300"
 )
 )
@@ -3695,5 +3849,5 @@
 preAdd 0
 posAdd 0
-o 29
+o 31
 suid 32,0
 i "'0'"
@@ -3701,5 +3855,5 @@
 )
 )
-*97 (CptPort
+*101 (CptPort
 uid 8406,0
 ps "OnEdgeStrategy"
@@ -3711,5 +3865,5 @@
 fg "0,65535,0"
 )
-xt "126250,74625,127000,75375"
+xt "127250,74625,128000,75375"
 )
 tg (CPTG
@@ -3721,7 +3875,7 @@
 va (VaSet
 )
-xt "128000,74500,133600,75500"
+xt "129000,74500,134600,75500"
 st "data_valid_ack"
-blo "128000,75300"
+blo "129000,75300"
 )
 )
@@ -3737,5 +3891,5 @@
 )
 )
-*98 (CptPort
+*102 (CptPort
 uid 8748,0
 ps "OnEdgeStrategy"
@@ -3747,5 +3901,5 @@
 fg "0,65535,0"
 )
-xt "148000,76625,148750,77375"
+xt "149000,76625,149750,77375"
 )
 tg (CPTG
@@ -3757,8 +3911,8 @@
 va (VaSet
 )
-xt "142300,76500,147000,77500"
+xt "143300,76500,148000,77500"
 st "sclk_enable"
 ju 2
-blo "147000,77300"
+blo "148000,77300"
 )
 )
@@ -3770,5 +3924,5 @@
 eolc "-- default DWRITE HIGH."
 posAdd 0
-o 30
+o 32
 suid 35,0
 i "'1'"
@@ -3776,5 +3930,5 @@
 )
 )
-*99 (CptPort
+*103 (CptPort
 uid 9223,0
 ps "OnEdgeStrategy"
@@ -3786,5 +3940,5 @@
 fg "0,65535,0"
 )
-xt "148000,80625,148750,81375"
+xt "149000,80625,149750,81375"
 )
 tg (CPTG
@@ -3796,8 +3950,8 @@
 va (VaSet
 )
-xt "142100,80500,147000,81500"
+xt "143100,80500,148000,81500"
 st "ps_direction"
 ju 2
-blo "147000,81300"
+blo "148000,81300"
 )
 )
@@ -3809,5 +3963,5 @@
 eolc "-- default phase shift upwards"
 posAdd 0
-o 31
+o 33
 suid 36,0
 i "'1'"
@@ -3815,5 +3969,5 @@
 )
 )
-*100 (CptPort
+*104 (CptPort
 uid 9227,0
 ps "OnEdgeStrategy"
@@ -3825,5 +3979,5 @@
 fg "0,65535,0"
 )
-xt "148000,81625,148750,82375"
+xt "149000,81625,149750,82375"
 )
 tg (CPTG
@@ -3835,8 +3989,8 @@
 va (VaSet
 )
-xt "140000,81500,147000,82500"
+xt "141000,81500,148000,82500"
 st "ps_do_phase_shift"
 ju 2
-blo "147000,82300"
+blo "148000,82300"
 )
 )
@@ -3849,5 +4003,5 @@
 preAdd 0
 posAdd 0
-o 32
+o 34
 suid 37,0
 i "'0'"
@@ -3855,5 +4009,5 @@
 )
 )
-*101 (CptPort
+*105 (CptPort
 uid 9933,0
 ps "OnEdgeStrategy"
@@ -3865,5 +4019,5 @@
 fg "0,65535,0"
 )
-xt "148000,82625,148750,83375"
+xt "149000,82625,149750,83375"
 )
 tg (CPTG
@@ -3875,8 +4029,8 @@
 va (VaSet
 )
-xt "143700,82500,147000,83500"
+xt "144700,82500,148000,83500"
 st "ps_reset"
 ju 2
-blo "147000,83300"
+blo "148000,83300"
 )
 )
@@ -3888,5 +4042,5 @@
 eolc "-- pulse this to reset the variable phase shift"
 posAdd 0
-o 33
+o 35
 suid 38,0
 i "'0'"
@@ -3894,5 +4048,5 @@
 )
 )
-*102 (CptPort
+*106 (CptPort
 uid 9937,0
 ps "OnEdgeStrategy"
@@ -3904,5 +4058,5 @@
 fg "0,65535,0"
 )
-xt "148000,84625,148750,85375"
+xt "149000,84625,149750,85375"
 )
 tg (CPTG
@@ -3914,8 +4068,8 @@
 va (VaSet
 )
-xt "142000,84500,147000,85500"
+xt "143000,84500,148000,85500"
 st "srclk_enable"
 ju 2
-blo "147000,85300"
+blo "148000,85300"
 )
 )
@@ -3927,7 +4081,81 @@
 eolc "-- default SRCLK on."
 posAdd 0
-o 34
+o 36
 suid 39,0
 i "'1'"
+)
+)
+)
+*107 (CptPort
+uid 10212,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10213,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "127250,84625,128000,85375"
+)
+tg (CPTG
+uid 10214,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10215,0
+va (VaSet
+)
+xt "129000,84500,134600,85500"
+st "config_rw_ack"
+blo "129000,85300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 27
+suid 40,0
+)
+)
+)
+*108 (CptPort
+uid 10216,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10217,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "127250,85625,128000,86375"
+)
+tg (CPTG
+uid 10218,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10219,0
+va (VaSet
+)
+xt "129000,85500,135300,86500"
+st "config_rw_ready"
+blo "129000,86300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 28
+suid 41,0
 )
 )
@@ -3942,5 +4170,5 @@
 lineWidth 2
 )
-xt "127000,51000,148000,89000"
+xt "128000,51000,149000,89000"
 )
 oxt "43000,2000,56000,22000"
@@ -3950,32 +4178,32 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*103 (Text
+*109 (Text
 uid 1609,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "126700,87000,132900,88000"
+xt "127700,87000,133900,88000"
 st "FACT_FAD_lib"
-blo "126700,87800"
+blo "127700,87800"
 tm "BdLibraryNameMgr"
 )
-*104 (Text
+*110 (Text
 uid 1610,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "126700,88000,132400,89000"
+xt "127700,88000,133400,89000"
 st "w5300_modul"
-blo "126700,88800"
+blo "127700,88800"
 tm "CptNameMgr"
 )
-*105 (Text
+*111 (Text
 uid 1611,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "126700,89000,133400,90000"
+xt "127700,89000,134400,90000"
 st "I_main_ethernet"
-blo "126700,89800"
+blo "127700,89800"
 tm "InstanceNameMgr"
 )
@@ -3992,5 +4220,5 @@
 font "Courier New,8,0"
 )
-xt "127000,50200,154500,51000"
+xt "128000,50200,155500,51000"
 st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2    ( integer )  "
 )
@@ -4012,5 +4240,5 @@
 fg "49152,49152,49152"
 )
-xt "127250,87250,128750,88750"
+xt "128250,87250,129750,88750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -4023,5 +4251,5 @@
 archFileType "UNKNOWN"
 )
-*106 (Net
+*112 (Net
 uid 1680,0
 decl (Decl
@@ -4038,12 +4266,11 @@
 )
 xt "-103000,24600,-74500,25400"
-st "crate_id               : std_logic_vector(1 downto 0)
-"
-)
-)
-*107 (SaComponent
+st "crate_id               : std_logic_vector(1 downto 0)"
+)
+)
+*113 (SaComponent
 uid 1768,0
 optionalChildren [
-*108 (CptPort
+*114 (CptPort
 uid 1760,0
 ps "OnEdgeStrategy"
@@ -4085,5 +4312,5 @@
 )
 )
-*109 (CptPort
+*115 (CptPort
 uid 1764,0
 ps "OnEdgeStrategy"
@@ -4122,5 +4349,5 @@
 )
 )
-*110 (CptPort
+*116 (CptPort
 uid 6207,0
 ps "OnEdgeStrategy"
@@ -4174,5 +4401,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*111 (Text
+*117 (Text
 uid 1771,0
 va (VaSet
@@ -4184,5 +4411,5 @@
 tm "BdLibraryNameMgr"
 )
-*112 (Text
+*118 (Text
 uid 1772,0
 va (VaSet
@@ -4194,5 +4421,5 @@
 tm "CptNameMgr"
 )
-*113 (Text
+*119 (Text
 uid 1773,0
 va (VaSet
@@ -4242,5 +4469,5 @@
 archFileType "UNKNOWN"
 )
-*114 (Net
+*120 (Net
 uid 1981,0
 lang 2
@@ -4259,10 +4486,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,97800,-70500,98600"
-st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
-"
-)
-)
-*115 (Net
+xt "-103000,106600,-70500,107400"
+st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
+)
+)
+*121 (Net
 uid 2297,0
 decl (Decl
@@ -4280,13 +4506,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,89000,-63000,89800"
-st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
-"
-)
-)
-*116 (SaComponent
+xt "-103000,93800,-63000,94600"
+st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+)
+)
+*122 (SaComponent
 uid 2311,0
 optionalChildren [
-*117 (CptPort
+*123 (CptPort
 uid 2307,0
 ps "OnEdgeStrategy"
@@ -4323,5 +4548,5 @@
 preAdd 0
 posAdd 0
-o 18
+o 19
 suid 1,0
 i "(others => '0')"
@@ -4329,5 +4554,5 @@
 )
 )
-*118 (CptPort
+*124 (CptPort
 uid 2351,0
 ps "OnEdgeStrategy"
@@ -4365,5 +4590,5 @@
 )
 )
-*119 (CptPort
+*125 (CptPort
 uid 2361,0
 ps "OnEdgeStrategy"
@@ -4397,5 +4622,5 @@
 n "config_ready"
 t "std_logic"
-o 6
+o 7
 suid 5,0
 i "'0'"
@@ -4403,5 +4628,5 @@
 )
 )
-*120 (CptPort
+*126 (CptPort
 uid 2365,0
 ps "OnEdgeStrategy"
@@ -4439,5 +4664,5 @@
 )
 )
-*121 (CptPort
+*127 (CptPort
 uid 2369,0
 ps "OnEdgeStrategy"
@@ -4471,5 +4696,5 @@
 n "ram_write_ea"
 t "std_logic"
-o 5
+o 6
 suid 4,0
 i "'0'"
@@ -4477,5 +4702,5 @@
 )
 )
-*122 (CptPort
+*128 (CptPort
 uid 2373,0
 ps "OnEdgeStrategy"
@@ -4508,4 +4733,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 3
 suid 12,0
@@ -4513,5 +4739,5 @@
 )
 )
-*123 (CptPort
+*129 (CptPort
 uid 2377,0
 ps "OnEdgeStrategy"
@@ -4546,5 +4772,5 @@
 t "roi_max_type"
 posAdd 0
-o 8
+o 9
 suid 14,0
 i "(others => conv_std_logic_vector (0, 11))"
@@ -4552,5 +4778,5 @@
 )
 )
-*124 (CptPort
+*130 (CptPort
 uid 2381,0
 ps "OnEdgeStrategy"
@@ -4584,10 +4810,10 @@
 n "wiz_busy"
 t "std_logic"
-o 16
+o 17
 suid 13,0
 )
 )
 )
-*125 (CptPort
+*131 (CptPort
 uid 2385,0
 ps "OnEdgeStrategy"
@@ -4623,5 +4849,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 12
+o 13
 suid 6,0
 i "(others => '0')"
@@ -4629,5 +4855,5 @@
 )
 )
-*126 (CptPort
+*132 (CptPort
 uid 2389,0
 ps "OnEdgeStrategy"
@@ -4664,5 +4890,5 @@
 b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
 preAdd 0
-o 10
+o 11
 suid 7,0
 i "(others => '0')"
@@ -4670,5 +4896,5 @@
 )
 )
-*127 (CptPort
+*133 (CptPort
 uid 2393,0
 ps "OnEdgeStrategy"
@@ -4703,5 +4929,5 @@
 n "wiz_write_ea"
 t "std_logic"
-o 13
+o 14
 suid 8,0
 i "'0'"
@@ -4709,5 +4935,5 @@
 )
 )
-*128 (CptPort
+*134 (CptPort
 uid 2397,0
 ps "OnEdgeStrategy"
@@ -4742,5 +4968,5 @@
 n "wiz_write_end"
 t "std_logic"
-o 15
+o 16
 suid 9,0
 i "'0'"
@@ -4748,5 +4974,5 @@
 )
 )
-*129 (CptPort
+*135 (CptPort
 uid 2401,0
 ps "OnEdgeStrategy"
@@ -4781,5 +5007,5 @@
 n "wiz_write_header"
 t "std_logic"
-o 14
+o 15
 suid 10,0
 i "'0'"
@@ -4787,5 +5013,5 @@
 )
 )
-*130 (CptPort
+*136 (CptPort
 uid 2405,0
 ps "OnEdgeStrategy"
@@ -4821,5 +5047,5 @@
 t "std_logic_vector"
 b "(16 downto 0)"
-o 11
+o 12
 suid 11,0
 i "(others => '0')"
@@ -4827,5 +5053,5 @@
 )
 )
-*131 (CptPort
+*137 (CptPort
 uid 2454,0
 ps "OnEdgeStrategy"
@@ -4858,10 +5084,12 @@
 n "roi_array"
 t "roi_array_type"
-o 4
+prec "-- --"
+preAdd 0
+o 5
 suid 15,0
 )
 )
 )
-*132 (CptPort
+*138 (CptPort
 uid 2628,0
 ps "OnEdgeStrategy"
@@ -4896,5 +5124,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 9
+o 10
 suid 18,0
 i "(others => '0')"
@@ -4902,5 +5130,5 @@
 )
 )
-*133 (CptPort
+*139 (CptPort
 uid 5991,0
 ps "OnEdgeStrategy"
@@ -4934,5 +5162,5 @@
 n "config_started"
 t "std_logic"
-o 7
+o 8
 suid 21,0
 i "'0'"
@@ -4940,5 +5168,5 @@
 )
 )
-*134 (CptPort
+*140 (CptPort
 uid 8410,0
 ps "OnEdgeStrategy"
@@ -4972,6 +5200,47 @@
 n "wiz_ack"
 t "std_logic"
-o 17
+o 18
 suid 22,0
+)
+)
+)
+*141 (CptPort
+uid 10232,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10233,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "71250,72625,72000,73375"
+)
+tg (CPTG
+uid 10234,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10235,0
+va (VaSet
+font "arial,8,0"
+)
+xt "73000,72500,80800,73500"
+st "ram_write_ready_ack"
+blo "73000,73300"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 4
+suid 23,0
+i "'0'"
 )
 )
@@ -4994,5 +5263,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*135 (Text
+*142 (Text
 uid 2314,0
 va (VaSet
@@ -5004,5 +5273,5 @@
 tm "BdLibraryNameMgr"
 )
-*136 (Text
+*143 (Text
 uid 2315,0
 va (VaSet
@@ -5014,5 +5283,5 @@
 tm "CptNameMgr"
 )
-*137 (Text
+*144 (Text
 uid 2316,0
 va (VaSet
@@ -5073,5 +5342,5 @@
 archFileType "UNKNOWN"
 )
-*138 (Net
+*145 (Net
 uid 2468,0
 lang 2
@@ -5087,10 +5356,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,99400,-80500,100200"
-st "SIGNAL wiz_busy               : std_logic
-"
-)
-)
-*139 (Net
+xt "-103000,109000,-80500,109800"
+st "SIGNAL wiz_busy               : std_logic"
+)
+)
+*146 (Net
 uid 2474,0
 lang 2
@@ -5107,10 +5375,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,101800,-59500,102600"
-st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
-"
-)
-)
-*140 (Net
+xt "-103000,111400,-59500,112200"
+st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
+)
+)
+*147 (Net
 uid 2480,0
 lang 2
@@ -5128,10 +5395,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,104200,-53500,105000"
-st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
-"
-)
-)
-*141 (Net
+xt "-103000,113800,-53500,114600"
+st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
+)
+)
+*148 (Net
 uid 2486,0
 lang 2
@@ -5150,10 +5416,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,101000,-53500,101800"
-st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
-"
-)
-)
-*142 (Net
+xt "-103000,110600,-53500,111400"
+st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
+)
+)
+*149 (Net
 uid 2492,0
 lang 2
@@ -5171,10 +5436,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,100200,-53500,101000"
-st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
-"
-)
-)
-*143 (Net
+xt "-103000,109800,-53500,110600"
+st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
+)
+)
+*150 (Net
 uid 2498,0
 lang 2
@@ -5191,10 +5455,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,102600,-59500,103400"
-st "SIGNAL wiz_write_end          : std_logic                                    := '0'
-"
-)
-)
-*144 (Net
+xt "-103000,112200,-59500,113000"
+st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
+)
+)
+*151 (Net
 uid 2504,0
 lang 2
@@ -5211,10 +5474,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,103400,-59500,104200"
-st "SIGNAL wiz_write_header       : std_logic                                    := '0'
-"
-)
-)
-*145 (Net
+xt "-103000,113000,-59500,113800"
+st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
+)
+)
+*152 (Net
 uid 2574,0
 decl (Decl
@@ -5229,10 +5491,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,89800,-80500,90600"
-st "SIGNAL ram_write_ea           : std_logic
-"
-)
-)
-*146 (Net
+xt "-103000,94600,-80500,95400"
+st "SIGNAL ram_write_ea           : std_logic"
+)
+)
+*153 (Net
 uid 2580,0
 decl (Decl
@@ -5248,10 +5509,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,90600,-59500,91400"
-st "SIGNAL ram_write_ready        : std_logic                                    := '0'
-"
-)
-)
-*147 (Net
+xt "-103000,95400,-59500,96200"
+st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
+)
+)
+*154 (Net
 uid 2586,0
 decl (Decl
@@ -5267,10 +5527,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,68200,-59500,69000"
-st "SIGNAL config_start           : std_logic                                    := '0'
-"
-)
-)
-*148 (Net
+xt "-103000,72200,-59500,73000"
+st "SIGNAL config_start           : std_logic                                    := '0'"
+)
+)
+*155 (Net
 uid 2592,0
 decl (Decl
@@ -5285,10 +5544,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,65800,-80500,66600"
-st "SIGNAL config_ready           : std_logic
-"
-)
-)
-*149 (Net
+xt "-103000,66600,-80500,67400"
+st "SIGNAL config_ready           : std_logic"
+)
+)
+*156 (Net
 uid 2598,0
 decl (Decl
@@ -5303,10 +5561,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,92200,-79000,93000"
-st "SIGNAL roi_max                : roi_max_type
-"
-)
-)
-*150 (Net
+xt "-103000,98600,-79000,99400"
+st "SIGNAL roi_max                : roi_max_type"
+)
+)
+*157 (Net
 uid 2640,0
 decl (Decl
@@ -5322,10 +5579,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,84200,-70500,85000"
-st "SIGNAL package_length         : std_logic_vector(15 downto 0)
-"
-)
-)
-*151 (Net
+xt "-103000,89000,-70500,89800"
+st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
+)
+)
+*158 (Net
 uid 2776,0
 decl (Decl
@@ -5341,10 +5597,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,39800,-63000,40600"
-st "adc_oeb                : std_logic                                    := '1'
-"
-)
-)
-*152 (PortIoOut
+xt "-103000,40600,-63000,41400"
+st "adc_oeb                : std_logic                                    := '1'"
+)
+)
+*159 (PortIoOut
 uid 2798,0
 shape (CompositeShape
@@ -5391,5 +5646,5 @@
 )
 )
-*153 (PortIoIn
+*160 (PortIoIn
 uid 2804,0
 shape (CompositeShape
@@ -5436,5 +5691,5 @@
 )
 )
-*154 (Net
+*161 (Net
 uid 2924,0
 decl (Decl
@@ -5449,10 +5704,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,91400,-78000,92200"
-st "SIGNAL roi_array              : roi_array_type
-"
-)
-)
-*155 (PortIoIn
+xt "-103000,97800,-78000,98600"
+st "SIGNAL roi_array              : roi_array_type"
+)
+)
+*162 (PortIoIn
 uid 2950,0
 shape (CompositeShape
@@ -5499,5 +5753,5 @@
 )
 )
-*156 (PortIoIn
+*163 (PortIoIn
 uid 2956,0
 shape (CompositeShape
@@ -5544,8 +5798,8 @@
 )
 )
-*157 (Grouping
+*164 (Grouping
 uid 3137,0
 optionalChildren [
-*158 (CommentText
+*165 (CommentText
 uid 3139,0
 shape (Rectangle
@@ -5565,5 +5819,5 @@
 bg "0,0,32768"
 )
-xt "125200,175000,134900,176000"
+xt "125200,175000,134700,176000"
 st "
 by %user on %dd %month %year
@@ -5578,5 +5832,5 @@
 titleBlock 1
 )
-*159 (CommentText
+*166 (CommentText
 uid 3142,0
 shape (Rectangle
@@ -5609,5 +5863,5 @@
 titleBlock 1
 )
-*160 (CommentText
+*167 (CommentText
 uid 3145,0
 shape (Rectangle
@@ -5640,5 +5894,5 @@
 titleBlock 1
 )
-*161 (CommentText
+*168 (CommentText
 uid 3148,0
 shape (Rectangle
@@ -5671,5 +5925,5 @@
 titleBlock 1
 )
-*162 (CommentText
+*169 (CommentText
 uid 3151,0
 shape (Rectangle
@@ -5701,5 +5955,5 @@
 titleBlock 1
 )
-*163 (CommentText
+*170 (CommentText
 uid 3154,0
 shape (Rectangle
@@ -5732,5 +5986,5 @@
 titleBlock 1
 )
-*164 (CommentText
+*171 (CommentText
 uid 3157,0
 shape (Rectangle
@@ -5764,5 +6018,5 @@
 titleBlock 1
 )
-*165 (CommentText
+*172 (CommentText
 uid 3160,0
 shape (Rectangle
@@ -5795,5 +6049,5 @@
 titleBlock 1
 )
-*166 (CommentText
+*173 (CommentText
 uid 3163,0
 shape (Rectangle
@@ -5826,5 +6080,5 @@
 titleBlock 1
 )
-*167 (CommentText
+*174 (CommentText
 uid 3166,0
 shape (Rectangle
@@ -5870,5 +6124,5 @@
 oxt "14000,66000,55000,71000"
 )
-*168 (Net
+*175 (Net
 uid 3894,0
 decl (Decl
@@ -5884,9 +6138,8 @@
 )
 xt "-103000,29400,-84500,30200"
-st "CLK_25_PS              : std_logic
-"
-)
-)
-*169 (PortIoOut
+st "CLK_25_PS              : std_logic"
+)
+)
+*176 (PortIoOut
 uid 3978,0
 shape (CompositeShape
@@ -5933,5 +6186,5 @@
 )
 )
-*170 (Net
+*177 (Net
 uid 4068,0
 decl (Decl
@@ -5947,9 +6200,8 @@
 )
 xt "-103000,30200,-84500,31000"
-st "CLK_50                 : std_logic
-"
-)
-)
-*171 (Net
+st "CLK_50                 : std_logic"
+)
+)
+*178 (Net
 uid 4204,0
 decl (Decl
@@ -5964,10 +6216,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,57800,-80500,58600"
-st "SIGNAL CLK_25                 : std_logic
-"
-)
-)
-*172 (PortIoOut
+xt "-103000,58600,-80500,59400"
+st "SIGNAL CLK_25                 : std_logic"
+)
+)
+*179 (PortIoOut
 uid 4220,0
 shape (CompositeShape
@@ -6014,5 +6265,5 @@
 )
 )
-*173 (Net
+*180 (Net
 uid 4232,0
 decl (Decl
@@ -6028,9 +6279,8 @@
 )
 xt "-103000,18200,-84500,19000"
-st "CLK                    : std_logic
-"
-)
-)
-*174 (Net
+st "CLK                    : std_logic"
+)
+)
+*181 (Net
 uid 4260,0
 decl (Decl
@@ -6047,9 +6297,8 @@
 )
 xt "-103000,23000,-74500,23800"
-st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*175 (Net
+st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*182 (Net
 uid 4270,0
 decl (Decl
@@ -6065,9 +6314,8 @@
 )
 xt "-103000,22200,-79000,23000"
-st "adc_data_array         : adc_data_array_type
-"
-)
-)
-*176 (PortIoIn
+st "adc_data_array         : adc_data_array_type"
+)
+)
+*183 (PortIoIn
 uid 4307,0
 shape (CompositeShape
@@ -6114,5 +6362,5 @@
 )
 )
-*177 (Net
+*184 (Net
 uid 4399,0
 decl (Decl
@@ -6128,10 +6376,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,78600,-59500,79400"
-st "SIGNAL drs_clk_en             : std_logic                                    := '0'
-"
-)
-)
-*178 (Net
+xt "-103000,82600,-59500,83400"
+st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
+)
+)
+*185 (Net
 uid 4405,0
 decl (Decl
@@ -6146,10 +6393,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,81000,-74500,81800"
-st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
-"
-)
-)
-*179 (Net
+xt "-103000,85000,-74500,85800"
+st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
+)
+)
+*186 (Net
 uid 4417,0
 decl (Decl
@@ -6165,10 +6411,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,79400,-59500,80200"
-st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
-"
-)
-)
-*180 (Net
+xt "-103000,83400,-59500,84200"
+st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
+)
+)
+*187 (Net
 uid 4535,0
 decl (Decl
@@ -6185,10 +6430,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,42200,-57000,43000"
-st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
-"
-)
-)
-*181 (Net
+xt "-103000,43000,-57000,43800"
+st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
+)
+)
+*188 (Net
 uid 4543,0
 decl (Decl
@@ -6204,10 +6448,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,43000,-63000,43800"
-st "drs_dwrite             : std_logic                                    := '1'
-"
-)
-)
-*182 (PortIoOut
+xt "-103000,43800,-63000,44600"
+st "drs_dwrite             : std_logic                                    := '1'"
+)
+)
+*189 (PortIoOut
 uid 4551,0
 shape (CompositeShape
@@ -6254,5 +6497,5 @@
 )
 )
-*183 (PortIoOut
+*190 (PortIoOut
 uid 4557,0
 shape (CompositeShape
@@ -6299,5 +6542,5 @@
 )
 )
-*184 (Net
+*191 (Net
 uid 4669,0
 decl (Decl
@@ -6313,9 +6556,8 @@
 )
 xt "-103000,19000,-84500,19800"
-st "SROUT_in_0             : std_logic
-"
-)
-)
-*185 (Net
+st "SROUT_in_0             : std_logic"
+)
+)
+*192 (Net
 uid 4677,0
 decl (Decl
@@ -6331,9 +6573,8 @@
 )
 xt "-103000,19800,-84500,20600"
-st "SROUT_in_1             : std_logic
-"
-)
-)
-*186 (Net
+st "SROUT_in_1             : std_logic"
+)
+)
+*193 (Net
 uid 4685,0
 decl (Decl
@@ -6349,9 +6590,8 @@
 )
 xt "-103000,20600,-84500,21400"
-st "SROUT_in_2             : std_logic
-"
-)
-)
-*187 (Net
+st "SROUT_in_2             : std_logic"
+)
+)
+*194 (Net
 uid 4693,0
 decl (Decl
@@ -6367,9 +6607,8 @@
 )
 xt "-103000,21400,-84500,22200"
-st "SROUT_in_3             : std_logic
-"
-)
-)
-*188 (PortIoIn
+st "SROUT_in_3             : std_logic"
+)
+)
+*195 (PortIoIn
 uid 4701,0
 shape (CompositeShape
@@ -6416,5 +6655,5 @@
 )
 )
-*189 (PortIoIn
+*196 (PortIoIn
 uid 4707,0
 shape (CompositeShape
@@ -6461,5 +6700,5 @@
 )
 )
-*190 (PortIoIn
+*197 (PortIoIn
 uid 4713,0
 shape (CompositeShape
@@ -6506,5 +6745,5 @@
 )
 )
-*191 (PortIoIn
+*198 (PortIoIn
 uid 4719,0
 shape (CompositeShape
@@ -6551,5 +6790,5 @@
 )
 )
-*192 (Net
+*199 (Net
 uid 4741,0
 decl (Decl
@@ -6564,13 +6803,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,80200,-80500,81000"
-st "SIGNAL drs_read_s_cell_ready  : std_logic
-"
-)
-)
-*193 (SaComponent
+xt "-103000,84200,-80500,85000"
+st "SIGNAL drs_read_s_cell_ready  : std_logic"
+)
+)
+*200 (SaComponent
 uid 4903,0
 optionalChildren [
-*194 (CptPort
+*201 (CptPort
 uid 4867,0
 ps "OnEdgeStrategy"
@@ -6605,5 +6843,5 @@
 )
 )
-*195 (CptPort
+*202 (CptPort
 uid 4871,0
 ps "OnEdgeStrategy"
@@ -6615,5 +6853,5 @@
 fg "0,65535,0"
 )
-xt "1000,52625,1750,53375"
+xt "1000,48625,1750,49375"
 )
 tg (CPTG
@@ -6625,8 +6863,8 @@
 va (VaSet
 )
-xt "-7500,52500,0,53500"
+xt "-7500,48500,0,49500"
 st "start_endless_mode"
 ju 2
-blo "0,53300"
+blo "0,49300"
 )
 )
@@ -6639,5 +6877,5 @@
 )
 )
-*196 (CptPort
+*203 (CptPort
 uid 4875,0
 ps "OnEdgeStrategy"
@@ -6649,5 +6887,5 @@
 fg "0,65535,0"
 )
-xt "1000,49625,1750,50375"
+xt "1000,45625,1750,46375"
 )
 tg (CPTG
@@ -6659,8 +6897,8 @@
 va (VaSet
 )
-xt "-10200,49500,0,50500"
+xt "-10200,45500,0,46500"
 st "start_read_stop_pos_mode"
 ju 2
-blo "0,50300"
+blo "0,46300"
 )
 )
@@ -6673,5 +6911,5 @@
 )
 )
-*197 (CptPort
+*204 (CptPort
 uid 4879,0
 ps "OnEdgeStrategy"
@@ -6706,5 +6944,5 @@
 )
 )
-*198 (CptPort
+*205 (CptPort
 uid 4883,0
 ps "OnEdgeStrategy"
@@ -6739,5 +6977,5 @@
 )
 )
-*199 (CptPort
+*206 (CptPort
 uid 4887,0
 ps "OnEdgeStrategy"
@@ -6772,5 +7010,5 @@
 )
 )
-*200 (CptPort
+*207 (CptPort
 uid 4891,0
 ps "OnEdgeStrategy"
@@ -6805,5 +7043,5 @@
 )
 )
-*201 (CptPort
+*208 (CptPort
 uid 4895,0
 ps "OnEdgeStrategy"
@@ -6815,5 +7053,5 @@
 fg "0,65535,0"
 )
-xt "1000,51625,1750,52375"
+xt "1000,47625,1750,48375"
 )
 tg (CPTG
@@ -6825,8 +7063,8 @@
 va (VaSet
 )
-xt "-3400,51500,0,52500"
+xt "-3400,47500,0,48500"
 st "stop_pos"
 ju 2
-blo "0,52300"
+blo "0,48300"
 )
 )
@@ -6840,5 +7078,5 @@
 )
 )
-*202 (CptPort
+*209 (CptPort
 uid 4899,0
 ps "OnEdgeStrategy"
@@ -6850,5 +7088,5 @@
 fg "0,65535,0"
 )
-xt "1000,50625,1750,51375"
+xt "1000,46625,1750,47375"
 )
 tg (CPTG
@@ -6860,8 +7098,8 @@
 va (VaSet
 )
-xt "-5700,50500,0,51500"
+xt "-5700,46500,0,47500"
 st "stop_pos_valid"
 ju 2
-blo "0,51300"
+blo "0,47300"
 )
 )
@@ -6876,5 +7114,5 @@
 )
 )
-*203 (CptPort
+*210 (CptPort
 uid 4938,0
 ps "OnEdgeStrategy"
@@ -6906,10 +7144,10 @@
 n "RSRLOAD"
 t "std_logic"
-o 10
+o 15
 i "'0'"
 )
 )
 )
-*204 (CptPort
+*211 (CptPort
 uid 4942,0
 ps "OnEdgeStrategy"
@@ -6941,6 +7179,182 @@
 n "SRCLK"
 t "std_logic"
+o 16
+i "'0'"
+)
+)
+)
+*212 (CptPort
+uid 10272,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10273,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,56625,1750,57375"
+)
+tg (CPTG
+uid 10274,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10275,0
+va (VaSet
+)
+xt "-6100,56500,0,57500"
+st "srin_data : (7:0)"
+ju 2
+blo "0,57300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "srin_data"
+t "std_logic_vector"
+b "(7 downto 0)"
+o 13
+)
+)
+)
+*213 (CptPort
+uid 10276,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10277,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-18750,56625,-18000,57375"
+)
+tg (CPTG
+uid 10278,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10279,0
+va (VaSet
+)
+xt "-17000,56500,-13300,57500"
+st "SRIN_out"
+blo "-17000,57300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 14
+i "'0'"
+)
+)
+)
+*214 (CptPort
+uid 10280,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10281,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,54625,1750,55375"
+)
+tg (CPTG
+uid 10282,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10283,0
+va (VaSet
+)
+xt "-5600,54500,0,55500"
+st "srin_write_ack"
+ju 2
+blo "0,55300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "srin_write_ack"
+t "std_logic"
+o 12
+i "'0'"
+)
+)
+)
+*215 (CptPort
+uid 10284,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10285,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,55625,1750,56375"
+)
+tg (CPTG
+uid 10286,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10287,0
+va (VaSet
+)
+xt "-6300,55500,0,56500"
+st "srin_write_ready"
+ju 2
+blo "0,56300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "srin_write_ready"
+t "std_logic"
 o 11
 i "'0'"
+)
+)
+)
+*216 (CptPort
+uid 10288,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10289,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "1000,53625,1750,54375"
+)
+tg (CPTG
+uid 10290,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10291,0
+va (VaSet
+)
+xt "-7200,53500,0,54500"
+st "start_srin_write_8b"
+ju 2
+blo "0,54300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "start_srin_write_8b"
+t "std_logic"
+o 10
 )
 )
@@ -6955,5 +7369,5 @@
 lineWidth 2
 )
-xt "-18000,44000,1000,54000"
+xt "-18000,44000,1000,59000"
 )
 oxt "0,0,8000,10000"
@@ -6963,32 +7377,32 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*205 (Text
+*217 (Text
 uid 4906,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "-17400,54000,-10800,55000"
+xt "-12400,41000,-5800,42000"
 st "FACT_FAD_LIB"
-blo "-17400,54800"
+blo "-12400,41800"
 tm "BdLibraryNameMgr"
 )
-*206 (Text
+*218 (Text
 uid 4907,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "-17400,55000,-12700,56000"
+xt "-12400,42000,-7700,43000"
 st "drs_pulser"
-blo "-17400,55800"
+blo "-12400,42800"
 tm "CptNameMgr"
 )
-*207 (Text
+*219 (Text
 uid 4908,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "-17400,56000,-9900,57000"
+xt "-12400,43000,-4900,44000"
 st "I_main_drs_pulser"
-blo "-17400,56800"
+blo "-12400,43800"
 tm "InstanceNameMgr"
 )
@@ -7019,5 +7433,5 @@
 fg "49152,49152,49152"
 )
-xt "-17750,52250,-16250,53750"
+xt "-17750,57250,-16250,58750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -7030,5 +7444,5 @@
 archFileType "UNKNOWN"
 )
-*208 (Net
+*220 (Net
 uid 4946,0
 decl (Decl
@@ -7045,9 +7459,8 @@
 )
 xt "-103000,37400,-63000,38200"
-st "RSRLOAD                : std_logic                                    := '0'
-"
-)
-)
-*209 (PortIoOut
+st "RSRLOAD                : std_logic                                    := '0'"
+)
+)
+*221 (PortIoOut
 uid 4954,0
 shape (CompositeShape
@@ -7094,5 +7507,5 @@
 )
 )
-*210 (Net
+*222 (Net
 uid 4960,0
 decl (Decl
@@ -7109,9 +7522,8 @@
 )
 xt "-103000,38200,-63000,39000"
-st "SRCLK                  : std_logic                                    := '0'
-"
-)
-)
-*211 (PortIoOut
+st "SRCLK                  : std_logic                                    := '0'"
+)
+)
+*223 (PortIoOut
 uid 4968,0
 shape (CompositeShape
@@ -7158,8 +7570,8 @@
 )
 )
-*212 (SaComponent
+*224 (SaComponent
 uid 5072,0
 optionalChildren [
-*213 (CptPort
+*225 (CptPort
 uid 5028,0
 ps "OnEdgeStrategy"
@@ -7195,5 +7607,5 @@
 )
 )
-*214 (CptPort
+*226 (CptPort
 uid 5032,0
 ps "OnEdgeStrategy"
@@ -7231,5 +7643,5 @@
 )
 )
-*215 (CptPort
+*227 (CptPort
 uid 5036,0
 ps "OnEdgeStrategy"
@@ -7267,5 +7679,5 @@
 )
 )
-*216 (CptPort
+*228 (CptPort
 uid 5040,0
 ps "OnEdgeStrategy"
@@ -7303,5 +7715,5 @@
 )
 )
-*217 (CptPort
+*229 (CptPort
 uid 5044,0
 ps "OnEdgeStrategy"
@@ -7340,5 +7752,5 @@
 )
 )
-*218 (CptPort
+*230 (CptPort
 uid 5048,0
 ps "OnEdgeStrategy"
@@ -7375,5 +7787,5 @@
 )
 )
-*219 (CptPort
+*231 (CptPort
 uid 5052,0
 ps "OnEdgeStrategy"
@@ -7410,5 +7822,5 @@
 )
 )
-*220 (CptPort
+*232 (CptPort
 uid 5056,0
 ps "OnEdgeStrategy"
@@ -7440,10 +7852,10 @@
 n "dac_array"
 t "dac_array_type"
-o 10
+o 12
 suid 8,0
 )
 )
 )
-*221 (CptPort
+*233 (CptPort
 uid 5060,0
 ps "OnEdgeStrategy"
@@ -7480,5 +7892,5 @@
 )
 )
-*222 (CptPort
+*234 (CptPort
 uid 5064,0
 ps "OnEdgeStrategy"
@@ -7514,5 +7926,5 @@
 )
 )
-*223 (CptPort
+*235 (CptPort
 uid 5068,0
 ps "OnEdgeStrategy"
@@ -7549,5 +7961,5 @@
 )
 )
-*224 (CptPort
+*236 (CptPort
 uid 5995,0
 ps "OnEdgeStrategy"
@@ -7579,5 +7991,5 @@
 n "config_started"
 t "std_logic"
-o 9
+o 11
 suid 12,0
 i "'0'"
@@ -7585,9 +7997,9 @@
 )
 )
-*225 (CptPort
-uid 8500,0
+*237 (CptPort
+uid 10184,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 8501,0
+uid 10185,0
 ro 90
 va (VaSet
@@ -7598,13 +8010,13 @@
 )
 tg (CPTG
-uid 8502,0
+uid 10186,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 8503,0
-va (VaSet
-)
-xt "83800,109500,91000,110500"
-st "drs_address : (3:0)"
+uid 10187,0
+va (VaSet
+)
+xt "85400,109500,91000,110500"
+st "config_rw_ack"
 ju 2
 blo "91000,110300"
@@ -7614,17 +8026,20 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 11
-suid 13,0
-)
-)
-)
-*226 (CptPort
-uid 8504,0
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
+suid 15,0
+i "'0'"
+)
+)
+)
+*238 (CptPort
+uid 10188,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 8505,0
+uid 10189,0
 ro 90
 va (VaSet
@@ -7635,13 +8050,13 @@
 )
 tg (CPTG
-uid 8506,0
+uid 10190,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 8507,0
-va (VaSet
-)
-xt "83800,110500,91000,111500"
-st "drs_address_mode"
+uid 10191,0
+va (VaSet
+)
+xt "84700,110500,91000,111500"
+st "config_rw_ready"
 ju 2
 blo "91000,111300"
@@ -7651,8 +8066,12 @@
 m 1
 decl (Decl
-n "drs_address_mode"
-t "std_logic"
-o 12
-suid 14,0
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
+suid 16,0
+i "'0'"
 )
 )
@@ -7675,5 +8094,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*227 (Text
+*239 (Text
 uid 5075,0
 va (VaSet
@@ -7685,5 +8104,5 @@
 tm "BdLibraryNameMgr"
 )
-*228 (Text
+*240 (Text
 uid 5076,0
 va (VaSet
@@ -7695,5 +8114,5 @@
 tm "CptNameMgr"
 )
-*229 (Text
+*241 (Text
 uid 5077,0
 va (VaSet
@@ -7741,5 +8160,5 @@
 archFileType "UNKNOWN"
 )
-*230 (Net
+*242 (Net
 uid 5088,0
 decl (Decl
@@ -7755,10 +8174,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,61800,-71000,62600"
-st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
-"
-)
-)
-*231 (Net
+xt "-103000,62600,-71000,63400"
+st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
+)
+)
+*243 (Net
 uid 5096,0
 decl (Decl
@@ -7773,10 +8191,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,64200,-80500,65000"
-st "SIGNAL config_data_valid      : std_logic
-"
-)
-)
-*232 (Net
+xt "-103000,65000,-80500,65800"
+st "SIGNAL config_data_valid      : std_logic"
+)
+)
+*244 (Net
 uid 5104,0
 decl (Decl
@@ -7791,10 +8208,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,62600,-80500,63400"
-st "SIGNAL config_busy            : std_logic
-"
-)
-)
-*233 (Net
+xt "-103000,63400,-80500,64200"
+st "SIGNAL config_busy            : std_logic"
+)
+)
+*245 (Net
 uid 5112,0
 decl (Decl
@@ -7810,10 +8226,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,63400,-70500,64200"
-st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
-"
-)
-)
-*234 (Net
+xt "-103000,64200,-70500,65000"
+st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
+)
+)
+*246 (Net
 uid 5120,0
 decl (Decl
@@ -7828,10 +8243,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,73800,-80500,74600"
-st "SIGNAL config_wr_en           : std_logic
-"
-)
-)
-*235 (Net
+xt "-103000,77800,-80500,78600"
+st "SIGNAL config_wr_en           : std_logic"
+)
+)
+*247 (Net
 uid 5128,0
 decl (Decl
@@ -7846,10 +8260,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,65000,-80500,65800"
-st "SIGNAL config_rd_en           : std_logic
-"
-)
-)
-*236 (Net
+xt "-103000,65800,-80500,66600"
+st "SIGNAL config_rd_en           : std_logic"
+)
+)
+*248 (Net
 uid 5144,0
 decl (Decl
@@ -7864,10 +8277,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,74600,-78000,75400"
-st "SIGNAL dac_array              : dac_array_type
-"
-)
-)
-*237 (Net
+xt "-103000,78600,-78000,79400"
+st "SIGNAL dac_array              : dac_array_type"
+)
+)
+*249 (Net
 uid 5194,0
 decl (Decl
@@ -7882,10 +8294,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,69000,-80500,69800"
-st "SIGNAL config_start_cm        : std_logic
-"
-)
-)
-*238 (Net
+xt "-103000,73000,-80500,73800"
+st "SIGNAL config_start_cm        : std_logic"
+)
+)
+*250 (Net
 uid 5196,0
 decl (Decl
@@ -7900,10 +8311,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,66600,-80500,67400"
-st "SIGNAL config_ready_cm        : std_logic
-"
-)
-)
-*239 (Net
+xt "-103000,67400,-80500,68200"
+st "SIGNAL config_ready_cm        : std_logic"
+)
+)
+*251 (Net
 uid 5220,0
 decl (Decl
@@ -7921,29 +8331,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,43800,-57000,44600"
-st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
-"
-)
-)
-*240 (Net
-uid 5279,0
-decl (Decl
-n "s_trigger"
-t "std_logic"
-o 69
-suid 134,0
-i "'0'"
-)
-declText (MLText
-uid 5280,0
-va (VaSet
-font "Courier New,8,0"
-)
-xt "-103000,93000,-59500,93800"
-st "SIGNAL s_trigger              : std_logic                                    := '0'
-"
-)
-)
-*241 (Net
+xt "-103000,44600,-57000,45400"
+st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
+)
+)
+*252 (Net
 uid 5472,0
 decl (Decl
@@ -7958,10 +8348,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,96200,-80500,97000"
-st "SIGNAL sensor_ready           : std_logic
-"
-)
-)
-*242 (Net
+xt "-103000,102600,-80500,103400"
+st "SIGNAL sensor_ready           : std_logic"
+)
+)
+*253 (Net
 uid 5478,0
 decl (Decl
@@ -7976,10 +8365,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,95400,-76500,96200"
-st "SIGNAL sensor_array           : sensor_array_type
-"
-)
-)
-*243 (Net
+xt "-103000,101800,-76500,102600"
+st "SIGNAL sensor_array           : sensor_array_type"
+)
+)
+*254 (Net
 uid 5588,0
 decl (Decl
@@ -7994,10 +8382,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,67400,-80500,68200"
-st "SIGNAL config_ready_spi       : std_logic
-"
-)
-)
-*244 (Net
+xt "-103000,68200,-80500,69000"
+st "SIGNAL config_ready_spi       : std_logic"
+)
+)
+*255 (Net
 uid 5632,0
 lang 10
@@ -8014,10 +8401,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,60200,-71000,61000"
-st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*245 (Net
+xt "-103000,61000,-71000,61800"
+st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*256 (Net
 uid 5640,0
 decl (Decl
@@ -8032,13 +8418,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,59400,-75500,60200"
-st "SIGNAL adc_data_array_int     : adc_data_array_type
-"
-)
-)
-*246 (SaComponent
+xt "-103000,60200,-75500,61000"
+st "SIGNAL adc_data_array_int     : adc_data_array_type"
+)
+)
+*257 (SaComponent
 uid 5678,0
 optionalChildren [
-*247 (CptPort
+*258 (CptPort
 uid 5658,0
 ps "OnEdgeStrategy"
@@ -8075,5 +8460,5 @@
 )
 )
-*248 (CptPort
+*259 (CptPort
 uid 5662,0
 ps "OnEdgeStrategy"
@@ -8112,5 +8497,5 @@
 )
 )
-*249 (CptPort
+*260 (CptPort
 uid 5666,0
 ps "OnEdgeStrategy"
@@ -8151,5 +8536,5 @@
 )
 )
-*250 (CptPort
+*261 (CptPort
 uid 5670,0
 ps "OnEdgeStrategy"
@@ -8187,5 +8572,5 @@
 )
 )
-*251 (CptPort
+*262 (CptPort
 uid 5674,0
 ps "OnEdgeStrategy"
@@ -8240,5 +8625,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*252 (Text
+*263 (Text
 uid 5681,0
 va (VaSet
@@ -8250,5 +8635,5 @@
 tm "BdLibraryNameMgr"
 )
-*253 (Text
+*264 (Text
 uid 5682,0
 va (VaSet
@@ -8260,5 +8645,5 @@
 tm "CptNameMgr"
 )
-*254 (Text
+*265 (Text
 uid 5683,0
 va (VaSet
@@ -8309,5 +8694,5 @@
 archFileType "UNKNOWN"
 )
-*255 (Net
+*266 (Net
 uid 5743,0
 decl (Decl
@@ -8323,13 +8708,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,69800,-59500,70600"
-st "SIGNAL config_start_spi       : std_logic                                    := '0'
-"
-)
-)
-*256 (SaComponent
+xt "-103000,73800,-59500,74600"
+st "SIGNAL config_start_spi       : std_logic                                    := '0'"
+)
+)
+*267 (SaComponent
 uid 5793,0
 optionalChildren [
-*257 (CptPort
+*268 (CptPort
 uid 5753,0
 ps "OnEdgeStrategy"
@@ -8366,5 +8750,5 @@
 )
 )
-*258 (CptPort
+*269 (CptPort
 uid 5761,0
 ps "OnEdgeStrategy"
@@ -8401,5 +8785,5 @@
 )
 )
-*259 (CptPort
+*270 (CptPort
 uid 5765,0
 ps "OnEdgeStrategy"
@@ -8437,5 +8821,5 @@
 )
 )
-*260 (CptPort
+*271 (CptPort
 uid 5769,0
 ps "OnEdgeStrategy"
@@ -8472,5 +8856,5 @@
 )
 )
-*261 (CptPort
+*272 (CptPort
 uid 5773,0
 ps "OnEdgeStrategy"
@@ -8508,5 +8892,5 @@
 )
 )
-*262 (CptPort
+*273 (CptPort
 uid 5777,0
 ps "OnEdgeStrategy"
@@ -8544,5 +8928,5 @@
 )
 )
-*263 (CptPort
+*274 (CptPort
 uid 5781,0
 ps "OnEdgeStrategy"
@@ -8579,5 +8963,5 @@
 )
 )
-*264 (CptPort
+*275 (CptPort
 uid 5785,0
 ps "OnEdgeStrategy"
@@ -8615,5 +8999,5 @@
 )
 )
-*265 (CptPort
+*276 (CptPort
 uid 5789,0
 ps "OnEdgeStrategy"
@@ -8651,5 +9035,5 @@
 )
 )
-*266 (CptPort
+*277 (CptPort
 uid 5986,0
 ps "OnEdgeStrategy"
@@ -8688,5 +9072,5 @@
 )
 )
-*267 (CptPort
+*278 (CptPort
 uid 6154,0
 ps "OnEdgeStrategy"
@@ -8724,5 +9108,5 @@
 )
 )
-*268 (CptPort
+*279 (CptPort
 uid 6317,0
 ps "OnEdgeStrategy"
@@ -8778,5 +9162,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*269 (Text
+*280 (Text
 uid 5796,0
 va (VaSet
@@ -8788,5 +9172,5 @@
 tm "BdLibraryNameMgr"
 )
-*270 (Text
+*281 (Text
 uid 5797,0
 va (VaSet
@@ -8798,5 +9182,5 @@
 tm "CptNameMgr"
 )
-*271 (Text
+*282 (Text
 uid 5798,0
 va (VaSet
@@ -8844,5 +9228,5 @@
 archFileType "UNKNOWN"
 )
-*272 (Net
+*283 (Net
 uid 5811,0
 decl (Decl
@@ -8857,10 +9241,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,47000,-84500,47800"
-st "sclk                   : std_logic
-"
-)
-)
-*273 (Net
+xt "-103000,47800,-84500,48600"
+st "sclk                   : std_logic"
+)
+)
+*284 (Net
 uid 5819,0
 decl (Decl
@@ -8877,10 +9260,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,54200,-84500,55000"
-st "sio                    : std_logic
-"
-)
-)
-*274 (Net
+xt "-103000,55000,-84500,55800"
+st "sio                    : std_logic"
+)
+)
+*285 (Net
 uid 5827,0
 decl (Decl
@@ -8895,10 +9277,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,40600,-84500,41400"
-st "dac_cs                 : std_logic
-"
-)
-)
-*275 (Net
+xt "-103000,41400,-84500,42200"
+st "dac_cs                 : std_logic"
+)
+)
+*286 (Net
 uid 5835,0
 decl (Decl
@@ -8914,10 +9295,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,47800,-74500,48600"
-st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*276 (PortIoOut
+xt "-103000,48600,-74500,49400"
+st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*287 (PortIoOut
 uid 5843,0
 shape (CompositeShape
@@ -8964,5 +9344,5 @@
 )
 )
-*277 (PortIoInOut
+*288 (PortIoInOut
 uid 5849,0
 shape (CompositeShape
@@ -9009,5 +9389,5 @@
 )
 )
-*278 (PortIoOut
+*289 (PortIoOut
 uid 5855,0
 shape (CompositeShape
@@ -9054,5 +9434,5 @@
 )
 )
-*279 (PortIoOut
+*290 (PortIoOut
 uid 5861,0
 shape (CompositeShape
@@ -9099,5 +9479,5 @@
 )
 )
-*280 (Net
+*291 (Net
 uid 5948,0
 decl (Decl
@@ -9113,10 +9493,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,83400,-59500,84200"
-st "SIGNAL new_config             : std_logic                                    := '0'
-"
-)
-)
-*281 (Net
+xt "-103000,88200,-59500,89000"
+st "SIGNAL new_config             : std_logic                                    := '0'"
+)
+)
+*292 (Net
 uid 5960,0
 decl (Decl
@@ -9131,10 +9510,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,70600,-80500,71400"
-st "SIGNAL config_started         : std_logic
-"
-)
-)
-*282 (Net
+xt "-103000,74600,-80500,75400"
+st "SIGNAL config_started         : std_logic"
+)
+)
+*293 (Net
 uid 6012,0
 decl (Decl
@@ -9150,10 +9528,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,73000,-59500,73800"
-st "SIGNAL config_started_spi     : std_logic                                    := '0'
-"
-)
-)
-*283 (Net
+xt "-103000,77000,-59500,77800"
+st "SIGNAL config_started_spi     : std_logic                                    := '0'"
+)
+)
+*294 (Net
 uid 6014,0
 decl (Decl
@@ -9169,10 +9546,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,71400,-59500,72200"
-st "SIGNAL config_started_cu      : std_logic                                    := '0'
-"
-)
-)
-*284 (Net
+xt "-103000,75400,-59500,76200"
+st "SIGNAL config_started_cu      : std_logic                                    := '0'"
+)
+)
+*295 (Net
 uid 6016,0
 decl (Decl
@@ -9187,10 +9563,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,72200,-80500,73000"
-st "SIGNAL config_started_mm      : std_logic
-"
-)
-)
-*285 (Net
+xt "-103000,76200,-80500,77000"
+st "SIGNAL config_started_mm      : std_logic"
+)
+)
+*296 (Net
 uid 6158,0
 decl (Decl
@@ -9206,10 +9581,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,44600,-63000,45400"
-st "mosi                   : std_logic                                    := '0'
-"
-)
-)
-*286 (PortIoOut
+xt "-103000,45400,-63000,46200"
+st "mosi                   : std_logic                                    := '0'"
+)
+)
+*297 (PortIoOut
 uid 6166,0
 shape (CompositeShape
@@ -9256,5 +9630,5 @@
 )
 )
-*287 (Net
+*298 (Net
 uid 6360,0
 decl (Decl
@@ -9272,10 +9646,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,41400,-49500,42200"
-st "denable                : std_logic                                    := '0' -- default domino wave off
-"
-)
-)
-*288 (PortIoOut
+xt "-103000,42200,-49500,43000"
+st "denable                : std_logic                                    := '0' -- default domino wave off"
+)
+)
+*299 (PortIoOut
 uid 6368,0
 shape (CompositeShape
@@ -9290,5 +9663,5 @@
 sl 0
 ro 270
-xt "153500,74625,155000,75375"
+xt "154500,74625,156000,75375"
 )
 (Line
@@ -9296,8 +9669,8 @@
 sl 0
 ro 270
-xt "153000,75000,153500,75000"
-pts [
-"153000,75000"
-"153500,75000"
+xt "154000,75000,154500,75000"
+pts [
+"154000,75000"
+"154500,75000"
 ]
 )
@@ -9314,12 +9687,12 @@
 va (VaSet
 )
-xt "156000,74500,159000,75500"
+xt "157000,74500,160000,75500"
 st "denable"
-blo "156000,75300"
+blo "157000,75300"
 tm "WireNameMgr"
 )
 )
 )
-*289 (Net
+*300 (Net
 uid 6450,0
 decl (Decl
@@ -9335,16 +9708,15 @@
 font "Courier New,8,0"
 )
-xt "-103000,82600,-59500,83400"
-st "SIGNAL dwrite_enable          : std_logic                                    := '1'
-"
-)
-)
-*290 (MWC
+xt "-103000,87400,-59500,88200"
+st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
+)
+)
+*301 (MWC
 uid 6529,0
 optionalChildren [
-*291 (CptPort
+*302 (CptPort
 uid 6501,0
 optionalChildren [
-*292 (Line
+*303 (Line
 uid 6505,0
 layer 5
@@ -9359,5 +9731,5 @@
 ]
 )
-*293 (Property
+*304 (Property
 uid 6506,0
 pclass "_MW_GEOM_"
@@ -9404,8 +9776,8 @@
 )
 )
-*294 (CptPort
+*305 (CptPort
 uid 6507,0
 optionalChildren [
-*295 (Line
+*306 (Line
 uid 6511,0
 layer 5
@@ -9459,8 +9831,8 @@
 )
 )
-*296 (CptPort
+*307 (CptPort
 uid 6512,0
 optionalChildren [
-*297 (Line
+*308 (Line
 uid 6516,0
 layer 5
@@ -9514,8 +9886,8 @@
 )
 )
-*298 (CommentGraphic
+*309 (CommentGraphic
 uid 6517,0
 optionalChildren [
-*299 (Property
+*310 (Property
 uid 6519,0
 pclass "_MW_GEOM_"
@@ -9541,8 +9913,8 @@
 oxt "11000,10000,11000,10000"
 )
-*300 (CommentGraphic
+*311 (CommentGraphic
 uid 6520,0
 optionalChildren [
-*301 (Property
+*312 (Property
 uid 6522,0
 pclass "_MW_GEOM_"
@@ -9568,8 +9940,8 @@
 oxt "11000,6000,11000,6000"
 )
-*302 (Grouping
+*313 (Grouping
 uid 6523,0
 optionalChildren [
-*303 (CommentGraphic
+*314 (CommentGraphic
 uid 6525,0
 shape (PolyLine2D
@@ -9592,5 +9964,5 @@
 oxt "9000,6000,11000,10000"
 )
-*304 (CommentGraphic
+*315 (CommentGraphic
 uid 6527,0
 shape (Arc2D
@@ -9645,5 +10017,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*305 (Text
+*316 (Text
 uid 6532,0
 va (VaSet
@@ -9655,5 +10027,5 @@
 blo "3500,59300"
 )
-*306 (Text
+*317 (Text
 uid 6533,0
 va (VaSet
@@ -9664,5 +10036,5 @@
 blo "3500,60300"
 )
-*307 (Text
+*318 (Text
 uid 6534,0
 va (VaSet
@@ -9709,5 +10081,5 @@
 )
 )
-*308 (Net
+*319 (Net
 uid 6544,0
 decl (Decl
@@ -9723,13 +10095,12 @@
 font "Courier New,8,0"
 )
-xt "-103000,81800,-59500,82600"
-st "SIGNAL dwrite                 : std_logic                                    := '1'
-"
-)
-)
-*309 (SaComponent
+xt "-103000,86600,-59500,87400"
+st "SIGNAL dwrite                 : std_logic                                    := '1'"
+)
+)
+*320 (SaComponent
 uid 8277,0
 optionalChildren [
-*310 (CptPort
+*321 (CptPort
 uid 8246,0
 ps "OnEdgeStrategy"
@@ -9768,5 +10139,5 @@
 )
 )
-*311 (CptPort
+*322 (CptPort
 uid 8250,0
 ps "OnEdgeStrategy"
@@ -9806,5 +10177,5 @@
 )
 )
-*312 (CptPort
+*323 (CptPort
 uid 8254,0
 ps "OnEdgeStrategy"
@@ -9844,5 +10215,5 @@
 )
 )
-*313 (CptPort
+*324 (CptPort
 uid 8258,0
 ps "OnEdgeStrategy"
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 )
 )
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 uid 8262,0
 ps "OnEdgeStrategy"
@@ -9920,5 +10291,5 @@
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 )
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 uid 8266,0
 ps "OnEdgeStrategy"
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 )
 )
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 uid 8270,0
 ps "OnEdgeStrategy"
@@ -10016,5 +10387,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
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 uid 8280,0
 va (VaSet
@@ -10026,5 +10397,5 @@
 tm "BdLibraryNameMgr"
 )
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 uid 8281,0
 va (VaSet
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 tm "CptNameMgr"
 )
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 uid 8282,0
 va (VaSet
@@ -10084,5 +10455,5 @@
 archFileType "UNKNOWN"
 )
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 uid 8414,0
 lang 2
@@ -10098,10 +10469,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,98600,-80500,99400"
-st "SIGNAL wiz_ack                : std_logic
-"
-)
-)
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+xt "-103000,108200,-80500,109000"
+st "SIGNAL wiz_ack                : std_logic"
+)
+)
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 uid 8508,0
 decl (Decl
@@ -10118,10 +10488,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,76200,-53500,77000"
-st "SIGNAL drs_address            : std_logic_vector(3 DOWNTO 0)                 := (others => '0')
-"
-)
-)
-*322 (Net
+xt "-103000,80200,-53500,81000"
+st "SIGNAL drs_address            : std_logic_vector(3 DOWNTO 0)                 := (others => '0')"
+)
+)
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 uid 8516,0
 decl (Decl
@@ -10136,16 +10505,15 @@
 font "Courier New,8,0"
 )
-xt "-103000,77000,-80500,77800"
-st "SIGNAL drs_address_mode       : std_logic
-"
-)
-)
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+xt "-103000,81000,-80500,81800"
+st "SIGNAL drs_address_mode       : std_logic"
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+)
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 uid 8562,0
 optionalChildren [
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 uid 8524,0
 optionalChildren [
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 layer 5
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 )
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 optionalChildren [
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 uid 8533,0
 layer 5
@@ -10228,5 +10596,5 @@
 ]
 )
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 uid 8534,0
 pclass "_MW_GEOM_"
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 )
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 uid 8535,0
 optionalChildren [
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 layer 5
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 )
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 uid 8540,0
 optionalChildren [
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 layer 5
@@ -10413,5 +10781,5 @@
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 )
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 uid 8545,0
 shape (CustomPolygon
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 oxt "7000,7000,9000,11000"
 )
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 optionalChildren [
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 uid 8549,0
 pclass "_MW_GEOM_"
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 oxt "9000,7000,9000,7000"
 )
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 uid 8550,0
 optionalChildren [
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 uid 8552,0
 pclass "_MW_GEOM_"
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 oxt "9000,11000,9000,11000"
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 shape (Rectangle
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 )
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 shape (Rectangle
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 )
 )
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 shape (Rectangle
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 stg "VerticalLayoutStrategy"
 textVec [
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 uid 8565,0
 va (VaSet
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 blo "-30650,102900"
 )
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 uid 8566,0
 va (VaSet
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 blo "-30650,103900"
 )
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 uid 8567,0
 va (VaSet
@@ -10669,5 +11037,5 @@
 )
 )
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 uid 8583,0
 decl (Decl
@@ -10684,16 +11052,15 @@
 font "Courier New,8,0"
 )
-xt "-103000,77800,-53500,78600"
-st "SIGNAL drs_channel_internal   : std_logic_vector(3 DOWNTO 0)                 := (others => '0')
-"
-)
-)
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+xt "-103000,81800,-53500,82600"
+st "SIGNAL drs_channel_internal   : std_logic_vector(3 DOWNTO 0)                 := (others => '0')"
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+)
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 uid 8721,0
 optionalChildren [
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 optionalChildren [
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 layer 5
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 ]
 )
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 uid 8698,0
 pclass "_MW_GEOM_"
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 )
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 uid 8699,0
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 layer 5
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 )
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 optionalChildren [
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 layer 5
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 )
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 optionalChildren [
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 uid 8711,0
 pclass "_MW_GEOM_"
@@ -10887,8 +11254,8 @@
 oxt "11000,6000,11000,6000"
 )
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 optionalChildren [
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 uid 8714,0
 pclass "_MW_GEOM_"
@@ -10914,8 +11281,8 @@
 oxt "11000,10000,11000,10000"
 )
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 uid 8715,0
 optionalChildren [
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 uid 8717,0
 shape (PolyLine2D
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 oxt "9000,6000,11000,10000"
 )
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 uid 8719,0
 shape (Arc2D
@@ -10991,5 +11358,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
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 uid 8724,0
 va (VaSet
@@ -11001,5 +11368,5 @@
 blo "-11500,113300"
 )
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 uid 8725,0
 va (VaSet
@@ -11010,5 +11377,5 @@
 blo "-11500,114300"
 )
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 uid 8726,0
 va (VaSet
@@ -11055,5 +11422,5 @@
 )
 )
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 uid 8730,0
 decl (Decl
@@ -11068,10 +11435,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,93800,-80500,94600"
-st "SIGNAL sclk1                  : std_logic
-"
-)
-)
-*364 (Net
+xt "-103000,100200,-80500,101000"
+st "SIGNAL sclk1                  : std_logic"
+)
+)
+*375 (Net
 uid 8746,0
 decl (Decl
@@ -11086,10 +11452,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,94600,-80500,95400"
-st "SIGNAL sclk_enable            : std_logic
-"
-)
-)
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+xt "-103000,101000,-80500,101800"
+st "SIGNAL sclk_enable            : std_logic"
+)
+)
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 uid 9004,0
 decl (Decl
@@ -11105,10 +11470,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,39000,-63000,39800"
-st "adc_clk_en             : std_logic                                    := '0'
-"
-)
-)
-*366 (PortIoOut
+xt "-103000,39800,-63000,40600"
+st "adc_clk_en             : std_logic                                    := '0'"
+)
+)
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 uid 9012,0
 shape (CompositeShape
@@ -11155,8 +11519,8 @@
 )
 )
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 uid 9175,0
 optionalChildren [
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 uid 9120,0
 ps "OnEdgeStrategy"
@@ -11190,10 +11554,10 @@
 n "CLK_50"
 t "std_logic"
-o 6
+o 7
 suid 2,0
 )
 )
 )
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 uid 9124,0
 ps "OnEdgeStrategy"
@@ -11227,10 +11591,10 @@
 n "CLK_25"
 t "std_logic"
-o 4
+o 5
 suid 3,0
 )
 )
 )
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 uid 9128,0
 ps "OnEdgeStrategy"
@@ -11267,5 +11631,5 @@
 )
 )
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 uid 9132,0
 ps "OnEdgeStrategy"
@@ -11311,5 +11675,5 @@
 preAdd 0
 posAdd 0
-o 14
+o 15
 suid 14,0
 i "'0'"
@@ -11317,5 +11681,5 @@
 )
 )
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 uid 9137,0
 ps "OnEdgeStrategy"
@@ -11362,5 +11726,5 @@
 preAdd 0
 posAdd 0
-o 15
+o 16
 suid 15,0
 i "'0'"
@@ -11368,5 +11732,5 @@
 )
 )
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 uid 9142,0
 ps "OnEdgeStrategy"
@@ -11413,5 +11777,5 @@
 preAdd 0
 posAdd 0
-o 13
+o 14
 suid 16,0
 i "(OTHERS => '0')"
@@ -11419,5 +11783,5 @@
 )
 )
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 uid 9147,0
 ps "OnEdgeStrategy"
@@ -11453,10 +11817,10 @@
 preAdd 0
 posAdd 0
-o 7
+o 8
 suid 17,0
 )
 )
 )
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 uid 9155,0
 ps "OnEdgeStrategy"
@@ -11490,10 +11854,10 @@
 n "PSCLK_OUT"
 t "std_logic"
-o 9
+o 10
 suid 19,0
 )
 )
 )
-*376 (CptPort
+*387 (CptPort
 uid 9159,0
 ps "OnEdgeStrategy"
@@ -11527,10 +11891,10 @@
 n "PSEN_OUT"
 t "std_logic"
-o 11
+o 12
 suid 20,0
 )
 )
 )
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 uid 9163,0
 ps "OnEdgeStrategy"
@@ -11564,10 +11928,10 @@
 n "PSINCDEC_OUT"
 t "std_logic"
-o 12
+o 13
 suid 21,0
 )
 )
 )
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 uid 9167,0
 ps "OnEdgeStrategy"
@@ -11601,10 +11965,10 @@
 n "PSDONE_extraOUT"
 t "std_logic"
-o 10
+o 11
 suid 22,0
 )
 )
 )
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 uid 9171,0
 ps "OnEdgeStrategy"
@@ -11638,10 +12002,10 @@
 n "LOCKED_extraOUT"
 t "std_logic"
-o 8
+o 9
 suid 23,0
 )
 )
 )
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+*391 (CptPort
 uid 9211,0
 ps "OnEdgeStrategy"
@@ -11675,10 +12039,10 @@
 n "CLK_25_PS"
 t "std_logic"
-o 5
+o 6
 suid 24,0
 )
 )
 )
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+*392 (CptPort
 uid 9215,0
 ps "OnEdgeStrategy"
@@ -11710,10 +12074,10 @@
 n "direction"
 t "std_logic"
-o 2
+o 3
 suid 26,0
 )
 )
 )
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+*393 (CptPort
 uid 9219,0
 ps "OnEdgeStrategy"
@@ -11745,6 +12109,41 @@
 n "do_shift"
 t "std_logic"
-o 3
+o 4
 suid 25,0
+)
+)
+)
+*394 (CptPort
+uid 10030,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10031,0
+ro 90
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+vasetType 1
+fg "0,65535,0"
+)
+xt "-20750,20625,-20000,21375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10033,0
+va (VaSet
+font "arial,8,0"
+)
+xt "-19000,20500,-15800,21500"
+st "RST_IN"
+blo "-19000,21300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "RST_IN"
+t "std_logic"
+o 2
+suid 27,0
 )
 )
@@ -11767,5 +12166,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
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 uid 9178,0
 va (VaSet
@@ -11777,5 +12176,5 @@
 tm "BdLibraryNameMgr"
 )
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 uid 9179,0
 va (VaSet
@@ -11787,5 +12186,5 @@
 tm "CptNameMgr"
 )
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 uid 9180,0
 va (VaSet
@@ -11834,5 +12233,5 @@
 archFileType "UNKNOWN"
 )
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 uid 9231,0
 decl (Decl
@@ -11850,10 +12249,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,85000,-44000,85800"
-st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards
-"
-)
-)
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+xt "-103000,89800,-44000,90600"
+st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards"
+)
+)
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 uid 9239,0
 decl (Decl
@@ -11872,10 +12270,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,85800,-43000,86600"
-st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once
-"
-)
-)
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+xt "-103000,90600,-43000,91400"
+st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once"
+)
+)
+*400 (Net
 uid 9267,0
 decl (Decl
@@ -11891,9 +12288,8 @@
 )
 xt "-103000,31800,-84500,32600"
-st "LOCKED_extraOUT        : std_logic
-"
-)
-)
-*389 (PortIoOut
+st "LOCKED_extraOUT        : std_logic"
+)
+)
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 uid 9275,0
 shape (CompositeShape
@@ -11939,5 +12335,5 @@
 )
 )
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+*402 (Net
 uid 9281,0
 decl (Decl
@@ -11953,9 +12349,8 @@
 )
 xt "-103000,33400,-84500,34200"
-st "PSDONE_extraOUT        : std_logic
-"
-)
-)
-*391 (PortIoOut
+st "PSDONE_extraOUT        : std_logic"
+)
+)
+*403 (PortIoOut
 uid 9289,0
 shape (CompositeShape
@@ -12001,5 +12396,5 @@
 )
 )
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+*404 (Net
 uid 9295,0
 decl (Decl
@@ -12015,9 +12410,8 @@
 )
 xt "-103000,35000,-84500,35800"
-st "PSINCDEC_OUT           : std_logic
-"
-)
-)
-*393 (PortIoOut
+st "PSINCDEC_OUT           : std_logic"
+)
+)
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 uid 9303,0
 shape (CompositeShape
@@ -12063,5 +12457,5 @@
 )
 )
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+*406 (Net
 uid 9309,0
 decl (Decl
@@ -12077,9 +12471,8 @@
 )
 xt "-103000,34200,-84500,35000"
-st "PSEN_OUT               : std_logic
-"
-)
-)
-*395 (PortIoOut
+st "PSEN_OUT               : std_logic"
+)
+)
+*407 (PortIoOut
 uid 9317,0
 shape (CompositeShape
@@ -12125,5 +12518,5 @@
 )
 )
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+*408 (Net
 uid 9323,0
 decl (Decl
@@ -12139,9 +12532,8 @@
 )
 xt "-103000,32600,-84500,33400"
-st "PSCLK_OUT              : std_logic
-"
-)
-)
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+st "PSCLK_OUT              : std_logic"
+)
+)
+*409 (PortIoOut
 uid 9331,0
 shape (CompositeShape
@@ -12187,5 +12579,5 @@
 )
 )
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+*410 (Net
 uid 9351,0
 decl (Decl
@@ -12203,9 +12595,8 @@
 )
 xt "-103000,31000,-84500,31800"
-st "DCM_locked             : std_logic
-"
-)
-)
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+st "DCM_locked             : std_logic"
+)
+)
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 uid 9359,0
 shape (CompositeShape
@@ -12251,5 +12642,5 @@
 )
 )
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+*412 (Net
 uid 9365,0
 decl (Decl
@@ -12268,10 +12659,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,45400,-57000,46200"
-st "offset                 : std_logic_vector(7 downto 0)                 := (OTHERS => '0')
-"
-)
-)
-*401 (PortIoOut
+xt "-103000,46200,-57000,47000"
+st "offset                 : std_logic_vector(7 downto 0)                 := (OTHERS => '0')"
+)
+)
+*413 (PortIoOut
 uid 9374,0
 shape (CompositeShape
@@ -12317,5 +12707,5 @@
 )
 )
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+*414 (Net
 uid 9380,0
 decl (Decl
@@ -12334,11 +12724,10 @@
 font "Courier New,8,0"
 )
-xt "-103000,48600,-63000,50200"
+xt "-103000,49400,-63000,51000"
 st "-- status:
-shifting               : std_logic                                    := '0'
-"
-)
-)
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+shifting               : std_logic                                    := '0'"
+)
+)
+*415 (PortIoOut
 uid 9389,0
 shape (CompositeShape
@@ -12384,5 +12773,5 @@
 )
 )
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+*416 (Net
 uid 9395,0
 decl (Decl
@@ -12400,10 +12789,9 @@
 font "Courier New,8,0"
 )
-xt "-103000,46200,-63000,47000"
-st "ready                  : std_logic                                    := '0'
-"
-)
-)
-*405 (PortIoOut
+xt "-103000,47000,-63000,47800"
+st "ready                  : std_logic                                    := '0'"
+)
+)
+*417 (PortIoOut
 uid 9404,0
 shape (CompositeShape
@@ -12449,11 +12837,11 @@
 )
 )
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 uid 9430,0
 optionalChildren [
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 uid 9410,0
 optionalChildren [
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 uid 9414,0
 layer 5
@@ -12518,8 +12906,8 @@
 )
 )
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 uid 9415,0
 optionalChildren [
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+*422 (Line
 uid 9419,0
 layer 5
@@ -12583,5 +12971,5 @@
 )
 )
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+*423 (CommentGraphic
 uid 9420,0
 shape (PolyLine2D
@@ -12604,5 +12992,5 @@
 oxt "6000,6000,7000,7000"
 )
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+*424 (CommentGraphic
 uid 9422,0
 shape (PolyLine2D
@@ -12625,5 +13013,5 @@
 oxt "6000,7000,7000,8000"
 )
-*413 (CommentGraphic
+*425 (CommentGraphic
 uid 9424,0
 shape (PolyLine2D
@@ -12646,5 +13034,5 @@
 oxt "6988,7329,7988,7329"
 )
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+*426 (CommentGraphic
 uid 9426,0
 shape (PolyLine2D
@@ -12665,5 +13053,5 @@
 oxt "8000,7000,9000,7000"
 )
-*415 (CommentGraphic
+*427 (CommentGraphic
 uid 9428,0
 shape (PolyLine2D
@@ -12706,5 +13094,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
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+*428 (Text
 uid 9433,0
 va (VaSet
@@ -12716,5 +13104,5 @@
 blo "-2650,-11100"
 )
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+*429 (Text
 uid 9434,0
 va (VaSet
@@ -12725,5 +13113,5 @@
 blo "-2650,-10100"
 )
-*418 (Text
+*430 (Text
 uid 9435,0
 va (VaSet
@@ -12770,11 +13158,11 @@
 )
 )
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+*431 (MWC
 uid 9472,0
 optionalChildren [
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+*432 (CptPort
 uid 9481,0
 optionalChildren [
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+*433 (Line
 uid 9486,0
 layer 5
@@ -12837,8 +13225,8 @@
 )
 )
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 uid 9487,0
 optionalChildren [
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 uid 9492,0
 layer 5
@@ -12901,5 +13289,5 @@
 )
 )
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 uid 9493,0
 shape (PolyLine2D
@@ -12922,5 +13310,5 @@
 oxt "6000,6000,7000,7000"
 )
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+*437 (CommentGraphic
 uid 9495,0
 shape (PolyLine2D
@@ -12943,5 +13331,5 @@
 oxt "6000,7000,7000,8000"
 )
-*426 (CommentGraphic
+*438 (CommentGraphic
 uid 9497,0
 shape (PolyLine2D
@@ -12964,5 +13352,5 @@
 oxt "6988,7329,7988,7329"
 )
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+*439 (CommentGraphic
 uid 9499,0
 shape (PolyLine2D
@@ -12983,5 +13371,5 @@
 oxt "8000,7000,9000,7000"
 )
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+*440 (CommentGraphic
 uid 9501,0
 shape (PolyLine2D
@@ -13024,5 +13412,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
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+*441 (Text
 uid 9475,0
 va (VaSet
@@ -13034,5 +13422,5 @@
 blo "-2650,-7100"
 )
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+*442 (Text
 uid 9476,0
 va (VaSet
@@ -13043,5 +13431,5 @@
 blo "-2650,-6100"
 )
-*431 (Text
+*443 (Text
 uid 9477,0
 va (VaSet
@@ -13088,5 +13476,5 @@
 )
 )
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+*444 (PortIoOut
 uid 9523,0
 shape (CompositeShape
@@ -13132,5 +13520,5 @@
 )
 )
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+"-29000,71000"
+]
+uid 10378,0
+layer 0
+sl 0
+va (VaSet
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+transparent 1
+fg "49152,49152,49152"
+)
+xt "-29000,71000,-29000,71000"
+)
+oxt "7000,10000,7000,10000"
+)
+]
+shape (Rectangle
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+va (VaSet
+vasetType 1
+transparent 1
+fg "65535,65535,65535"
+lineWidth -1
+)
+xt "-30000,67000,-24000,71000"
+fos 1
+)
+showPorts 0
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+ttg (MlTextGroup
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+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*543 (Text
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+va (VaSet
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+font "arial,8,0"
+)
+xt "-28500,69500,-23700,70500"
+st "moduleware"
+blo "-28500,70300"
+)
+*544 (Text
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+va (VaSet
+font "arial,8,0"
+)
+xt "-28500,70500,-27400,71500"
+st "or"
+blo "-28500,71300"
+)
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+va (VaSet
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+)
+xt "-28500,71500,-26700,72500"
+st "U_9"
+blo "-28500,72300"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
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+ps "EdgeToEdgeStrategy"
+matrix (Matrix
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+text (MLText
+uid 10388,0
+va (VaSet
+font "arial,8,0"
+)
+xt "-45000,58000,-45000,58000"
+)
+header ""
+)
+elements [
+]
+)
+sed 1
+awe 1
+portVis (PortSigDisplay
+sN 0
+sTC 0
+selT 0
+)
+prms (Property
+pclass "params"
+pname "params"
+ptn "String"
+)
+de 2
+visOptions (mwParamsVisibilityOptions
+)
+)
+*546 (Net
+uid 10449,0
+decl (Decl
+n "trigger_out"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 115
+suid 240,0
+)
+declText (MLText
+uid 10450,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-103000,107400,-80500,108200"
+st "SIGNAL trigger_out            : std_logic"
+)
+)
+*547 (Net
+uid 10465,0
+lang 2
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 115
+suid 242,0
+i "'0'"
+)
+declText (MLText
+uid 10466,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-103000,96200,-59500,97800"
+st "-- --
+SIGNAL ram_write_ready_ack    : std_logic                                    := '0'"
+)
+)
+*548 (Wire
 uid 322,0
 shape (OrthoPolyLine
@@ -14786,5 +15858,5 @@
 )
 start &26
-end &313
+end &324
 sat 32
 eat 32
@@ -14809,5 +15881,5 @@
 on &2
 )
-*503 (Wire
+*549 (Wire
 uid 328,0
 shape (OrthoPolyLine
@@ -14825,5 +15897,5 @@
 )
 start &25
-end &312
+end &323
 sat 32
 eat 32
@@ -14848,5 +15920,5 @@
 on &3
 )
-*504 (Wire
+*550 (Wire
 uid 334,0
 shape (OrthoPolyLine
@@ -14864,5 +15936,5 @@
 )
 start &24
-end &311
+end &322
 sat 32
 eat 32
@@ -14887,5 +15959,5 @@
 on &4
 )
-*505 (Wire
+*551 (Wire
 uid 364,0
 shape (OrthoPolyLine
@@ -14895,14 +15967,14 @@
 lineWidth 2
 )
-xt "91750,49000,126250,54000"
-pts [
-"126250,54000"
-"113000,54000"
-"113000,49000"
+xt "91750,49000,127250,54000"
+pts [
+"127250,54000"
+"123000,54000"
+"123000,49000"
 "91750,49000"
 ]
 )
-start &80
-end &315
+start &84
+end &326
 sat 32
 eat 32
@@ -14927,5 +15999,5 @@
 on &5
 )
-*506 (Wire
+*552 (Wire
 uid 370,0
 shape (OrthoPolyLine
@@ -14935,14 +16007,14 @@
 lineWidth 2
 )
-xt "91750,50000,126250,55000"
-pts [
-"126250,55000"
-"112000,55000"
-"112000,50000"
+xt "91750,50000,127250,55000"
+pts [
+"127250,55000"
+"124000,55000"
+"124000,50000"
 "91750,50000"
 ]
 )
-start &79
-end &316
+start &83
+end &327
 sat 32
 eat 32
@@ -14967,5 +16039,5 @@
 on &6
 )
-*507 (Wire
+*553 (Wire
 uid 376,0
 shape (OrthoPolyLine
@@ -14974,11 +16046,11 @@
 vasetType 3
 )
-xt "148750,52000,153000,52000"
-pts [
-"148750,52000"
-"153000,52000"
-]
-)
-start &70
+xt "149750,52000,154000,52000"
+pts [
+"149750,52000"
+"154000,52000"
+]
+)
+start &74
 end &14
 sat 32
@@ -14997,7 +16069,7 @@
 isHidden 1
 )
-xt "150000,51000,153600,52000"
+xt "151000,51000,154600,52000"
 st "wiz_reset"
-blo "150000,51800"
+blo "151000,51800"
 tm "WireNameMgr"
 )
@@ -15005,5 +16077,5 @@
 on &7
 )
-*508 (Wire
+*554 (Wire
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 shape (OrthoPolyLine
@@ -15013,11 +16085,11 @@
 lineWidth 2
 )
-xt "148750,60000,153000,60000"
-pts [
-"148750,60000"
-"153000,60000"
-]
-)
-start &71
+xt "149750,60000,154000,60000"
+pts [
+"149750,60000"
+"154000,60000"
+]
+)
+start &75
 end &15
 sat 32
@@ -15037,7 +16109,7 @@
 isHidden 1
 )
-xt "150000,59000,153400,60000"
+xt "151000,59000,154400,60000"
 st "wiz_addr"
-blo "150000,59800"
+blo "151000,59800"
 tm "WireNameMgr"
 )
@@ -15045,5 +16117,5 @@
 on &8
 )
-*509 (Wire
+*555 (Wire
 uid 392,0
 shape (OrthoPolyLine
@@ -15053,11 +16125,11 @@
 lineWidth 2
 )
-xt "148750,61000,153000,61000"
-pts [
-"148750,61000"
-"153000,61000"
-]
-)
-start &72
+xt "149750,61000,154000,61000"
+pts [
+"149750,61000"
+"154000,61000"
+]
+)
+start &76
 end &16
 sat 32
@@ -15077,7 +16149,7 @@
 isHidden 1
 )
-xt "150000,60000,153300,61000"
+xt "151000,60000,154300,61000"
 st "wiz_data"
-blo "150000,60800"
+blo "151000,60800"
 tm "WireNameMgr"
 )
@@ -15085,5 +16157,5 @@
 on &9
 )
-*510 (Wire
+*556 (Wire
 uid 400,0
 shape (OrthoPolyLine
@@ -15092,11 +16164,11 @@
 vasetType 3
 )
-xt "148750,53000,153000,53000"
-pts [
-"148750,53000"
-"153000,53000"
-]
-)
-start &73
+xt "149750,53000,154000,53000"
+pts [
+"149750,53000"
+"154000,53000"
+]
+)
+start &77
 end &17
 sat 32
@@ -15115,7 +16187,7 @@
 isHidden 1
 )
-xt "150000,52000,152700,53000"
+xt "151000,52000,153700,53000"
 st "wiz_cs"
-blo "150000,52800"
+blo "151000,52800"
 tm "WireNameMgr"
 )
@@ -15123,5 +16195,5 @@
 on &10
 )
-*511 (Wire
+*557 (Wire
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 shape (OrthoPolyLine
@@ -15130,11 +16202,11 @@
 vasetType 3
 )
-xt "148750,54000,153000,54000"
-pts [
-"148750,54000"
-"153000,54000"
-]
-)
-start &74
+xt "149750,54000,154000,54000"
+pts [
+"149750,54000"
+"154000,54000"
+]
+)
+start &78
 end &18
 sat 32
@@ -15153,7 +16225,7 @@
 isHidden 1
 )
-xt "150000,53000,152700,54000"
+xt "151000,53000,153700,54000"
 st "wiz_wr"
-blo "150000,53800"
+blo "151000,53800"
 tm "WireNameMgr"
 )
@@ -15161,5 +16233,5 @@
 on &11
 )
-*512 (Wire
+*558 (Wire
 uid 424,0
 shape (OrthoPolyLine
@@ -15168,11 +16240,11 @@
 vasetType 3
 )
-xt "148750,55000,153000,55000"
-pts [
-"148750,55000"
-"153000,55000"
-]
-)
-start &75
+xt "149750,55000,154000,55000"
+pts [
+"149750,55000"
+"154000,55000"
+]
+)
+start &79
 end &20
 sat 32
@@ -15191,7 +16263,7 @@
 isHidden 1
 )
-xt "150000,54000,152600,55000"
+xt "151000,54000,153600,55000"
 st "wiz_rd"
-blo "150000,54800"
+blo "151000,54800"
 tm "WireNameMgr"
 )
@@ -15199,5 +16271,5 @@
 on &12
 )
-*513 (Wire
+*559 (Wire
 uid 432,0
 shape (OrthoPolyLine
@@ -15206,12 +16278,12 @@
 vasetType 3
 )
-xt "148750,56000,153000,56000"
-pts [
-"153000,56000"
-"148750,56000"
+xt "149750,56000,154000,56000"
+pts [
+"154000,56000"
+"149750,56000"
 ]
 )
 start &21
-end &76
+end &80
 sat 32
 eat 32
@@ -15229,7 +16301,7 @@
 isHidden 1
 )
-xt "150000,55000,152700,56000"
+xt "151000,55000,153700,56000"
 st "wiz_int"
-blo "150000,55800"
+blo "151000,55800"
 tm "WireNameMgr"
 )
@@ -15237,5 +16309,5 @@
 on &13
 )
-*514 (Wire
+*560 (Wire
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 shape (OrthoPolyLine
@@ -15251,5 +16323,5 @@
 ]
 )
-start &155
+start &162
 end &28
 sat 32
@@ -15274,22 +16346,8 @@
 )
 )
-on &65
-)
-*515 (Wire
+on &69
+)
+*561 (Wire
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-optionalChildren [
-*516 (BdJunction
-uid 4391,0
-ps "OnConnectorStrategy"
-shape (Circle
-uid 4392,0
-va (VaSet
-vasetType 1
-)
-xt "-22400,68600,-21600,69400"
-radius 400
-)
-)
-]
 shape (OrthoPolyLine
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@@ -15297,12 +16355,12 @@
 vasetType 3
 )
-xt "-26000,69000,18250,69000"
-pts [
-"-26000,69000"
-"18250,69000"
-]
-)
-start &67
-end &30
+xt "-32000,70000,-30000,70000"
+pts [
+"-32000,70000"
+"-30000,70000"
+]
+)
+start &71
+end &524
 es 0
 sat 32
@@ -15321,13 +16379,13 @@
 isHidden 1
 )
-xt "5000,63000,7800,64000"
+xt "-38000,69000,-35200,70000"
 st "trigger"
-blo "5000,63800"
+blo "-38000,69800"
 tm "WireNameMgr"
 )
 )
-on &66
-)
-*517 (Wire
+on &70
+)
+*562 (Wire
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 shape (OrthoPolyLine
@@ -15343,5 +16401,5 @@
 ]
 )
-start &156
+start &163
 end &31
 sat 32
@@ -15366,7 +16424,7 @@
 )
 )
-on &106
-)
-*518 (Wire
+on &112
+)
+*563 (Wire
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 shape (OrthoPolyLine
@@ -15384,5 +16442,5 @@
 ]
 )
-start &108
+start &114
 end &29
 sat 32
@@ -15405,7 +16463,7 @@
 )
 )
-on &114
-)
-*519 (Wire
+on &120
+)
+*564 (Wire
 uid 2299,0
 shape (OrthoPolyLine
@@ -15423,5 +16481,5 @@
 ]
 )
-start &117
+start &123
 end &27
 sat 32
@@ -15445,7 +16503,7 @@
 )
 )
-on &115
-)
-*520 (Wire
+on &121
+)
+*565 (Wire
 uid 2470,0
 shape (OrthoPolyLine
@@ -15454,13 +16512,12 @@
 vasetType 3
 )
-xt "103750,68000,126250,68000"
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 pts [
 "103750,68000"
-"115000,68000"
-"126250,68000"
-]
-)
-start &124
-end &82
+"127250,68000"
+]
+)
+start &130
+end &86
 sat 32
 eat 32
@@ -15482,7 +16539,7 @@
 )
 )
-on &138
-)
-*521 (Wire
+on &145
+)
+*566 (Wire
 uid 2476,0
 shape (OrthoPolyLine
@@ -15491,13 +16548,12 @@
 vasetType 3
 )
-xt "103750,69000,126250,69000"
+xt "103750,69000,127250,69000"
 pts [
 "103750,69000"
-"115000,69000"
-"126250,69000"
-]
-)
-start &127
-end &81
+"127250,69000"
+]
+)
+start &133
+end &85
 sat 32
 eat 32
@@ -15519,7 +16575,7 @@
 )
 )
-on &139
-)
-*522 (Wire
+on &146
+)
+*567 (Wire
 uid 2482,0
 shape (OrthoPolyLine
@@ -15529,13 +16585,12 @@
 lineWidth 2
 )
-xt "103750,70000,126250,70000"
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 pts [
 "103750,70000"
-"115000,70000"
-"126250,70000"
-]
-)
-start &130
-end &77
+"127250,70000"
+]
+)
+start &136
+end &81
 sat 32
 eat 32
@@ -15558,7 +16613,7 @@
 )
 )
-on &140
-)
-*523 (Wire
+on &147
+)
+*568 (Wire
 uid 2488,0
 shape (OrthoPolyLine
@@ -15568,13 +16623,12 @@
 lineWidth 2
 )
-xt "103750,71000,126250,71000"
+xt "103750,71000,127250,71000"
 pts [
 "103750,71000"
-"115000,71000"
-"126250,71000"
-]
-)
-start &126
-end &78
+"127250,71000"
+]
+)
+start &132
+end &82
 sat 32
 eat 32
@@ -15597,7 +16651,7 @@
 )
 )
-on &141
-)
-*524 (Wire
+on &148
+)
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 shape (OrthoPolyLine
@@ -15607,13 +16661,12 @@
 lineWidth 2
 )
-xt "103750,72000,126250,72000"
+xt "103750,72000,127250,72000"
 pts [
 "103750,72000"
-"115000,72000"
-"126250,72000"
-]
-)
-start &125
-end &83
+"127250,72000"
+]
+)
+start &131
+end &87
 sat 32
 eat 32
@@ -15636,7 +16689,7 @@
 )
 )
-on &142
-)
-*525 (Wire
+on &149
+)
+*570 (Wire
 uid 2500,0
 shape (OrthoPolyLine
@@ -15645,13 +16698,12 @@
 vasetType 3
 )
-xt "103750,73000,126250,73000"
+xt "103750,73000,127250,73000"
 pts [
 "103750,73000"
-"115000,73000"
-"126250,73000"
-]
-)
-start &128
-end &84
+"127250,73000"
+]
+)
+start &134
+end &88
 sat 32
 eat 32
@@ -15673,7 +16725,7 @@
 )
 )
-on &143
-)
-*526 (Wire
+on &150
+)
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 uid 2506,0
 shape (OrthoPolyLine
@@ -15682,13 +16734,12 @@
 vasetType 3
 )
-xt "103750,74000,126250,74000"
+xt "103750,74000,127250,74000"
 pts [
 "103750,74000"
-"115000,74000"
-"126250,74000"
-]
-)
-start &129
-end &85
+"127250,74000"
+]
+)
+start &135
+end &89
 sat 32
 eat 32
@@ -15710,7 +16761,7 @@
 )
 )
-on &144
-)
-*527 (Wire
+on &151
+)
+*572 (Wire
 uid 2576,0
 shape (OrthoPolyLine
@@ -15728,5 +16779,5 @@
 )
 start &32
-end &121
+end &127
 sat 32
 eat 32
@@ -15748,7 +16799,7 @@
 )
 )
-on &145
-)
-*528 (Wire
+on &152
+)
+*573 (Wire
 uid 2582,0
 shape (OrthoPolyLine
@@ -15766,5 +16817,5 @@
 )
 start &33
-end &122
+end &128
 sat 32
 eat 32
@@ -15786,7 +16837,7 @@
 )
 )
-on &146
-)
-*529 (Wire
+on &153
+)
+*574 (Wire
 uid 2588,0
 shape (OrthoPolyLine
@@ -15798,11 +16849,11 @@
 pts [
 "40750,70000"
-"64000,70000"
-"64000,75000"
+"63000,70000"
+"63000,75000"
 "71250,75000"
 ]
 )
-start &53
-end &120
+start &52
+end &126
 ss 0
 sat 32
@@ -15825,7 +16876,7 @@
 )
 )
-on &147
-)
-*530 (Wire
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+)
+*575 (Wire
 uid 2594,0
 shape (OrthoPolyLine
@@ -15837,11 +16888,11 @@
 pts [
 "40750,72000"
-"62000,72000"
-"62000,77000"
+"61000,72000"
+"61000,77000"
 "71250,77000"
 ]
 )
-start &49
-end &119
+start &48
+end &125
 sat 32
 eat 32
@@ -15863,7 +16914,7 @@
 )
 )
-on &148
-)
-*531 (Wire
+on &155
+)
+*576 (Wire
 uid 2600,0
 shape (OrthoPolyLine
@@ -15875,11 +16926,11 @@
 pts [
 "40750,74000"
-"61000,74000"
-"61000,78000"
+"60000,74000"
+"60000,78000"
 "71250,78000"
 ]
 )
 start &34
-end &123
+end &129
 sat 32
 eat 32
@@ -15901,7 +16952,7 @@
 )
 )
-on &149
-)
-*532 (Wire
+on &156
+)
+*577 (Wire
 uid 2642,0
 shape (OrthoPolyLine
@@ -15914,11 +16965,11 @@
 pts [
 "40750,75000"
-"60000,75000"
-"60000,79000"
+"59000,75000"
+"59000,79000"
 "71250,79000"
 ]
 )
 start &36
-end &132
+end &138
 sat 32
 eat 32
@@ -15941,7 +16992,7 @@
 )
 )
-on &150
-)
-*533 (Wire
+on &157
+)
+*578 (Wire
 uid 2778,0
 shape (OrthoPolyLine
@@ -15957,5 +17008,5 @@
 )
 start &37
-end &152
+end &159
 sat 32
 eat 32
@@ -15979,7 +17030,7 @@
 )
 )
-on &151
-)
-*534 (Wire
+on &158
+)
+*579 (Wire
 uid 2786,0
 shape (OrthoPolyLine
@@ -15995,6 +17046,6 @@
 ]
 )
-start &153
-end &250
+start &160
+end &261
 sat 32
 eat 32
@@ -16019,48 +17070,10 @@
 )
 )
-on &174
-)
-*535 (Wire
-uid 2876,0
-shape (OrthoPolyLine
-uid 2877,0
-va (VaSet
-vasetType 3
-)
-xt "-22000,64000,-18750,69000"
-pts [
-"-22000,69000"
-"-22000,64000"
-"-18750,64000"
-]
-)
-start &516
-end &109
-es 0
-sat 32
-eat 32
-st 0
-sf 1
-tg (WTG
-uid 2880,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 2881,0
-ro 270
-va (VaSet
-)
-xt "-23000,64200,-22000,67000"
-st "trigger"
-blo "-22200,67000"
-tm "WireNameMgr"
-)
-)
-on &66
-)
-*536 (Wire
+on &181
+)
+*580 (Wire
 uid 3888,0
 optionalChildren [
-*537 (BdJunction
+*581 (BdJunction
 uid 4230,0
 ps "OnConnectorStrategy"
@@ -16074,5 +17087,5 @@
 )
 )
-*538 (BdJunction
+*582 (BdJunction
 uid 4244,0
 ps "OnConnectorStrategy"
@@ -16082,9 +17095,9 @@
 vasetType 1
 )
-xt "108600,18600,109400,19400"
+xt "108600,51600,109400,52400"
 radius 400
 )
 )
-*539 (BdJunction
+*583 (BdJunction
 uid 9677,0
 ps "OnConnectorStrategy"
@@ -16105,14 +17118,14 @@
 lineColor "0,0,65535"
 )
-xt "-1250,19000,126250,52000"
+xt "-1250,19000,127250,52000"
 pts [
 "-1250,19000"
-"123000,19000"
-"123000,52000"
-"126250,52000"
-]
-)
-start &368
-end &69
+"106000,19000"
+"106000,52000"
+"127250,52000"
+]
+)
+start &379
+end &73
 sat 32
 eat 32
@@ -16135,10 +17148,10 @@
 )
 )
-on &170
-)
-*540 (Wire
+on &177
+)
+*584 (Wire
 uid 3984,0
 optionalChildren [
-*541 (BdJunction
+*585 (BdJunction
 uid 9751,0
 ps "OnConnectorStrategy"
@@ -16167,6 +17180,6 @@
 ]
 )
-start &169
-end &380
+start &176
+end &391
 sat 32
 eat 32
@@ -16190,7 +17203,7 @@
 )
 )
-on &168
-)
-*542 (Wire
+on &175
+)
+*586 (Wire
 uid 4042,0
 shape (OrthoPolyLine
@@ -16206,5 +17219,5 @@
 )
 start &1
-end &370
+end &381
 sat 32
 eat 32
@@ -16228,7 +17241,7 @@
 )
 )
-on &173
-)
-*543 (Wire
+on &180
+)
+*587 (Wire
 uid 4226,0
 shape (OrthoPolyLine
@@ -16245,6 +17258,6 @@
 ]
 )
-start &172
-end &537
+start &179
+end &581
 sat 32
 eat 32
@@ -16268,7 +17281,7 @@
 )
 )
-on &170
-)
-*544 (Wire
+on &177
+)
+*588 (Wire
 uid 4240,0
 shape (OrthoPolyLine
@@ -16278,13 +17291,13 @@
 lineColor "0,0,65535"
 )
-xt "91750,19000,109000,44000"
+xt "91750,44000,109000,52000"
 pts [
 "91750,44000"
 "109000,44000"
-"109000,19000"
-]
-)
-start &314
-end &538
+"109000,52000"
+]
+)
+start &325
+end &582
 sat 32
 eat 32
@@ -16307,7 +17320,7 @@
 )
 )
-on &170
-)
-*545 (Wire
+on &177
+)
+*589 (Wire
 uid 4272,0
 shape (OrthoPolyLine
@@ -16322,6 +17335,6 @@
 ]
 )
-start &176
-end &247
+start &183
+end &258
 sat 32
 eat 32
@@ -16345,7 +17358,7 @@
 )
 )
-on &175
-)
-*546 (Wire
+on &182
+)
+*590 (Wire
 uid 4401,0
 shape (OrthoPolyLine
@@ -16354,12 +17367,14 @@
 vasetType 3
 )
-xt "1750,53000,18250,53000"
+xt "1750,49000,18250,53000"
 pts [
 "18250,53000"
-"1750,53000"
+"7000,53000"
+"7000,49000"
+"1750,49000"
 ]
 )
 start &40
-end &195
+end &202
 sat 32
 eat 32
@@ -16381,7 +17396,7 @@
 )
 )
-on &177
-)
-*547 (Wire
+on &184
+)
+*591 (Wire
 uid 4407,0
 shape (OrthoPolyLine
@@ -16390,12 +17405,14 @@
 vasetType 3
 )
-xt "1750,52000,18250,52000"
+xt "1750,48000,18250,52000"
 pts [
 "18250,52000"
-"1750,52000"
+"8000,52000"
+"8000,48000"
+"1750,48000"
 ]
 )
 start &44
-end &201
+end &208
 sat 32
 eat 32
@@ -16417,7 +17434,7 @@
 )
 )
-on &178
-)
-*548 (Wire
+on &185
+)
+*592 (Wire
 uid 4419,0
 shape (OrthoPolyLine
@@ -16426,12 +17443,14 @@
 vasetType 3
 )
-xt "1750,50000,18250,50000"
+xt "1750,46000,18250,50000"
 pts [
 "18250,50000"
-"1750,50000"
+"10000,50000"
+"10000,46000"
+"1750,46000"
 ]
 )
 start &42
-end &196
+end &203
 sat 32
 eat 32
@@ -16453,7 +17472,7 @@
 )
 )
-on &179
-)
-*549 (Wire
+on &186
+)
+*593 (Wire
 uid 4537,0
 shape (OrthoPolyLine
@@ -16469,6 +17488,6 @@
 ]
 )
-start &326
-end &182
+start &337
+end &189
 sat 32
 eat 32
@@ -16493,7 +17512,7 @@
 )
 )
-on &180
-)
-*550 (Wire
+on &187
+)
+*594 (Wire
 uid 4545,0
 shape (OrthoPolyLine
@@ -16508,6 +17527,6 @@
 ]
 )
-start &291
-end &183
+start &302
+end &190
 sat 32
 eat 32
@@ -16530,7 +17549,7 @@
 )
 )
-on &181
-)
-*551 (Wire
+on &188
+)
+*595 (Wire
 uid 4671,0
 shape (OrthoPolyLine
@@ -16545,6 +17564,6 @@
 ]
 )
-start &188
-end &197
+start &195
+end &204
 sat 32
 eat 32
@@ -16568,7 +17587,7 @@
 )
 )
-on &184
-)
-*552 (Wire
+on &191
+)
+*596 (Wire
 uid 4679,0
 shape (OrthoPolyLine
@@ -16583,6 +17602,6 @@
 ]
 )
-start &189
-end &198
+start &196
+end &205
 sat 32
 eat 32
@@ -16606,7 +17625,7 @@
 )
 )
-on &185
-)
-*553 (Wire
+on &192
+)
+*597 (Wire
 uid 4687,0
 shape (OrthoPolyLine
@@ -16621,6 +17640,6 @@
 ]
 )
-start &190
-end &199
+start &197
+end &206
 sat 32
 eat 32
@@ -16644,7 +17663,7 @@
 )
 )
-on &186
-)
-*554 (Wire
+on &193
+)
+*598 (Wire
 uid 4695,0
 shape (OrthoPolyLine
@@ -16659,6 +17678,6 @@
 ]
 )
-start &191
-end &200
+start &198
+end &207
 sat 32
 eat 32
@@ -16682,7 +17701,7 @@
 )
 )
-on &187
-)
-*555 (Wire
+on &194
+)
+*599 (Wire
 uid 4743,0
 shape (OrthoPolyLine
@@ -16691,11 +17710,13 @@
 vasetType 3
 )
-xt "1750,51000,18250,51000"
-pts [
-"1750,51000"
+xt "1750,47000,18250,51000"
+pts [
+"1750,47000"
+"9000,47000"
+"9000,51000"
 "18250,51000"
 ]
 )
-start &202
+start &209
 end &43
 sat 32
@@ -16718,10 +17739,10 @@
 )
 )
-on &192
-)
-*556 (Wire
+on &199
+)
+*600 (Wire
 uid 4757,0
 optionalChildren [
-*557 (BdJunction
+*601 (BdJunction
 uid 6076,0
 ps "OnConnectorStrategy"
@@ -16750,6 +17771,6 @@
 ]
 )
-start &194
-end *558 (BdJunction
+start &201
+end *602 (BdJunction
 uid 6080,0
 ps "OnConnectorStrategy"
@@ -16783,7 +17804,7 @@
 )
 )
-on &171
-)
-*559 (Wire
+on &178
+)
+*603 (Wire
 uid 4948,0
 shape (OrthoPolyLine
@@ -16798,6 +17819,6 @@
 ]
 )
-start &203
-end &209
+start &210
+end &221
 sat 32
 eat 32
@@ -16821,7 +17842,7 @@
 )
 )
-on &208
-)
-*560 (Wire
+on &220
+)
+*604 (Wire
 uid 4962,0
 shape (OrthoPolyLine
@@ -16836,6 +17857,6 @@
 ]
 )
-start &484
-end &211
+start &496
+end &223
 sat 32
 eat 32
@@ -16859,7 +17880,7 @@
 )
 )
-on &210
-)
-*561 (Wire
+on &222
+)
+*605 (Wire
 uid 5090,0
 shape (OrthoPolyLine
@@ -16869,14 +17890,14 @@
 lineWidth 2
 )
-xt "92750,79000,126250,100000"
-pts [
-"126250,79000"
-"116000,79000"
-"116000,100000"
+xt "92750,79000,127250,100000"
+pts [
+"127250,79000"
+"120000,79000"
+"120000,100000"
 "92750,100000"
 ]
 )
-start &88
-end &214
+start &92
+end &226
 sat 32
 eat 32
@@ -16892,13 +17913,13 @@
 va (VaSet
 )
-xt "119000,78000,126000,79000"
+xt "120000,78000,127000,79000"
 st "config_addr : (7:0)"
-blo "119000,78800"
+blo "120000,78800"
 tm "WireNameMgr"
 )
 )
-on &230
-)
-*562 (Wire
+on &242
+)
+*606 (Wire
 uid 5098,0
 shape (OrthoPolyLine
@@ -16913,5 +17934,5 @@
 ]
 )
-start &215
+start &227
 sat 32
 eat 16
@@ -16932,7 +17953,7 @@
 )
 )
-on &231
-)
-*563 (Wire
+on &243
+)
+*607 (Wire
 uid 5106,0
 shape (OrthoPolyLine
@@ -16941,14 +17962,14 @@
 vasetType 3
 )
-xt "92750,84000,126250,106000"
+xt "92750,84000,127250,106000"
 pts [
 "92750,106000"
-"121000,106000"
-"121000,84000"
-"126250,84000"
-]
-)
-start &216
-end &89
+"124000,106000"
+"124000,84000"
+"127250,84000"
+]
+)
+start &228
+end &93
 sat 32
 eat 32
@@ -16969,7 +17990,7 @@
 )
 )
-on &232
-)
-*564 (Wire
+on &244
+)
+*608 (Wire
 uid 5114,0
 shape (OrthoPolyLine
@@ -16979,14 +18000,14 @@
 lineWidth 2
 )
-xt "92750,80000,126250,101000"
+xt "92750,80000,127250,101000"
 pts [
 "92750,101000"
-"117000,101000"
-"117000,80000"
-"126250,80000"
-]
-)
-start &217
-end &90
+"121000,101000"
+"121000,80000"
+"127250,80000"
+]
+)
+start &229
+end &94
 sat 32
 eat 32
@@ -17008,7 +18029,7 @@
 )
 )
-on &233
-)
-*565 (Wire
+on &245
+)
+*609 (Wire
 uid 5122,0
 shape (OrthoPolyLine
@@ -17017,14 +18038,14 @@
 vasetType 3
 )
-xt "92750,82000,126250,104000"
-pts [
-"126250,82000"
-"119000,82000"
-"119000,104000"
+xt "92750,82000,127250,104000"
+pts [
+"127250,82000"
+"122000,82000"
+"122000,104000"
 "92750,104000"
 ]
 )
-start &92
-end &219
+start &96
+end &231
 sat 32
 eat 32
@@ -17039,13 +18060,13 @@
 va (VaSet
 )
-xt "121000,81000,126300,82000"
+xt "122000,81000,127300,82000"
 st "config_wr_en"
-blo "121000,81800"
+blo "122000,81800"
 tm "WireNameMgr"
 )
 )
-on &234
-)
-*566 (Wire
+on &246
+)
+*610 (Wire
 uid 5130,0
 shape (OrthoPolyLine
@@ -17054,14 +18075,14 @@
 vasetType 3
 )
-xt "92750,83000,126250,105000"
-pts [
-"126250,83000"
-"120000,83000"
-"120000,105000"
+xt "92750,83000,127250,105000"
+pts [
+"127250,83000"
+"123000,83000"
+"123000,105000"
 "92750,105000"
 ]
 )
-start &94
-end &221
+start &98
+end &233
 sat 32
 eat 32
@@ -17076,16 +18097,16 @@
 va (VaSet
 )
-xt "121000,82000,126200,83000"
+xt "122000,82000,127200,83000"
 st "config_rd_en"
-blo "121000,82800"
+blo "122000,82800"
 tm "WireNameMgr"
 )
 )
-on &235
-)
-*567 (Wire
+on &247
+)
+*611 (Wire
 uid 5138,0
 optionalChildren [
-*568 (BdJunction
+*612 (BdJunction
 uid 5400,0
 ps "OnConnectorStrategy"
@@ -17113,5 +18134,5 @@
 ]
 )
-start &218
+start &230
 end &35
 ss 0
@@ -17135,7 +18156,7 @@
 )
 )
-on &154
-)
-*569 (Wire
+on &161
+)
+*613 (Wire
 uid 5146,0
 shape (OrthoPolyLine
@@ -17150,6 +18171,6 @@
 ]
 )
-start &220
-end &258
+start &232
+end &269
 es 0
 sat 32
@@ -17171,7 +18192,7 @@
 )
 )
-on &236
-)
-*570 (Wire
+on &248
+)
+*614 (Wire
 uid 5168,0
 shape (OrthoPolyLine
@@ -17186,6 +18207,6 @@
 ]
 )
-start &568
-end &131
+start &612
+end &137
 sat 32
 eat 32
@@ -17207,7 +18228,7 @@
 )
 )
-on &154
-)
-*571 (Wire
+on &161
+)
+*615 (Wire
 uid 5184,0
 shape (OrthoPolyLine
@@ -17224,5 +18245,5 @@
 ]
 )
-start &222
+start &234
 end &47
 sat 32
@@ -17244,7 +18265,7 @@
 )
 )
-on &237
-)
-*572 (Wire
+on &249
+)
+*616 (Wire
 uid 5190,0
 shape (OrthoPolyLine
@@ -17261,5 +18282,5 @@
 ]
 )
-start &223
+start &235
 end &46
 sat 32
@@ -17281,7 +18302,7 @@
 )
 )
-on &238
-)
-*573 (Wire
+on &250
+)
+*617 (Wire
 uid 5222,0
 shape (OrthoPolyLine
@@ -17291,11 +18312,11 @@
 lineWidth 2
 )
-xt "148750,71000,153000,71000"
-pts [
-"148750,71000"
-"153000,71000"
-]
-)
-start &86
+xt "149750,71000,154000,71000"
+pts [
+"149750,71000"
+"154000,71000"
+]
+)
+start &90
 end &19
 sat 32
@@ -17315,51 +18336,13 @@
 isHidden 1
 )
-xt "150750,70000,152150,71000"
+xt "151750,70000,153150,71000"
 st "led"
-blo "150750,70800"
+blo "151750,70800"
 tm "WireNameMgr"
 )
 )
-on &239
-)
-*574 (Wire
-uid 5281,0
-shape (OrthoPolyLine
-uid 5282,0
-va (VaSet
-vasetType 3
-)
-xt "40750,53000,126250,59000"
-pts [
-"126250,59000"
-"73000,59000"
-"73000,53000"
-"40750,53000"
-]
-)
-start &87
-end &48
-sat 32
-eat 32
-st 0
-sf 1
-si 0
-tg (WTG
-uid 5283,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 5284,0
-va (VaSet
-)
-xt "121250,58000,124850,59000"
-st "s_trigger"
-blo "121250,58800"
-tm "WireNameMgr"
-)
-)
-on &240
-)
-*575 (Wire
+on &251
+)
+*618 (Wire
 uid 5404,0
 shape (OrthoPolyLine
@@ -17376,6 +18359,6 @@
 ]
 )
-start &259
-end &50
+start &270
+end &49
 sat 32
 eat 32
@@ -17396,7 +18379,7 @@
 )
 )
-on &243
-)
-*576 (Wire
+on &254
+)
+*619 (Wire
 uid 5474,0
 shape (OrthoPolyLine
@@ -17413,6 +18396,6 @@
 ]
 )
-start &262
-end &52
+start &273
+end &51
 sat 32
 eat 32
@@ -17433,7 +18416,7 @@
 )
 )
-on &241
-)
-*577 (Wire
+on &252
+)
+*620 (Wire
 uid 5480,0
 shape (OrthoPolyLine
@@ -17450,6 +18433,6 @@
 ]
 )
-start &261
-end &51
+start &272
+end &50
 sat 32
 eat 32
@@ -17470,7 +18453,7 @@
 )
 )
-on &242
-)
-*578 (Wire
+on &253
+)
+*621 (Wire
 uid 5582,0
 shape (OrthoPolyLine
@@ -17486,5 +18469,5 @@
 ]
 )
-end &213
+end &225
 sat 16
 eat 32
@@ -17505,11 +18488,11 @@
 )
 )
-on &170
-)
-*579 (Wire
+on &177
+)
+*622 (Wire
 uid 5602,0
 optionalChildren [
-&558
-*580 (BdJunction
+&602
+*623 (BdJunction
 uid 6086,0
 ps "OnConnectorStrategy"
@@ -17541,5 +18524,5 @@
 )
 start &23
-end &310
+end &321
 sat 32
 eat 32
@@ -17562,7 +18545,7 @@
 )
 )
-on &171
-)
-*581 (Wire
+on &178
+)
+*624 (Wire
 uid 5626,0
 shape (OrthoPolyLine
@@ -17578,5 +18561,5 @@
 )
 start &45
-end &248
+end &259
 sat 32
 eat 32
@@ -17598,7 +18581,7 @@
 )
 )
-on &245
-)
-*582 (Wire
+on &256
+)
+*625 (Wire
 uid 5634,0
 shape (OrthoPolyLine
@@ -17615,5 +18598,5 @@
 )
 start &38
-end &249
+end &260
 sat 32
 eat 32
@@ -17636,7 +18619,7 @@
 )
 )
-on &244
-)
-*583 (Wire
+on &255
+)
+*626 (Wire
 uid 5646,0
 shape (OrthoPolyLine
@@ -17652,5 +18635,5 @@
 ]
 )
-end &251
+end &262
 sat 16
 eat 32
@@ -17672,7 +18655,7 @@
 )
 )
-on &168
-)
-*584 (Wire
+on &175
+)
+*627 (Wire
 uid 5745,0
 shape (OrthoPolyLine
@@ -17689,6 +18672,6 @@
 ]
 )
-start &54
-end &260
+start &53
+end &271
 sat 32
 eat 32
@@ -17710,7 +18693,7 @@
 )
 )
-on &255
-)
-*585 (Wire
+on &266
+)
+*628 (Wire
 uid 5805,0
 shape (OrthoPolyLine
@@ -17725,5 +18708,5 @@
 ]
 )
-end &265
+end &276
 sat 16
 eat 32
@@ -17744,7 +18727,7 @@
 )
 )
-on &170
-)
-*586 (Wire
+on &177
+)
+*629 (Wire
 uid 5813,0
 shape (OrthoPolyLine
@@ -17759,6 +18742,6 @@
 ]
 )
-start &346
-end &276
+start &357
+end &287
 sat 32
 eat 32
@@ -17782,7 +18765,7 @@
 )
 )
-on &272
-)
-*587 (Wire
+on &283
+)
+*630 (Wire
 uid 5821,0
 shape (OrthoPolyLine
@@ -17797,6 +18780,6 @@
 ]
 )
-start &268
-end &277
+start &279
+end &288
 sat 32
 eat 32
@@ -17820,7 +18803,7 @@
 )
 )
-on &273
-)
-*588 (Wire
+on &284
+)
+*631 (Wire
 uid 5829,0
 shape (OrthoPolyLine
@@ -17835,6 +18818,6 @@
 ]
 )
-start &263
-end &278
+start &274
+end &289
 sat 32
 eat 32
@@ -17858,7 +18841,7 @@
 )
 )
-on &274
-)
-*589 (Wire
+on &285
+)
+*632 (Wire
 uid 5837,0
 shape (OrthoPolyLine
@@ -17874,6 +18857,6 @@
 ]
 )
-start &264
-end &279
+start &275
+end &290
 sat 32
 eat 32
@@ -17898,7 +18881,7 @@
 )
 )
-on &275
-)
-*590 (Wire
+on &286
+)
+*633 (Wire
 uid 5950,0
 shape (OrthoPolyLine
@@ -17907,14 +18890,14 @@
 vasetType 3
 )
-xt "40750,54000,126250,60000"
-pts [
-"126250,60000"
-"72000,60000"
-"72000,54000"
+xt "40750,54000,127250,60000"
+pts [
+"127250,60000"
+"110000,60000"
+"110000,54000"
 "40750,54000"
 ]
 )
-start &93
-end &56
+start &97
+end &55
 sat 32
 eat 32
@@ -17930,13 +18913,13 @@
 va (VaSet
 )
-xt "120250,59000,124850,60000"
+xt "121250,59000,125850,60000"
 st "new_config"
-blo "120250,59800"
+blo "121250,59800"
 tm "WireNameMgr"
 )
 )
-on &280
-)
-*591 (Wire
+on &291
+)
+*634 (Wire
 uid 5962,0
 shape (OrthoPolyLine
@@ -17945,14 +18928,14 @@
 vasetType 3
 )
-xt "40750,55000,126250,61000"
-pts [
-"126250,61000"
-"71000,61000"
-"71000,55000"
+xt "40750,55000,127250,61000"
+pts [
+"127250,61000"
+"111000,61000"
+"111000,55000"
 "40750,55000"
 ]
 )
-start &91
-end &55
+start &95
+end &54
 sat 32
 eat 32
@@ -17968,13 +18951,13 @@
 va (VaSet
 )
-xt "119250,60000,124850,61000"
+xt "120250,60000,125850,61000"
 st "config_started"
-blo "119250,60800"
+blo "120250,60800"
 tm "WireNameMgr"
 )
 )
-on &281
-)
-*592 (Wire
+on &292
+)
+*635 (Wire
 uid 6002,0
 shape (OrthoPolyLine
@@ -17991,6 +18974,6 @@
 ]
 )
-start &224
-end &57
+start &236
+end &56
 sat 32
 eat 32
@@ -18012,7 +18995,7 @@
 )
 )
-on &283
-)
-*593 (Wire
+on &294
+)
+*636 (Wire
 uid 6008,0
 shape (OrthoPolyLine
@@ -18029,6 +19012,6 @@
 ]
 )
-start &266
-end &59
+start &277
+end &58
 sat 32
 eat 32
@@ -18050,7 +19033,7 @@
 )
 )
-on &282
-)
-*594 (Wire
+on &293
+)
+*637 (Wire
 uid 6018,0
 shape (OrthoPolyLine
@@ -18062,11 +19045,11 @@
 pts [
 "40750,71000"
-"63000,71000"
-"63000,76000"
+"62000,71000"
+"62000,76000"
 "71250,76000"
 ]
 )
-start &58
-end &133
+start &57
+end &139
 sat 32
 eat 32
@@ -18088,7 +19071,7 @@
 )
 )
-on &284
-)
-*595 (Wire
+on &295
+)
+*638 (Wire
 uid 6064,0
 shape (OrthoPolyLine
@@ -18103,5 +19086,5 @@
 ]
 )
-end &60
+end &59
 sat 16
 eat 32
@@ -18123,10 +19106,10 @@
 )
 )
-on &236
-)
-*596 (Wire
+on &248
+)
+*639 (Wire
 uid 6072,0
 optionalChildren [
-*597 (BdJunction
+*640 (BdJunction
 uid 9745,0
 ps "OnConnectorStrategy"
@@ -18154,6 +19137,6 @@
 ]
 )
-start &369
-end &557
+start &380
+end &601
 sat 32
 eat 32
@@ -18176,7 +19159,7 @@
 )
 )
-on &171
-)
-*598 (Wire
+on &178
+)
+*641 (Wire
 uid 6082,0
 shape (OrthoPolyLine
@@ -18193,6 +19176,6 @@
 ]
 )
-start &118
-end &580
+start &124
+end &623
 sat 32
 eat 32
@@ -18215,7 +19198,7 @@
 )
 )
-on &171
-)
-*599 (Wire
+on &178
+)
+*642 (Wire
 uid 6160,0
 shape (OrthoPolyLine
@@ -18230,6 +19213,6 @@
 ]
 )
-start &267
-end &286
+start &278
+end &297
 sat 32
 eat 32
@@ -18253,7 +19236,7 @@
 )
 )
-on &285
-)
-*600 (Wire
+on &296
+)
+*643 (Wire
 uid 6276,0
 shape (OrthoPolyLine
@@ -18268,5 +19251,5 @@
 ]
 )
-end &110
+end &116
 sat 16
 eat 32
@@ -18287,7 +19270,7 @@
 )
 )
-on &168
-)
-*601 (Wire
+on &175
+)
+*644 (Wire
 uid 6362,0
 shape (OrthoPolyLine
@@ -18296,12 +19279,12 @@
 vasetType 3
 )
-xt "148750,75000,153000,75000"
-pts [
-"148750,75000"
-"153000,75000"
-]
-)
-start &95
-end &288
+xt "149750,75000,154000,75000"
+pts [
+"149750,75000"
+"154000,75000"
+]
+)
+start &99
+end &299
 sat 32
 eat 32
@@ -18319,13 +19302,13 @@
 isHidden 1
 )
-xt "150000,74000,153000,75000"
+xt "151000,74000,154000,75000"
 st "denable"
-blo "150000,74800"
+blo "151000,74800"
 tm "WireNameMgr"
 )
 )
-on &287
-)
-*602 (Wire
+on &298
+)
+*645 (Wire
 uid 6452,0
 shape (OrthoPolyLine
@@ -18334,11 +19317,11 @@
 vasetType 3
 )
-xt "148750,76000,154000,76000"
-pts [
-"148750,76000"
-"154000,76000"
-]
-)
-start &96
+xt "149750,76000,155000,76000"
+pts [
+"149750,76000"
+"155000,76000"
+]
+)
+start &100
 sat 32
 eat 16
@@ -18355,13 +19338,13 @@
 va (VaSet
 )
-xt "155000,76000,160400,77000"
+xt "156000,76000,161400,77000"
 st "dwrite_enable"
-blo "155000,76800"
+blo "156000,76800"
 tm "WireNameMgr"
 )
 )
-on &289
-)
-*603 (Wire
+on &300
+)
+*646 (Wire
 uid 6540,0
 shape (OrthoPolyLine
@@ -18376,5 +19359,5 @@
 ]
 )
-start &294
+start &305
 end &41
 sat 32
@@ -18398,7 +19381,7 @@
 )
 )
-on &308
-)
-*604 (Wire
+on &319
+)
+*647 (Wire
 uid 6548,0
 shape (OrthoPolyLine
@@ -18409,11 +19392,13 @@
 xt "7000,61000,15000,61000"
 pts [
+"15000,61000"
 "7000,61000"
-"15000,61000"
-]
-)
-start &296
-sat 32
-eat 16
+]
+)
+end &307
+ss 0
+es 0
+sat 16
+eat 32
 stc 0
 st 0
@@ -18428,13 +19413,13 @@
 va (VaSet
 )
-xt "7000,60000,12400,61000"
+xt "15000,60000,20400,61000"
 st "dwrite_enable"
-blo "7000,60800"
+blo "15000,60800"
 tm "WireNameMgr"
 )
 )
-on &289
-)
-*605 (Wire
+on &300
+)
+*648 (Wire
 uid 8416,0
 shape (OrthoPolyLine
@@ -18443,12 +19428,12 @@
 vasetType 3
 )
-xt "103750,75000,126250,75000"
+xt "103750,75000,127250,75000"
 pts [
 "103750,75000"
-"126250,75000"
-]
-)
-start &134
-end &97
+"127250,75000"
+]
+)
+start &140
+end &101
 sat 32
 eat 32
@@ -18470,79 +19455,7 @@
 )
 )
-on &320
-)
-*606 (Wire
-uid 8510,0
-shape (OrthoPolyLine
-uid 8511,0
-va (VaSet
-vasetType 3
-lineWidth 2
-)
-xt "92750,110000,102000,110000"
-pts [
-"92750,110000"
-"102000,110000"
-]
-)
-start &225
-sat 32
-eat 16
-sty 1
-st 0
-sf 1
-si 0
-tg (WTG
-uid 8514,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 8515,0
-va (VaSet
-)
-xt "94000,109000,101200,110000"
-st "drs_address : (3:0)"
-blo "94000,109800"
-tm "WireNameMgr"
-)
-)
-on &321
-)
-*607 (Wire
-uid 8518,0
-shape (OrthoPolyLine
-uid 8519,0
-va (VaSet
-vasetType 3
-)
-xt "92750,111000,102000,111000"
-pts [
-"92750,111000"
-"102000,111000"
-]
-)
-start &226
-sat 32
-eat 16
-st 0
-sf 1
-si 0
-tg (WTG
-uid 8522,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 8523,0
-va (VaSet
-)
-xt "94000,110000,101200,111000"
-st "drs_address_mode"
-blo "94000,110800"
-tm "WireNameMgr"
-)
-)
-on &322
-)
-*608 (Wire
+on &331
+)
+*649 (Wire
 uid 8577,0
 shape (OrthoPolyLine
@@ -18552,8 +19465,9 @@
 lineWidth 2
 )
-xt "7000,57000,18250,57000"
-pts [
-"18250,57000"
-"7000,57000"
+xt "13000,64000,18250,64000"
+pts [
+"18250,64000"
+"13000,64000"
+"13000,64000"
 ]
 )
@@ -18573,13 +19487,13 @@
 va (VaSet
 )
-xt "8000,56000,18400,57000"
+xt "8000,62000,18400,63000"
 st "drs_channel_internal : (3:0)"
-blo "8000,56800"
+blo "8000,62800"
 tm "WireNameMgr"
 )
 )
-on &344
-)
-*609 (Wire
+on &355
+)
+*650 (Wire
 uid 8587,0
 shape (OrthoPolyLine
@@ -18595,5 +19509,5 @@
 ]
 )
-end &324
+end &335
 sat 16
 eat 32
@@ -18617,7 +19531,7 @@
 )
 )
-on &344
-)
-*610 (Wire
+on &355
+)
+*651 (Wire
 uid 8595,0
 shape (OrthoPolyLine
@@ -18633,5 +19547,5 @@
 ]
 )
-end &329
+end &340
 sat 16
 eat 32
@@ -18655,7 +19569,7 @@
 )
 )
-on &321
-)
-*611 (Wire
+on &332
+)
+*652 (Wire
 uid 8603,0
 shape (OrthoPolyLine
@@ -18671,5 +19585,5 @@
 ]
 )
-end &331
+end &342
 sat 16
 eat 32
@@ -18692,7 +19606,7 @@
 )
 )
-on &322
-)
-*612 (Wire
+on &333
+)
+*653 (Wire
 uid 8732,0
 shape (OrthoPolyLine
@@ -18709,6 +19623,6 @@
 ]
 )
-start &257
-end &351
+start &268
+end &362
 sat 32
 eat 32
@@ -18730,7 +19644,7 @@
 )
 )
-on &363
-)
-*613 (Wire
+on &374
+)
+*654 (Wire
 uid 8738,0
 shape (OrthoPolyLine
@@ -18745,5 +19659,5 @@
 ]
 )
-end &349
+end &360
 sat 16
 eat 32
@@ -18766,7 +19680,7 @@
 )
 )
-on &364
-)
-*614 (Wire
+on &375
+)
+*655 (Wire
 uid 8752,0
 shape (OrthoPolyLine
@@ -18775,11 +19689,11 @@
 vasetType 3
 )
-xt "148750,77000,154000,77000"
-pts [
-"148750,77000"
-"154000,77000"
-]
-)
-start &98
+xt "149750,77000,155000,77000"
+pts [
+"149750,77000"
+"155000,77000"
+]
+)
+start &102
 sat 32
 eat 16
@@ -18795,13 +19709,13 @@
 va (VaSet
 )
-xt "155000,77000,159700,78000"
+xt "156000,77000,160700,78000"
 st "sclk_enable"
-blo "155000,77800"
+blo "156000,77800"
 tm "WireNameMgr"
 )
 )
-on &364
-)
-*615 (Wire
+on &375
+)
+*656 (Wire
 uid 9006,0
 shape (OrthoPolyLine
@@ -18816,6 +19730,6 @@
 ]
 )
-start &61
-end &366
+start &60
+end &377
 sat 32
 eat 32
@@ -18839,7 +19753,7 @@
 )
 )
-on &365
-)
-*616 (Wire
+on &376
+)
+*657 (Wire
 uid 9233,0
 shape (OrthoPolyLine
@@ -18848,11 +19762,11 @@
 vasetType 3
 )
-xt "148750,81000,154000,81000"
-pts [
-"148750,81000"
-"154000,81000"
-]
-)
-start &99
+xt "149750,81000,155000,81000"
+pts [
+"149750,81000"
+"155000,81000"
+]
+)
+start &103
 sat 32
 eat 16
@@ -18868,13 +19782,13 @@
 va (VaSet
 )
-xt "155000,81000,159900,82000"
+xt "156000,81000,160900,82000"
 st "ps_direction"
-blo "155000,81800"
+blo "156000,81800"
 tm "WireNameMgr"
 )
 )
-on &386
-)
-*617 (Wire
+on &398
+)
+*658 (Wire
 uid 9241,0
 shape (OrthoPolyLine
@@ -18883,11 +19797,11 @@
 vasetType 3
 )
-xt "148750,82000,154000,82000"
-pts [
-"148750,82000"
-"154000,82000"
-]
-)
-start &100
+xt "149750,82000,155000,82000"
+pts [
+"149750,82000"
+"155000,82000"
+]
+)
+start &104
 sat 32
 eat 16
@@ -18903,16 +19817,16 @@
 va (VaSet
 )
-xt "155000,82000,162000,83000"
+xt "156000,82000,163000,83000"
 st "ps_do_phase_shift"
-blo "155000,82800"
+blo "156000,82800"
 tm "WireNameMgr"
 )
 )
-on &387
-)
-*618 (Wire
+on &399
+)
+*659 (Wire
 uid 9253,0
 optionalChildren [
-*619 (BdJunction
+*660 (BdJunction
 uid 9507,0
 ps "OnConnectorStrategy"
@@ -18938,5 +19852,5 @@
 ]
 )
-end &381
+end &392
 sat 16
 eat 32
@@ -18957,10 +19871,10 @@
 )
 )
-on &386
-)
-*620 (Wire
+on &398
+)
+*661 (Wire
 uid 9261,0
 optionalChildren [
-*621 (BdJunction
+*662 (BdJunction
 uid 9513,0
 ps "OnConnectorStrategy"
@@ -18986,5 +19900,5 @@
 ]
 )
-end &382
+end &393
 sat 16
 eat 32
@@ -19005,7 +19919,7 @@
 )
 )
-on &387
-)
-*622 (Wire
+on &399
+)
+*663 (Wire
 uid 9269,0
 shape (OrthoPolyLine
@@ -19020,6 +19934,6 @@
 ]
 )
-start &379
-end &389
+start &390
+end &401
 sat 32
 eat 32
@@ -19043,7 +19957,7 @@
 )
 )
-on &388
-)
-*623 (Wire
+on &400
+)
+*664 (Wire
 uid 9283,0
 shape (OrthoPolyLine
@@ -19058,6 +19972,6 @@
 ]
 )
-start &378
-end &391
+start &389
+end &403
 sat 32
 eat 32
@@ -19081,7 +19995,7 @@
 )
 )
-on &390
-)
-*624 (Wire
+on &402
+)
+*665 (Wire
 uid 9297,0
 shape (OrthoPolyLine
@@ -19096,6 +20010,6 @@
 ]
 )
-start &377
-end &393
+start &388
+end &405
 sat 32
 eat 32
@@ -19119,7 +20033,7 @@
 )
 )
-on &392
-)
-*625 (Wire
+on &404
+)
+*666 (Wire
 uid 9311,0
 shape (OrthoPolyLine
@@ -19134,6 +20048,6 @@
 ]
 )
-start &376
-end &395
+start &387
+end &407
 sat 32
 eat 32
@@ -19157,7 +20071,7 @@
 )
 )
-on &394
-)
-*626 (Wire
+on &406
+)
+*667 (Wire
 uid 9325,0
 shape (OrthoPolyLine
@@ -19172,6 +20086,6 @@
 ]
 )
-start &375
-end &397
+start &386
+end &409
 sat 32
 eat 32
@@ -19195,7 +20109,7 @@
 )
 )
-on &396
-)
-*627 (Wire
+on &408
+)
+*668 (Wire
 uid 9353,0
 shape (OrthoPolyLine
@@ -19210,6 +20124,6 @@
 ]
 )
-start &374
-end &399
+start &385
+end &411
 sat 32
 eat 32
@@ -19233,7 +20147,7 @@
 )
 )
-on &398
-)
-*628 (Wire
+on &410
+)
+*669 (Wire
 uid 9367,0
 shape (OrthoPolyLine
@@ -19249,6 +20163,6 @@
 ]
 )
-start &373
-end &401
+start &384
+end &413
 sat 32
 eat 32
@@ -19273,7 +20187,7 @@
 )
 )
-on &400
-)
-*629 (Wire
+on &412
+)
+*670 (Wire
 uid 9382,0
 shape (OrthoPolyLine
@@ -19288,6 +20202,6 @@
 ]
 )
-start &372
-end &403
+start &383
+end &415
 sat 32
 eat 32
@@ -19311,7 +20225,7 @@
 )
 )
-on &402
-)
-*630 (Wire
+on &414
+)
+*671 (Wire
 uid 9397,0
 shape (OrthoPolyLine
@@ -19326,6 +20240,6 @@
 ]
 )
-start &371
-end &405
+start &382
+end &417
 sat 32
 eat 32
@@ -19349,7 +20263,7 @@
 )
 )
-on &404
-)
-*631 (Wire
+on &416
+)
+*672 (Wire
 uid 9503,0
 shape (OrthoPolyLine
@@ -19365,6 +20279,6 @@
 ]
 )
-start &619
-end &420
+start &660
+end &432
 sat 32
 eat 32
@@ -19387,7 +20301,7 @@
 )
 )
-on &386
-)
-*632 (Wire
+on &398
+)
+*673 (Wire
 uid 9509,0
 shape (OrthoPolyLine
@@ -19403,6 +20317,6 @@
 ]
 )
-start &621
-end &407
+start &662
+end &419
 sat 32
 eat 32
@@ -19425,7 +20339,7 @@
 )
 )
-on &387
-)
-*633 (Wire
+on &399
+)
+*674 (Wire
 uid 9517,0
 shape (OrthoPolyLine
@@ -19442,6 +20356,6 @@
 ]
 )
-start &409
-end &432
+start &421
+end &444
 sat 32
 eat 32
@@ -19465,7 +20379,7 @@
 )
 )
-on &435
-)
-*634 (Wire
+on &447
+)
+*675 (Wire
 uid 9539,0
 shape (OrthoPolyLine
@@ -19482,6 +20396,6 @@
 ]
 )
-start &422
-end &433
+start &434
+end &445
 sat 32
 eat 32
@@ -19505,7 +20419,7 @@
 )
 )
-on &434
-)
-*635 (Wire
+on &446
+)
+*676 (Wire
 uid 9673,0
 shape (OrthoPolyLine
@@ -19521,6 +20435,6 @@
 ]
 )
-start &539
-end &437
+start &583
+end &449
 sat 32
 eat 32
@@ -19543,7 +20457,7 @@
 )
 )
-on &170
-)
-*636 (Wire
+on &177
+)
+*677 (Wire
 uid 9741,0
 shape (OrthoPolyLine
@@ -19560,6 +20474,6 @@
 ]
 )
-start &597
-end &450
+start &640
+end &462
 sat 32
 eat 32
@@ -19582,7 +20496,7 @@
 )
 )
-on &171
-)
-*637 (Wire
+on &178
+)
+*678 (Wire
 uid 9747,0
 shape (OrthoPolyLine
@@ -19599,6 +20513,6 @@
 ]
 )
-start &541
-end &463
+start &585
+end &475
 sat 32
 eat 32
@@ -19621,7 +20535,7 @@
 )
 )
-on &168
-)
-*638 (Wire
+on &175
+)
+*679 (Wire
 uid 9755,0
 shape (OrthoPolyLine
@@ -19636,6 +20550,6 @@
 ]
 )
-start &439
-end &475
+start &451
+end &487
 sat 32
 eat 32
@@ -19659,7 +20573,7 @@
 )
 )
-on &476
-)
-*639 (Wire
+on &488
+)
+*680 (Wire
 uid 9771,0
 shape (OrthoPolyLine
@@ -19674,6 +20588,6 @@
 ]
 )
-start &452
-end &477
+start &464
+end &489
 sat 32
 eat 32
@@ -19697,7 +20611,7 @@
 )
 )
-on &478
-)
-*640 (Wire
+on &490
+)
+*681 (Wire
 uid 9787,0
 shape (OrthoPolyLine
@@ -19712,6 +20626,6 @@
 ]
 )
-start &465
-end &479
+start &477
+end &491
 sat 32
 eat 32
@@ -19735,7 +20649,7 @@
 )
 )
-on &480
-)
-*641 (Wire
+on &492
+)
+*682 (Wire
 uid 9943,0
 shape (OrthoPolyLine
@@ -19744,11 +20658,11 @@
 vasetType 3
 )
-xt "148750,83000,154000,83000"
-pts [
-"148750,83000"
-"154000,83000"
-]
-)
-start &101
+xt "149750,83000,155000,83000"
+pts [
+"149750,83000"
+"155000,83000"
+]
+)
+start &105
 sat 32
 eat 16
@@ -19764,13 +20678,13 @@
 va (VaSet
 )
-xt "155000,83000,158300,84000"
+xt "156000,83000,159300,84000"
 st "ps_reset"
-blo "155000,83800"
+blo "156000,83800"
 tm "WireNameMgr"
 )
 )
-on &481
-)
-*642 (Wire
+on &493
+)
+*683 (Wire
 uid 9951,0
 shape (OrthoPolyLine
@@ -19779,11 +20693,11 @@
 vasetType 3
 )
-xt "148750,85000,154000,85000"
-pts [
-"148750,85000"
-"154000,85000"
-]
-)
-start &102
+xt "149750,85000,155000,85000"
+pts [
+"149750,85000"
+"155000,85000"
+]
+)
+start &106
 sat 32
 eat 16
@@ -19799,13 +20713,13 @@
 va (VaSet
 )
-xt "155000,85000,160000,86000"
+xt "156000,85000,161000,86000"
 st "srclk_enable"
-blo "155000,85800"
+blo "156000,85800"
 tm "WireNameMgr"
 )
 )
-on &482
-)
-*643 (Wire
+on &494
+)
+*684 (Wire
 uid 10010,0
 shape (OrthoPolyLine
@@ -19822,6 +20736,6 @@
 ]
 )
-start &204
-end &487
+start &211
+end &499
 sat 32
 eat 32
@@ -19843,7 +20757,7 @@
 )
 )
-on &501
-)
-*644 (Wire
+on &513
+)
+*685 (Wire
 uid 10018,0
 shape (OrthoPolyLine
@@ -19858,5 +20772,5 @@
 ]
 )
-end &489
+end &501
 sat 16
 eat 32
@@ -19879,5 +20793,500 @@
 )
 )
-on &482
+on &494
+)
+*686 (Wire
+uid 10036,0
+shape (OrthoPolyLine
+uid 10037,0
+va (VaSet
+vasetType 3
+)
+xt "-26000,21000,-20750,21000"
+pts [
+"-26000,21000"
+"-20750,21000"
+]
+)
+end &394
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 10040,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10041,0
+va (VaSet
+)
+xt "-25000,20000,-21700,21000"
+st "ps_reset"
+blo "-25000,20800"
+tm "WireNameMgr"
+)
+)
+on &493
+)
+*687 (Wire
+uid 10194,0
+shape (OrthoPolyLine
+uid 10195,0
+va (VaSet
+vasetType 3
+)
+xt "92750,85000,127250,110000"
+pts [
+"92750,110000"
+"125000,110000"
+"125000,85000"
+"127250,85000"
+]
+)
+start &237
+end &107
+ss 0
+es 0
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10198,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10199,0
+va (VaSet
+)
+xt "94750,109000,100350,110000"
+st "config_rw_ack"
+blo "94750,109800"
+tm "WireNameMgr"
+)
+)
+on &514
+)
+*688 (Wire
+uid 10202,0
+shape (OrthoPolyLine
+uid 10203,0
+va (VaSet
+vasetType 3
+)
+xt "92750,86000,127250,111000"
+pts [
+"92750,111000"
+"126000,111000"
+"126000,86000"
+"127250,86000"
+]
+)
+start &238
+end &108
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10206,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10207,0
+va (VaSet
+)
+xt "94750,110000,101050,111000"
+st "config_rw_ready"
+blo "94750,110800"
+tm "WireNameMgr"
+)
+)
+on &515
+)
+*689 (Wire
+uid 10266,0
+shape (OrthoPolyLine
+uid 10267,0
+va (VaSet
+vasetType 3
+)
+xt "121000,64000,127250,64000"
+pts [
+"127250,64000"
+"124000,64000"
+"121000,64000"
+]
+)
+start &91
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10270,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10271,0
+va (VaSet
+)
+xt "122000,63000,125600,64000"
+st "s_trigger"
+blo "122000,63800"
+tm "WireNameMgr"
+)
+)
+on &516
+)
+*690 (Wire
+uid 10298,0
+shape (OrthoPolyLine
+uid 10299,0
+va (VaSet
+vasetType 3
+)
+xt "1750,54000,18250,54000"
+pts [
+"1750,54000"
+"18250,54000"
+]
+)
+start &216
+end &62
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10300,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10301,0
+va (VaSet
+)
+xt "3750,53000,10950,54000"
+st "start_srin_write_8b"
+blo "3750,53800"
+tm "WireNameMgr"
+)
+)
+on &517
+)
+*691 (Wire
+uid 10304,0
+shape (OrthoPolyLine
+uid 10305,0
+va (VaSet
+vasetType 3
+)
+xt "1750,55000,18250,55000"
+pts [
+"1750,55000"
+"18250,55000"
+]
+)
+start &214
+end &63
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10306,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10307,0
+va (VaSet
+)
+xt "3750,54000,9350,55000"
+st "srin_write_ack"
+blo "3750,54800"
+tm "WireNameMgr"
+)
+)
+on &518
+)
+*692 (Wire
+uid 10310,0
+shape (OrthoPolyLine
+uid 10311,0
+va (VaSet
+vasetType 3
+)
+xt "1750,56000,18250,56000"
+pts [
+"1750,56000"
+"18250,56000"
+]
+)
+start &215
+end &64
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10312,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10313,0
+va (VaSet
+)
+xt "3750,55000,10050,56000"
+st "srin_write_ready"
+blo "3750,55800"
+tm "WireNameMgr"
+)
+)
+on &519
+)
+*693 (Wire
+uid 10316,0
+shape (OrthoPolyLine
+uid 10317,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "1750,57000,18250,57000"
+pts [
+"18250,57000"
+"1750,57000"
+]
+)
+start &61
+end &212
+sat 32
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10318,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10319,0
+va (VaSet
+)
+xt "4000,56000,12000,57000"
+st "drs_srin_data : (7:0)"
+blo "4000,56800"
+tm "WireNameMgr"
+)
+)
+on &520
+)
+*694 (Wire
+uid 10322,0
+shape (OrthoPolyLine
+uid 10323,0
+va (VaSet
+vasetType 3
+)
+xt "-34000,57000,-18750,57000"
+pts [
+"-18750,57000"
+"-34000,57000"
+]
+)
+start &213
+end &522
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10326,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10327,0
+va (VaSet
+isHidden 1
+)
+xt "-24000,56000,-20300,57000"
+st "SRIN_out"
+blo "-24000,56800"
+tm "WireNameMgr"
+)
+)
+on &521
+)
+*695 (Wire
+uid 10431,0
+shape (OrthoPolyLine
+uid 10432,0
+va (VaSet
+vasetType 3
+)
+xt "-34000,68000,-30000,68000"
+pts [
+"-34000,68000"
+"-30000,68000"
+]
+)
+end &529
+sat 16
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10435,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10436,0
+va (VaSet
+)
+xt "-33000,67000,-29400,68000"
+st "s_trigger"
+blo "-33000,67800"
+tm "WireNameMgr"
+)
+)
+on &516
+)
+*696 (Wire
+uid 10439,0
+optionalChildren [
+*697 (BdJunction
+uid 10447,0
+ps "OnConnectorStrategy"
+shape (Circle
+uid 10448,0
+va (VaSet
+vasetType 1
+)
+xt "-21400,68600,-20600,69400"
+radius 400
+)
+)
+]
+shape (OrthoPolyLine
+uid 10440,0
+va (VaSet
+vasetType 3
+)
+xt "-24000,69000,18250,69000"
+pts [
+"18250,69000"
+"-24000,69000"
+]
+)
+start &30
+end &526
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10441,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10442,0
+va (VaSet
+)
+xt "14250,68000,18850,69000"
+st "trigger_out"
+blo "14250,68800"
+tm "WireNameMgr"
+)
+)
+on &546
+)
+*698 (Wire
+uid 10443,0
+shape (OrthoPolyLine
+uid 10444,0
+va (VaSet
+vasetType 3
+)
+xt "-21000,64000,-18750,69000"
+pts [
+"-18750,64000"
+"-21000,64000"
+"-21000,69000"
+]
+)
+start &115
+end &697
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10445,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10446,0
+va (VaSet
+)
+xt "-20000,68000,-15400,69000"
+st "trigger_out"
+blo "-20000,68800"
+tm "WireNameMgr"
+)
+)
+on &546
+)
+*699 (Wire
+uid 10467,0
+shape (OrthoPolyLine
+uid 10468,0
+va (VaSet
+vasetType 3
+)
+xt "40750,66000,71250,73000"
+pts [
+"71250,73000"
+"64000,73000"
+"64000,66000"
+"40750,66000"
+]
+)
+start &141
+end &65
+es 0
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 10471,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 10472,0
+va (VaSet
+)
+xt "42000,65000,49800,66000"
+st "ram_write_ready_ack"
+blo "42000,65800"
+tm "WireNameMgr"
+)
+)
+on &547
 )
 ]
@@ -19893,9 +21302,9 @@
 color "26368,26368,26368"
 )
-packageList *645 (PackageList
+packageList *700 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*646 (Text
+*701 (Text
 uid 42,0
 va (VaSet
@@ -19906,5 +21315,5 @@
 blo "-87000,1800"
 )
-*647 (MLText
+*702 (MLText
 uid 43,0
 va (VaSet
@@ -19931,5 +21340,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*648 (Text
+*703 (Text
 uid 45,0
 va (VaSet
@@ -19941,5 +21350,5 @@
 blo "20000,800"
 )
-*649 (Text
+*704 (Text
 uid 46,0
 va (VaSet
@@ -19951,5 +21360,5 @@
 blo "20000,1800"
 )
-*650 (MLText
+*705 (MLText
 uid 47,0
 va (VaSet
@@ -19961,5 +21370,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*651 (Text
+*706 (Text
 uid 48,0
 va (VaSet
@@ -19971,5 +21380,5 @@
 blo "20000,4800"
 )
-*652 (MLText
+*707 (MLText
 uid 49,0
 va (VaSet
@@ -19979,5 +21388,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*653 (Text
+*708 (Text
 uid 50,0
 va (VaSet
@@ -19989,5 +21398,5 @@
 blo "20000,5800"
 )
-*654 (MLText
+*709 (MLText
 uid 51,0
 va (VaSet
@@ -20001,6 +21410,6 @@
 )
 windowSize "1280,0,2561,1024"
-viewArea "-45840,31462,24186,89212"
-cachedDiagramExtent "-105000,-60500,162300,343294"
+viewArea "1300,44100,167081,180819"
+cachedDiagramExtent "-105000,-60500,163300,343294"
 pageSetupInfo (PageSetupInfo
 ptrCmd "eDocPrintPro,winspool,"
@@ -20027,5 +21436,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
-lastUid 10029,0
+lastUid 10547,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -20089,5 +21498,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*655 (Text
+*710 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20098,5 +21507,5 @@
 tm "BdLibraryNameMgr"
 )
-*656 (Text
+*711 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20107,5 +21516,5 @@
 tm "BlkNameMgr"
 )
-*657 (Text
+*712 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20158,5 +21567,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*658 (Text
+*713 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20166,5 +21575,5 @@
 blo "550,4300"
 )
-*659 (Text
+*714 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20174,5 +21583,5 @@
 blo "550,5300"
 )
-*660 (Text
+*715 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20223,5 +21632,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*661 (Text
+*716 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20232,5 +21641,5 @@
 tm "BdLibraryNameMgr"
 )
-*662 (Text
+*717 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20241,5 +21650,5 @@
 tm "CptNameMgr"
 )
-*663 (Text
+*718 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20295,5 +21704,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*664 (Text
+*719 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20303,5 +21712,5 @@
 blo "500,4300"
 )
-*665 (Text
+*720 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20311,5 +21720,5 @@
 blo "500,5300"
 )
-*666 (Text
+*721 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20356,5 +21765,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*667 (Text
+*722 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20364,5 +21773,5 @@
 blo "50,4300"
 )
-*668 (Text
+*723 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20372,5 +21781,5 @@
 blo "50,5300"
 )
-*669 (Text
+*724 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20413,5 +21822,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*670 (Text
+*725 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20422,5 +21831,5 @@
 tm "HdlTextNameMgr"
 )
-*671 (Text
+*726 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20825,5 +22234,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*672 (Text
+*727 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20833,5 +22242,5 @@
 blo "14100,20800"
 )
-*673 (MLText
+*728 (MLText
 va (VaSet
 )
@@ -20885,5 +22294,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*674 (Text
+*729 (Text
 va (VaSet
 font "Arial,8,1"
@@ -20893,5 +22302,5 @@
 blo "14100,20800"
 )
-*675 (MLText
+*730 (MLText
 va (VaSet
 )
@@ -20992,7 +22401,7 @@
 font "Arial,8,1"
 )
-xt "-105000,55800,-101200,56800"
+xt "-105000,56600,-101200,57600"
 st "Pre User:"
-blo "-105000,56600"
+blo "-105000,57400"
 )
 preUserText (MLText
@@ -21009,7 +22418,7 @@
 font "Arial,8,1"
 )
-xt "-105000,56800,-97900,57800"
+xt "-105000,57600,-97900,58600"
 st "Diagram Signals:"
-blo "-105000,57600"
+blo "-105000,58400"
 )
 postUserLabel (Text
@@ -21018,7 +22427,7 @@
 font "Arial,8,1"
 )
-xt "-105000,105800,-100300,106800"
+xt "-105000,115400,-100300,116400"
 st "Post User:"
-blo "-105000,106600"
+blo "-105000,116200"
 )
 postUserText (MLText
@@ -21033,44 +22442,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 225,0
+suid 242,0
 usingSuid 1
-emptyRow *676 (LEmptyRow
+emptyRow *731 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*677 (RefLabelRowHdr
-)
-*678 (TitleRowHdr
-)
-*679 (FilterRowHdr
-)
-*680 (RefLabelColHdr
+*732 (RefLabelRowHdr
+)
+*733 (TitleRowHdr
+)
+*734 (FilterRowHdr
+)
+*735 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*681 (RowExpandColHdr
+*736 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*682 (GroupColHdr
+*737 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*683 (NameColHdr
+*738 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*684 (ModeColHdr
+*739 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*685 (TypeColHdr
+*740 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*686 (BoundsColHdr
+*741 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*687 (InitColHdr
+*742 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*688 (EolColHdr
+*743 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*689 (LeafLogPort
+*744 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21086,5 +22495,5 @@
 uid 516,0
 )
-*690 (LeafLogPort
+*745 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21099,5 +22508,5 @@
 uid 518,0
 )
-*691 (LeafLogPort
+*746 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21112,5 +22521,5 @@
 uid 520,0
 )
-*692 (LeafLogPort
+*747 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21125,5 +22534,5 @@
 uid 530,0
 )
-*693 (LeafLogPort
+*748 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21138,5 +22547,5 @@
 uid 532,0
 )
-*694 (LeafLogPort
+*749 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21151,5 +22560,5 @@
 uid 534,0
 )
-*695 (LeafLogPort
+*750 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21164,5 +22573,5 @@
 uid 536,0
 )
-*696 (LeafLogPort
+*751 (LeafLogPort
 port (LogicalPort
 m 2
@@ -21177,5 +22586,5 @@
 uid 538,0
 )
-*697 (LeafLogPort
+*752 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21190,5 +22599,5 @@
 uid 540,0
 )
-*698 (LeafLogPort
+*753 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21203,5 +22612,5 @@
 uid 542,0
 )
-*699 (LeafLogPort
+*754 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21216,5 +22625,5 @@
 uid 546,0
 )
-*700 (LeafLogPort
+*755 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21227,5 +22636,5 @@
 uid 548,0
 )
-*701 (LeafLogPort
+*756 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21241,5 +22650,5 @@
 uid 1455,0
 )
-*702 (LeafLogPort
+*757 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21254,5 +22663,5 @@
 uid 1457,0
 )
-*703 (LeafLogPort
+*758 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21266,5 +22675,5 @@
 uid 1694,0
 )
-*704 (LeafLogPort
+*759 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21282,5 +22691,5 @@
 uid 1993,0
 )
-*705 (LeafLogPort
+*760 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21297,5 +22706,5 @@
 uid 2305,0
 )
-*706 (LeafLogPort
+*761 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21310,5 +22719,5 @@
 uid 2510,0
 )
-*707 (LeafLogPort
+*762 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21324,5 +22733,5 @@
 uid 2512,0
 )
-*708 (LeafLogPort
+*763 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21339,5 +22748,5 @@
 uid 2514,0
 )
-*709 (LeafLogPort
+*764 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21355,5 +22764,5 @@
 uid 2516,0
 )
-*710 (LeafLogPort
+*765 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21370,5 +22779,5 @@
 uid 2518,0
 )
-*711 (LeafLogPort
+*766 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21384,5 +22793,5 @@
 uid 2520,0
 )
-*712 (LeafLogPort
+*767 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -21398,5 +22807,5 @@
 uid 2522,0
 )
-*713 (LeafLogPort
+*768 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21410,5 +22819,5 @@
 uid 2604,0
 )
-*714 (LeafLogPort
+*769 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21423,5 +22832,5 @@
 uid 2606,0
 )
-*715 (LeafLogPort
+*770 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21436,5 +22845,5 @@
 uid 2608,0
 )
-*716 (LeafLogPort
+*771 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21448,5 +22857,5 @@
 uid 2610,0
 )
-*717 (LeafLogPort
+*772 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21460,5 +22869,5 @@
 uid 2612,0
 )
-*718 (LeafLogPort
+*773 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21473,5 +22882,5 @@
 uid 2646,0
 )
-*719 (LeafLogPort
+*774 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21486,5 +22895,5 @@
 uid 2812,0
 )
-*720 (LeafLogPort
+*775 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21498,5 +22907,5 @@
 uid 2962,0
 )
-*721 (LeafLogPort
+*776 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21510,5 +22919,5 @@
 uid 3902,0
 )
-*722 (LeafLogPort
+*777 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21522,5 +22931,5 @@
 uid 4070,0
 )
-*723 (LeafLogPort
+*778 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21534,5 +22943,5 @@
 uid 4212,0
 )
-*724 (LeafLogPort
+*779 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21545,5 +22954,5 @@
 uid 4234,0
 )
-*725 (LeafLogPort
+*780 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21557,5 +22966,5 @@
 uid 4262,0
 )
-*726 (LeafLogPort
+*781 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21568,5 +22977,5 @@
 uid 4276,0
 )
-*727 (LeafLogPort
+*782 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21581,5 +22990,5 @@
 uid 4563,0
 )
-*728 (LeafLogPort
+*783 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21593,5 +23002,5 @@
 uid 4565,0
 )
-*729 (LeafLogPort
+*784 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21606,5 +23015,5 @@
 uid 4569,0
 )
-*730 (LeafLogPort
+*785 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21620,5 +23029,5 @@
 uid 4585,0
 )
-*731 (LeafLogPort
+*786 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21633,5 +23042,5 @@
 uid 4587,0
 )
-*732 (LeafLogPort
+*787 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21644,5 +23053,5 @@
 uid 4733,0
 )
-*733 (LeafLogPort
+*788 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21655,5 +23064,5 @@
 uid 4735,0
 )
-*734 (LeafLogPort
+*789 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21666,5 +23075,5 @@
 uid 4737,0
 )
-*735 (LeafLogPort
+*790 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -21677,5 +23086,5 @@
 uid 4739,0
 )
-*736 (LeafLogPort
+*791 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21689,5 +23098,5 @@
 uid 4749,0
 )
-*737 (LeafLogPort
+*792 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21702,5 +23111,5 @@
 uid 4974,0
 )
-*738 (LeafLogPort
+*793 (LeafLogPort
 port (LogicalPort
 m 1
@@ -21715,5 +23124,5 @@
 uid 4976,0
 )
-*739 (LeafLogPort
+*794 (LeafLogPort
 port (LogicalPort
 m 4
@@ -21728,5 +23137,5 @@
 uid 5198,0
 )
-*740 (LeafLogPort
+*795 (LeafLogPort
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-litem &764
-pos 77
-dimension 20
 uid 6027,0
 )
-*876 (MRCItem
-litem &765
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 pos 29
 dimension 20
 uid 6173,0
 )
-*877 (MRCItem
-litem &766
+*940 (MRCItem
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 pos 30
 dimension 20
 uid 6375,0
 )
-*878 (MRCItem
-litem &767
+*941 (MRCItem
+litem &821
+pos 77
+dimension 20
+uid 6465,0
+)
+*942 (MRCItem
+litem &822
 pos 78
 dimension 20
-uid 6465,0
-)
-*879 (MRCItem
-litem &768
+uid 6555,0
+)
+*943 (MRCItem
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 pos 79
 dimension 20
-uid 6555,0
-)
-*880 (MRCItem
-litem &769
+uid 8421,0
+)
+*944 (MRCItem
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 pos 80
 dimension 20
-uid 8421,0
-)
-*881 (MRCItem
-litem &770
+uid 8610,0
+)
+*945 (MRCItem
+litem &825
 pos 81
 dimension 20
-uid 8610,0
-)
-*882 (MRCItem
-litem &771
+uid 8612,0
+)
+*946 (MRCItem
+litem &826
 pos 82
 dimension 20
-uid 8612,0
-)
-*883 (MRCItem
-litem &772
+uid 8614,0
+)
+*947 (MRCItem
+litem &827
 pos 83
 dimension 20
-uid 8614,0
-)
-*884 (MRCItem
-litem &773
+uid 8759,0
+)
+*948 (MRCItem
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 pos 84
 dimension 20
-uid 8759,0
-)
-*885 (MRCItem
-litem &774
+uid 8761,0
+)
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 pos 85
 dimension 20
-uid 8761,0
-)
-*886 (MRCItem
-litem &775
+uid 9019,0
+)
+*950 (MRCItem
+litem &830
 pos 86
 dimension 20
-uid 9019,0
-)
-*887 (MRCItem
-litem &776
+uid 9248,0
+)
+*951 (MRCItem
+litem &831
 pos 87
 dimension 20
-uid 9248,0
-)
-*888 (MRCItem
-litem &777
+uid 9250,0
+)
+*952 (MRCItem
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 pos 88
 dimension 20
-uid 9250,0
-)
-*889 (MRCItem
-litem &778
+uid 9556,0
+)
+*953 (MRCItem
+litem &833
 pos 89
 dimension 20
-uid 9556,0
-)
-*890 (MRCItem
-litem &779
+uid 9558,0
+)
+*954 (MRCItem
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 pos 90
 dimension 20
-uid 9558,0
-)
-*891 (MRCItem
-litem &780
+uid 9560,0
+)
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 pos 91
 dimension 20
-uid 9560,0
-)
-*892 (MRCItem
-litem &781
+uid 9562,0
+)
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 pos 92
 dimension 20
-uid 9562,0
-)
-*893 (MRCItem
-litem &782
+uid 9564,0
+)
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 pos 93
 dimension 20
-uid 9564,0
-)
-*894 (MRCItem
-litem &783
+uid 9568,0
+)
+*958 (MRCItem
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 pos 94
 dimension 20
-uid 9568,0
-)
-*895 (MRCItem
-litem &784
+uid 9570,0
+)
+*959 (MRCItem
+litem &839
 pos 95
 dimension 20
-uid 9570,0
-)
-*896 (MRCItem
-litem &785
+uid 9572,0
+)
+*960 (MRCItem
+litem &840
 pos 96
 dimension 20
-uid 9572,0
-)
-*897 (MRCItem
-litem &786
+uid 9574,0
+)
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 pos 97
 dimension 20
-uid 9574,0
-)
-*898 (MRCItem
-litem &787
+uid 9576,0
+)
+*962 (MRCItem
+litem &842
 pos 98
 dimension 20
-uid 9576,0
-)
-*899 (MRCItem
-litem &788
+uid 9578,0
+)
+*963 (MRCItem
+litem &843
 pos 99
 dimension 20
-uid 9578,0
-)
-*900 (MRCItem
-litem &789
+uid 9802,0
+)
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+litem &844
 pos 100
 dimension 20
-uid 9802,0
-)
-*901 (MRCItem
-litem &790
+uid 9804,0
+)
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 pos 101
 dimension 20
-uid 9804,0
-)
-*902 (MRCItem
-litem &791
+uid 9806,0
+)
+*966 (MRCItem
+litem &846
 pos 102
 dimension 20
-uid 9806,0
-)
-*903 (MRCItem
-litem &792
+uid 10025,0
+)
+*967 (MRCItem
+litem &847
 pos 103
 dimension 20
-uid 10025,0
-)
-*904 (MRCItem
-litem &793
+uid 10027,0
+)
+*968 (MRCItem
+litem &848
 pos 104
 dimension 20
-uid 10027,0
-)
-*905 (MRCItem
-litem &794
+uid 10029,0
+)
+*969 (MRCItem
+litem &849
 pos 105
 dimension 20
-uid 10029,0
+uid 10209,0
+)
+*970 (MRCItem
+litem &850
+pos 106
+dimension 20
+uid 10211,0
+)
+*971 (MRCItem
+litem &851
+pos 107
+dimension 20
+uid 10295,0
+)
+*972 (MRCItem
+litem &852
+pos 108
+dimension 20
+uid 10335,0
+)
+*973 (MRCItem
+litem &853
+pos 109
+dimension 20
+uid 10337,0
+)
+*974 (MRCItem
+litem &854
+pos 110
+dimension 20
+uid 10339,0
+)
+*975 (MRCItem
+litem &855
+pos 111
+dimension 20
+uid 10341,0
+)
+*976 (MRCItem
+litem &856
+pos 112
+dimension 20
+uid 10343,0
+)
+*977 (MRCItem
+litem &857
+pos 113
+dimension 20
+uid 10474,0
+)
+*978 (MRCItem
+litem &858
+pos 114
+dimension 20
+uid 10476,0
 )
 ]
@@ -23136,48 +24726,48 @@
 uid 73,0
 optionalChildren [
-*906 (MRCItem
-litem &680
+*979 (MRCItem
+litem &735
 pos 0
 dimension 20
 uid 74,0
 )
-*907 (MRCItem
-litem &682
+*980 (MRCItem
+litem &737
 pos 1
 dimension 50
 uid 75,0
 )
-*908 (MRCItem
-litem &683
+*981 (MRCItem
+litem &738
 pos 2
 dimension 100
 uid 76,0
 )
-*909 (MRCItem
-litem &684
+*982 (MRCItem
+litem &739
 pos 3
 dimension 50
 uid 77,0
 )
-*910 (MRCItem
-litem &685
+*983 (MRCItem
+litem &740
 pos 4
 dimension 100
 uid 78,0
 )
-*911 (MRCItem
-litem &686
+*984 (MRCItem
+litem &741
 pos 5
 dimension 100
 uid 79,0
 )
-*912 (MRCItem
-litem &687
+*985 (MRCItem
+litem &742
 pos 6
 dimension 50
 uid 80,0
 )
-*913 (MRCItem
-litem &688
+*986 (MRCItem
+litem &743
 pos 7
 dimension 80
@@ -23199,39 +24789,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *914 (LEmptyRow
+emptyRow *987 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*915 (RefLabelRowHdr
-)
-*916 (TitleRowHdr
-)
-*917 (FilterRowHdr
-)
-*918 (RefLabelColHdr
+*988 (RefLabelRowHdr
+)
+*989 (TitleRowHdr
+)
+*990 (FilterRowHdr
+)
+*991 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*919 (RowExpandColHdr
+*992 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*920 (GroupColHdr
+*993 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*921 (NameColHdr
+*994 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*922 (TypeColHdr
+*995 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*923 (InitColHdr
+*996 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*924 (PragmaColHdr
+*997 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*925 (EolColHdr
+*998 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*926 (LogGeneric
+*999 (LogGeneric
 generic (GiElement
 name "RAMADDRWIDTH64b"
@@ -23248,5 +24838,5 @@
 uid 95,0
 optionalChildren [
-*927 (Sheet
+*1000 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -23265,6 +24855,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *928 (MRCItem
-litem &914
+emptyMRCItem *1001 (MRCItem
+litem &987
 pos 1
 dimension 20
@@ -23272,18 +24862,18 @@
 uid 97,0
 optionalChildren [
-*929 (MRCItem
-litem &915
+*1002 (MRCItem
+litem &988
 pos 0
 dimension 20
 uid 98,0
 )
-*930 (MRCItem
-litem &916
+*1003 (MRCItem
+litem &989
 pos 1
 dimension 23
 uid 99,0
 )
-*931 (MRCItem
-litem &917
+*1004 (MRCItem
+litem &990
 pos 2
 hidden 1
@@ -23291,6 +24881,6 @@
 uid 100,0
 )
-*932 (MRCItem
-litem &926
+*1005 (MRCItem
+litem &999
 pos 0
 dimension 20
@@ -23308,42 +24898,42 @@
 uid 101,0
 optionalChildren [
-*933 (MRCItem
-litem &918
+*1006 (MRCItem
+litem &991
 pos 0
 dimension 20
 uid 102,0
 )
-*934 (MRCItem
-litem &920
+*1007 (MRCItem
+litem &993
 pos 1
 dimension 50
 uid 103,0
 )
-*935 (MRCItem
-litem &921
+*1008 (MRCItem
+litem &994
 pos 2
 dimension 186
 uid 104,0
 )
-*936 (MRCItem
-litem &922
+*1009 (MRCItem
+litem &995
 pos 3
 dimension 96
 uid 105,0
 )
-*937 (MRCItem
-litem &923
+*1010 (MRCItem
+litem &996
 pos 4
 dimension 50
 uid 106,0
 )
-*938 (MRCItem
-litem &924
+*1011 (MRCItem
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 pos 5
 dimension 50
 uid 107,0
 )
-*939 (MRCItem
-litem &925
+*1012 (MRCItem
+litem &998
 pos 6
 dimension 80
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb	(revision 10073)
@@ -26,5 +26,5 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 84,0
+suid 85,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -71,5 +71,5 @@
 n "wiz_reset"
 t "std_logic"
-o 43
+o 44
 suid 2,0
 i "'1'"
@@ -86,5 +86,5 @@
 b "(7 DOWNTO 0)"
 posAdd 0
-o 33
+o 34
 suid 7,0
 i "(OTHERS => '0')"
@@ -112,5 +112,5 @@
 n "adc_oeb"
 t "std_logic"
-o 28
+o 29
 suid 21,0
 i "'1'"
@@ -152,5 +152,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 40
+o 41
 suid 26,0
 )
@@ -165,5 +165,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 46
+o 47
 suid 27,0
 )
@@ -177,5 +177,5 @@
 n "wiz_cs"
 t "std_logic"
-o 41
+o 42
 suid 28,0
 i "'1'"
@@ -190,5 +190,5 @@
 n "wiz_wr"
 t "std_logic"
-o 44
+o 45
 suid 29,0
 i "'1'"
@@ -203,5 +203,5 @@
 n "wiz_rd"
 t "std_logic"
-o 42
+o 43
 suid 30,0
 i "'1'"
@@ -286,5 +286,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 31
+o 32
 suid 48,0
 i "(others => '0')"
@@ -299,5 +299,5 @@
 n "drs_dwrite"
 t "std_logic"
-o 32
+o 33
 suid 49,0
 i "'1'"
@@ -382,5 +382,5 @@
 n "sclk"
 t "std_logic"
-o 37
+o 38
 suid 62,0
 )
@@ -396,5 +396,5 @@
 preAdd 0
 posAdd 0
-o 45
+o 46
 suid 63,0
 )
@@ -408,5 +408,5 @@
 n "dac_cs"
 t "std_logic"
-o 29
+o 30
 suid 64,0
 )
@@ -421,5 +421,5 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 38
+o 39
 suid 65,0
 )
@@ -433,5 +433,5 @@
 n "mosi"
 t "std_logic"
-o 34
+o 35
 suid 66,0
 i "'0'"
@@ -448,5 +448,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 30
+o 31
 suid 67,0
 i "'0'"
@@ -461,5 +461,5 @@
 n "adc_clk_en"
 t "std_logic"
-o 27
+o 28
 suid 69,0
 i "'0'"
@@ -551,5 +551,5 @@
 preAdd 0
 posAdd 0
-o 35
+o 36
 suid 77,0
 i "(OTHERS => '0')"
@@ -567,5 +567,5 @@
 preAdd 0
 posAdd 0
-o 39
+o 40
 suid 78,0
 i "'0'"
@@ -582,5 +582,5 @@
 preAdd 0
 posAdd 0
-o 36
+o 37
 suid 79,0
 i "'0'"
@@ -648,4 +648,17 @@
 )
 uid 4578,0
+)
+*60 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 27
+suid 85,0
+i "'0'"
+)
+)
+uid 4779,0
 )
 ]
@@ -656,5 +669,5 @@
 uid 66,0
 optionalChildren [
-*60 (Sheet
+*61 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -673,5 +686,5 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *61 (MRCItem
+emptyMRCItem *62 (MRCItem
 litem &1
 pos 17
@@ -680,5 +693,5 @@
 uid 68,0
 optionalChildren [
-*62 (MRCItem
+*63 (MRCItem
 litem &2
 pos 0
@@ -686,5 +699,5 @@
 uid 69,0
 )
-*63 (MRCItem
+*64 (MRCItem
 litem &3
 pos 1
@@ -692,5 +705,5 @@
 uid 70,0
 )
-*64 (MRCItem
+*65 (MRCItem
 litem &4
 pos 2
@@ -699,5 +712,5 @@
 uid 71,0
 )
-*65 (MRCItem
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 litem &14
 pos 0
@@ -705,5 +718,5 @@
 uid 110,0
 )
-*66 (MRCItem
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 litem &15
 pos 24
@@ -711,5 +724,5 @@
 uid 120,0
 )
-*67 (MRCItem
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 litem &16
 pos 7
@@ -717,5 +730,5 @@
 uid 452,0
 )
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 litem &17
 pos 10
@@ -723,5 +736,5 @@
 uid 824,0
 )
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 litem &18
 pos 8
@@ -729,5 +742,5 @@
 uid 919,0
 )
-*70 (MRCItem
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 litem &19
 pos 9
@@ -735,5 +748,5 @@
 uid 921,0
 )
-*71 (MRCItem
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 litem &20
 pos 1
@@ -741,5 +754,5 @@
 uid 1025,0
 )
-*72 (MRCItem
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 litem &21
 pos 2
@@ -747,5 +760,5 @@
 uid 1027,0
 )
-*73 (MRCItem
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 litem &22
 pos 3
@@ -753,5 +766,5 @@
 uid 1029,0
 )
-*74 (MRCItem
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 litem &23
 pos 4
@@ -759,5 +772,5 @@
 uid 1031,0
 )
-*75 (MRCItem
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 litem &24
 pos 5
@@ -765,5 +778,5 @@
 uid 1033,0
 )
-*76 (MRCItem
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 litem &25
 pos 6
@@ -771,5 +784,5 @@
 uid 1035,0
 )
-*77 (MRCItem
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 litem &26
 pos 11
@@ -777,5 +790,5 @@
 uid 1387,0
 )
-*78 (MRCItem
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 litem &27
 pos 12
@@ -783,5 +796,5 @@
 uid 1723,0
 )
-*79 (MRCItem
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 litem &28
 pos 13
@@ -789,5 +802,5 @@
 uid 1753,0
 )
-*80 (MRCItem
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 litem &29
 pos 14
@@ -795,5 +808,5 @@
 uid 1974,0
 )
-*81 (MRCItem
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 litem &30
 pos 15
@@ -801,5 +814,5 @@
 uid 2280,0
 )
-*82 (MRCItem
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 litem &31
 pos 16
@@ -807,5 +820,5 @@
 uid 2414,0
 )
-*83 (MRCItem
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 litem &32
 pos 17
@@ -813,5 +826,5 @@
 uid 2416,0
 )
-*84 (MRCItem
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 litem &33
 pos 18
@@ -819,5 +832,5 @@
 uid 2692,0
 )
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 litem &34
 pos 19
@@ -825,5 +838,5 @@
 uid 2694,0
 )
-*86 (MRCItem
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 litem &35
 pos 20
@@ -831,5 +844,5 @@
 uid 2696,0
 )
-*87 (MRCItem
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 litem &36
 pos 21
@@ -837,5 +850,5 @@
 uid 2698,0
 )
-*88 (MRCItem
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 litem &37
 pos 22
@@ -843,5 +856,5 @@
 uid 2983,0
 )
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 litem &38
 pos 23
@@ -849,5 +862,5 @@
 uid 2985,0
 )
-*90 (MRCItem
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 litem &39
 pos 25
@@ -855,5 +868,5 @@
 uid 3623,0
 )
-*91 (MRCItem
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 litem &40
 pos 26
@@ -861,5 +874,5 @@
 uid 3625,0
 )
-*92 (MRCItem
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 litem &41
 pos 27
@@ -867,5 +880,5 @@
 uid 3627,0
 )
-*93 (MRCItem
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 litem &42
 pos 28
@@ -873,5 +886,5 @@
 uid 3629,0
 )
-*94 (MRCItem
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 litem &43
 pos 29
@@ -879,5 +892,5 @@
 uid 4065,0
 )
-*95 (MRCItem
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 litem &44
 pos 30
@@ -885,5 +898,5 @@
 uid 4142,0
 )
-*96 (MRCItem
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 litem &45
 pos 31
@@ -891,5 +904,5 @@
 uid 4321,0
 )
-*97 (MRCItem
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 litem &46
 pos 32
@@ -897,5 +910,5 @@
 uid 4443,0
 )
-*98 (MRCItem
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 litem &47
 pos 33
@@ -903,5 +916,5 @@
 uid 4445,0
 )
-*99 (MRCItem
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 litem &48
 pos 34
@@ -909,5 +922,5 @@
 uid 4447,0
 )
-*100 (MRCItem
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 litem &49
 pos 35
@@ -915,5 +928,5 @@
 uid 4449,0
 )
-*101 (MRCItem
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 litem &50
 pos 36
@@ -921,5 +934,5 @@
 uid 4451,0
 )
-*102 (MRCItem
+*103 (MRCItem
 litem &51
 pos 37
@@ -927,5 +940,5 @@
 uid 4455,0
 )
-*103 (MRCItem
+*104 (MRCItem
 litem &52
 pos 38
@@ -933,5 +946,5 @@
 uid 4457,0
 )
-*104 (MRCItem
+*105 (MRCItem
 litem &53
 pos 39
@@ -939,5 +952,5 @@
 uid 4459,0
 )
-*105 (MRCItem
+*106 (MRCItem
 litem &54
 pos 40
@@ -945,5 +958,5 @@
 uid 4461,0
 )
-*106 (MRCItem
+*107 (MRCItem
 litem &55
 pos 41
@@ -951,5 +964,5 @@
 uid 4463,0
 )
-*107 (MRCItem
+*108 (MRCItem
 litem &56
 pos 42
@@ -957,5 +970,5 @@
 uid 4465,0
 )
-*108 (MRCItem
+*109 (MRCItem
 litem &57
 pos 43
@@ -963,5 +976,5 @@
 uid 4573,0
 )
-*109 (MRCItem
+*110 (MRCItem
 litem &58
 pos 44
@@ -969,9 +982,15 @@
 uid 4575,0
 )
-*110 (MRCItem
+*111 (MRCItem
 litem &59
 pos 45
 dimension 20
 uid 4577,0
+)
+*112 (MRCItem
+litem &60
+pos 46
+dimension 20
+uid 4778,0
 )
 ]
@@ -986,5 +1005,5 @@
 uid 72,0
 optionalChildren [
-*111 (MRCItem
+*113 (MRCItem
 litem &5
 pos 0
@@ -992,5 +1011,5 @@
 uid 73,0
 )
-*112 (MRCItem
+*114 (MRCItem
 litem &7
 pos 1
@@ -998,5 +1017,5 @@
 uid 74,0
 )
-*113 (MRCItem
+*115 (MRCItem
 litem &8
 pos 2
@@ -1004,5 +1023,5 @@
 uid 75,0
 )
-*114 (MRCItem
+*116 (MRCItem
 litem &9
 pos 3
@@ -1010,5 +1029,5 @@
 uid 76,0
 )
-*115 (MRCItem
+*117 (MRCItem
 litem &10
 pos 4
@@ -1016,5 +1035,5 @@
 uid 77,0
 )
-*116 (MRCItem
+*118 (MRCItem
 litem &11
 pos 5
@@ -1022,5 +1041,5 @@
 uid 78,0
 )
-*117 (MRCItem
+*119 (MRCItem
 litem &12
 pos 6
@@ -1028,5 +1047,5 @@
 uid 79,0
 )
-*118 (MRCItem
+*120 (MRCItem
 litem &13
 pos 7
@@ -1049,39 +1068,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *119 (LEmptyRow
+emptyRow *121 (LEmptyRow
 )
 uid 82,0
 optionalChildren [
-*120 (RefLabelRowHdr
-)
-*121 (TitleRowHdr
-)
-*122 (FilterRowHdr
-)
-*123 (RefLabelColHdr
+*122 (RefLabelRowHdr
+)
+*123 (TitleRowHdr
+)
+*124 (FilterRowHdr
+)
+*125 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*124 (RowExpandColHdr
+*126 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*125 (GroupColHdr
+*127 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*126 (NameColHdr
+*128 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*127 (TypeColHdr
+*129 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*128 (InitColHdr
+*130 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*129 (PragmaColHdr
+*131 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*130 (EolColHdr
+*132 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*131 (LogGeneric
+*133 (LogGeneric
 generic (GiElement
 name "RAMADDRWIDTH64b"
@@ -1098,5 +1117,5 @@
 uid 94,0
 optionalChildren [
-*132 (Sheet
+*134 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -1115,6 +1134,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *133 (MRCItem
-litem &119
+emptyMRCItem *135 (MRCItem
+litem &121
 pos 0
 dimension 20
@@ -1122,18 +1141,18 @@
 uid 96,0
 optionalChildren [
-*134 (MRCItem
-litem &120
+*136 (MRCItem
+litem &122
 pos 0
 dimension 20
 uid 97,0
 )
-*135 (MRCItem
-litem &121
+*137 (MRCItem
+litem &123
 pos 1
 dimension 23
 uid 98,0
 )
-*136 (MRCItem
-litem &122
+*138 (MRCItem
+litem &124
 pos 2
 hidden 1
@@ -1141,6 +1160,6 @@
 uid 99,0
 )
-*137 (MRCItem
-litem &131
+*139 (MRCItem
+litem &133
 pos 0
 dimension 20
@@ -1158,42 +1177,42 @@
 uid 100,0
 optionalChildren [
-*138 (MRCItem
-litem &123
+*140 (MRCItem
+litem &125
 pos 0
 dimension 20
 uid 101,0
 )
-*139 (MRCItem
-litem &125
+*141 (MRCItem
+litem &127
 pos 1
 dimension 50
 uid 102,0
 )
-*140 (MRCItem
-litem &126
+*142 (MRCItem
+litem &128
 pos 2
 dimension 100
 uid 103,0
 )
-*141 (MRCItem
-litem &127
+*143 (MRCItem
+litem &129
 pos 3
 dimension 100
 uid 104,0
 )
-*142 (MRCItem
-litem &128
+*144 (MRCItem
+litem &130
 pos 4
 dimension 50
 uid 105,0
 )
-*143 (MRCItem
-litem &129
+*145 (MRCItem
+litem &131
 pos 5
 dimension 50
 uid 106,0
 )
-*144 (MRCItem
-litem &130
+*146 (MRCItem
+litem &132
 pos 6
 dimension 80
@@ -1218,21 +1237,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -1250,25 +1269,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main"
 )
 (vvPair
 variable "date"
-value "30.08.2010"
+value "04.01.2011"
 )
 (vvPair
 variable "day"
-value "Mo"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Montag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "30"
+value "04"
 )
 (vvPair
@@ -1334,5 +1353,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -1342,17 +1361,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb"
 )
 (vvPair
@@ -1410,5 +1429,5 @@
 (vvPair
 variable "time"
-value "10:49:09"
+value "11:02:29"
 )
 (vvPair
@@ -1430,9 +1449,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -1441,8 +1460,8 @@
 uid 51,0
 optionalChildren [
-*145 (SymbolBody
+*147 (SymbolBody
 uid 8,0
 optionalChildren [
-*146 (CptPort
+*148 (CptPort
 uid 135,0
 ps "OnEdgeStrategy"
@@ -1476,5 +1495,5 @@
 font "Courier New,8,0"
 )
-xt "44000,36400,77500,37200"
+xt "44000,37200,77500,38000"
 st "wiz_reset       : OUT    std_logic                     := '1' ;"
 )
@@ -1484,5 +1503,5 @@
 n "wiz_reset"
 t "std_logic"
-o 43
+o 44
 suid 2,0
 i "'1'"
@@ -1490,5 +1509,5 @@
 )
 )
-*147 (CptPort
+*149 (CptPort
 uid 163,0
 ps "OnEdgeStrategy"
@@ -1522,5 +1541,5 @@
 font "Courier New,8,0"
 )
-xt "44000,27600,83500,28400"
+xt "44000,28400,83500,29200"
 st "led             : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;"
 )
@@ -1532,5 +1551,5 @@
 b "(7 DOWNTO 0)"
 posAdd 0
-o 33
+o 34
 suid 7,0
 i "(OTHERS => '0')"
@@ -1538,5 +1557,5 @@
 )
 )
-*148 (CptPort
+*150 (CptPort
 uid 464,0
 ps "OnEdgeStrategy"
@@ -1583,5 +1602,5 @@
 )
 )
-*149 (CptPort
+*151 (CptPort
 uid 833,0
 ps "OnEdgeStrategy"
@@ -1614,5 +1633,5 @@
 font "Courier New,8,0"
 )
-xt "44000,23600,77500,24400"
+xt "44000,24400,77500,25200"
 st "adc_oeb         : OUT    std_logic                     := '1' ;"
 )
@@ -1622,5 +1641,5 @@
 n "adc_oeb"
 t "std_logic"
-o 28
+o 29
 suid 21,0
 i "'1'"
@@ -1628,5 +1647,5 @@
 )
 )
-*150 (CptPort
+*152 (CptPort
 uid 923,0
 ps "OnEdgeStrategy"
@@ -1674,5 +1693,5 @@
 )
 )
-*151 (CptPort
+*153 (CptPort
 uid 928,0
 ps "OnEdgeStrategy"
@@ -1718,5 +1737,5 @@
 )
 )
-*152 (CptPort
+*154 (CptPort
 uid 1037,0
 ps "OnEdgeStrategy"
@@ -1750,5 +1769,5 @@
 font "Courier New,8,0"
 )
-xt "44000,34000,74000,34800"
+xt "44000,34800,74000,35600"
 st "wiz_addr        : OUT    std_logic_vector (9 DOWNTO 0) ;"
 )
@@ -1759,10 +1778,10 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 40
+o 41
 suid 26,0
 )
 )
 )
-*153 (CptPort
+*155 (CptPort
 uid 1042,0
 ps "OnEdgeStrategy"
@@ -1796,5 +1815,5 @@
 font "Courier New,8,0"
 )
-xt "44000,38800,73500,39600"
+xt "44000,39600,73500,40400"
 st "wiz_data        : INOUT  std_logic_vector (15 DOWNTO 0)"
 )
@@ -1805,10 +1824,10 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 46
+o 47
 suid 27,0
 )
 )
 )
-*154 (CptPort
+*156 (CptPort
 uid 1047,0
 ps "OnEdgeStrategy"
@@ -1842,5 +1861,5 @@
 font "Courier New,8,0"
 )
-xt "44000,34800,77500,35600"
+xt "44000,35600,77500,36400"
 st "wiz_cs          : OUT    std_logic                     := '1' ;"
 )
@@ -1850,5 +1869,5 @@
 n "wiz_cs"
 t "std_logic"
-o 41
+o 42
 suid 28,0
 i "'1'"
@@ -1856,5 +1875,5 @@
 )
 )
-*155 (CptPort
+*157 (CptPort
 uid 1052,0
 ps "OnEdgeStrategy"
@@ -1888,5 +1907,5 @@
 font "Courier New,8,0"
 )
-xt "44000,37200,77500,38000"
+xt "44000,38000,77500,38800"
 st "wiz_wr          : OUT    std_logic                     := '1' ;"
 )
@@ -1896,5 +1915,5 @@
 n "wiz_wr"
 t "std_logic"
-o 44
+o 45
 suid 29,0
 i "'1'"
@@ -1902,5 +1921,5 @@
 )
 )
-*156 (CptPort
+*158 (CptPort
 uid 1057,0
 ps "OnEdgeStrategy"
@@ -1934,5 +1953,5 @@
 font "Courier New,8,0"
 )
-xt "44000,35600,77500,36400"
+xt "44000,36400,77500,37200"
 st "wiz_rd          : OUT    std_logic                     := '1' ;"
 )
@@ -1942,5 +1961,5 @@
 n "wiz_rd"
 t "std_logic"
-o 42
+o 43
 suid 30,0
 i "'1'"
@@ -1948,5 +1967,5 @@
 )
 )
-*157 (CptPort
+*159 (CptPort
 uid 1062,0
 ps "OnEdgeStrategy"
@@ -1992,5 +2011,5 @@
 )
 )
-*158 (CptPort
+*160 (CptPort
 uid 1389,0
 ps "OnEdgeStrategy"
@@ -2036,5 +2055,5 @@
 )
 )
-*159 (CptPort
+*161 (CptPort
 uid 1725,0
 ps "OnEdgeStrategy"
@@ -2080,5 +2099,5 @@
 )
 )
-*160 (CptPort
+*162 (CptPort
 uid 1755,0
 ps "OnEdgeStrategy"
@@ -2123,5 +2142,5 @@
 )
 )
-*161 (CptPort
+*163 (CptPort
 uid 1976,0
 ps "OnEdgeStrategy"
@@ -2167,5 +2186,5 @@
 )
 )
-*162 (CptPort
+*164 (CptPort
 uid 2282,0
 ps "OnEdgeStrategy"
@@ -2210,5 +2229,5 @@
 )
 )
-*163 (CptPort
+*165 (CptPort
 uid 2448,0
 ps "OnEdgeStrategy"
@@ -2241,5 +2260,5 @@
 font "Courier New,8,0"
 )
-xt "44000,26000,83500,26800"
+xt "44000,26800,83500,27600"
 st "drs_channel_id  : OUT    std_logic_vector (3 downto 0) := (others => '0') ;"
 )
@@ -2250,5 +2269,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 31
+o 32
 suid 48,0
 i "(others => '0')"
@@ -2256,5 +2275,5 @@
 )
 )
-*164 (CptPort
+*166 (CptPort
 uid 2453,0
 ps "OnEdgeStrategy"
@@ -2287,5 +2306,5 @@
 font "Courier New,8,0"
 )
-xt "44000,26800,77500,27600"
+xt "44000,27600,77500,28400"
 st "drs_dwrite      : OUT    std_logic                     := '1' ;"
 )
@@ -2295,5 +2314,5 @@
 n "drs_dwrite"
 t "std_logic"
-o 32
+o 33
 suid 49,0
 i "'1'"
@@ -2301,5 +2320,5 @@
 )
 )
-*165 (CptPort
+*167 (CptPort
 uid 2710,0
 ps "OnEdgeStrategy"
@@ -2344,5 +2363,5 @@
 )
 )
-*166 (CptPort
+*168 (CptPort
 uid 2715,0
 ps "OnEdgeStrategy"
@@ -2387,5 +2406,5 @@
 )
 )
-*167 (CptPort
+*169 (CptPort
 uid 2720,0
 ps "OnEdgeStrategy"
@@ -2430,5 +2449,5 @@
 )
 )
-*168 (CptPort
+*170 (CptPort
 uid 2725,0
 ps "OnEdgeStrategy"
@@ -2473,5 +2492,5 @@
 )
 )
-*169 (CptPort
+*171 (CptPort
 uid 2987,0
 ps "OnEdgeStrategy"
@@ -2518,5 +2537,5 @@
 )
 )
-*170 (CptPort
+*172 (CptPort
 uid 2992,0
 ps "OnEdgeStrategy"
@@ -2563,5 +2582,5 @@
 )
 )
-*171 (CptPort
+*173 (CptPort
 uid 3631,0
 ps "OnEdgeStrategy"
@@ -2595,5 +2614,5 @@
 font "Courier New,8,0"
 )
-xt "44000,30800,64000,31600"
+xt "44000,31600,64000,32400"
 st "sclk            : OUT    std_logic  ;"
 )
@@ -2603,10 +2622,10 @@
 n "sclk"
 t "std_logic"
-o 37
+o 38
 suid 62,0
 )
 )
 )
-*172 (CptPort
+*174 (CptPort
 uid 3636,0
 ps "OnEdgeStrategy"
@@ -2640,5 +2659,5 @@
 font "Courier New,8,0"
 )
-xt "44000,38000,64000,38800"
+xt "44000,38800,64000,39600"
 st "sio             : INOUT  std_logic  ;"
 )
@@ -2650,10 +2669,10 @@
 preAdd 0
 posAdd 0
-o 45
+o 46
 suid 63,0
 )
 )
 )
-*173 (CptPort
+*175 (CptPort
 uid 3641,0
 ps "OnEdgeStrategy"
@@ -2687,5 +2706,5 @@
 font "Courier New,8,0"
 )
-xt "44000,24400,64000,25200"
+xt "44000,25200,64000,26000"
 st "dac_cs          : OUT    std_logic  ;"
 )
@@ -2695,10 +2714,10 @@
 n "dac_cs"
 t "std_logic"
-o 29
+o 30
 suid 64,0
 )
 )
 )
-*174 (CptPort
+*176 (CptPort
 uid 3646,0
 ps "OnEdgeStrategy"
@@ -2732,5 +2751,5 @@
 font "Courier New,8,0"
 )
-xt "44000,31600,74000,32400"
+xt "44000,32400,74000,33200"
 st "sensor_cs       : OUT    std_logic_vector (3 DOWNTO 0) ;"
 )
@@ -2741,10 +2760,10 @@
 t "std_logic_vector"
 b "(3 DOWNTO 0)"
-o 38
+o 39
 suid 65,0
 )
 )
 )
-*175 (CptPort
+*177 (CptPort
 uid 4067,0
 ps "OnEdgeStrategy"
@@ -2778,5 +2797,5 @@
 font "Courier New,8,0"
 )
-xt "44000,28400,77500,29200"
+xt "44000,29200,77500,30000"
 st "mosi            : OUT    std_logic                     := '0' ;"
 )
@@ -2786,5 +2805,5 @@
 n "mosi"
 t "std_logic"
-o 34
+o 35
 suid 66,0
 i "'0'"
@@ -2792,5 +2811,5 @@
 )
 )
-*176 (CptPort
+*178 (CptPort
 uid 4144,0
 ps "OnEdgeStrategy"
@@ -2824,5 +2843,5 @@
 font "Courier New,8,0"
 )
-xt "44000,25200,91000,26000"
+xt "44000,26000,91000,26800"
 st "denable         : OUT    std_logic                     := '0' ; -- default domino wave off"
 )
@@ -2834,5 +2853,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 30
+o 31
 suid 67,0
 i "'0'"
@@ -2840,5 +2859,5 @@
 )
 )
-*177 (CptPort
+*179 (CptPort
 uid 4323,0
 ps "OnEdgeStrategy"
@@ -2872,5 +2891,5 @@
 font "Courier New,8,0"
 )
-xt "44000,22800,77500,23600"
+xt "44000,23600,77500,24400"
 st "adc_clk_en      : OUT    std_logic                     := '0' ;"
 )
@@ -2880,5 +2899,5 @@
 n "adc_clk_en"
 t "std_logic"
-o 27
+o 28
 suid 69,0
 i "'0'"
@@ -2886,5 +2905,5 @@
 )
 )
-*178 (CptPort
+*180 (CptPort
 uid 4467,0
 ps "OnEdgeStrategy"
@@ -2931,5 +2950,5 @@
 )
 )
-*179 (CptPort
+*181 (CptPort
 uid 4472,0
 ps "OnEdgeStrategy"
@@ -2976,5 +2995,5 @@
 )
 )
-*180 (CptPort
+*182 (CptPort
 uid 4477,0
 ps "OnEdgeStrategy"
@@ -3021,5 +3040,5 @@
 )
 )
-*181 (CptPort
+*183 (CptPort
 uid 4482,0
 ps "OnEdgeStrategy"
@@ -3066,5 +3085,5 @@
 )
 )
-*182 (CptPort
+*184 (CptPort
 uid 4487,0
 ps "OnEdgeStrategy"
@@ -3111,5 +3130,5 @@
 )
 )
-*183 (CptPort
+*185 (CptPort
 uid 4497,0
 ps "OnEdgeStrategy"
@@ -3158,5 +3177,5 @@
 )
 )
-*184 (CptPort
+*186 (CptPort
 uid 4502,0
 ps "OnEdgeStrategy"
@@ -3190,5 +3209,5 @@
 font "Courier New,8,0"
 )
-xt "44000,29200,83500,30000"
+xt "44000,30000,83500,30800"
 st "offset          : OUT    std_logic_vector (7 downto 0) := (OTHERS => '0') ;"
 )
@@ -3201,5 +3220,5 @@
 preAdd 0
 posAdd 0
-o 35
+o 36
 suid 77,0
 i "(OTHERS => '0')"
@@ -3207,5 +3226,5 @@
 )
 )
-*185 (CptPort
+*187 (CptPort
 uid 4507,0
 ps "OnEdgeStrategy"
@@ -3239,5 +3258,5 @@
 font "Courier New,8,0"
 )
-xt "44000,32400,77500,34000"
+xt "44000,33200,77500,34800"
 st "-- status:
 shifting        : OUT    std_logic                     := '0' ;"
@@ -3251,5 +3270,5 @@
 preAdd 0
 posAdd 0
-o 39
+o 40
 suid 78,0
 i "'0'"
@@ -3257,5 +3276,5 @@
 )
 )
-*186 (CptPort
+*188 (CptPort
 uid 4512,0
 ps "OnEdgeStrategy"
@@ -3289,5 +3308,5 @@
 font "Courier New,8,0"
 )
-xt "44000,30000,77500,30800"
+xt "44000,30800,77500,31600"
 st "ready           : OUT    std_logic                     := '0' ;"
 )
@@ -3299,5 +3318,5 @@
 preAdd 0
 posAdd 0
-o 36
+o 37
 suid 79,0
 i "'0'"
@@ -3305,5 +3324,5 @@
 )
 )
-*187 (CptPort
+*189 (CptPort
 uid 4517,0
 ps "OnEdgeStrategy"
@@ -3350,5 +3369,5 @@
 )
 )
-*188 (CptPort
+*190 (CptPort
 uid 4522,0
 ps "OnEdgeStrategy"
@@ -3395,5 +3414,5 @@
 )
 )
-*189 (CptPort
+*191 (CptPort
 uid 4579,0
 ps "OnEdgeStrategy"
@@ -3440,5 +3459,5 @@
 )
 )
-*190 (CptPort
+*192 (CptPort
 uid 4584,0
 ps "OnEdgeStrategy"
@@ -3485,5 +3504,5 @@
 )
 )
-*191 (CptPort
+*193 (CptPort
 uid 4589,0
 ps "OnEdgeStrategy"
@@ -3530,4 +3549,50 @@
 )
 )
+*194 (CptPort
+uid 4780,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4781,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "43000,60625,43750,61375"
+)
+tg (CPTG
+uid 4782,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4783,0
+va (VaSet
+)
+xt "38300,60500,42000,61500"
+st "SRIN_out"
+ju 2
+blo "42000,61300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 4784,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,22800,77500,23600"
+st "SRIN_out        : OUT    std_logic                     := '0' ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 27
+suid 85,0
+i "'0'"
+)
+)
+)
 ]
 shape (Rectangle
@@ -3539,5 +3604,5 @@
 lineWidth 2
 )
-xt "15000,-8000,43000,61000"
+xt "15000,-8000,43000,62000"
 )
 oxt "15000,-8000,43000,45000"
@@ -3565,5 +3630,5 @@
 )
 )
-gi *192 (GenericInterface
+gi *195 (GenericInterface
 uid 13,0
 ps "CenterOffsetStrategy"
@@ -3597,8 +3662,8 @@
 )
 )
-*193 (Grouping
+*196 (Grouping
 uid 16,0
 optionalChildren [
-*194 (CommentText
+*197 (CommentText
 uid 18,0
 shape (Rectangle
@@ -3618,5 +3683,5 @@
 bg "0,0,32768"
 )
-xt "36200,48000,45900,49000"
+xt "36200,48000,45700,49000"
 st "
 by %user on %dd %month %year
@@ -3631,5 +3696,5 @@
 titleBlock 1
 )
-*195 (CommentText
+*198 (CommentText
 uid 21,0
 shape (Rectangle
@@ -3662,5 +3727,5 @@
 titleBlock 1
 )
-*196 (CommentText
+*199 (CommentText
 uid 24,0
 shape (Rectangle
@@ -3693,5 +3758,5 @@
 titleBlock 1
 )
-*197 (CommentText
+*200 (CommentText
 uid 27,0
 shape (Rectangle
@@ -3724,5 +3789,5 @@
 titleBlock 1
 )
-*198 (CommentText
+*201 (CommentText
 uid 30,0
 shape (Rectangle
@@ -3754,5 +3819,5 @@
 titleBlock 1
 )
-*199 (CommentText
+*202 (CommentText
 uid 33,0
 shape (Rectangle
@@ -3785,5 +3850,5 @@
 titleBlock 1
 )
-*200 (CommentText
+*203 (CommentText
 uid 36,0
 shape (Rectangle
@@ -3816,5 +3881,5 @@
 titleBlock 1
 )
-*201 (CommentText
+*204 (CommentText
 uid 39,0
 shape (Rectangle
@@ -3847,5 +3912,5 @@
 titleBlock 1
 )
-*202 (CommentText
+*205 (CommentText
 uid 42,0
 shape (Rectangle
@@ -3878,5 +3943,5 @@
 titleBlock 1
 )
-*203 (CommentText
+*206 (CommentText
 uid 45,0
 shape (Rectangle
@@ -3934,9 +3999,9 @@
 color "26368,26368,26368"
 )
-packageList *204 (PackageList
+packageList *207 (PackageList
 uid 48,0
 stg "VerticalLayoutStrategy"
 textVec [
-*205 (Text
+*208 (Text
 uid 49,0
 va (VaSet
@@ -3947,5 +4012,5 @@
 blo "0,800"
 )
-*206 (MLText
+*209 (MLText
 uid 50,0
 va (VaSet
@@ -4048,5 +4113,5 @@
 )
 )
-gi *207 (GenericInterface
+gi *210 (GenericInterface
 ps "CenterOffsetStrategy"
 matrix (Matrix
@@ -4145,5 +4210,5 @@
 )
 )
-DeclarativeBlock *208 (SymDeclBlock
+DeclarativeBlock *211 (SymDeclBlock
 uid 1,0
 stg "SymDeclLayoutStrategy"
@@ -4171,7 +4236,7 @@
 font "Arial,8,1"
 )
-xt "42000,39600,44400,40600"
+xt "42000,40400,44400,41400"
 st "User:"
-blo "42000,40400"
+blo "42000,41200"
 )
 internalLabel (Text
@@ -4190,5 +4255,5 @@
 font "Courier New,8,0"
 )
-xt "44000,40600,44000,40600"
+xt "44000,41400,44000,41400"
 tm "SyDeclarativeTextMgr"
 )
@@ -4203,5 +4268,5 @@
 )
 )
-lastUid 4662,0
+lastUid 4876,0
 okToSyncOnLoad 1
 OkToSyncGenericsOnLoad 1
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_manager/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_manager/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_manager/symbol.sb	(revision 10073)
@@ -35,5 +35,5 @@
 ldm (LogicalDM
 ordering 1
-suid 25,0
+suid 27,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -209,5 +209,5 @@
 preAdd 0
 posAdd 0
-o 15
+o 17
 suid 15,0
 )
@@ -223,5 +223,5 @@
 preAdd 0
 posAdd 0
-o 16
+o 18
 suid 16,0
 )
@@ -236,5 +236,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 13
+o 15
 suid 19,0
 )
@@ -249,5 +249,5 @@
 t "std_logic_vector"
 b "(0 DOWNTO 0)"
-o 14
+o 16
 suid 20,0
 )
@@ -274,5 +274,7 @@
 t "std_logic_vector"
 b "(ADDR_WIDTH - 1 DOWNTO 0)"
-o 12
+prec "-- --"
+preAdd 0
+o 14
 suid 22,0
 )
@@ -297,12 +299,15 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 17
-suid 24,0
-)
-)
-uid 538,0
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 12
+suid 26,0
+i "'0'"
+)
+)
+uid 581,0
 )
 *31 (LogPort
@@ -310,11 +315,15 @@
 m 1
 decl (Decl
-n "drs_address_mode"
+n "config_rw_ready"
 t "std_logic"
-o 18
-suid 25,0
-)
-)
-uid 540,0
+prec "-- --"
+preAdd 0
+posAdd 0
+o 13
+suid 27,0
+i "'0'"
+)
+)
+uid 583,0
 )
 ]
@@ -468,5 +477,5 @@
 pos 16
 dimension 20
-uid 539,0
+uid 582,0
 )
 *54 (MRCItem
@@ -474,5 +483,5 @@
 pos 17
 dimension 20
-uid 541,0
+uid 584,0
 )
 ]
@@ -590,5 +599,5 @@
 value "36"
 )
-uid 542,0
+uid 585,0
 )
 *76 (LogGeneric
@@ -598,5 +607,5 @@
 value "8"
 )
-uid 544,0
+uid 587,0
 )
 *77 (LogGeneric
@@ -606,5 +615,5 @@
 value "8"
 )
-uid 546,0
+uid 589,0
 )
 ]
@@ -662,5 +671,5 @@
 pos 0
 dimension 20
-uid 543,0
+uid 586,0
 )
 *84 (MRCItem
@@ -668,5 +677,5 @@
 pos 1
 dimension 20
-uid 545,0
+uid 588,0
 )
 *85 (MRCItem
@@ -674,5 +683,5 @@
 pos 2
 dimension 20
-uid 547,0
+uid 590,0
 )
 ]
@@ -747,21 +756,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -779,13 +788,13 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_manager"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_manager"
 )
 (vvPair
 variable "date"
-value "12.07.2010"
+value "03.01.2011"
 )
 (vvPair
@@ -799,5 +808,5 @@
 (vvPair
 variable "dd"
-value "12"
+value "03"
 )
 (vvPair
@@ -827,5 +836,5 @@
 (vvPair
 variable "host"
-value "TU-CC4900F8C7D2"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -838,4 +847,8 @@
 )
 (vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
+)
+(vvPair
 variable "library_downstream_ISEPARInvoke"
 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
@@ -855,5 +868,5 @@
 (vvPair
 variable "mm"
-value "07"
+value "01"
 )
 (vvPair
@@ -863,17 +876,17 @@
 (vvPair
 variable "month"
-value "Jul"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "Juli"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
 )
 (vvPair
@@ -931,5 +944,5 @@
 (vvPair
 variable "time"
-value "14:11:44"
+value "16:28:33"
 )
 (vvPair
@@ -951,9 +964,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -1429,5 +1442,5 @@
 font "Courier New,8,0"
 )
-xt "2000,22200,26000,23000"
+xt "2000,26200,26000,27000"
 st "dac_array         : OUT    dac_array_type  ;
 "
@@ -1440,5 +1453,5 @@
 preAdd 0
 posAdd 0
-o 15
+o 17
 suid 15,0
 )
@@ -1477,6 +1490,6 @@
 font "Courier New,8,0"
 )
-xt "2000,23000,26000,23800"
-st "roi_array         : OUT    roi_array_type  ;
+xt "2000,27000,25000,27800"
+st "roi_array         : OUT    roi_array_type 
 "
 )
@@ -1488,5 +1501,5 @@
 preAdd 0
 posAdd 0
-o 16
+o 18
 suid 16,0
 )
@@ -1525,5 +1538,5 @@
 font "Courier New,8,0"
 )
-xt "2000,20600,33500,21400"
+xt "2000,24600,33500,25400"
 st "ram_data_in       : OUT    std_logic_vector (15 DOWNTO 0) ;
 "
@@ -1535,5 +1548,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 13
+o 15
 suid 19,0
 )
@@ -1572,5 +1585,5 @@
 font "Courier New,8,0"
 )
-xt "2000,21400,33000,22200"
+xt "2000,25400,33000,26200"
 st "ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0) ;
 "
@@ -1582,5 +1595,5 @@
 t "std_logic_vector"
 b "(0 DOWNTO 0)"
-o 14
+o 16
 suid 20,0
 )
@@ -1664,6 +1677,7 @@
 font "Courier New,8,0"
 )
-xt "2000,19800,39500,20600"
-st "ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0) ;
+xt "2000,23000,39500,24600"
+st "-- --
+ram_addr          : OUT    std_logic_vector (ADDR_WIDTH - 1 DOWNTO 0) ;
 "
 )
@@ -1674,5 +1688,7 @@
 t "std_logic_vector"
 b "(ADDR_WIDTH - 1 DOWNTO 0)"
-o 12
+prec "-- --"
+preAdd 0
+o 14
 suid 22,0
 )
@@ -1727,8 +1743,8 @@
 )
 *110 (CptPort
-uid 528,0
+uid 571,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 529,0
+uid 572,0
 ro 90
 va (VaSet
@@ -1739,13 +1755,13 @@
 )
 tg (CPTG
-uid 530,0
+uid 573,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 531,0
-va (VaSet
-)
-xt "58800,32500,66000,33500"
-st "drs_address : (3:0)"
+uid 574,0
+va (VaSet
+)
+xt "60400,32500,66000,33500"
+st "config_rw_ack"
 ju 2
 blo "66000,33300"
@@ -1754,10 +1770,11 @@
 )
 dt (MLText
-uid 532,0
+uid 575,0
 va (VaSet
 font "Courier New,8,0"
 )
-xt "2000,23800,33000,24600"
-st "drs_address       : OUT    std_logic_vector (3 DOWNTO 0) ;
+xt "2000,19800,37000,21400"
+st "-- --
+config_rw_ack     : OUT    std_logic                      := '0' ;
 "
 )
@@ -1765,17 +1782,20 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 17
-suid 24,0
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 12
+suid 26,0
+i "'0'"
 )
 )
 )
 *111 (CptPort
-uid 533,0
+uid 576,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 534,0
+uid 577,0
 ro 90
 va (VaSet
@@ -1786,13 +1806,13 @@
 )
 tg (CPTG
-uid 535,0
+uid 578,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 536,0
-va (VaSet
-)
-xt "58800,33500,66000,34500"
-st "drs_address_mode"
+uid 579,0
+va (VaSet
+)
+xt "59700,33500,66000,34500"
+st "config_rw_ready"
 ju 2
 blo "66000,34300"
@@ -1801,10 +1821,11 @@
 )
 dt (MLText
-uid 537,0
+uid 580,0
 va (VaSet
 font "Courier New,8,0"
 )
-xt "2000,24600,22000,25400"
-st "drs_address_mode  : OUT    std_logic 
+xt "2000,21400,37000,23000"
+st "-- --
+config_rw_ready   : OUT    std_logic                      := '0' ;
 "
 )
@@ -1812,8 +1833,12 @@
 m 1
 decl (Decl
-n "drs_address_mode"
+n "config_rw_ready"
 t "std_logic"
-o 18
-suid 25,0
+prec "-- --"
+preAdd 0
+posAdd 0
+o 13
+suid 27,0
+i "'0'"
 )
 )
@@ -2505,7 +2530,7 @@
 font "Arial,8,1"
 )
-xt "0,25400,2400,26400"
+xt "0,27800,2400,28800"
 st "User:"
-blo "0,26200"
+blo "0,28600"
 )
 internalLabel (Text
@@ -2524,5 +2549,5 @@
 font "Courier New,8,0"
 )
-xt "2000,26400,2000,26400"
+xt "2000,28800,2000,28800"
 tm "SyDeclarativeTextMgr"
 )
@@ -2537,5 +2562,5 @@
 )
 )
-lastUid 547,0
+lastUid 590,0
 activeModelName "Symbol:CDM"
 )
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/struct.bd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/struct.bd	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/struct.bd	(revision 10073)
@@ -67,21 +67,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -99,13 +99,13 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit"
 )
 (vvPair
 variable "date"
-value "12.07.2010"
+value "03.01.2011"
 )
 (vvPair
@@ -119,5 +119,5 @@
 (vvPair
 variable "dd"
-value "12"
+value "03"
 )
 (vvPair
@@ -147,5 +147,5 @@
 (vvPair
 variable "host"
-value "TU-CC4900F8C7D2"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -158,4 +158,8 @@
 )
 (vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
+)
+(vvPair
 variable "library_downstream_ISEPARInvoke"
 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
@@ -175,5 +179,5 @@
 (vvPair
 variable "mm"
-value "07"
+value "01"
 )
 (vvPair
@@ -183,17 +187,17 @@
 (vvPair
 variable "month"
-value "Jul"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "Juli"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
 )
 (vvPair
@@ -251,5 +255,5 @@
 (vvPair
 variable "time"
-value "14:13:34"
+value "16:29:16"
 )
 (vvPair
@@ -271,9 +275,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -640,5 +644,5 @@
 font "Courier New,8,0"
 )
-xt "29000,16800,58500,17600"
+xt "29000,18400,58500,19200"
 st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)
 "
@@ -678,5 +682,5 @@
 font "Courier New,8,0"
 )
-xt "29000,15200,59000,16000"
+xt "29000,16800,59000,17600"
 st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)
 "
@@ -733,5 +737,5 @@
 font "Courier New,8,0"
 )
-xt "29000,12600,55500,13400"
+xt "29000,14200,55500,15000"
 st "config_data       : std_logic_vector(15 DOWNTO 0)
 "
@@ -751,5 +755,5 @@
 font "Courier New,8,0"
 )
-xt "29000,11800,47500,12600"
+xt "29000,13400,47500,14200"
 st "roi_array         : roi_array_type
 "
@@ -770,5 +774,5 @@
 font "Courier New,8,0"
 )
-xt "29000,14400,58500,15200"
+xt "29000,16000,58500,16800"
 st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)
 "
@@ -807,5 +811,5 @@
 font "Courier New,8,0"
 )
-xt "29000,16000,59000,16800"
+xt "29000,17600,59000,18400"
 st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)
 "
@@ -825,5 +829,5 @@
 font "Courier New,8,0"
 )
-xt "29000,9400,47500,10200"
+xt "29000,12600,47500,13400"
 st "dac_array         : dac_array_type
 "
@@ -1745,5 +1749,5 @@
 preAdd 0
 posAdd 0
-o 15
+o 17
 suid 15,0
 )
@@ -1783,5 +1787,5 @@
 preAdd 0
 posAdd 0
-o 16
+o 18
 suid 16,0
 )
@@ -1820,5 +1824,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 13
+o 15
 suid 19,0
 )
@@ -1857,5 +1861,5 @@
 t "std_logic_vector"
 b "(0 DOWNTO 0)"
-o 14
+o 16
 suid 20,0
 )
@@ -1929,5 +1933,7 @@
 t "std_logic_vector"
 b "(ADDR_WIDTH - 1 DOWNTO 0)"
-o 12
+prec "-- --"
+preAdd 0
+o 14
 suid 22,0
 )
@@ -1972,8 +1978,8 @@
 )
 *55 (CptPort
-uid 1198,0
+uid 1263,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 1199,0
+uid 1264,0
 ro 90
 va (VaSet
@@ -1981,16 +1987,56 @@
 fg "0,65535,0"
 )
-xt "32000,21625,32750,22375"
+xt "32000,20625,32750,21375"
 )
 tg (CPTG
-uid 1200,0
+uid 1265,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 1201,0
-va (VaSet
-)
-xt "23800,21500,31000,22500"
-st "drs_address : (3:0)"
+uid 1266,0
+va (VaSet
+)
+xt "25400,20500,31000,21500"
+st "config_rw_ack"
+ju 2
+blo "31000,21300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 12
+suid 26,0
+i "'0'"
+)
+)
+)
+*56 (CptPort
+uid 1267,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1268,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32000,21625,32750,22375"
+)
+tg (CPTG
+uid 1269,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1270,0
+va (VaSet
+)
+xt "24700,21500,31000,22500"
+st "config_rw_ready"
 ju 2
 blo "31000,22300"
@@ -2000,45 +2046,12 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 17
-suid 24,0
-)
-)
-)
-*56 (CptPort
-uid 1202,0
-ps "OnEdgeStrategy"
-shape (Triangle
-uid 1203,0
-ro 90
-va (VaSet
-vasetType 1
-fg "0,65535,0"
-)
-xt "32000,20625,32750,21375"
-)
-tg (CPTG
-uid 1204,0
-ps "CptPortTextPlaceStrategy"
-stg "RightVerticalLayoutStrategy"
-f (Text
-uid 1205,0
-va (VaSet
-)
-xt "23800,20500,31000,21500"
-st "drs_address_mode"
-ju 2
-blo "31000,21300"
-)
-)
-thePort (LogicalPort
-m 1
-decl (Decl
-n "drs_address_mode"
+n "config_rw_ready"
 t "std_logic"
-o 18
-suid 25,0
+prec "-- --"
+preAdd 0
+posAdd 0
+o 13
+suid 27,0
+i "'0'"
 )
 )
@@ -2436,5 +2449,5 @@
 font "Courier New,8,0"
 )
-xt "29000,8600,48500,9400"
+xt "29000,11800,48500,12600"
 st "config_started    : std_logic := '0'
 "
@@ -2486,26 +2499,30 @@
 )
 *71 (Net
-uid 1206,0
-decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
+uid 1279,0
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
 o 17
-suid 19,0
+suid 22,0
+i "'0'"
 )
 declText (MLText
-uid 1207,0
+uid 1280,0
 va (VaSet
 font "Courier New,8,0"
 )
-xt "29000,10200,55000,11000"
-st "drs_address       : std_logic_vector(3 DOWNTO 0)
+xt "29000,8600,48500,10200"
+st "-- --
+config_rw_ack     : std_logic := '0'
 "
 )
 )
 *72 (PortIoOut
-uid 1214,0
+uid 1287,0
 shape (CompositeShape
-uid 1215,0
+uid 1288,0
 va (VaSet
 vasetType 1
@@ -2514,17 +2531,17 @@
 optionalChildren [
 (Pentagon
-uid 1216,0
+uid 1289,0
 sl 0
 ro 270
-xt "36500,21625,38000,22375"
+xt "41500,20625,43000,21375"
 )
 (Line
-uid 1217,0
+uid 1290,0
 sl 0
 ro 270
-xt "36000,22000,36500,22000"
+xt "41000,21000,41500,21000"
 pts [
-"36000,22000"
-"36500,22000"
+"41000,21000"
+"41500,21000"
 ]
 )
@@ -2534,14 +2551,14 @@
 sf 1
 tg (WTG
-uid 1218,0
+uid 1291,0
 ps "PortIoTextPlaceStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 1219,0
-va (VaSet
-)
-xt "39000,21500,44000,22500"
-st "drs_address"
-blo "39000,22300"
+uid 1292,0
+va (VaSet
+)
+xt "44000,20500,49600,21500"
+st "config_rw_ack"
+blo "44000,21300"
 tm "WireNameMgr"
 )
@@ -2549,25 +2566,30 @@
 )
 *73 (Net
-uid 1220,0
-decl (Decl
-n "drs_address_mode"
+uid 1293,0
+decl (Decl
+n "config_rw_ready"
 t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
 o 18
-suid 20,0
+suid 23,0
+i "'0'"
 )
 declText (MLText
-uid 1221,0
+uid 1294,0
 va (VaSet
 font "Courier New,8,0"
 )
-xt "29000,11000,45000,11800"
-st "drs_address_mode  : std_logic
+xt "29000,10200,48500,11800"
+st "-- --
+config_rw_ready   : std_logic := '0'
 "
 )
 )
 *74 (PortIoOut
-uid 1228,0
+uid 1301,0
 shape (CompositeShape
-uid 1229,0
+uid 1302,0
 va (VaSet
 vasetType 1
@@ -2576,17 +2598,17 @@
 optionalChildren [
 (Pentagon
-uid 1230,0
+uid 1303,0
 sl 0
 ro 270
-xt "36500,20625,38000,21375"
+xt "41500,21625,43000,22375"
 )
 (Line
-uid 1231,0
+uid 1304,0
 sl 0
 ro 270
-xt "36000,21000,36500,21000"
+xt "41000,22000,41500,22000"
 pts [
-"36000,21000"
-"36500,21000"
+"41000,22000"
+"41500,22000"
 ]
 )
@@ -2596,14 +2618,14 @@
 sf 1
 tg (WTG
-uid 1232,0
+uid 1305,0
 ps "PortIoTextPlaceStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 1233,0
-va (VaSet
-)
-xt "39000,20500,46200,21500"
-st "drs_address_mode"
-blo "39000,21300"
+uid 1306,0
+va (VaSet
+)
+xt "44000,21500,50300,22500"
+st "config_rw_ready"
+blo "44000,22300"
 tm "WireNameMgr"
 )
@@ -3270,15 +3292,14 @@
 )
 *92 (Wire
-uid 1208,0
+uid 1281,0
 shape (OrthoPolyLine
-uid 1209,0
+uid 1282,0
 va (VaSet
 vasetType 3
-lineWidth 2
-)
-xt "32750,22000,36000,22000"
+)
+xt "32750,21000,41000,21000"
 pts [
-"32750,22000"
-"36000,22000"
+"32750,21000"
+"41000,21000"
 ]
 )
@@ -3287,5 +3308,4 @@
 sat 32
 eat 32
-sty 1
 stc 0
 st 0
@@ -3293,15 +3313,15 @@
 si 0
 tg (WTG
-uid 1212,0
+uid 1285,0
 ps "ConnStartEndStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 1213,0
+uid 1286,0
 va (VaSet
 isHidden 1
 )
-xt "34000,21000,39000,22000"
-st "drs_address"
-blo "34000,21800"
+xt "34000,20000,39600,21000"
+st "config_rw_ack"
+blo "34000,20800"
 tm "WireNameMgr"
 )
@@ -3310,14 +3330,14 @@
 )
 *93 (Wire
-uid 1222,0
+uid 1295,0
 shape (OrthoPolyLine
-uid 1223,0
+uid 1296,0
 va (VaSet
 vasetType 3
 )
-xt "32750,21000,36000,21000"
+xt "32750,22000,41000,22000"
 pts [
-"32750,21000"
-"36000,21000"
+"32750,22000"
+"41000,22000"
 ]
 )
@@ -3331,15 +3351,15 @@
 si 0
 tg (WTG
-uid 1226,0
+uid 1299,0
 ps "ConnStartEndStrategy"
 stg "STSignalDisplayStrategy"
 f (Text
-uid 1227,0
+uid 1300,0
 va (VaSet
 isHidden 1
 )
-xt "34000,20000,41200,21000"
-st "drs_address_mode"
-blo "34000,20800"
+xt "34000,21000,40300,22000"
+st "config_rw_ready"
+blo "34000,21800"
 tm "WireNameMgr"
 )
@@ -3459,5 +3479,5 @@
 associable 1
 )
-windowSize "0,0,1281,1002"
+windowSize "0,22,1281,1024"
 viewArea "-6400,12000,60443,65739"
 cachedDiagramExtent "700,0,59000,77000"
@@ -3487,5 +3507,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "0,0"
-lastUid 1237,0
+lastUid 1310,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -4471,7 +4491,7 @@
 font "Arial,8,1"
 )
-xt "27000,13400,34100,14400"
+xt "27000,15000,34100,16000"
 st "Diagram Signals:"
-blo "27000,14200"
+blo "27000,15800"
 )
 postUserLabel (Text
@@ -4497,5 +4517,5 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 20,0
+suid 23,0
 usingSuid 1
 emptyRow *125 (LEmptyRow
@@ -4734,12 +4754,15 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
 o 17
-suid 19,0
-)
-)
-uid 1234,0
+suid 22,0
+i "'0'"
+)
+)
+uid 1307,0
 )
 *155 (LeafLogPort
@@ -4747,11 +4770,15 @@
 m 1
 decl (Decl
-n "drs_address_mode"
+n "config_rw_ready"
 t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
 o 18
-suid 20,0
-)
-)
-uid 1236,0
+suid 23,0
+i "'0'"
+)
+)
+uid 1309,0
 )
 ]
@@ -4905,5 +4932,5 @@
 pos 16
 dimension 20
-uid 1235,0
+uid 1308,0
 )
 *178 (MRCItem
@@ -4911,5 +4938,5 @@
 pos 17
 dimension 20
-uid 1237,0
+uid 1310,0
 )
 ]
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/struct.bd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/struct.bd.bak	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/struct.bd.bak	(revision 10073)
@@ -251,5 +251,5 @@
 (vvPair
 variable "time"
-value "13:47:38"
+value "14:13:34"
 )
 (vvPair
@@ -622,5 +622,6 @@
 )
 xt "29000,2200,45000,3000"
-st "clk               : STD_LOGIC"
+st "clk               : STD_LOGIC
+"
 )
 )
@@ -639,6 +640,7 @@
 font "Courier New,8,0"
 )
-xt "29000,15200,58500,16000"
-st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)"
+xt "29000,16800,58500,17600"
+st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)
+"
 )
 )
@@ -658,5 +660,6 @@
 )
 xt "29000,3000,55000,3800"
-st "config_addr       : std_logic_vector(7 DOWNTO 0)"
+st "config_addr       : std_logic_vector(7 DOWNTO 0)
+"
 )
 )
@@ -675,6 +678,7 @@
 font "Courier New,8,0"
 )
-xt "29000,13600,59000,14400"
-st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)"
+xt "29000,15200,59000,16000"
+st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)
+"
 )
 )
@@ -693,5 +697,6 @@
 )
 xt "29000,7000,45000,7800"
-st "config_data_valid : std_logic"
+st "config_data_valid : std_logic
+"
 )
 )
@@ -710,5 +715,6 @@
 )
 xt "29000,6200,45000,7000"
-st "config_busy       : std_logic"
+st "config_busy       : std_logic
+"
 )
 )
@@ -727,6 +733,7 @@
 font "Courier New,8,0"
 )
-xt "29000,11000,55500,11800"
-st "config_data       : std_logic_vector(15 DOWNTO 0)"
+xt "29000,12600,55500,13400"
+st "config_data       : std_logic_vector(15 DOWNTO 0)
+"
 )
 )
@@ -744,6 +751,7 @@
 font "Courier New,8,0"
 )
-xt "29000,10200,47500,11000"
-st "roi_array         : roi_array_type"
+xt "29000,11800,47500,12600"
+st "roi_array         : roi_array_type
+"
 )
 )
@@ -762,6 +770,7 @@
 font "Courier New,8,0"
 )
-xt "29000,12800,58500,13600"
-st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)"
+xt "29000,14400,58500,15200"
+st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)
+"
 )
 )
@@ -780,5 +789,6 @@
 )
 xt "29000,5400,45000,6200"
-st "config_wr_en      : std_logic"
+st "config_wr_en      : std_logic
+"
 )
 )
@@ -797,6 +807,7 @@
 font "Courier New,8,0"
 )
-xt "29000,14400,59000,15200"
-st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)"
+xt "29000,16000,59000,16800"
+st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)
+"
 )
 )
@@ -815,5 +826,6 @@
 )
 xt "29000,9400,47500,10200"
-st "dac_array         : dac_array_type"
+st "dac_array         : dac_array_type
+"
 )
 )
@@ -832,5 +844,6 @@
 )
 xt "29000,3800,45000,4600"
-st "config_rd_en      : std_logic"
+st "config_rd_en      : std_logic
+"
 )
 )
@@ -849,5 +862,6 @@
 )
 xt "29000,4600,45000,5400"
-st "config_start      : std_logic"
+st "config_start      : std_logic
+"
 )
 )
@@ -866,5 +880,6 @@
 )
 xt "29000,7800,45000,8600"
-st "config_ready      : std_logic"
+st "config_ready      : std_logic
+"
 )
 )
@@ -1956,4 +1971,77 @@
 )
 )
+*55 (CptPort
+uid 1198,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1199,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32000,21625,32750,22375"
+)
+tg (CPTG
+uid 1200,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1201,0
+va (VaSet
+)
+xt "23800,21500,31000,22500"
+st "drs_address : (3:0)"
+ju 2
+blo "31000,22300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 17
+suid 24,0
+)
+)
+)
+*56 (CptPort
+uid 1202,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1203,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32000,20625,32750,21375"
+)
+tg (CPTG
+uid 1204,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1205,0
+va (VaSet
+)
+xt "23800,20500,31000,21500"
+st "drs_address_mode"
+ju 2
+blo "31000,21300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 18
+suid 25,0
+)
+)
+)
 ]
 shape (Rectangle
@@ -1965,5 +2053,5 @@
 lineWidth 2
 )
-xt "7000,23000,32000,42000"
+xt "7000,20000,32000,41000"
 )
 oxt "42000,14000,67000,32000"
@@ -1973,5 +2061,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*55 (Text
+*57 (Text
 uid 963,0
 va (VaSet
@@ -1983,5 +2071,5 @@
 tm "BdLibraryNameMgr"
 )
-*56 (Text
+*58 (Text
 uid 964,0
 va (VaSet
@@ -1993,5 +2081,5 @@
 tm "CptNameMgr"
 )
-*57 (Text
+*59 (Text
 uid 965,0
 va (VaSet
@@ -2015,5 +2103,5 @@
 font "Courier New,8,0"
 )
-xt "10000,20600,27500,23000"
+xt "10000,17600,27500,20000"
 st "NO_OF_ROI  = 36    ( integer )  
 NO_OF_DAC  = 8     ( integer )  
@@ -2047,5 +2135,5 @@
 fg "49152,49152,49152"
 )
-xt "7250,40250,8750,41750"
+xt "7250,39250,8750,40750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -2058,8 +2146,8 @@
 archFileType "UNKNOWN"
 )
-*58 (SaComponent
+*60 (SaComponent
 uid 993,0
 optionalChildren [
-*59 (CptPort
+*61 (CptPort
 uid 970,0
 ps "OnEdgeStrategy"
@@ -2099,5 +2187,5 @@
 )
 )
-*60 (CptPort
+*62 (CptPort
 uid 974,0
 ps "OnEdgeStrategy"
@@ -2136,5 +2224,5 @@
 )
 )
-*61 (CptPort
+*63 (CptPort
 uid 978,0
 ps "OnEdgeStrategy"
@@ -2173,5 +2261,5 @@
 )
 )
-*62 (CptPort
+*64 (CptPort
 uid 982,0
 ps "OnEdgeStrategy"
@@ -2210,5 +2298,5 @@
 )
 )
-*63 (CptPort
+*65 (CptPort
 uid 986,0
 ps "OnEdgeStrategy"
@@ -2266,5 +2354,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*64 (Text
+*66 (Text
 uid 996,0
 va (VaSet
@@ -2276,5 +2364,5 @@
 tm "BdLibraryNameMgr"
 )
-*65 (Text
+*67 (Text
 uid 997,0
 va (VaSet
@@ -2286,5 +2374,5 @@
 tm "CptNameMgr"
 )
-*66 (Text
+*68 (Text
 uid 998,0
 va (VaSet
@@ -2334,5 +2422,5 @@
 archFileType "UNKNOWN"
 )
-*67 (Net
+*69 (Net
 uid 1082,0
 decl (Decl
@@ -2349,8 +2437,9 @@
 )
 xt "29000,8600,48500,9400"
-st "config_started    : std_logic := '0'"
-)
-)
-*68 (PortIoOut
+st "config_started    : std_logic := '0'
+"
+)
+)
+*70 (PortIoOut
 uid 1090,0
 shape (CompositeShape
@@ -2396,5 +2485,130 @@
 )
 )
-*69 (Wire
+*71 (Net
+uid 1206,0
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 17
+suid 19,0
+)
+declText (MLText
+uid 1207,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "29000,10200,55000,11000"
+st "drs_address       : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*72 (PortIoOut
+uid 1214,0
+shape (CompositeShape
+uid 1215,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 1216,0
+sl 0
+ro 270
+xt "36500,21625,38000,22375"
+)
+(Line
+uid 1217,0
+sl 0
+ro 270
+xt "36000,22000,36500,22000"
+pts [
+"36000,22000"
+"36500,22000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 1218,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1219,0
+va (VaSet
+)
+xt "39000,21500,44000,22500"
+st "drs_address"
+blo "39000,22300"
+tm "WireNameMgr"
+)
+)
+)
+*73 (Net
+uid 1220,0
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 18
+suid 20,0
+)
+declText (MLText
+uid 1221,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "29000,11000,45000,11800"
+st "drs_address_mode  : std_logic
+"
+)
+)
+*74 (PortIoOut
+uid 1228,0
+shape (CompositeShape
+uid 1229,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 1230,0
+sl 0
+ro 270
+xt "36500,20625,38000,21375"
+)
+(Line
+uid 1231,0
+sl 0
+ro 270
+xt "36000,21000,36500,21000"
+pts [
+"36000,21000"
+"36500,21000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 1232,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1233,0
+va (VaSet
+)
+xt "39000,20500,46200,21500"
+st "drs_address_mode"
+blo "39000,21300"
+tm "WireNameMgr"
+)
+)
+)
+*75 (Wire
 uid 227,0
 shape (OrthoPolyLine
@@ -2436,5 +2650,5 @@
 on &14
 )
-*70 (Wire
+*76 (Wire
 uid 233,0
 shape (OrthoPolyLine
@@ -2452,5 +2666,5 @@
 ]
 )
-start &62
+start &64
 end &51
 sat 32
@@ -2476,5 +2690,5 @@
 on &13
 )
-*71 (Wire
+*77 (Wire
 uid 237,0
 shape (OrthoPolyLine
@@ -2492,5 +2706,5 @@
 ]
 )
-start &60
+start &62
 end &50
 sat 32
@@ -2516,5 +2730,5 @@
 on &15
 )
-*72 (Wire
+*78 (Wire
 uid 241,0
 shape (OrthoPolyLine
@@ -2556,5 +2770,5 @@
 on &12
 )
-*73 (Wire
+*79 (Wire
 uid 255,0
 shape (OrthoPolyLine
@@ -2594,5 +2808,5 @@
 on &16
 )
-*74 (Wire
+*80 (Wire
 uid 261,0
 shape (OrthoPolyLine
@@ -2632,5 +2846,5 @@
 on &17
 )
-*75 (Wire
+*81 (Wire
 uid 267,0
 shape (OrthoPolyLine
@@ -2672,5 +2886,5 @@
 on &18
 )
-*76 (Wire
+*82 (Wire
 uid 273,0
 shape (OrthoPolyLine
@@ -2710,5 +2924,5 @@
 on &19
 )
-*77 (Wire
+*83 (Wire
 uid 279,0
 shape (OrthoPolyLine
@@ -2723,5 +2937,5 @@
 ]
 )
-end &59
+end &61
 sat 16
 eat 32
@@ -2745,5 +2959,5 @@
 on &12
 )
-*78 (Wire
+*84 (Wire
 uid 285,0
 shape (OrthoPolyLine
@@ -2762,5 +2976,5 @@
 )
 start &53
-end &61
+end &63
 sat 32
 eat 32
@@ -2785,5 +2999,5 @@
 on &20
 )
-*79 (Wire
+*85 (Wire
 uid 289,0
 shape (OrthoPolyLine
@@ -2823,5 +3037,5 @@
 on &25
 )
-*80 (Wire
+*86 (Wire
 uid 295,0
 shape (OrthoPolyLine
@@ -2861,5 +3075,5 @@
 on &21
 )
-*81 (Wire
+*87 (Wire
 uid 301,0
 shape (OrthoPolyLine
@@ -2880,5 +3094,5 @@
 )
 start &52
-end &63
+end &65
 sat 32
 eat 32
@@ -2903,5 +3117,5 @@
 on &22
 )
-*82 (Wire
+*88 (Wire
 uid 305,0
 shape (OrthoPolyLine
@@ -2941,5 +3155,5 @@
 on &23
 )
-*83 (Wire
+*89 (Wire
 uid 311,0
 shape (OrthoPolyLine
@@ -2979,5 +3193,5 @@
 on &24
 )
-*84 (Wire
+*90 (Wire
 uid 321,0
 shape (OrthoPolyLine
@@ -3017,5 +3231,5 @@
 on &26
 )
-*85 (Wire
+*91 (Wire
 uid 1084,0
 shape (OrthoPolyLine
@@ -3031,5 +3245,5 @@
 )
 start &54
-end &68
+end &70
 sat 32
 eat 32
@@ -3053,5 +3267,83 @@
 )
 )
-on &67
+on &69
+)
+*92 (Wire
+uid 1208,0
+shape (OrthoPolyLine
+uid 1209,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "32750,22000,36000,22000"
+pts [
+"32750,22000"
+"36000,22000"
+]
+)
+start &55
+end &72
+sat 32
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 1212,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1213,0
+va (VaSet
+isHidden 1
+)
+xt "34000,21000,39000,22000"
+st "drs_address"
+blo "34000,21800"
+tm "WireNameMgr"
+)
+)
+on &71
+)
+*93 (Wire
+uid 1222,0
+shape (OrthoPolyLine
+uid 1223,0
+va (VaSet
+vasetType 3
+)
+xt "32750,21000,36000,21000"
+pts [
+"32750,21000"
+"36000,21000"
+]
+)
+start &56
+end &74
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 1226,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1227,0
+va (VaSet
+isHidden 1
+)
+xt "34000,20000,41200,21000"
+st "drs_address_mode"
+blo "34000,20800"
+tm "WireNameMgr"
+)
+)
+on &73
 )
 ]
@@ -3067,9 +3359,9 @@
 color "26368,26368,26368"
 )
-packageList *86 (PackageList
+packageList *94 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*87 (Text
+*95 (Text
 uid 42,0
 va (VaSet
@@ -3080,5 +3372,5 @@
 blo "1000,1800"
 )
-*88 (MLText
+*96 (MLText
 uid 43,0
 va (VaSet
@@ -3098,5 +3390,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*89 (Text
+*97 (Text
 uid 45,0
 va (VaSet
@@ -3108,5 +3400,5 @@
 blo "20000,800"
 )
-*90 (Text
+*98 (Text
 uid 46,0
 va (VaSet
@@ -3118,5 +3410,5 @@
 blo "20000,1800"
 )
-*91 (MLText
+*99 (MLText
 uid 47,0
 va (VaSet
@@ -3128,5 +3420,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*92 (Text
+*100 (Text
 uid 48,0
 va (VaSet
@@ -3138,5 +3430,5 @@
 blo "20000,4800"
 )
-*93 (MLText
+*101 (MLText
 uid 49,0
 va (VaSet
@@ -3146,5 +3438,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*94 (Text
+*102 (Text
 uid 50,0
 va (VaSet
@@ -3156,5 +3448,5 @@
 blo "20000,5800"
 )
-*95 (MLText
+*103 (MLText
 uid 51,0
 va (VaSet
@@ -3168,5 +3460,5 @@
 )
 windowSize "0,0,1281,1002"
-viewArea "-6400,12035,60443,65774"
+viewArea "-6400,12000,60443,65739"
 cachedDiagramExtent "700,0,59000,77000"
 pageSetupInfo (PageSetupInfo
@@ -3195,5 +3487,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "0,0"
-lastUid 1172,0
+lastUid 1237,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -3257,5 +3549,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*96 (Text
+*104 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3266,5 +3558,5 @@
 tm "BdLibraryNameMgr"
 )
-*97 (Text
+*105 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3275,5 +3567,5 @@
 tm "BlkNameMgr"
 )
-*98 (Text
+*106 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3326,5 +3618,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*99 (Text
+*107 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3334,5 +3626,5 @@
 blo "550,4300"
 )
-*100 (Text
+*108 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3342,5 +3634,5 @@
 blo "550,5300"
 )
-*101 (Text
+*109 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3391,5 +3683,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*102 (Text
+*110 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3400,5 +3692,5 @@
 tm "BdLibraryNameMgr"
 )
-*103 (Text
+*111 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3409,5 +3701,5 @@
 tm "CptNameMgr"
 )
-*104 (Text
+*112 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3463,5 +3755,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*105 (Text
+*113 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3471,5 +3763,5 @@
 blo "500,4300"
 )
-*106 (Text
+*114 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3479,5 +3771,5 @@
 blo "500,5300"
 )
-*107 (Text
+*115 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3524,5 +3816,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*108 (Text
+*116 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3532,5 +3824,5 @@
 blo "50,4300"
 )
-*109 (Text
+*117 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3540,5 +3832,5 @@
 blo "50,5300"
 )
-*110 (Text
+*118 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3581,5 +3873,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*111 (Text
+*119 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3590,5 +3882,5 @@
 tm "HdlTextNameMgr"
 )
-*112 (Text
+*120 (Text
 va (VaSet
 font "Arial,8,1"
@@ -3993,5 +4285,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*113 (Text
+*121 (Text
 va (VaSet
 font "Arial,8,1"
@@ -4001,5 +4293,5 @@
 blo "14100,20800"
 )
-*114 (MLText
+*122 (MLText
 va (VaSet
 )
@@ -4053,5 +4345,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*115 (Text
+*123 (Text
 va (VaSet
 font "Arial,8,1"
@@ -4061,5 +4353,5 @@
 blo "14100,20800"
 )
-*116 (MLText
+*124 (MLText
 va (VaSet
 )
@@ -4179,7 +4471,7 @@
 font "Arial,8,1"
 )
-xt "27000,11800,34100,12800"
+xt "27000,13400,34100,14400"
 st "Diagram Signals:"
-blo "27000,12600"
+blo "27000,14200"
 )
 postUserLabel (Text
@@ -4205,44 +4497,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 18,0
+suid 20,0
 usingSuid 1
-emptyRow *117 (LEmptyRow
+emptyRow *125 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*118 (RefLabelRowHdr
-)
-*119 (TitleRowHdr
-)
-*120 (FilterRowHdr
-)
-*121 (RefLabelColHdr
+*126 (RefLabelRowHdr
+)
+*127 (TitleRowHdr
+)
+*128 (FilterRowHdr
+)
+*129 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*122 (RowExpandColHdr
+*130 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*123 (GroupColHdr
+*131 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*124 (NameColHdr
+*132 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*125 (ModeColHdr
+*133 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*126 (TypeColHdr
+*134 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*127 (BoundsColHdr
+*135 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*128 (InitColHdr
+*136 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*129 (EolColHdr
+*137 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*130 (LeafLogPort
+*138 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -4255,5 +4547,5 @@
 uid 427,0
 )
-*131 (LeafLogPort
+*139 (LeafLogPort
 port (LogicalPort
 m 4
@@ -4268,5 +4560,5 @@
 uid 429,0
 )
-*132 (LeafLogPort
+*140 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -4280,5 +4572,5 @@
 uid 431,0
 )
-*133 (LeafLogPort
+*141 (LeafLogPort
 port (LogicalPort
 m 4
@@ -4293,5 +4585,5 @@
 uid 433,0
 )
-*134 (LeafLogPort
+*142 (LeafLogPort
 port (LogicalPort
 m 1
@@ -4305,5 +4597,5 @@
 uid 435,0
 )
-*135 (LeafLogPort
+*143 (LeafLogPort
 port (LogicalPort
 m 1
@@ -4317,5 +4609,5 @@
 uid 437,0
 )
-*136 (LeafLogPort
+*144 (LeafLogPort
 port (LogicalPort
 m 2
@@ -4330,5 +4622,5 @@
 uid 439,0
 )
-*137 (LeafLogPort
+*145 (LeafLogPort
 port (LogicalPort
 m 1
@@ -4342,5 +4634,5 @@
 uid 441,0
 )
-*138 (LeafLogPort
+*146 (LeafLogPort
 port (LogicalPort
 m 4
@@ -4355,5 +4647,5 @@
 uid 443,0
 )
-*139 (LeafLogPort
+*147 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -4366,5 +4658,5 @@
 uid 445,0
 )
-*140 (LeafLogPort
+*148 (LeafLogPort
 port (LogicalPort
 m 4
@@ -4379,5 +4671,5 @@
 uid 447,0
 )
-*141 (LeafLogPort
+*149 (LeafLogPort
 port (LogicalPort
 m 1
@@ -4391,5 +4683,5 @@
 uid 449,0
 )
-*142 (LeafLogPort
+*150 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -4402,5 +4694,5 @@
 uid 451,0
 )
-*143 (LeafLogPort
+*151 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -4413,5 +4705,5 @@
 uid 453,0
 )
-*144 (LeafLogPort
+*152 (LeafLogPort
 port (LogicalPort
 m 1
@@ -4425,5 +4717,5 @@
 uid 457,0
 )
-*145 (LeafLogPort
+*153 (LeafLogPort
 port (LogicalPort
 m 1
@@ -4438,4 +4730,29 @@
 uid 1096,0
 )
+*154 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_address"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 17
+suid 19,0
+)
+)
+uid 1234,0
+)
+*155 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_address_mode"
+t "std_logic"
+o 18
+suid 20,0
+)
+)
+uid 1236,0
+)
 ]
 )
@@ -4445,5 +4762,5 @@
 uid 67,0
 optionalChildren [
-*146 (Sheet
+*156 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -4462,25 +4779,25 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *147 (MRCItem
-litem &117
-pos 16
+emptyMRCItem *157 (MRCItem
+litem &125
+pos 18
 dimension 20
 )
 uid 69,0
 optionalChildren [
-*148 (MRCItem
-litem &118
+*158 (MRCItem
+litem &126
 pos 0
 dimension 20
 uid 70,0
 )
-*149 (MRCItem
-litem &119
+*159 (MRCItem
+litem &127
 pos 1
 dimension 23
 uid 71,0
 )
-*150 (MRCItem
-litem &120
+*160 (MRCItem
+litem &128
 pos 2
 hidden 1
@@ -4488,99 +4805,111 @@
 uid 72,0
 )
-*151 (MRCItem
-litem &130
+*161 (MRCItem
+litem &138
 pos 0
 dimension 20
 uid 428,0
 )
-*152 (MRCItem
-litem &131
+*162 (MRCItem
+litem &139
 pos 11
 dimension 20
 uid 430,0
 )
-*153 (MRCItem
-litem &132
+*163 (MRCItem
+litem &140
 pos 1
 dimension 20
 uid 432,0
 )
-*154 (MRCItem
-litem &133
+*164 (MRCItem
+litem &141
 pos 12
 dimension 20
 uid 434,0
 )
-*155 (MRCItem
-litem &134
+*165 (MRCItem
+litem &142
 pos 2
 dimension 20
 uid 436,0
 )
-*156 (MRCItem
-litem &135
+*166 (MRCItem
+litem &143
 pos 3
 dimension 20
 uid 438,0
 )
-*157 (MRCItem
-litem &136
+*167 (MRCItem
+litem &144
 pos 4
 dimension 20
 uid 440,0
 )
-*158 (MRCItem
-litem &137
+*168 (MRCItem
+litem &145
 pos 5
 dimension 20
 uid 442,0
 )
-*159 (MRCItem
-litem &138
+*169 (MRCItem
+litem &146
 pos 13
 dimension 20
 uid 444,0
 )
-*160 (MRCItem
-litem &139
+*170 (MRCItem
+litem &147
 pos 6
 dimension 20
 uid 446,0
 )
-*161 (MRCItem
-litem &140
+*171 (MRCItem
+litem &148
 pos 14
 dimension 20
 uid 448,0
 )
-*162 (MRCItem
-litem &141
+*172 (MRCItem
+litem &149
 pos 7
 dimension 20
 uid 450,0
 )
-*163 (MRCItem
-litem &142
+*173 (MRCItem
+litem &150
 pos 8
 dimension 20
 uid 452,0
 )
-*164 (MRCItem
-litem &143
+*174 (MRCItem
+litem &151
 pos 9
 dimension 20
 uid 454,0
 )
-*165 (MRCItem
-litem &144
+*175 (MRCItem
+litem &152
 pos 10
 dimension 20
 uid 458,0
 )
-*166 (MRCItem
-litem &145
+*176 (MRCItem
+litem &153
 pos 15
 dimension 20
 uid 1097,0
+)
+*177 (MRCItem
+litem &154
+pos 16
+dimension 20
+uid 1235,0
+)
+*178 (MRCItem
+litem &155
+pos 17
+dimension 20
+uid 1237,0
 )
 ]
@@ -4595,48 +4924,48 @@
 uid 73,0
 optionalChildren [
-*167 (MRCItem
-litem &121
+*179 (MRCItem
+litem &129
 pos 0
 dimension 20
 uid 74,0
 )
-*168 (MRCItem
-litem &123
+*180 (MRCItem
+litem &131
 pos 1
 dimension 50
 uid 75,0
 )
-*169 (MRCItem
-litem &124
+*181 (MRCItem
+litem &132
 pos 2
 dimension 100
 uid 76,0
 )
-*170 (MRCItem
-litem &125
+*182 (MRCItem
+litem &133
 pos 3
 dimension 50
 uid 77,0
 )
-*171 (MRCItem
-litem &126
+*183 (MRCItem
+litem &134
 pos 4
 dimension 100
 uid 78,0
 )
-*172 (MRCItem
-litem &127
+*184 (MRCItem
+litem &135
 pos 5
 dimension 100
 uid 79,0
 )
-*173 (MRCItem
-litem &128
+*185 (MRCItem
+litem &136
 pos 6
 dimension 50
 uid 80,0
 )
-*174 (MRCItem
-litem &129
+*186 (MRCItem
+litem &137
 pos 7
 dimension 80
@@ -4658,36 +4987,36 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *175 (LEmptyRow
+emptyRow *187 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*176 (RefLabelRowHdr
-)
-*177 (TitleRowHdr
-)
-*178 (FilterRowHdr
-)
-*179 (RefLabelColHdr
+*188 (RefLabelRowHdr
+)
+*189 (TitleRowHdr
+)
+*190 (FilterRowHdr
+)
+*191 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*180 (RowExpandColHdr
+*192 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*181 (GroupColHdr
+*193 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*182 (NameColHdr
+*194 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*183 (TypeColHdr
+*195 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*184 (InitColHdr
+*196 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*185 (PragmaColHdr
+*197 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*186 (EolColHdr
+*198 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
@@ -4699,5 +5028,5 @@
 uid 95,0
 optionalChildren [
-*187 (Sheet
+*199 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -4716,6 +5045,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *188 (MRCItem
-litem &175
+emptyMRCItem *200 (MRCItem
+litem &187
 pos 0
 dimension 20
@@ -4723,18 +5052,18 @@
 uid 97,0
 optionalChildren [
-*189 (MRCItem
-litem &176
+*201 (MRCItem
+litem &188
 pos 0
 dimension 20
 uid 98,0
 )
-*190 (MRCItem
-litem &177
+*202 (MRCItem
+litem &189
 pos 1
 dimension 23
 uid 99,0
 )
-*191 (MRCItem
-litem &178
+*203 (MRCItem
+litem &190
 pos 2
 hidden 1
@@ -4753,42 +5082,42 @@
 uid 101,0
 optionalChildren [
-*192 (MRCItem
-litem &179
+*204 (MRCItem
+litem &191
 pos 0
 dimension 20
 uid 102,0
 )
-*193 (MRCItem
-litem &181
+*205 (MRCItem
+litem &193
 pos 1
 dimension 50
 uid 103,0
 )
-*194 (MRCItem
-litem &182
+*206 (MRCItem
+litem &194
 pos 2
 dimension 100
 uid 104,0
 )
-*195 (MRCItem
-litem &183
+*207 (MRCItem
+litem &195
 pos 3
 dimension 100
 uid 105,0
 )
-*196 (MRCItem
-litem &184
+*208 (MRCItem
+litem &196
 pos 4
 dimension 50
 uid 106,0
 )
-*197 (MRCItem
-litem &185
+*209 (MRCItem
+litem &197
 pos 5
 dimension 50
 uid 107,0
 )
-*198 (MRCItem
-litem &186
+*210 (MRCItem
+litem &198
 pos 6
 dimension 80
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/control_unit/symbol.sb	(revision 10073)
@@ -29,5 +29,5 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 14,0
+suid 16,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -157,5 +157,5 @@
 n "dac_array"
 t "dac_array_type"
-o 10
+o 12
 suid 8,0
 )
@@ -203,5 +203,5 @@
 n "config_started"
 t "std_logic"
-o 9
+o 11
 suid 12,0
 i "'0'"
@@ -214,12 +214,15 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 11
-suid 13,0
-)
-)
-uid 518,0
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
+suid 15,0
+i "'0'"
+)
+)
+uid 555,0
 )
 *27 (LogPort
@@ -227,11 +230,15 @@
 m 1
 decl (Decl
-n "drs_address_mode"
+n "config_rw_ready"
 t "std_logic"
-o 12
-suid 14,0
-)
-)
-uid 520,0
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
+suid 16,0
+i "'0'"
+)
+)
+uid 557,0
 )
 ]
@@ -361,5 +368,5 @@
 pos 12
 dimension 20
-uid 517,0
+uid 554,0
 )
 *46 (MRCItem
@@ -367,5 +374,5 @@
 pos 13
 dimension 20
-uid 519,0
+uid 556,0
 )
 ]
@@ -598,21 +605,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -630,13 +637,13 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit"
 )
 (vvPair
 variable "date"
-value "12.07.2010"
+value "03.01.2011"
 )
 (vvPair
@@ -650,5 +657,5 @@
 (vvPair
 variable "dd"
-value "12"
+value "03"
 )
 (vvPair
@@ -678,5 +685,5 @@
 (vvPair
 variable "host"
-value "TU-CC4900F8C7D2"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -689,4 +696,8 @@
 )
 (vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
+)
+(vvPair
 variable "library_downstream_ISEPARInvoke"
 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
@@ -706,5 +717,5 @@
 (vvPair
 variable "mm"
-value "07"
+value "01"
 )
 (vvPair
@@ -714,17 +725,17 @@
 (vvPair
 variable "month"
-value "Jul"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "Juli"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
 )
 (vvPair
@@ -782,5 +793,5 @@
 (vvPair
 variable "time"
-value "14:13:34"
+value "16:29:16"
 )
 (vvPair
@@ -802,9 +813,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -1030,5 +1041,5 @@
 font "Courier New,8,0"
 )
-xt "44000,12400,74500,13200"
+xt "44000,14000,74500,14800"
 st "config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
 "
@@ -1077,5 +1088,5 @@
 font "Courier New,8,0"
 )
-xt "44000,11600,68000,12400"
+xt "44000,13200,68000,14000"
 st "roi_array         : OUT    roi_array_type  ;
 "
@@ -1168,5 +1179,5 @@
 font "Courier New,8,0"
 )
-xt "44000,9200,68000,10000"
+xt "44000,12400,68000,13200"
 st "dac_array         : OUT    dac_array_type  ;
 "
@@ -1177,5 +1188,5 @@
 n "dac_array"
 t "dac_array_type"
-o 10
+o 12
 suid 8,0
 )
@@ -1360,5 +1371,5 @@
 font "Courier New,8,0"
 )
-xt "44000,8400,69000,9200"
+xt "44000,11600,69000,12400"
 st "config_started    : OUT    std_logic  := '0' ;
 "
@@ -1369,5 +1380,5 @@
 n "config_started"
 t "std_logic"
-o 9
+o 11
 suid 12,0
 i "'0'"
@@ -1376,8 +1387,8 @@
 )
 *92 (CptPort
-uid 521,0
+uid 558,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 522,0
+uid 559,0
 ro 90
 va (VaSet
@@ -1388,25 +1399,36 @@
 )
 tg (CPTG
-uid 523,0
+uid 560,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 524,0
-va (VaSet
-)
-xt "24800,28500,32000,29500"
-st "drs_address : (3:0)"
+uid 561,0
+va (VaSet
+)
+xt "26400,28500,32000,29500"
+st "config_rw_ack"
 ju 2
 blo "32000,29300"
 tm "CptPortNameMgr"
 )
+t (Text
+uid 562,0
+va (VaSet
+)
+xt "30800,29500,32000,30500"
+st "'0'"
+ju 2
+blo "32000,30300"
+tm "InitValueDelayMgr"
+)
 )
 dt (MLText
-uid 525,0
+uid 563,0
 va (VaSet
 font "Courier New,8,0"
 )
-xt "44000,10000,75000,10800"
-st "drs_address       : OUT    std_logic_vector (3 DOWNTO 0) ;
+xt "44000,8400,69000,10000"
+st "-- --
+config_rw_ack     : OUT    std_logic  := '0' ;
 "
 )
@@ -1414,17 +1436,20 @@
 m 1
 decl (Decl
-n "drs_address"
-t "std_logic_vector"
-b "(3 DOWNTO 0)"
-o 11
-suid 13,0
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
+suid 15,0
+i "'0'"
 )
 )
 )
 *93 (CptPort
-uid 526,0
+uid 564,0
 ps "OnEdgeStrategy"
 shape (Triangle
-uid 527,0
+uid 565,0
 ro 90
 va (VaSet
@@ -1435,25 +1460,36 @@
 )
 tg (CPTG
-uid 528,0
+uid 566,0
 ps "CptPortTextPlaceStrategy"
 stg "RightVerticalLayoutStrategy"
 f (Text
-uid 529,0
-va (VaSet
-)
-xt "24800,30500,32000,31500"
-st "drs_address_mode"
+uid 567,0
+va (VaSet
+)
+xt "25700,30500,32000,31500"
+st "config_rw_ready"
 ju 2
 blo "32000,31300"
 tm "CptPortNameMgr"
 )
+t (Text
+uid 568,0
+va (VaSet
+)
+xt "30800,31500,32000,32500"
+st "'0'"
+ju 2
+blo "32000,32300"
+tm "InitValueDelayMgr"
+)
 )
 dt (MLText
-uid 530,0
+uid 569,0
 va (VaSet
 font "Courier New,8,0"
 )
-xt "44000,10800,65000,11600"
-st "drs_address_mode  : OUT    std_logic  ;
+xt "44000,10000,69000,11600"
+st "-- --
+config_rw_ready   : OUT    std_logic  := '0' ;
 "
 )
@@ -1461,8 +1497,12 @@
 m 1
 decl (Decl
-n "drs_address_mode"
+n "config_rw_ready"
 t "std_logic"
-o 12
-suid 14,0
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
+suid 16,0
+i "'0'"
 )
 )
@@ -2105,7 +2145,7 @@
 font "Arial,8,1"
 )
-xt "42000,13200,44400,14200"
+xt "42000,14800,44400,15800"
 st "User:"
-blo "42000,14000"
+blo "42000,15600"
 )
 internalLabel (Text
@@ -2124,5 +2164,5 @@
 font "Courier New,8,0"
 )
-xt "44000,14200,44000,14200"
+xt "44000,15800,44000,15800"
 tm "SyDeclarativeTextMgr"
 )
@@ -2137,5 +2177,5 @@
 )
 )
-lastUid 530,0
+lastUid 569,0
 okToSyncOnLoad 1
 OkToSyncGenericsOnLoad 1
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb	(revision 10073)
@@ -34,5 +34,5 @@
 ldm (LogicalDM
 ordering 1
-suid 55,0
+suid 60,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -78,4 +78,5 @@
 n "clk"
 t "std_logic"
+prec "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');"
 preAdd 0
 posAdd 0
@@ -154,5 +155,5 @@
 preAdd 0
 posAdd 0
-o 23
+o 24
 suid 9,0
 )
@@ -168,5 +169,5 @@
 preAdd 0
 posAdd 0
-o 25
+o 26
 suid 10,0
 )
@@ -181,5 +182,5 @@
 preAdd 0
 posAdd 0
-o 26
+o 27
 suid 11,0
 )
@@ -193,5 +194,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 24
+o 25
 suid 12,0
 )
@@ -216,4 +217,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 7
 suid 17,0
@@ -228,5 +230,5 @@
 n "roi_max"
 t "roi_max_type"
-o 18
+o 19
 suid 18,0
 )
@@ -239,5 +241,5 @@
 n "roi_array"
 t "roi_array_type"
-o 17
+o 18
 suid 19,0
 )
@@ -251,5 +253,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 22
+o 23
 suid 20,0
 )
@@ -315,5 +317,5 @@
 n "drs_read_s_cell_ready"
 t "std_logic"
-o 38
+o 42
 suid 34,0
 )
@@ -326,5 +328,5 @@
 n "drs_s_cell_array"
 t "drs_s_cell_array_type"
-o 39
+o 43
 suid 35,0
 )
@@ -361,5 +363,5 @@
 n "config_ready_cm"
 t "std_logic"
-o 12
+o 13
 suid 39,0
 )
@@ -373,5 +375,8 @@
 n "config_start_cm"
 t "std_logic"
-o 9
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
 suid 40,0
 i "'0'"
@@ -383,40 +388,29 @@
 port (LogicalPort
 decl (Decl
-n "s_trigger"
-t "std_logic"
-o 27
-suid 41,0
-)
-)
-uid 1023,0
+n "config_ready_mm"
+t "std_logic"
+o 12
+suid 42,0
+)
+)
+uid 1058,0
 )
 *39 (LogPort
 port (LogicalPort
 decl (Decl
-n "config_ready_mm"
-t "std_logic"
-o 11
-suid 42,0
-)
-)
-uid 1058,0
+n "config_ready_spi"
+t "std_logic"
+o 14
+suid 43,0
+)
+)
+uid 1060,0
 )
 *40 (LogPort
-port (LogicalPort
-decl (Decl
-n "config_ready_spi"
-t "std_logic"
-o 13
-suid 43,0
-)
-)
-uid 1060,0
-)
-*41 (LogPort
 port (LogicalPort
 decl (Decl
 n "sensor_array"
 t "sensor_array_type"
-o 19
+o 20
 suid 44,0
 )
@@ -424,22 +418,25 @@
 uid 1095,0
 )
+*41 (LogPort
+port (LogicalPort
+decl (Decl
+n "sensor_ready"
+t "std_logic"
+o 21
+suid 45,0
+)
+)
+uid 1097,0
+)
 *42 (LogPort
 port (LogicalPort
-decl (Decl
-n "sensor_ready"
-t "std_logic"
-o 20
-suid 45,0
-)
-)
-uid 1097,0
-)
-*43 (LogPort
-port (LogicalPort
 m 1
 decl (Decl
 n "config_start_mm"
 t "std_logic"
-o 8
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
 suid 46,0
 i "'0'"
@@ -448,5 +445,5 @@
 uid 1132,0
 )
-*44 (LogPort
+*43 (LogPort
 port (LogicalPort
 m 1
@@ -454,5 +451,7 @@
 n "config_start_spi"
 t "std_logic"
-o 10
+prec "-- --"
+preAdd 0
+o 11
 suid 47,0
 i "'0'"
@@ -461,5 +460,5 @@
 uid 1134,0
 )
-*45 (LogPort
+*44 (LogPort
 port (LogicalPort
 m 1
@@ -474,9 +473,11 @@
 uid 1169,0
 )
-*46 (LogPort
+*45 (LogPort
 port (LogicalPort
 decl (Decl
 n "new_config"
 t "std_logic"
+prec "--      s_trigger      : in std_logic;"
+preAdd 0
 o 28
 suid 49,0
@@ -485,43 +486,43 @@
 uid 1171,0
 )
+*46 (LogPort
+port (LogicalPort
+decl (Decl
+n "config_started_cm"
+t "std_logic"
+o 16
+suid 50,0
+)
+)
+uid 1211,0
+)
 *47 (LogPort
 port (LogicalPort
 decl (Decl
-n "config_started_cm"
+n "config_started_mm"
 t "std_logic"
 o 15
-suid 50,0
-)
-)
-uid 1211,0
+suid 51,0
+)
+)
+uid 1213,0
 )
 *48 (LogPort
 port (LogicalPort
 decl (Decl
-n "config_started_mm"
-t "std_logic"
-o 14
-suid 51,0
-)
-)
-uid 1213,0
+n "config_started_spi"
+t "std_logic"
+o 17
+suid 52,0
+)
+)
+uid 1215,0
 )
 *49 (LogPort
-port (LogicalPort
-decl (Decl
-n "config_started_spi"
-t "std_logic"
-o 16
-suid 52,0
-)
-)
-uid 1215,0
-)
-*50 (LogPort
 port (LogicalPort
 decl (Decl
 n "dac_array"
 t "dac_array_type"
-o 21
+o 22
 suid 53,0
 )
@@ -529,5 +530,5 @@
 uid 1245,0
 )
-*51 (LogPort
+*50 (LogPort
 port (LogicalPort
 m 1
@@ -542,5 +543,5 @@
 uid 1400,0
 )
-*52 (LogPort
+*51 (LogPort
 port (LogicalPort
 decl (Decl
@@ -554,4 +555,67 @@
 uid 1432,0
 )
+*52 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_data"
+t "std_logic_vector"
+b "(7 downto 0)"
+o 40
+suid 56,0
+i "(others => '0')"
+)
+)
+uid 1484,0
+)
+*53 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_write_8b"
+t "std_logic"
+o 38
+suid 57,0
+i "'0'"
+)
+)
+uid 1486,0
+)
+*54 (LogPort
+port (LogicalPort
+decl (Decl
+n "drs_srin_write_ack"
+t "std_logic"
+o 39
+suid 58,0
+)
+)
+uid 1488,0
+)
+*55 (LogPort
+port (LogicalPort
+decl (Decl
+n "drs_srin_write_ready"
+t "std_logic"
+o 41
+suid 59,0
+)
+)
+uid 1490,0
+)
+*56 (LogPort
+port (LogicalPort
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 8
+suid 60,0
+)
+)
+uid 1492,0
+)
 ]
 )
@@ -561,5 +625,5 @@
 uid 149,0
 optionalChildren [
-*53 (Sheet
+*57 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -578,5 +642,5 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *54 (MRCItem
+emptyMRCItem *58 (MRCItem
 litem &1
 pos 3
@@ -585,5 +649,5 @@
 uid 151,0
 optionalChildren [
-*55 (MRCItem
+*59 (MRCItem
 litem &2
 pos 0
@@ -591,5 +655,5 @@
 uid 152,0
 )
-*56 (MRCItem
+*60 (MRCItem
 litem &3
 pos 1
@@ -597,5 +661,5 @@
 uid 153,0
 )
-*57 (MRCItem
+*61 (MRCItem
 litem &4
 pos 2
@@ -604,5 +668,5 @@
 uid 154,0
 )
-*58 (MRCItem
+*62 (MRCItem
 litem &14
 pos 0
@@ -610,5 +674,5 @@
 uid 110,0
 )
-*59 (MRCItem
+*63 (MRCItem
 litem &15
 pos 1
@@ -616,5 +680,5 @@
 uid 112,0
 )
-*60 (MRCItem
+*64 (MRCItem
 litem &16
 pos 2
@@ -622,5 +686,5 @@
 uid 114,0
 )
-*61 (MRCItem
+*65 (MRCItem
 litem &17
 pos 3
@@ -628,5 +692,5 @@
 uid 120,0
 )
-*62 (MRCItem
+*66 (MRCItem
 litem &18
 pos 4
@@ -634,5 +698,5 @@
 uid 122,0
 )
-*63 (MRCItem
+*67 (MRCItem
 litem &19
 pos 5
@@ -640,5 +704,5 @@
 uid 126,0
 )
-*64 (MRCItem
+*68 (MRCItem
 litem &20
 pos 6
@@ -646,5 +710,5 @@
 uid 128,0
 )
-*65 (MRCItem
+*69 (MRCItem
 litem &21
 pos 7
@@ -652,5 +716,5 @@
 uid 130,0
 )
-*66 (MRCItem
+*70 (MRCItem
 litem &22
 pos 8
@@ -658,5 +722,5 @@
 uid 291,0
 )
-*67 (MRCItem
+*71 (MRCItem
 litem &23
 pos 9
@@ -664,5 +728,5 @@
 uid 422,0
 )
-*68 (MRCItem
+*72 (MRCItem
 litem &24
 pos 10
@@ -670,5 +734,5 @@
 uid 424,0
 )
-*69 (MRCItem
+*73 (MRCItem
 litem &25
 pos 11
@@ -676,5 +740,5 @@
 uid 426,0
 )
-*70 (MRCItem
+*74 (MRCItem
 litem &26
 pos 12
@@ -682,5 +746,5 @@
 uid 479,0
 )
-*71 (MRCItem
+*75 (MRCItem
 litem &27
 pos 13
@@ -688,5 +752,5 @@
 uid 532,0
 )
-*72 (MRCItem
+*76 (MRCItem
 litem &28
 pos 14
@@ -694,5 +758,5 @@
 uid 650,0
 )
-*73 (MRCItem
+*77 (MRCItem
 litem &29
 pos 15
@@ -700,5 +764,5 @@
 uid 702,0
 )
-*74 (MRCItem
+*78 (MRCItem
 litem &30
 pos 16
@@ -706,5 +770,5 @@
 uid 704,0
 )
-*75 (MRCItem
+*79 (MRCItem
 litem &31
 pos 17
@@ -712,5 +776,5 @@
 uid 817,0
 )
-*76 (MRCItem
+*80 (MRCItem
 litem &32
 pos 18
@@ -718,5 +782,5 @@
 uid 819,0
 )
-*77 (MRCItem
+*81 (MRCItem
 litem &33
 pos 19
@@ -724,5 +788,5 @@
 uid 821,0
 )
-*78 (MRCItem
+*82 (MRCItem
 litem &34
 pos 20
@@ -730,5 +794,5 @@
 uid 851,0
 )
-*79 (MRCItem
+*83 (MRCItem
 litem &35
 pos 21
@@ -736,5 +800,5 @@
 uid 904,0
 )
-*80 (MRCItem
+*84 (MRCItem
 litem &36
 pos 22
@@ -742,5 +806,5 @@
 uid 969,0
 )
-*81 (MRCItem
+*85 (MRCItem
 litem &37
 pos 23
@@ -748,93 +812,117 @@
 uid 971,0
 )
-*82 (MRCItem
+*86 (MRCItem
 litem &38
 pos 24
 dimension 20
-uid 1024,0
-)
-*83 (MRCItem
+uid 1059,0
+)
+*87 (MRCItem
 litem &39
 pos 25
 dimension 20
-uid 1059,0
-)
-*84 (MRCItem
+uid 1061,0
+)
+*88 (MRCItem
 litem &40
 pos 26
 dimension 20
-uid 1061,0
-)
-*85 (MRCItem
+uid 1096,0
+)
+*89 (MRCItem
 litem &41
 pos 27
 dimension 20
-uid 1096,0
-)
-*86 (MRCItem
+uid 1098,0
+)
+*90 (MRCItem
 litem &42
 pos 28
 dimension 20
-uid 1098,0
-)
-*87 (MRCItem
+uid 1133,0
+)
+*91 (MRCItem
 litem &43
 pos 29
 dimension 20
-uid 1133,0
-)
-*88 (MRCItem
+uid 1135,0
+)
+*92 (MRCItem
 litem &44
 pos 30
 dimension 20
-uid 1135,0
-)
-*89 (MRCItem
+uid 1170,0
+)
+*93 (MRCItem
 litem &45
 pos 31
 dimension 20
-uid 1170,0
-)
-*90 (MRCItem
+uid 1172,0
+)
+*94 (MRCItem
 litem &46
 pos 32
 dimension 20
-uid 1172,0
-)
-*91 (MRCItem
+uid 1212,0
+)
+*95 (MRCItem
 litem &47
 pos 33
 dimension 20
-uid 1212,0
-)
-*92 (MRCItem
+uid 1214,0
+)
+*96 (MRCItem
 litem &48
 pos 34
 dimension 20
-uid 1214,0
-)
-*93 (MRCItem
+uid 1216,0
+)
+*97 (MRCItem
 litem &49
 pos 35
 dimension 20
-uid 1216,0
-)
-*94 (MRCItem
+uid 1246,0
+)
+*98 (MRCItem
 litem &50
 pos 36
 dimension 20
-uid 1246,0
-)
-*95 (MRCItem
+uid 1401,0
+)
+*99 (MRCItem
 litem &51
 pos 37
 dimension 20
-uid 1401,0
-)
-*96 (MRCItem
+uid 1433,0
+)
+*100 (MRCItem
 litem &52
 pos 38
 dimension 20
-uid 1433,0
+uid 1485,0
+)
+*101 (MRCItem
+litem &53
+pos 39
+dimension 20
+uid 1487,0
+)
+*102 (MRCItem
+litem &54
+pos 40
+dimension 20
+uid 1489,0
+)
+*103 (MRCItem
+litem &55
+pos 41
+dimension 20
+uid 1491,0
+)
+*104 (MRCItem
+litem &56
+pos 42
+dimension 20
+uid 1493,0
 )
 ]
@@ -849,5 +937,5 @@
 uid 155,0
 optionalChildren [
-*97 (MRCItem
+*105 (MRCItem
 litem &5
 pos 0
@@ -855,5 +943,5 @@
 uid 156,0
 )
-*98 (MRCItem
+*106 (MRCItem
 litem &7
 pos 1
@@ -861,5 +949,5 @@
 uid 157,0
 )
-*99 (MRCItem
+*107 (MRCItem
 litem &8
 pos 2
@@ -867,5 +955,5 @@
 uid 158,0
 )
-*100 (MRCItem
+*108 (MRCItem
 litem &9
 pos 3
@@ -873,5 +961,5 @@
 uid 159,0
 )
-*101 (MRCItem
+*109 (MRCItem
 litem &10
 pos 4
@@ -879,5 +967,5 @@
 uid 160,0
 )
-*102 (MRCItem
+*110 (MRCItem
 litem &11
 pos 5
@@ -885,5 +973,5 @@
 uid 161,0
 )
-*103 (MRCItem
+*111 (MRCItem
 litem &12
 pos 6
@@ -891,5 +979,5 @@
 uid 162,0
 )
-*104 (MRCItem
+*112 (MRCItem
 litem &13
 pos 7
@@ -912,39 +1000,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *105 (LEmptyRow
+emptyRow *113 (LEmptyRow
 )
 uid 165,0
 optionalChildren [
-*106 (RefLabelRowHdr
-)
-*107 (TitleRowHdr
-)
-*108 (FilterRowHdr
-)
-*109 (RefLabelColHdr
+*114 (RefLabelRowHdr
+)
+*115 (TitleRowHdr
+)
+*116 (FilterRowHdr
+)
+*117 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*110 (RowExpandColHdr
+*118 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*111 (GroupColHdr
+*119 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*112 (NameColHdr
+*120 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*113 (TypeColHdr
+*121 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*114 (InitColHdr
+*122 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*115 (PragmaColHdr
+*123 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*116 (EolColHdr
+*124 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*117 (LogGeneric
+*125 (LogGeneric
 generic (GiElement
 name "RAM_ADDR_WIDTH"
@@ -952,5 +1040,5 @@
 value "12"
 )
-uid 1434,0
+uid 1494,0
 )
 ]
@@ -961,5 +1049,5 @@
 uid 177,0
 optionalChildren [
-*118 (Sheet
+*126 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -978,6 +1066,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *119 (MRCItem
-litem &105
+emptyMRCItem *127 (MRCItem
+litem &113
 pos 3
 dimension 20
@@ -985,18 +1073,18 @@
 uid 179,0
 optionalChildren [
-*120 (MRCItem
-litem &106
+*128 (MRCItem
+litem &114
 pos 0
 dimension 20
 uid 180,0
 )
-*121 (MRCItem
-litem &107
+*129 (MRCItem
+litem &115
 pos 1
 dimension 23
 uid 181,0
 )
-*122 (MRCItem
-litem &108
+*130 (MRCItem
+litem &116
 pos 2
 hidden 1
@@ -1004,9 +1092,9 @@
 uid 182,0
 )
-*123 (MRCItem
-litem &117
+*131 (MRCItem
+litem &125
 pos 0
 dimension 20
-uid 1435,0
+uid 1495,0
 )
 ]
@@ -1021,42 +1109,42 @@
 uid 183,0
 optionalChildren [
-*124 (MRCItem
-litem &109
+*132 (MRCItem
+litem &117
 pos 0
 dimension 20
 uid 184,0
 )
-*125 (MRCItem
-litem &111
+*133 (MRCItem
+litem &119
 pos 1
 dimension 50
 uid 185,0
 )
-*126 (MRCItem
-litem &112
+*134 (MRCItem
+litem &120
 pos 2
 dimension 100
 uid 186,0
 )
-*127 (MRCItem
-litem &113
+*135 (MRCItem
+litem &121
 pos 3
 dimension 100
 uid 187,0
 )
-*128 (MRCItem
-litem &114
+*136 (MRCItem
+litem &122
 pos 4
 dimension 50
 uid 188,0
 )
-*129 (MRCItem
-litem &115
+*137 (MRCItem
+litem &123
 pos 5
 dimension 50
 uid 189,0
 )
-*130 (MRCItem
-litem &116
+*138 (MRCItem
+litem &124
 pos 6
 dimension 80
@@ -1081,21 +1169,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -1113,13 +1201,13 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\data_generator"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\data_generator"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"
 )
 (vvPair
 variable "date"
-value "02.08.2010"
+value "03.01.2011"
 )
 (vvPair
@@ -1133,5 +1221,5 @@
 (vvPair
 variable "dd"
-value "02"
+value "03"
 )
 (vvPair
@@ -1197,5 +1285,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -1205,17 +1293,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"
 )
 (vvPair
@@ -1273,5 +1361,5 @@
 (vvPair
 variable "time"
-value "13:38:20"
+value "16:31:49"
 )
 (vvPair
@@ -1293,9 +1381,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -1304,8 +1392,8 @@
 uid 134,0
 optionalChildren [
-*131 (SymbolBody
+*139 (SymbolBody
 uid 8,0
 optionalChildren [
-*132 (CptPort
+*140 (CptPort
 uid 48,0
 ps "OnEdgeStrategy"
@@ -1338,6 +1426,7 @@
 font "Courier New,8,0"
 )
-xt "2000,12000,25500,12800"
-st "clk                   : IN     std_logic  ;
+xt "2000,12000,44500,13600"
+st "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+clk                   : IN     std_logic  ;
 "
 )
@@ -1346,4 +1435,5 @@
 n "clk"
 t "std_logic"
+prec "--      led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');"
 preAdd 0
 posAdd 0
@@ -1353,5 +1443,5 @@
 )
 )
-*133 (CptPort
+*141 (CptPort
 uid 53,0
 ps "OnEdgeStrategy"
@@ -1385,5 +1475,5 @@
 font "Courier New,8,0"
 )
-xt "2000,12800,35500,13600"
+xt "2000,13600,35500,14400"
 st "data_out              : OUT    std_logic_vector (63 downto 0) ;
 "
@@ -1402,5 +1492,5 @@
 )
 )
-*134 (CptPort
+*142 (CptPort
 uid 58,0
 ps "OnEdgeStrategy"
@@ -1434,5 +1524,5 @@
 font "Courier New,8,0"
 )
-xt "2000,13600,42500,14400"
+xt "2000,14400,42500,15200"
 st "addr_out              : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
 "
@@ -1451,5 +1541,5 @@
 )
 )
-*135 (CptPort
+*143 (CptPort
 uid 73,0
 ps "OnEdgeStrategy"
@@ -1483,5 +1573,5 @@
 font "Courier New,8,0"
 )
-xt "2000,14400,38500,15200"
+xt "2000,15200,38500,16000"
 st "write_ea              : OUT    std_logic_vector (0 downto 0) := \"0\" ;
 "
@@ -1501,5 +1591,5 @@
 )
 )
-*136 (CptPort
+*144 (CptPort
 uid 78,0
 ps "OnEdgeStrategy"
@@ -1533,5 +1623,5 @@
 font "Courier New,8,0"
 )
-xt "2000,15200,42500,16000"
+xt "2000,16000,42500,16800"
 st "ram_start_addr        : IN     std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) ;
 "
@@ -1549,5 +1639,5 @@
 )
 )
-*137 (CptPort
+*145 (CptPort
 uid 88,0
 ps "OnEdgeStrategy"
@@ -1580,5 +1670,5 @@
 font "Courier New,8,0"
 )
-xt "2000,29600,35000,30400"
+xt "2000,34400,35000,35200"
 st "board_id              : IN     std_logic_vector (3 downto 0) ;
 "
@@ -1591,10 +1681,10 @@
 preAdd 0
 posAdd 0
-o 23
+o 24
 suid 9,0
 )
 )
 )
-*138 (CptPort
+*146 (CptPort
 uid 93,0
 ps "OnEdgeStrategy"
@@ -1627,5 +1717,5 @@
 font "Courier New,8,0"
 )
-xt "2000,31200,35500,32000"
+xt "2000,36000,35500,36800"
 st "trigger_id            : IN     std_logic_vector (47 downto 0) ;
 "
@@ -1638,10 +1728,10 @@
 preAdd 0
 posAdd 0
-o 25
+o 26
 suid 10,0
 )
 )
 )
-*139 (CptPort
+*147 (CptPort
 uid 98,0
 ps "OnEdgeStrategy"
@@ -1674,5 +1764,5 @@
 font "Courier New,8,0"
 )
-xt "2000,32000,25500,32800"
+xt "2000,36800,25500,37600"
 st "trigger               : IN     std_logic  ;
 "
@@ -1684,10 +1774,10 @@
 preAdd 0
 posAdd 0
-o 26
+o 27
 suid 11,0
 )
 )
 )
-*140 (CommentText
+*148 (CommentText
 uid 106,0
 ps "EdgeToEdgeStrategy"
@@ -1723,5 +1813,5 @@
 excludeCommentLeader 1
 )
-*141 (CptPort
+*149 (CptPort
 uid 285,0
 ps "OnEdgeStrategy"
@@ -1754,5 +1844,5 @@
 font "Courier New,8,0"
 )
-xt "2000,30400,35000,31200"
+xt "2000,35200,35000,36000"
 st "crate_id              : IN     std_logic_vector (1 downto 0) ;
 "
@@ -1763,10 +1853,10 @@
 t "std_logic_vector"
 b "(1 downto 0)"
-o 24
+o 25
 suid 12,0
 )
 )
 )
-*142 (CptPort
+*150 (CptPort
 uid 402,0
 ps "OnEdgeStrategy"
@@ -1799,5 +1889,5 @@
 font "Courier New,8,0"
 )
-xt "2000,16000,25500,16800"
+xt "2000,16800,25500,17600"
 st "ram_write_ea          : IN     std_logic  ;
 "
@@ -1812,5 +1902,5 @@
 )
 )
-*143 (CptPort
+*151 (CptPort
 uid 407,0
 ps "OnEdgeStrategy"
@@ -1844,5 +1934,5 @@
 font "Courier New,8,0"
 )
-xt "2000,16800,38500,17600"
+xt "2000,17600,38500,18400"
 st "ram_write_ready       : OUT    std_logic                     := '0' ;
 "
@@ -1853,4 +1943,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 7
 suid 17,0
@@ -1859,5 +1950,5 @@
 )
 )
-*144 (CptPort
+*152 (CptPort
 uid 412,0
 ps "OnEdgeStrategy"
@@ -1890,5 +1981,5 @@
 font "Courier New,8,0"
 )
-xt "2000,25600,27000,26400"
+xt "2000,30400,27000,31200"
 st "roi_max               : IN     roi_max_type  ;
 "
@@ -1898,10 +1989,10 @@
 n "roi_max"
 t "roi_max_type"
-o 18
+o 19
 suid 18,0
 )
 )
 )
-*145 (CptPort
+*153 (CptPort
 uid 473,0
 ps "OnEdgeStrategy"
@@ -1934,5 +2025,5 @@
 font "Courier New,8,0"
 )
-xt "2000,24800,28000,25600"
+xt "2000,29600,28000,30400"
 st "roi_array             : IN     roi_array_type  ;
 "
@@ -1942,10 +2033,10 @@
 n "roi_array"
 t "roi_array_type"
-o 17
+o 18
 suid 19,0
 )
 )
 )
-*146 (CptPort
+*154 (CptPort
 uid 526,0
 ps "OnEdgeStrategy"
@@ -1978,5 +2069,5 @@
 font "Courier New,8,0"
 )
-xt "2000,28800,35500,29600"
+xt "2000,33600,35500,34400"
 st "package_length        : IN     std_logic_vector (15 downto 0) ;
 "
@@ -1987,10 +2078,10 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 22
+o 23
 suid 20,0
 )
 )
 )
-*147 (CptPort
+*155 (CptPort
 uid 637,0
 ps "OnEdgeStrategy"
@@ -2024,5 +2115,5 @@
 font "Courier New,8,0"
 )
-xt "2000,36000,38500,36800"
+xt "2000,40800,38500,41600"
 st "adc_oeb               : OUT    std_logic                     := '1' ;
 "
@@ -2039,5 +2130,5 @@
 )
 )
-*148 (CptPort
+*156 (CptPort
 uid 676,0
 ps "OnEdgeStrategy"
@@ -2071,5 +2162,5 @@
 font "Courier New,8,0"
 )
-xt "2000,38400,44500,39200"
+xt "2000,43200,44500,44000"
 st "drs_channel_id        : OUT    std_logic_vector (3 downto 0) := (others => '0') ;
 "
@@ -2087,5 +2178,5 @@
 )
 )
-*149 (CptPort
+*157 (CptPort
 uid 681,0
 ps "OnEdgeStrategy"
@@ -2119,5 +2210,5 @@
 font "Courier New,8,0"
 )
-xt "2000,40000,38500,40800"
+xt "2000,44800,38500,45600"
 st "drs_clk_en            : OUT    std_logic                     := '0' ;
 "
@@ -2134,5 +2225,5 @@
 )
 )
-*150 (CptPort
+*158 (CptPort
 uid 801,0
 ps "OnEdgeStrategy"
@@ -2166,5 +2257,5 @@
 font "Courier New,8,0"
 )
-xt "2000,40800,38500,41600"
+xt "2000,45600,38500,46400"
 st "drs_read_s_cell       : OUT    std_logic                     := '0' ;
 "
@@ -2181,5 +2272,5 @@
 )
 )
-*151 (CptPort
+*159 (CptPort
 uid 806,0
 ps "OnEdgeStrategy"
@@ -2212,5 +2303,5 @@
 font "Courier New,8,0"
 )
-xt "2000,41600,25500,42400"
+xt "2000,49600,25500,50400"
 st "drs_read_s_cell_ready : IN     std_logic  ;
 "
@@ -2220,10 +2311,10 @@
 n "drs_read_s_cell_ready"
 t "std_logic"
-o 38
+o 42
 suid 34,0
 )
 )
 )
-*152 (CptPort
+*160 (CptPort
 uid 811,0
 ps "OnEdgeStrategy"
@@ -2256,5 +2347,5 @@
 font "Courier New,8,0"
 )
-xt "2000,42400,30500,43200"
+xt "2000,50400,30500,51200"
 st "drs_s_cell_array      : IN     drs_s_cell_array_type 
 "
@@ -2264,10 +2355,10 @@
 n "drs_s_cell_array"
 t "drs_s_cell_array_type"
-o 39
+o 43
 suid 35,0
 )
 )
 )
-*153 (CptPort
+*161 (CptPort
 uid 845,0
 ps "OnEdgeStrategy"
@@ -2301,5 +2392,5 @@
 font "Courier New,8,0"
 )
-xt "2000,39200,38500,40000"
+xt "2000,44000,38500,44800"
 st "drs_dwrite            : OUT    std_logic                     := '1' ;
 "
@@ -2316,5 +2407,5 @@
 )
 )
-*154 (CptPort
+*162 (CptPort
 uid 898,0
 ps "OnEdgeStrategy"
@@ -2347,5 +2438,5 @@
 font "Courier New,8,0"
 )
-xt "2000,35200,30500,36000"
+xt "2000,40000,30500,40800"
 st "adc_data_array        : IN     adc_data_array_type  ;
 "
@@ -2360,5 +2451,5 @@
 )
 )
-*155 (CptPort
+*163 (CptPort
 uid 958,0
 ps "OnEdgeStrategy"
@@ -2391,5 +2482,5 @@
 font "Courier New,8,0"
 )
-xt "2000,20800,25500,21600"
+xt "2000,25600,25500,26400"
 st "config_ready_cm       : IN     std_logic  ;
 "
@@ -2399,10 +2490,10 @@
 n "config_ready_cm"
 t "std_logic"
-o 12
+o 13
 suid 39,0
 )
 )
 )
-*156 (CptPort
+*164 (CptPort
 uid 963,0
 ps "OnEdgeStrategy"
@@ -2436,6 +2527,7 @@
 font "Courier New,8,0"
 )
-xt "2000,18400,38500,19200"
-st "config_start_cm       : OUT    std_logic                     := '0' ;
+xt "2000,21600,38500,23200"
+st "-- --
+config_start_cm       : OUT    std_logic                     := '0' ;
 "
 )
@@ -2445,5 +2537,8 @@
 n "config_start_cm"
 t "std_logic"
-o 9
+prec "-- --"
+preAdd 0
+posAdd 0
+o 10
 suid 40,0
 i "'0'"
@@ -2451,49 +2546,5 @@
 )
 )
-*157 (CptPort
-uid 1018,0
-ps "OnEdgeStrategy"
-shape (Triangle
-uid 1019,0
-ro 90
-va (VaSet
-vasetType 1
-fg "0,65535,0"
-)
-xt "36250,24625,37000,25375"
-)
-tg (CPTG
-uid 1020,0
-ps "CptPortTextPlaceStrategy"
-stg "VerticalLayoutStrategy"
-f (Text
-uid 1021,0
-va (VaSet
-)
-xt "38000,24500,41600,25500"
-st "s_trigger"
-blo "38000,25300"
-tm "CptPortNameMgr"
-)
-)
-dt (MLText
-uid 1022,0
-va (VaSet
-font "Courier New,8,0"
-)
-xt "2000,32800,25500,33600"
-st "s_trigger             : IN     std_logic  ;
-"
-)
-thePort (LogicalPort
-decl (Decl
-n "s_trigger"
-t "std_logic"
-o 27
-suid 41,0
-)
-)
-)
-*158 (CptPort
+*165 (CptPort
 uid 1048,0
 ps "OnEdgeStrategy"
@@ -2526,5 +2577,5 @@
 font "Courier New,8,0"
 )
-xt "2000,20000,25500,20800"
+xt "2000,24800,25500,25600"
 st "config_ready_mm       : IN     std_logic  ;
 "
@@ -2534,10 +2585,10 @@
 n "config_ready_mm"
 t "std_logic"
-o 11
+o 12
 suid 42,0
 )
 )
 )
-*159 (CptPort
+*166 (CptPort
 uid 1053,0
 ps "OnEdgeStrategy"
@@ -2570,5 +2621,5 @@
 font "Courier New,8,0"
 )
-xt "2000,21600,25500,22400"
+xt "2000,26400,25500,27200"
 st "config_ready_spi      : IN     std_logic  ;
 "
@@ -2578,10 +2629,10 @@
 n "config_ready_spi"
 t "std_logic"
-o 13
+o 14
 suid 43,0
 )
 )
 )
-*160 (CptPort
+*167 (CptPort
 uid 1085,0
 ps "OnEdgeStrategy"
@@ -2614,5 +2665,5 @@
 font "Courier New,8,0"
 )
-xt "2000,26400,29500,27200"
+xt "2000,31200,29500,32000"
 st "sensor_array          : IN     sensor_array_type  ;
 "
@@ -2622,10 +2673,10 @@
 n "sensor_array"
 t "sensor_array_type"
-o 19
+o 20
 suid 44,0
 )
 )
 )
-*161 (CptPort
+*168 (CptPort
 uid 1090,0
 ps "OnEdgeStrategy"
@@ -2658,5 +2709,5 @@
 font "Courier New,8,0"
 )
-xt "2000,27200,25500,28000"
+xt "2000,32000,25500,32800"
 st "sensor_ready          : IN     std_logic  ;
 "
@@ -2666,10 +2717,10 @@
 n "sensor_ready"
 t "std_logic"
-o 20
+o 21
 suid 45,0
 )
 )
 )
-*162 (CptPort
+*169 (CptPort
 uid 1122,0
 ps "OnEdgeStrategy"
@@ -2703,6 +2754,7 @@
 font "Courier New,8,0"
 )
-xt "2000,17600,38500,18400"
-st "config_start_mm       : OUT    std_logic                     := '0' ;
+xt "2000,20000,38500,21600"
+st "-- --
+config_start_mm       : OUT    std_logic                     := '0' ;
 "
 )
@@ -2712,5 +2764,8 @@
 n "config_start_mm"
 t "std_logic"
-o 8
+prec "-- --"
+preAdd 0
+posAdd 0
+o 9
 suid 46,0
 i "'0'"
@@ -2718,5 +2773,5 @@
 )
 )
-*163 (CptPort
+*170 (CptPort
 uid 1127,0
 ps "OnEdgeStrategy"
@@ -2750,6 +2805,7 @@
 font "Courier New,8,0"
 )
-xt "2000,19200,38500,20000"
-st "config_start_spi      : OUT    std_logic                     := '0' ;
+xt "2000,23200,38500,24800"
+st "-- --
+config_start_spi      : OUT    std_logic                     := '0' ;
 "
 )
@@ -2759,5 +2815,7 @@
 n "config_start_spi"
 t "std_logic"
-o 10
+prec "-- --"
+preAdd 0
+o 11
 suid 47,0
 i "'0'"
@@ -2765,5 +2823,5 @@
 )
 )
-*164 (CptPort
+*171 (CptPort
 uid 1159,0
 ps "OnEdgeStrategy"
@@ -2797,5 +2855,5 @@
 font "Courier New,8,0"
 )
-xt "2000,34400,38500,35200"
+xt "2000,39200,38500,40000"
 st "config_started        : OUT    std_logic                     := '0' ;
 "
@@ -2812,5 +2870,5 @@
 )
 )
-*165 (CptPort
+*172 (CptPort
 uid 1164,0
 ps "OnEdgeStrategy"
@@ -2843,6 +2901,7 @@
 font "Courier New,8,0"
 )
-xt "2000,33600,25500,34400"
-st "new_config            : IN     std_logic  ;
+xt "2000,37600,25500,39200"
+st "--      s_trigger      : in std_logic;
+new_config            : IN     std_logic  ;
 "
 )
@@ -2851,4 +2910,6 @@
 n "new_config"
 t "std_logic"
+prec "--      s_trigger      : in std_logic;"
+preAdd 0
 o 28
 suid 49,0
@@ -2856,5 +2917,5 @@
 )
 )
-*166 (CptPort
+*173 (CptPort
 uid 1196,0
 ps "OnEdgeStrategy"
@@ -2887,5 +2948,5 @@
 font "Courier New,8,0"
 )
-xt "2000,23200,25500,24000"
+xt "2000,28000,25500,28800"
 st "config_started_cm     : IN     std_logic  ;
 "
@@ -2895,10 +2956,10 @@
 n "config_started_cm"
 t "std_logic"
-o 15
+o 16
 suid 50,0
 )
 )
 )
-*167 (CptPort
+*174 (CptPort
 uid 1201,0
 ps "OnEdgeStrategy"
@@ -2931,5 +2992,5 @@
 font "Courier New,8,0"
 )
-xt "2000,22400,25500,23200"
+xt "2000,27200,25500,28000"
 st "config_started_mm     : IN     std_logic  ;
 "
@@ -2939,10 +3000,10 @@
 n "config_started_mm"
 t "std_logic"
-o 14
+o 15
 suid 51,0
 )
 )
 )
-*168 (CptPort
+*175 (CptPort
 uid 1206,0
 ps "OnEdgeStrategy"
@@ -2975,5 +3036,5 @@
 font "Courier New,8,0"
 )
-xt "2000,24000,25500,24800"
+xt "2000,28800,25500,29600"
 st "config_started_spi    : IN     std_logic  ;
 "
@@ -2983,10 +3044,10 @@
 n "config_started_spi"
 t "std_logic"
-o 16
+o 17
 suid 52,0
 )
 )
 )
-*169 (CptPort
+*176 (CptPort
 uid 1240,0
 ps "OnEdgeStrategy"
@@ -3019,5 +3080,5 @@
 font "Courier New,8,0"
 )
-xt "2000,28000,28000,28800"
+xt "2000,32800,28000,33600"
 st "dac_array             : IN     dac_array_type  ;
 "
@@ -3027,10 +3088,10 @@
 n "dac_array"
 t "dac_array_type"
-o 21
+o 22
 suid 53,0
 )
 )
 )
-*170 (CptPort
+*177 (CptPort
 uid 1395,0
 ps "OnEdgeStrategy"
@@ -3064,5 +3125,5 @@
 font "Courier New,8,0"
 )
-xt "2000,36800,38500,37600"
+xt "2000,41600,38500,42400"
 st "adc_clk_en            : OUT    std_logic                     := '0' ;
 "
@@ -3079,5 +3140,5 @@
 )
 )
-*171 (CptPort
+*178 (CptPort
 uid 1427,0
 ps "OnEdgeStrategy"
@@ -3110,5 +3171,5 @@
 font "Courier New,8,0"
 )
-xt "2000,37600,35000,38400"
+xt "2000,42400,35000,43200"
 st "adc_otr               : IN     std_logic_vector (3 downto 0) ;
 "
@@ -3124,4 +3185,235 @@
 )
 )
+*179 (CptPort
+uid 1459,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1460,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "67000,32625,67750,33375"
+)
+tg (CPTG
+uid 1461,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1462,0
+va (VaSet
+)
+xt "58000,32500,66000,33500"
+st "drs_srin_data : (7:0)"
+ju 2
+blo "66000,33300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1463,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,48000,44500,48800"
+st "drs_srin_data         : OUT    std_logic_vector (7 downto 0) := (others => '0') ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_data"
+t "std_logic_vector"
+b "(7 downto 0)"
+o 40
+suid 56,0
+i "(others => '0')"
+)
+)
+)
+*180 (CptPort
+uid 1464,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1465,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "67000,33625,67750,34375"
+)
+tg (CPTG
+uid 1466,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1467,0
+va (VaSet
+)
+xt "59200,33500,66000,34500"
+st "drs_srin_write_8b"
+ju 2
+blo "66000,34300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1468,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,46400,38500,47200"
+st "drs_srin_write_8b     : OUT    std_logic                     := '0' ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_srin_write_8b"
+t "std_logic"
+o 38
+suid 57,0
+i "'0'"
+)
+)
+)
+*181 (CptPort
+uid 1469,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1470,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "36250,35625,37000,36375"
+)
+tg (CPTG
+uid 1471,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1472,0
+va (VaSet
+)
+xt "38000,35500,45100,36500"
+st "drs_srin_write_ack"
+blo "38000,36300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1473,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,47200,25500,48000"
+st "drs_srin_write_ack    : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_srin_write_ack"
+t "std_logic"
+o 39
+suid 58,0
+)
+)
+)
+*182 (CptPort
+uid 1474,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1475,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "36250,36625,37000,37375"
+)
+tg (CPTG
+uid 1476,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1477,0
+va (VaSet
+)
+xt "38000,36500,46200,37500"
+st "drs_srin_write_ready"
+blo "38000,37300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1478,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,48800,25500,49600"
+st "drs_srin_write_ready  : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_srin_write_ready"
+t "std_logic"
+o 41
+suid 59,0
+)
+)
+)
+*183 (CptPort
+uid 1479,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1480,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "36250,37625,37000,38375"
+)
+tg (CPTG
+uid 1481,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1482,0
+va (VaSet
+)
+xt "38000,37500,45800,38500"
+st "ram_write_ready_ack"
+blo "38000,38300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1483,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,18400,25500,20000"
+st "-- --
+ram_write_ready_ack   : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 8
+suid 60,0
+)
+)
+)
 ]
 shape (Rectangle
@@ -3133,5 +3425,5 @@
 lineWidth 2
 )
-xt "37000,1000,67000,36000"
+xt "37000,1000,67000,39000"
 )
 oxt "37000,1000,51000,21000"
@@ -3159,5 +3451,5 @@
 )
 )
-gi *172 (GenericInterface
+gi *184 (GenericInterface
 uid 13,0
 ps "CenterOffsetStrategy"
@@ -3192,8 +3484,8 @@
 )
 )
-*173 (Grouping
+*185 (Grouping
 uid 16,0
 optionalChildren [
-*174 (CommentText
+*186 (CommentText
 uid 18,0
 shape (Rectangle
@@ -3226,5 +3518,5 @@
 titleBlock 1
 )
-*175 (CommentText
+*187 (CommentText
 uid 21,0
 shape (Rectangle
@@ -3257,5 +3549,5 @@
 titleBlock 1
 )
-*176 (CommentText
+*188 (CommentText
 uid 24,0
 shape (Rectangle
@@ -3288,5 +3580,5 @@
 titleBlock 1
 )
-*177 (CommentText
+*189 (CommentText
 uid 27,0
 shape (Rectangle
@@ -3319,5 +3611,5 @@
 titleBlock 1
 )
-*178 (CommentText
+*190 (CommentText
 uid 30,0
 shape (Rectangle
@@ -3349,5 +3641,5 @@
 titleBlock 1
 )
-*179 (CommentText
+*191 (CommentText
 uid 33,0
 shape (Rectangle
@@ -3380,5 +3672,5 @@
 titleBlock 1
 )
-*180 (CommentText
+*192 (CommentText
 uid 36,0
 shape (Rectangle
@@ -3411,5 +3703,5 @@
 titleBlock 1
 )
-*181 (CommentText
+*193 (CommentText
 uid 39,0
 shape (Rectangle
@@ -3442,5 +3734,5 @@
 titleBlock 1
 )
-*182 (CommentText
+*194 (CommentText
 uid 42,0
 shape (Rectangle
@@ -3473,5 +3765,5 @@
 titleBlock 1
 )
-*183 (CommentText
+*195 (CommentText
 uid 45,0
 shape (Rectangle
@@ -3517,5 +3809,5 @@
 oxt "14000,66000,55000,71000"
 )
-*184 (CommentText
+*196 (CommentText
 uid 103,0
 shape (Rectangle
@@ -3560,9 +3852,9 @@
 color "26368,26368,26368"
 )
-packageList *185 (PackageList
+packageList *197 (PackageList
 uid 131,0
 stg "VerticalLayoutStrategy"
 textVec [
-*186 (Text
+*198 (Text
 uid 132,0
 va (VaSet
@@ -3573,5 +3865,5 @@
 blo "0,1800"
 )
-*187 (MLText
+*199 (MLText
 uid 133,0
 va (VaSet
@@ -3674,5 +3966,5 @@
 )
 )
-gi *188 (GenericInterface
+gi *200 (GenericInterface
 ps "CenterOffsetStrategy"
 matrix (Matrix
@@ -3771,5 +4063,5 @@
 )
 )
-DeclarativeBlock *189 (SymDeclBlock
+DeclarativeBlock *201 (SymDeclBlock
 uid 1,0
 stg "SymDeclLayoutStrategy"
@@ -3797,7 +4089,7 @@
 font "Arial,8,1"
 )
-xt "0,43200,2400,44200"
+xt "0,51200,2400,52200"
 st "User:"
-blo "0,44000"
+blo "0,52000"
 )
 internalLabel (Text
@@ -3816,5 +4108,5 @@
 font "Courier New,8,0"
 )
-xt "2000,44200,2000,44200"
+xt "2000,52200,2000,52200"
 tm "SyDeclarativeTextMgr"
 )
@@ -3829,5 +4121,5 @@
 )
 )
-lastUid 1435,0
+lastUid 1495,0
 activeModelName "Symbol:CDM"
 )
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/memory_manager/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/memory_manager/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/memory_manager/symbol.sb	(revision 10073)
@@ -31,5 +31,5 @@
 ldm (LogicalDM
 ordering 1
-suid 22,0
+suid 23,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -80,5 +80,5 @@
 preAdd 0
 posAdd 0
-o 18
+o 19
 suid 1,0
 i "(others => '0')"
@@ -118,5 +118,5 @@
 n "ram_write_ea"
 t "std_logic"
-o 5
+o 6
 suid 4,0
 i "'0'"
@@ -132,5 +132,5 @@
 n "config_ready"
 t "std_logic"
-o 6
+o 7
 suid 5,0
 i "'0'"
@@ -147,5 +147,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 12
+o 13
 suid 6,0
 i "(others => '0')"
@@ -163,5 +163,5 @@
 b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
 preAdd 0
-o 10
+o 11
 suid 7,0
 i "(others => '0')"
@@ -177,5 +177,5 @@
 n "wiz_write_ea"
 t "std_logic"
-o 13
+o 14
 suid 8,0
 i "'0'"
@@ -191,5 +191,5 @@
 n "wiz_write_end"
 t "std_logic"
-o 15
+o 16
 suid 9,0
 i "'0'"
@@ -205,5 +205,5 @@
 n "wiz_write_header"
 t "std_logic"
-o 14
+o 15
 suid 10,0
 i "'0'"
@@ -220,5 +220,5 @@
 t "std_logic_vector"
 b "(16 downto 0)"
-o 11
+o 12
 suid 11,0
 i "(others => '0')"
@@ -233,4 +233,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 3
 suid 12,0
@@ -245,5 +246,5 @@
 n "wiz_busy"
 t "std_logic"
-o 16
+o 17
 suid 13,0
 )
@@ -259,5 +260,5 @@
 t "roi_max_type"
 posAdd 0
-o 8
+o 9
 suid 14,0
 i "(others => conv_std_logic_vector (0, 11))"
@@ -272,5 +273,7 @@
 n "roi_array"
 t "roi_array_type"
-o 4
+prec "-- --"
+preAdd 0
+o 5
 suid 17,0
 )
@@ -286,5 +289,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 9
+o 10
 suid 18,0
 i "(others => '0')"
@@ -300,5 +303,5 @@
 n "config_started"
 t "std_logic"
-o 7
+o 8
 suid 21,0
 i "'0'"
@@ -313,9 +316,26 @@
 n "wiz_ack"
 t "std_logic"
-o 17
+o 18
 suid 22,0
 )
 )
 uid 920,0
+)
+*32 (LogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 4
+suid 23,0
+i "'0'"
+)
+)
+uid 954,0
 )
 ]
@@ -326,5 +346,5 @@
 uid 73,0
 optionalChildren [
-*32 (Sheet
+*33 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -343,5 +363,5 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *33 (MRCItem
+emptyMRCItem *34 (MRCItem
 litem &1
 pos 3
@@ -350,5 +370,5 @@
 uid 75,0
 optionalChildren [
-*34 (MRCItem
+*35 (MRCItem
 litem &2
 pos 0
@@ -356,5 +376,5 @@
 uid 76,0
 )
-*35 (MRCItem
+*36 (MRCItem
 litem &3
 pos 1
@@ -362,5 +382,5 @@
 uid 77,0
 )
-*36 (MRCItem
+*37 (MRCItem
 litem &4
 pos 2
@@ -369,5 +389,5 @@
 uid 78,0
 )
-*37 (MRCItem
+*38 (MRCItem
 litem &14
 pos 0
@@ -375,5 +395,5 @@
 uid 57,0
 )
-*38 (MRCItem
+*39 (MRCItem
 litem &15
 pos 1
@@ -381,5 +401,5 @@
 uid 144,0
 )
-*39 (MRCItem
+*40 (MRCItem
 litem &16
 pos 2
@@ -387,5 +407,5 @@
 uid 200,0
 )
-*40 (MRCItem
+*41 (MRCItem
 litem &17
 pos 3
@@ -393,5 +413,5 @@
 uid 230,0
 )
-*41 (MRCItem
+*42 (MRCItem
 litem &18
 pos 4
@@ -399,5 +419,5 @@
 uid 260,0
 )
-*42 (MRCItem
+*43 (MRCItem
 litem &19
 pos 5
@@ -405,5 +425,5 @@
 uid 315,0
 )
-*43 (MRCItem
+*44 (MRCItem
 litem &20
 pos 6
@@ -411,5 +431,5 @@
 uid 317,0
 )
-*44 (MRCItem
+*45 (MRCItem
 litem &21
 pos 7
@@ -417,5 +437,5 @@
 uid 319,0
 )
-*45 (MRCItem
+*46 (MRCItem
 litem &22
 pos 8
@@ -423,5 +443,5 @@
 uid 321,0
 )
-*46 (MRCItem
+*47 (MRCItem
 litem &23
 pos 9
@@ -429,5 +449,5 @@
 uid 323,0
 )
-*47 (MRCItem
+*48 (MRCItem
 litem &24
 pos 10
@@ -435,5 +455,5 @@
 uid 325,0
 )
-*48 (MRCItem
+*49 (MRCItem
 litem &25
 pos 11
@@ -441,5 +461,5 @@
 uid 355,0
 )
-*49 (MRCItem
+*50 (MRCItem
 litem &26
 pos 12
@@ -447,5 +467,5 @@
 uid 385,0
 )
-*50 (MRCItem
+*51 (MRCItem
 litem &27
 pos 13
@@ -453,5 +473,5 @@
 uid 439,0
 )
-*51 (MRCItem
+*52 (MRCItem
 litem &28
 pos 14
@@ -459,5 +479,5 @@
 uid 575,0
 )
-*52 (MRCItem
+*53 (MRCItem
 litem &29
 pos 15
@@ -465,5 +485,5 @@
 uid 628,0
 )
-*53 (MRCItem
+*54 (MRCItem
 litem &30
 pos 16
@@ -471,9 +491,15 @@
 uid 810,0
 )
-*54 (MRCItem
+*55 (MRCItem
 litem &31
 pos 17
 dimension 20
 uid 921,0
+)
+*56 (MRCItem
+litem &32
+pos 18
+dimension 20
+uid 955,0
 )
 ]
@@ -488,5 +514,5 @@
 uid 79,0
 optionalChildren [
-*55 (MRCItem
+*57 (MRCItem
 litem &5
 pos 0
@@ -494,5 +520,5 @@
 uid 80,0
 )
-*56 (MRCItem
+*58 (MRCItem
 litem &7
 pos 1
@@ -500,5 +526,5 @@
 uid 81,0
 )
-*57 (MRCItem
+*59 (MRCItem
 litem &8
 pos 2
@@ -506,5 +532,5 @@
 uid 82,0
 )
-*58 (MRCItem
+*60 (MRCItem
 litem &9
 pos 3
@@ -512,5 +538,5 @@
 uid 83,0
 )
-*59 (MRCItem
+*61 (MRCItem
 litem &10
 pos 4
@@ -518,5 +544,5 @@
 uid 84,0
 )
-*60 (MRCItem
+*62 (MRCItem
 litem &11
 pos 5
@@ -524,5 +550,5 @@
 uid 85,0
 )
-*61 (MRCItem
+*63 (MRCItem
 litem &12
 pos 6
@@ -530,5 +556,5 @@
 uid 86,0
 )
-*62 (MRCItem
+*64 (MRCItem
 litem &13
 pos 7
@@ -551,39 +577,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *63 (LEmptyRow
+emptyRow *65 (LEmptyRow
 )
 uid 89,0
 optionalChildren [
-*64 (RefLabelRowHdr
-)
-*65 (TitleRowHdr
-)
-*66 (FilterRowHdr
-)
-*67 (RefLabelColHdr
+*66 (RefLabelRowHdr
+)
+*67 (TitleRowHdr
+)
+*68 (FilterRowHdr
+)
+*69 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*68 (RowExpandColHdr
+*70 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*69 (GroupColHdr
+*71 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*70 (NameColHdr
+*72 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*71 (TypeColHdr
+*73 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*72 (InitColHdr
+*74 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*73 (PragmaColHdr
+*75 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*74 (EolColHdr
+*76 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*75 (LogGeneric
+*77 (LogGeneric
 generic (GiElement
 name "RAM_ADDR_WIDTH_64B"
@@ -591,7 +617,7 @@
 value "12"
 )
-uid 922,0
-)
-*76 (LogGeneric
+uid 956,0
+)
+*78 (LogGeneric
 generic (GiElement
 name "RAM_ADDR_WIDTH_16B"
@@ -599,5 +625,5 @@
 value "14"
 )
-uid 924,0
+uid 958,0
 )
 ]
@@ -608,5 +634,5 @@
 uid 101,0
 optionalChildren [
-*77 (Sheet
+*79 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -625,6 +651,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *78 (MRCItem
-litem &63
+emptyMRCItem *80 (MRCItem
+litem &65
 pos 3
 dimension 20
@@ -632,18 +658,18 @@
 uid 103,0
 optionalChildren [
-*79 (MRCItem
-litem &64
+*81 (MRCItem
+litem &66
 pos 0
 dimension 20
 uid 104,0
 )
-*80 (MRCItem
-litem &65
+*82 (MRCItem
+litem &67
 pos 1
 dimension 23
 uid 105,0
 )
-*81 (MRCItem
-litem &66
+*83 (MRCItem
+litem &68
 pos 2
 hidden 1
@@ -651,15 +677,15 @@
 uid 106,0
 )
-*82 (MRCItem
-litem &75
+*84 (MRCItem
+litem &77
 pos 0
 dimension 20
-uid 923,0
-)
-*83 (MRCItem
-litem &76
+uid 957,0
+)
+*85 (MRCItem
+litem &78
 pos 1
 dimension 20
-uid 925,0
+uid 959,0
 )
 ]
@@ -674,42 +700,42 @@
 uid 107,0
 optionalChildren [
-*84 (MRCItem
-litem &67
+*86 (MRCItem
+litem &69
 pos 0
 dimension 20
 uid 108,0
 )
-*85 (MRCItem
-litem &69
+*87 (MRCItem
+litem &71
 pos 1
 dimension 50
 uid 109,0
 )
-*86 (MRCItem
-litem &70
+*88 (MRCItem
+litem &72
 pos 2
 dimension 100
 uid 110,0
 )
-*87 (MRCItem
-litem &71
+*89 (MRCItem
+litem &73
 pos 3
 dimension 100
 uid 111,0
 )
-*88 (MRCItem
-litem &72
+*90 (MRCItem
+litem &74
 pos 4
 dimension 50
 uid 112,0
 )
-*89 (MRCItem
-litem &73
+*91 (MRCItem
+litem &75
 pos 5
 dimension 50
 uid 113,0
 )
-*90 (MRCItem
-litem &74
+*92 (MRCItem
+litem &76
 pos 6
 dimension 80
@@ -734,21 +760,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -766,25 +792,25 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\memory_manager"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\memory_manager"
 )
 (vvPair
 variable "date"
-value "02.07.2010"
+value "03.01.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Mo"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Montag"
 )
 (vvPair
 variable "dd"
-value "02"
+value "03"
 )
 (vvPair
@@ -814,5 +840,5 @@
 (vvPair
 variable "host"
-value "TU-CC4900F8C7D2"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -850,5 +876,5 @@
 (vvPair
 variable "mm"
-value "07"
+value "01"
 )
 (vvPair
@@ -858,17 +884,17 @@
 (vvPair
 variable "month"
-value "Jul"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "Juli"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\memory_manager\\symbol.sb"
 )
 (vvPair
@@ -926,5 +952,5 @@
 (vvPair
 variable "time"
-value "10:38:11"
+value "16:31:26"
 )
 (vvPair
@@ -946,9 +972,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -957,8 +983,8 @@
 uid 58,0
 optionalChildren [
-*91 (SymbolBody
+*93 (SymbolBody
 uid 8,0
 optionalChildren [
-*92 (CptPort
+*94 (CptPort
 uid 51,0
 ps "OnEdgeStrategy"
@@ -992,5 +1018,5 @@
 font "Courier New,8,0"
 )
-xt "44000,15600,95500,16400"
+xt "44000,18000,95500,18800"
 st "ram_start_addr         : OUT    std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
 "
@@ -1005,5 +1031,5 @@
 preAdd 0
 posAdd 0
-o 18
+o 19
 suid 1,0
 i "(others => '0')"
@@ -1011,5 +1037,5 @@
 )
 )
-*93 (CptPort
+*95 (CptPort
 uid 138,0
 ps "OnEdgeStrategy"
@@ -1057,5 +1083,5 @@
 )
 )
-*94 (CommentText
+*96 (CommentText
 uid 168,0
 ps "EdgeToEdgeStrategy"
@@ -1097,5 +1123,5 @@
 excludeCommentLeader 1
 )
-*95 (CptPort
+*97 (CptPort
 uid 194,0
 ps "OnEdgeStrategy"
@@ -1143,5 +1169,5 @@
 )
 )
-*96 (CptPort
+*98 (CptPort
 uid 224,0
 ps "OnEdgeStrategy"
@@ -1176,5 +1202,5 @@
 font "Courier New,8,0"
 )
-xt "44000,5200,90500,6000"
+xt "44000,7600,90500,8400"
 st "ram_write_ea           : OUT    std_logic                                        := '0' ;
 "
@@ -1186,5 +1212,5 @@
 n "ram_write_ea"
 t "std_logic"
-o 5
+o 6
 suid 4,0
 i "'0'"
@@ -1192,5 +1218,5 @@
 )
 )
-*97 (CptPort
+*99 (CptPort
 uid 254,0
 ps "OnEdgeStrategy"
@@ -1225,5 +1251,5 @@
 font "Courier New,8,0"
 )
-xt "44000,6000,90500,6800"
+xt "44000,8400,90500,9200"
 st "config_ready           : OUT    std_logic                                        := '0' ;
 "
@@ -1235,5 +1261,5 @@
 n "config_ready"
 t "std_logic"
-o 6
+o 7
 suid 5,0
 i "'0'"
@@ -1241,5 +1267,5 @@
 )
 )
-*98 (CptPort
+*100 (CptPort
 uid 284,0
 ps "OnEdgeStrategy"
@@ -1273,5 +1299,5 @@
 font "Courier New,8,0"
 )
-xt "44000,10800,96500,11600"
+xt "44000,13200,96500,14000"
 st "wiz_number_of_channels : OUT    std_logic_vector (3 downto 0)                    := (others => '0') ;
 "
@@ -1284,5 +1310,5 @@
 t "std_logic_vector"
 b "(3 downto 0)"
-o 12
+o 13
 suid 6,0
 i "(others => '0')"
@@ -1290,5 +1316,5 @@
 )
 )
-*99 (CptPort
+*101 (CptPort
 uid 289,0
 ps "OnEdgeStrategy"
@@ -1323,5 +1349,5 @@
 font "Courier New,8,0"
 )
-xt "44000,9200,96500,10000"
+xt "44000,11600,96500,12400"
 st "wiz_ram_start_addr     : OUT    std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0') ;
 "
@@ -1335,5 +1361,5 @@
 b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
 preAdd 0
-o 10
+o 11
 suid 7,0
 i "(others => '0')"
@@ -1341,5 +1367,5 @@
 )
 )
-*100 (CptPort
+*102 (CptPort
 uid 294,0
 ps "OnEdgeStrategy"
@@ -1374,5 +1400,5 @@
 font "Courier New,8,0"
 )
-xt "44000,11600,90500,12400"
+xt "44000,14000,90500,14800"
 st "wiz_write_ea           : OUT    std_logic                                        := '0' ;
 "
@@ -1384,5 +1410,5 @@
 n "wiz_write_ea"
 t "std_logic"
-o 13
+o 14
 suid 8,0
 i "'0'"
@@ -1390,5 +1416,5 @@
 )
 )
-*101 (CptPort
+*103 (CptPort
 uid 299,0
 ps "OnEdgeStrategy"
@@ -1423,5 +1449,5 @@
 font "Courier New,8,0"
 )
-xt "44000,13200,90500,14000"
+xt "44000,15600,90500,16400"
 st "wiz_write_end          : OUT    std_logic                                        := '0' ;
 "
@@ -1433,5 +1459,5 @@
 n "wiz_write_end"
 t "std_logic"
-o 15
+o 16
 suid 9,0
 i "'0'"
@@ -1439,5 +1465,5 @@
 )
 )
-*102 (CptPort
+*104 (CptPort
 uid 304,0
 ps "OnEdgeStrategy"
@@ -1472,5 +1498,5 @@
 font "Courier New,8,0"
 )
-xt "44000,12400,90500,13200"
+xt "44000,14800,90500,15600"
 st "wiz_write_header       : OUT    std_logic                                        := '0' ;
 "
@@ -1482,5 +1508,5 @@
 n "wiz_write_header"
 t "std_logic"
-o 14
+o 15
 suid 10,0
 i "'0'"
@@ -1488,5 +1514,5 @@
 )
 )
-*103 (CptPort
+*105 (CptPort
 uid 309,0
 ps "OnEdgeStrategy"
@@ -1521,5 +1547,5 @@
 font "Courier New,8,0"
 )
-xt "44000,10000,96500,10800"
+xt "44000,12400,96500,13200"
 st "wiz_write_length       : OUT    std_logic_vector (16 downto 0)                   := (others => '0') ;
 "
@@ -1532,5 +1558,5 @@
 t "std_logic_vector"
 b "(16 downto 0)"
-o 11
+o 12
 suid 11,0
 i "(others => '0')"
@@ -1538,5 +1564,5 @@
 )
 )
-*104 (CptPort
+*106 (CptPort
 uid 349,0
 ps "OnEdgeStrategy"
@@ -1579,4 +1605,5 @@
 n "ram_write_ready"
 t "std_logic"
+posAdd 0
 o 3
 suid 12,0
@@ -1584,5 +1611,5 @@
 )
 )
-*105 (CptPort
+*107 (CptPort
 uid 379,0
 ps "OnEdgeStrategy"
@@ -1616,5 +1643,5 @@
 font "Courier New,8,0"
 )
-xt "44000,14000,68000,14800"
+xt "44000,16400,68000,17200"
 st "wiz_busy               : IN     std_logic  ;
 "
@@ -1625,10 +1652,10 @@
 n "wiz_busy"
 t "std_logic"
-o 16
+o 17
 suid 13,0
 )
 )
 )
-*106 (CptPort
+*108 (CptPort
 uid 433,0
 ps "OnEdgeStrategy"
@@ -1663,5 +1690,5 @@
 font "Courier New,8,0"
 )
-xt "44000,7600,109500,8400"
+xt "44000,10000,109500,10800"
 st "roi_max                : OUT    roi_max_type                                     := (others => conv_std_logic_vector (0, 11)) ;
 "
@@ -1674,5 +1701,5 @@
 t "roi_max_type"
 posAdd 0
-o 8
+o 9
 suid 14,0
 i "(others => conv_std_logic_vector (0, 11))"
@@ -1680,5 +1707,5 @@
 )
 )
-*107 (CptPort
+*109 (CptPort
 uid 569,0
 ps "OnEdgeStrategy"
@@ -1712,6 +1739,7 @@
 font "Courier New,8,0"
 )
-xt "44000,4400,70500,5200"
-st "roi_array              : IN     roi_array_type  ;
+xt "44000,6000,70500,7600"
+st "-- --
+roi_array              : IN     roi_array_type  ;
 "
 )
@@ -1721,10 +1749,12 @@
 n "roi_array"
 t "roi_array_type"
-o 4
+prec "-- --"
+preAdd 0
+o 5
 suid 17,0
 )
 )
 )
-*108 (CptPort
+*110 (CptPort
 uid 622,0
 ps "OnEdgeStrategy"
@@ -1759,5 +1789,5 @@
 font "Courier New,8,0"
 )
-xt "44000,8400,96500,9200"
+xt "44000,10800,96500,11600"
 st "package_length         : OUT    std_logic_vector (15 downto 0)                   := (others => '0') ;
 "
@@ -1770,5 +1800,5 @@
 t "std_logic_vector"
 b "(15 downto 0)"
-o 9
+o 10
 suid 18,0
 i "(others => '0')"
@@ -1776,5 +1806,5 @@
 )
 )
-*109 (CptPort
+*111 (CptPort
 uid 804,0
 ps "OnEdgeStrategy"
@@ -1809,5 +1839,5 @@
 font "Courier New,8,0"
 )
-xt "44000,6800,90500,7600"
+xt "44000,9200,90500,10000"
 st "config_started         : OUT    std_logic                                        := '0' ;
 "
@@ -1819,5 +1849,5 @@
 n "config_started"
 t "std_logic"
-o 7
+o 8
 suid 21,0
 i "'0'"
@@ -1825,5 +1855,5 @@
 )
 )
-*110 (CptPort
+*112 (CptPort
 uid 915,0
 ps "OnEdgeStrategy"
@@ -1857,5 +1887,5 @@
 font "Courier New,8,0"
 )
-xt "44000,14800,68000,15600"
+xt "44000,17200,68000,18000"
 st "wiz_ack                : IN     std_logic  ;
 "
@@ -1866,6 +1896,59 @@
 n "wiz_ack"
 t "std_logic"
-o 17
+o 18
 suid 22,0
+)
+)
+)
+*113 (CptPort
+uid 949,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 950,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "43000,16625,43750,17375"
+)
+tg (CPTG
+uid 951,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 952,0
+va (VaSet
+font "arial,8,0"
+)
+xt "34200,16500,42000,17500"
+st "ram_write_ready_ack"
+ju 2
+blo "42000,17300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 953,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "44000,4400,90500,6000"
+st "-- --
+ram_write_ready_ack    : OUT    std_logic                                        := '0' ;
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ram_write_ready_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 4
+suid 23,0
+i "'0'"
 )
 )
@@ -1880,5 +1963,5 @@
 lineWidth 2
 )
-xt "15000,6000,43000,17000"
+xt "15000,6000,43000,18000"
 )
 oxt "15000,6000,23000,16000"
@@ -1906,5 +1989,5 @@
 )
 )
-gi *111 (GenericInterface
+gi *114 (GenericInterface
 uid 13,0
 ps "CenterOffsetStrategy"
@@ -1949,8 +2032,8 @@
 )
 )
-*112 (Grouping
+*115 (Grouping
 uid 16,0
 optionalChildren [
-*113 (CommentText
+*116 (CommentText
 uid 18,0
 shape (Rectangle
@@ -1983,5 +2066,5 @@
 titleBlock 1
 )
-*114 (CommentText
+*117 (CommentText
 uid 21,0
 shape (Rectangle
@@ -2014,5 +2097,5 @@
 titleBlock 1
 )
-*115 (CommentText
+*118 (CommentText
 uid 24,0
 shape (Rectangle
@@ -2045,5 +2128,5 @@
 titleBlock 1
 )
-*116 (CommentText
+*119 (CommentText
 uid 27,0
 shape (Rectangle
@@ -2076,5 +2159,5 @@
 titleBlock 1
 )
-*117 (CommentText
+*120 (CommentText
 uid 30,0
 shape (Rectangle
@@ -2106,5 +2189,5 @@
 titleBlock 1
 )
-*118 (CommentText
+*121 (CommentText
 uid 33,0
 shape (Rectangle
@@ -2137,5 +2220,5 @@
 titleBlock 1
 )
-*119 (CommentText
+*122 (CommentText
 uid 36,0
 shape (Rectangle
@@ -2168,5 +2251,5 @@
 titleBlock 1
 )
-*120 (CommentText
+*123 (CommentText
 uid 39,0
 shape (Rectangle
@@ -2199,5 +2282,5 @@
 titleBlock 1
 )
-*121 (CommentText
+*124 (CommentText
 uid 42,0
 shape (Rectangle
@@ -2230,5 +2313,5 @@
 titleBlock 1
 )
-*122 (CommentText
+*125 (CommentText
 uid 45,0
 shape (Rectangle
@@ -2286,9 +2369,9 @@
 color "26368,26368,26368"
 )
-packageList *123 (PackageList
+packageList *126 (PackageList
 uid 48,0
 stg "VerticalLayoutStrategy"
 textVec [
-*124 (Text
+*127 (Text
 uid 49,0
 va (VaSet
@@ -2299,5 +2382,5 @@
 blo "0,800"
 )
-*125 (MLText
+*128 (MLText
 uid 50,0
 va (VaSet
@@ -2403,5 +2486,5 @@
 )
 )
-gi *126 (GenericInterface
+gi *129 (GenericInterface
 ps "CenterOffsetStrategy"
 matrix (Matrix
@@ -2502,5 +2585,5 @@
 )
 )
-DeclarativeBlock *127 (SymDeclBlock
+DeclarativeBlock *130 (SymDeclBlock
 uid 1,0
 stg "SymDeclLayoutStrategy"
@@ -2528,7 +2611,7 @@
 font "arial,8,1"
 )
-xt "42000,16400,44400,17400"
+xt "42000,18800,44400,19800"
 st "User:"
-blo "42000,17200"
+blo "42000,19600"
 )
 internalLabel (Text
@@ -2547,5 +2630,5 @@
 font "Courier New,8,0"
 )
-xt "44000,17400,44000,17400"
+xt "44000,19800,44000,19800"
 tm "SyDeclarativeTextMgr"
 )
@@ -2560,5 +2643,5 @@
 )
 )
-lastUid 925,0
+lastUid 959,0
 activeModelName "Symbol:CDM"
 )
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb	(revision 10072)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb	(revision 10073)
@@ -35,5 +35,5 @@
 ldm (LogicalDM
 ordering 1
-suid 39,0
+suid 41,0
 usingSuid 1
 emptyRow *1 (LEmptyRow
@@ -355,5 +355,7 @@
 n "config_busy"
 t "std_logic"
-o 27
+prec "-- --"
+preAdd 0
+o 29
 suid 25,0
 )
@@ -418,4 +420,5 @@
 n "config_rd_en"
 t "std_logic"
+posAdd 0
 o 26
 suid 30,0
@@ -433,5 +436,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 28
+o 30
 suid 31,0
 i "'0'"
@@ -449,5 +452,5 @@
 preAdd 0
 posAdd 0
-o 29
+o 31
 suid 32,0
 i "'0'"
@@ -477,5 +480,5 @@
 eolc "-- default DWRITE HIGH."
 posAdd 0
-o 30
+o 32
 suid 35,0
 i "'1'"
@@ -492,5 +495,5 @@
 eolc "-- default phase shift upwards"
 posAdd 0
-o 31
+o 33
 suid 36,0
 i "'1'"
@@ -508,5 +511,5 @@
 preAdd 0
 posAdd 0
-o 32
+o 34
 suid 37,0
 i "'0'"
@@ -523,5 +526,5 @@
 eolc "-- pulse this to reset the variable phase shift"
 posAdd 0
-o 33
+o 35
 suid 38,0
 i "'0'"
@@ -538,5 +541,5 @@
 eolc "-- default SRCLK on."
 posAdd 0
-o 34
+o 36
 suid 39,0
 i "'1'"
@@ -544,4 +547,32 @@
 )
 uid 1025,0
+)
+*48 (LogPort
+port (LogicalPort
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 27
+suid 40,0
+)
+)
+uid 1062,0
+)
+*49 (LogPort
+port (LogicalPort
+decl (Decl
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 28
+suid 41,0
+)
+)
+uid 1064,0
 )
 ]
@@ -552,5 +583,5 @@
 uid 188,0
 optionalChildren [
-*48 (Sheet
+*50 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -569,5 +600,5 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *49 (MRCItem
+emptyMRCItem *51 (MRCItem
 litem &1
 pos 3
@@ -576,5 +607,5 @@
 uid 190,0
 optionalChildren [
-*50 (MRCItem
+*52 (MRCItem
 litem &2
 pos 0
@@ -582,5 +613,5 @@
 uid 191,0
 )
-*51 (MRCItem
+*53 (MRCItem
 litem &3
 pos 1
@@ -588,5 +619,5 @@
 uid 192,0
 )
-*52 (MRCItem
+*54 (MRCItem
 litem &4
 pos 2
@@ -595,5 +626,5 @@
 uid 193,0
 )
-*53 (MRCItem
+*55 (MRCItem
 litem &14
 pos 0
@@ -601,5 +632,5 @@
 uid 137,0
 )
-*54 (MRCItem
+*56 (MRCItem
 litem &15
 pos 1
@@ -607,5 +638,5 @@
 uid 139,0
 )
-*55 (MRCItem
+*57 (MRCItem
 litem &16
 pos 2
@@ -613,5 +644,5 @@
 uid 141,0
 )
-*56 (MRCItem
+*58 (MRCItem
 litem &17
 pos 3
@@ -619,5 +650,5 @@
 uid 143,0
 )
-*57 (MRCItem
+*59 (MRCItem
 litem &18
 pos 4
@@ -625,5 +656,5 @@
 uid 145,0
 )
-*58 (MRCItem
+*60 (MRCItem
 litem &19
 pos 5
@@ -631,5 +662,5 @@
 uid 147,0
 )
-*59 (MRCItem
+*61 (MRCItem
 litem &20
 pos 6
@@ -637,5 +668,5 @@
 uid 151,0
 )
-*60 (MRCItem
+*62 (MRCItem
 litem &21
 pos 7
@@ -643,5 +674,5 @@
 uid 153,0
 )
-*61 (MRCItem
+*63 (MRCItem
 litem &22
 pos 8
@@ -649,5 +680,5 @@
 uid 155,0
 )
-*62 (MRCItem
+*64 (MRCItem
 litem &23
 pos 9
@@ -655,5 +686,5 @@
 uid 157,0
 )
-*63 (MRCItem
+*65 (MRCItem
 litem &24
 pos 10
@@ -661,5 +692,5 @@
 uid 159,0
 )
-*64 (MRCItem
+*66 (MRCItem
 litem &25
 pos 11
@@ -667,5 +698,5 @@
 uid 161,0
 )
-*65 (MRCItem
+*67 (MRCItem
 litem &26
 pos 12
@@ -673,5 +704,5 @@
 uid 163,0
 )
-*66 (MRCItem
+*68 (MRCItem
 litem &27
 pos 13
@@ -679,5 +710,5 @@
 uid 165,0
 )
-*67 (MRCItem
+*69 (MRCItem
 litem &28
 pos 14
@@ -685,5 +716,5 @@
 uid 359,0
 )
-*68 (MRCItem
+*70 (MRCItem
 litem &29
 pos 15
@@ -691,5 +722,5 @@
 uid 361,0
 )
-*69 (MRCItem
+*71 (MRCItem
 litem &30
 pos 16
@@ -697,5 +728,5 @@
 uid 391,0
 )
-*70 (MRCItem
+*72 (MRCItem
 litem &31
 pos 17
@@ -703,5 +734,5 @@
 uid 497,0
 )
-*71 (MRCItem
+*73 (MRCItem
 litem &32
 pos 18
@@ -709,5 +740,5 @@
 uid 527,0
 )
-*72 (MRCItem
+*74 (MRCItem
 litem &33
 pos 19
@@ -715,5 +746,5 @@
 uid 582,0
 )
-*73 (MRCItem
+*75 (MRCItem
 litem &34
 pos 20
@@ -721,5 +752,5 @@
 uid 584,0
 )
-*74 (MRCItem
+*76 (MRCItem
 litem &35
 pos 21
@@ -727,5 +758,5 @@
 uid 586,0
 )
-*75 (MRCItem
+*77 (MRCItem
 litem &36
 pos 22
@@ -733,5 +764,5 @@
 uid 588,0
 )
-*76 (MRCItem
+*78 (MRCItem
 litem &37
 pos 23
@@ -739,5 +770,5 @@
 uid 590,0
 )
-*77 (MRCItem
+*79 (MRCItem
 litem &38
 pos 24
@@ -745,5 +776,5 @@
 uid 592,0
 )
-*78 (MRCItem
+*80 (MRCItem
 litem &39
 pos 25
@@ -751,5 +782,5 @@
 uid 646,0
 )
-*79 (MRCItem
+*81 (MRCItem
 litem &40
 pos 26
@@ -757,5 +788,5 @@
 uid 676,0
 )
-*80 (MRCItem
+*82 (MRCItem
 litem &41
 pos 27
@@ -763,5 +794,5 @@
 uid 729,0
 )
-*81 (MRCItem
+*83 (MRCItem
 litem &42
 pos 28
@@ -769,5 +800,5 @@
 uid 891,0
 )
-*82 (MRCItem
+*84 (MRCItem
 litem &43
 pos 29
@@ -775,5 +806,5 @@
 uid 923,0
 )
-*83 (MRCItem
+*85 (MRCItem
 litem &44
 pos 30
@@ -781,5 +812,5 @@
 uid 960,0
 )
-*84 (MRCItem
+*86 (MRCItem
 litem &45
 pos 31
@@ -787,5 +818,5 @@
 uid 962,0
 )
-*85 (MRCItem
+*87 (MRCItem
 litem &46
 pos 32
@@ -793,9 +824,21 @@
 uid 994,0
 )
-*86 (MRCItem
+*88 (MRCItem
 litem &47
 pos 33
 dimension 20
 uid 1026,0
+)
+*89 (MRCItem
+litem &48
+pos 34
+dimension 20
+uid 1063,0
+)
+*90 (MRCItem
+litem &49
+pos 35
+dimension 20
+uid 1065,0
 )
 ]
@@ -810,5 +853,5 @@
 uid 194,0
 optionalChildren [
-*87 (MRCItem
+*91 (MRCItem
 litem &5
 pos 0
@@ -816,5 +859,5 @@
 uid 195,0
 )
-*88 (MRCItem
+*92 (MRCItem
 litem &7
 pos 1
@@ -822,5 +865,5 @@
 uid 196,0
 )
-*89 (MRCItem
+*93 (MRCItem
 litem &8
 pos 2
@@ -828,5 +871,5 @@
 uid 197,0
 )
-*90 (MRCItem
+*94 (MRCItem
 litem &9
 pos 3
@@ -834,5 +877,5 @@
 uid 198,0
 )
-*91 (MRCItem
+*95 (MRCItem
 litem &10
 pos 4
@@ -840,5 +883,5 @@
 uid 199,0
 )
-*92 (MRCItem
+*96 (MRCItem
 litem &11
 pos 5
@@ -846,5 +889,5 @@
 uid 200,0
 )
-*93 (MRCItem
+*97 (MRCItem
 litem &12
 pos 6
@@ -852,5 +895,5 @@
 uid 201,0
 )
-*94 (MRCItem
+*98 (MRCItem
 litem &13
 pos 7
@@ -873,39 +916,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *95 (LEmptyRow
+emptyRow *99 (LEmptyRow
 )
 uid 204,0
 optionalChildren [
-*96 (RefLabelRowHdr
-)
-*97 (TitleRowHdr
-)
-*98 (FilterRowHdr
-)
-*99 (RefLabelColHdr
+*100 (RefLabelRowHdr
+)
+*101 (TitleRowHdr
+)
+*102 (FilterRowHdr
+)
+*103 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*100 (RowExpandColHdr
+*104 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*101 (GroupColHdr
+*105 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*102 (NameColHdr
+*106 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*103 (TypeColHdr
+*107 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*104 (InitColHdr
+*108 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*105 (PragmaColHdr
+*109 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*106 (EolColHdr
+*110 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*107 (LogGeneric
+*111 (LogGeneric
 generic (GiElement
 name "RAM_ADDR_WIDTH"
@@ -913,5 +956,5 @@
 value "14"
 )
-uid 1027,0
+uid 1066,0
 )
 ]
@@ -922,5 +965,5 @@
 uid 216,0
 optionalChildren [
-*108 (Sheet
+*112 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -939,6 +982,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *109 (MRCItem
-litem &95
+emptyMRCItem *113 (MRCItem
+litem &99
 pos 3
 dimension 20
@@ -946,18 +989,18 @@
 uid 218,0
 optionalChildren [
-*110 (MRCItem
-litem &96
+*114 (MRCItem
+litem &100
 pos 0
 dimension 20
 uid 219,0
 )
-*111 (MRCItem
-litem &97
+*115 (MRCItem
+litem &101
 pos 1
 dimension 23
 uid 220,0
 )
-*112 (MRCItem
-litem &98
+*116 (MRCItem
+litem &102
 pos 2
 hidden 1
@@ -965,9 +1008,9 @@
 uid 221,0
 )
-*113 (MRCItem
-litem &107
+*117 (MRCItem
+litem &111
 pos 0
 dimension 20
-uid 1028,0
+uid 1067,0
 )
 ]
@@ -982,42 +1025,42 @@
 uid 222,0
 optionalChildren [
-*114 (MRCItem
-litem &99
+*118 (MRCItem
+litem &103
 pos 0
 dimension 20
 uid 223,0
 )
-*115 (MRCItem
-litem &101
+*119 (MRCItem
+litem &105
 pos 1
 dimension 50
 uid 224,0
 )
-*116 (MRCItem
-litem &102
+*120 (MRCItem
+litem &106
 pos 2
 dimension 100
 uid 225,0
 )
-*117 (MRCItem
-litem &103
+*121 (MRCItem
+litem &107
 pos 3
 dimension 100
 uid 226,0
 )
-*118 (MRCItem
-litem &104
+*122 (MRCItem
+litem &108
 pos 4
 dimension 50
 uid 227,0
 )
-*119 (MRCItem
-litem &105
+*123 (MRCItem
+litem &109
 pos 5
 dimension 50
 uid 228,0
 )
-*120 (MRCItem
-litem &106
+*124 (MRCItem
+litem &110
 pos 6
 dimension 80
@@ -1042,21 +1085,21 @@
 (vvPair
 variable "HDLDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
 )
 (vvPair
@@ -1074,13 +1117,13 @@
 (vvPair
 variable "d"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\w5300_modul"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul"
 )
 (vvPair
 variable "d_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\w5300_modul"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul"
 )
 (vvPair
 variable "date"
-value "30.08.2010"
+value "03.01.2011"
 )
 (vvPair
@@ -1094,5 +1137,5 @@
 (vvPair
 variable "dd"
-value "30"
+value "03"
 )
 (vvPair
@@ -1158,5 +1201,5 @@
 (vvPair
 variable "mm"
-value "08"
+value "01"
 )
 (vvPair
@@ -1166,17 +1209,17 @@
 (vvPair
 variable "month"
-value "Aug"
+value "Jan"
 )
 (vvPair
 variable "month_long"
-value "August"
+value "Januar"
 )
 (vvPair
 variable "p"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "C:\\FPGA_projects\\ADC_CLK_VAR_PS\\FACT_FAD_20MHz_SRCLK\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
 )
 (vvPair
@@ -1234,5 +1277,5 @@
 (vvPair
 variable "time"
-value "10:38:27"
+value "16:29:46"
 )
 (vvPair
@@ -1254,9 +1297,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -1265,8 +1308,8 @@
 uid 173,0
 optionalChildren [
-*121 (SymbolBody
+*125 (SymbolBody
 uid 8,0
 optionalChildren [
-*122 (CptPort
+*126 (CptPort
 uid 48,0
 ps "OnEdgeStrategy"
@@ -1314,5 +1357,5 @@
 )
 )
-*123 (CptPort
+*127 (CptPort
 uid 53,0
 ps "OnEdgeStrategy"
@@ -1363,5 +1406,5 @@
 )
 )
-*124 (CptPort
+*128 (CptPort
 uid 58,0
 ps "OnEdgeStrategy"
@@ -1412,5 +1455,5 @@
 )
 )
-*125 (CptPort
+*129 (CptPort
 uid 63,0
 ps "OnEdgeStrategy"
@@ -1461,5 +1504,5 @@
 )
 )
-*126 (CptPort
+*130 (CptPort
 uid 68,0
 ps "OnEdgeStrategy"
@@ -1510,5 +1553,5 @@
 )
 )
-*127 (CptPort
+*131 (CptPort
 uid 73,0
 ps "OnEdgeStrategy"
@@ -1559,5 +1602,5 @@
 )
 )
-*128 (CptPort
+*132 (CptPort
 uid 83,0
 ps "OnEdgeStrategy"
@@ -1608,5 +1651,5 @@
 )
 )
-*129 (CptPort
+*133 (CptPort
 uid 88,0
 ps "OnEdgeStrategy"
@@ -1654,5 +1697,5 @@
 )
 )
-*130 (CptPort
+*134 (CptPort
 uid 93,0
 ps "OnEdgeStrategy"
@@ -1701,5 +1744,5 @@
 )
 )
-*131 (CptPort
+*135 (CptPort
 uid 98,0
 ps "OnEdgeStrategy"
@@ -1748,5 +1791,5 @@
 )
 )
-*132 (CptPort
+*136 (CptPort
 uid 103,0
 ps "OnEdgeStrategy"
@@ -1795,5 +1838,5 @@
 )
 )
-*133 (CptPort
+*137 (CptPort
 uid 108,0
 ps "OnEdgeStrategy"
@@ -1844,5 +1887,5 @@
 )
 )
-*134 (CptPort
+*138 (CptPort
 uid 113,0
 ps "OnEdgeStrategy"
@@ -1890,5 +1933,5 @@
 )
 )
-*135 (CptPort
+*139 (CptPort
 uid 118,0
 ps "OnEdgeStrategy"
@@ -1939,5 +1982,5 @@
 )
 )
-*136 (CommentText
+*140 (CommentText
 uid 299,0
 ps "EdgeToEdgeStrategy"
@@ -1973,5 +2016,5 @@
 excludeCommentLeader 1
 )
-*137 (CptPort
+*141 (CptPort
 uid 348,0
 ps "OnEdgeStrategy"
@@ -2017,5 +2060,5 @@
 )
 )
-*138 (CptPort
+*142 (CptPort
 uid 353,0
 ps "OnEdgeStrategy"
@@ -2061,5 +2104,5 @@
 )
 )
-*139 (CptPort
+*143 (CptPort
 uid 385,0
 ps "OnEdgeStrategy"
@@ -2106,5 +2149,5 @@
 )
 )
-*140 (CptPort
+*144 (CptPort
 uid 491,0
 ps "OnEdgeStrategy"
@@ -2155,5 +2198,5 @@
 )
 )
-*141 (CptPort
+*145 (CptPort
 uid 521,0
 ps "OnEdgeStrategy"
@@ -2202,5 +2245,5 @@
 )
 )
-*142 (CptPort
+*146 (CptPort
 uid 551,0
 ps "OnEdgeStrategy"
@@ -2249,5 +2292,5 @@
 )
 )
-*143 (CptPort
+*147 (CptPort
 uid 556,0
 ps "OnEdgeStrategy"
@@ -2280,6 +2323,7 @@
 font "Courier New,8,0"
 )
-xt "2000,36800,23000,37600"
-st "config_busy       : IN     std_logic  ;
+xt "2000,40000,23000,41600"
+st "-- --
+config_busy       : IN     std_logic  ;
 "
 )
@@ -2288,10 +2332,12 @@
 n "config_busy"
 t "std_logic"
-o 27
+prec "-- --"
+preAdd 0
+o 29
 suid 25,0
 )
 )
 )
-*144 (CptPort
+*148 (CptPort
 uid 561,0
 ps "OnEdgeStrategy"
@@ -2341,5 +2387,5 @@
 )
 )
-*145 (CptPort
+*149 (CptPort
 uid 566,0
 ps "OnEdgeStrategy"
@@ -2385,5 +2431,5 @@
 )
 )
-*146 (CptPort
+*150 (CptPort
 uid 571,0
 ps "OnEdgeStrategy"
@@ -2432,5 +2478,5 @@
 )
 )
-*147 (CptPort
+*151 (CptPort
 uid 576,0
 ps "OnEdgeStrategy"
@@ -2479,5 +2525,5 @@
 )
 )
-*148 (CptPort
+*152 (CptPort
 uid 640,0
 ps "OnEdgeStrategy"
@@ -2520,4 +2566,5 @@
 n "config_rd_en"
 t "std_logic"
+posAdd 0
 o 26
 suid 30,0
@@ -2526,5 +2573,5 @@
 )
 )
-*149 (CptPort
+*153 (CptPort
 uid 670,0
 ps "OnEdgeStrategy"
@@ -2558,5 +2605,5 @@
 font "Courier New,8,0"
 )
-xt "2000,37600,50500,38400"
+xt "2000,41600,50500,42400"
 st "denable           : OUT    std_logic                      := '0' ; -- default domino wave off
 "
@@ -2569,5 +2616,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 28
+o 30
 suid 31,0
 i "'0'"
@@ -2575,5 +2622,5 @@
 )
 )
-*150 (CptPort
+*154 (CptPort
 uid 723,0
 ps "OnEdgeStrategy"
@@ -2607,5 +2654,5 @@
 font "Courier New,8,0"
 )
-xt "2000,38400,48500,39200"
+xt "2000,42400,48500,43200"
 st "dwrite_enable     : OUT    std_logic                      := '0' ; -- default DWRITE low.
 "
@@ -2619,5 +2666,5 @@
 preAdd 0
 posAdd 0
-o 29
+o 31
 suid 32,0
 i "'0'"
@@ -2625,5 +2672,5 @@
 )
 )
-*151 (CptPort
+*155 (CptPort
 uid 885,0
 ps "OnEdgeStrategy"
@@ -2672,5 +2719,5 @@
 )
 )
-*152 (CptPort
+*156 (CptPort
 uid 917,0
 ps "OnEdgeStrategy"
@@ -2704,5 +2751,5 @@
 font "Courier New,8,0"
 )
-xt "2000,39200,49000,40000"
+xt "2000,43200,49000,44000"
 st "sclk_enable       : OUT    std_logic                      := '1' ; -- default DWRITE HIGH.
 "
@@ -2715,5 +2762,5 @@
 eolc "-- default DWRITE HIGH."
 posAdd 0
-o 30
+o 32
 suid 35,0
 i "'1'"
@@ -2721,5 +2768,5 @@
 )
 )
-*153 (CptPort
+*157 (CptPort
 uid 949,0
 ps "OnEdgeStrategy"
@@ -2753,5 +2800,5 @@
 font "Courier New,8,0"
 )
-xt "2000,40000,52500,40800"
+xt "2000,44000,52500,44800"
 st "ps_direction      : OUT    std_logic                      := '1' ; -- default phase shift upwards
 "
@@ -2764,5 +2811,5 @@
 eolc "-- default phase shift upwards"
 posAdd 0
-o 31
+o 33
 suid 36,0
 i "'1'"
@@ -2770,5 +2817,5 @@
 )
 )
-*154 (CptPort
+*158 (CptPort
 uid 954,0
 ps "OnEdgeStrategy"
@@ -2802,5 +2849,5 @@
 font "Courier New,8,0"
 )
-xt "2000,40800,53500,41600"
+xt "2000,44800,53500,45600"
 st "ps_do_phase_shift : OUT    std_logic                      := '0' ; --pulse this to phase shift once
 "
@@ -2814,5 +2861,5 @@
 preAdd 0
 posAdd 0
-o 32
+o 34
 suid 37,0
 i "'0'"
@@ -2820,5 +2867,5 @@
 )
 )
-*155 (CptPort
+*159 (CptPort
 uid 988,0
 ps "OnEdgeStrategy"
@@ -2852,5 +2899,5 @@
 font "Courier New,8,0"
 )
-xt "2000,41600,61000,42400"
+xt "2000,45600,61000,46400"
 st "ps_reset          : OUT    std_logic                      := '0' ; -- pulse this to reset the variable phase shift
 "
@@ -2863,5 +2910,5 @@
 eolc "-- pulse this to reset the variable phase shift"
 posAdd 0
-o 33
+o 35
 suid 38,0
 i "'0'"
@@ -2869,5 +2916,5 @@
 )
 )
-*156 (CptPort
+*160 (CptPort
 uid 1020,0
 ps "OnEdgeStrategy"
@@ -2901,5 +2948,5 @@
 font "Courier New,8,0"
 )
-xt "2000,42400,46500,43200"
+xt "2000,46400,46500,47200"
 st "srclk_enable      : OUT    std_logic                      := '1' -- default SRCLK on.
 "
@@ -2912,7 +2959,103 @@
 eolc "-- default SRCLK on."
 posAdd 0
-o 34
+o 36
 suid 39,0
 i "'1'"
+)
+)
+)
+*161 (CptPort
+uid 1052,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1053,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "42250,19625,43000,20375"
+)
+tg (CPTG
+uid 1054,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1055,0
+va (VaSet
+)
+xt "44000,19500,49600,20500"
+st "config_rw_ack"
+blo "44000,20300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1056,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,36800,23000,38400"
+st "-- --
+config_rw_ack     : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "config_rw_ack"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 27
+suid 40,0
+)
+)
+)
+*162 (CptPort
+uid 1057,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1058,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "42250,20625,43000,21375"
+)
+tg (CPTG
+uid 1059,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1060,0
+va (VaSet
+)
+xt "44000,20500,50300,21500"
+st "config_rw_ready"
+blo "44000,21300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1061,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "2000,38400,23000,40000"
+st "-- --
+config_rw_ready   : IN     std_logic  ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "config_rw_ready"
+t "std_logic"
+prec "-- --"
+preAdd 0
+posAdd 0
+o 28
+suid 41,0
 )
 )
@@ -2953,5 +3096,5 @@
 )
 )
-gi *157 (GenericInterface
+gi *163 (GenericInterface
 uid 13,0
 ps "CenterOffsetStrategy"
@@ -2989,8 +3132,8 @@
 )
 )
-*158 (Grouping
+*164 (Grouping
 uid 16,0
 optionalChildren [
-*159 (CommentText
+*165 (CommentText
 uid 18,0
 shape (Rectangle
@@ -3023,5 +3166,5 @@
 titleBlock 1
 )
-*160 (CommentText
+*166 (CommentText
 uid 21,0
 shape (Rectangle
@@ -3054,5 +3197,5 @@
 titleBlock 1
 )
-*161 (CommentText
+*167 (CommentText
 uid 24,0
 shape (Rectangle
@@ -3085,5 +3228,5 @@
 titleBlock 1
 )
-*162 (CommentText
+*168 (CommentText
 uid 27,0
 shape (Rectangle
@@ -3116,5 +3259,5 @@
 titleBlock 1
 )
-*163 (CommentText
+*169 (CommentText
 uid 30,0
 shape (Rectangle
@@ -3146,5 +3289,5 @@
 titleBlock 1
 )
-*164 (CommentText
+*170 (CommentText
 uid 33,0
 shape (Rectangle
@@ -3177,5 +3320,5 @@
 titleBlock 1
 )
-*165 (CommentText
+*171 (CommentText
 uid 36,0
 shape (Rectangle
@@ -3208,5 +3351,5 @@
 titleBlock 1
 )
-*166 (CommentText
+*172 (CommentText
 uid 39,0
 shape (Rectangle
@@ -3239,5 +3382,5 @@
 titleBlock 1
 )
-*167 (CommentText
+*173 (CommentText
 uid 42,0
 shape (Rectangle
@@ -3270,5 +3413,5 @@
 titleBlock 1
 )
-*168 (CommentText
+*174 (CommentText
 uid 45,0
 shape (Rectangle
@@ -3314,5 +3457,5 @@
 oxt "14000,66000,55000,71000"
 )
-*169 (CommentText
+*175 (CommentText
 uid 133,0
 shape (Rectangle
@@ -3357,9 +3500,9 @@
 color "26368,26368,26368"
 )
-packageList *170 (PackageList
+packageList *176 (PackageList
 uid 170,0
 stg "VerticalLayoutStrategy"
 textVec [
-*171 (Text
+*177 (Text
 uid 171,0
 va (VaSet
@@ -3370,5 +3513,5 @@
 blo "0,1800"
 )
-*172 (MLText
+*178 (MLText
 uid 172,0
 va (VaSet
@@ -3471,5 +3614,5 @@
 )
 )
-gi *173 (GenericInterface
+gi *179 (GenericInterface
 ps "CenterOffsetStrategy"
 matrix (Matrix
@@ -3568,5 +3711,5 @@
 )
 )
-DeclarativeBlock *174 (SymDeclBlock
+DeclarativeBlock *180 (SymDeclBlock
 uid 1,0
 stg "SymDeclLayoutStrategy"
@@ -3594,7 +3737,7 @@
 font "Arial,8,1"
 )
-xt "0,43200,2400,44200"
+xt "0,47200,2400,48200"
 st "User:"
-blo "0,44000"
+blo "0,48000"
 )
 internalLabel (Text
@@ -3613,5 +3756,5 @@
 font "Courier New,8,0"
 )
-xt "2000,44200,2000,44200"
+xt "2000,48200,2000,48200"
 tm "SyDeclarativeTextMgr"
 )
@@ -3626,5 +3769,5 @@
 )
 )
-lastUid 1028,0
+lastUid 1067,0
 activeModelName "Symbol:CDM"
 )
