Changeset 10074 for firmware


Ignore:
Timestamp:
Jan 4, 2011, 3:02:07 PM (9 years ago)
Author:
neise
Message:
added LED controller
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
2 added
18 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10073 r10074  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 14:00:25 01.10.2010
     5--          at - 12:35:56 04.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    4141-- Created:
    4242--          by - dneise.UNKNOWN (E5B-LABOR6)
    43 --          at - 14:00:25 01.10.2010
     43--          at - 12:35:56 04.01.2011
    4444--
    4545-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf

    r10073 r10074  
    253253# LEDs
    254254#######################################################
    255 NET LED<0> LOC  = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;         
    256 NET LED<1> LOC  = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2;
    257 NET LED<2> LOC  = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;       
    258 
    259 
     255NET AMBER_LED LOC  = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;              #schematic: LED_3 D3 AMBER
     256NET GREEN_LED LOC  = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; #schematic: LED_0 D1 GREEN
     257NET RED_LED LOC  = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2  RED
     258
     259
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak

    r9912 r10074  
    2525NET RS485_C_DE LOC  = C5 | IOSTANDARD=LVCMOS33;         #ok
    2626NET RS485_C_RE LOC  = C6 | IOSTANDARD=LVCMOS33;         #ok
    27 #NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;                #ok
    28 #NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;                #ok
     27NET RS485_C_DO LOC  = C7 | IOSTANDARD=LVCMOS33;         #ok
     28NET RS485_C_DI LOC  = C8 | IOSTANDARD=LVCMOS33;         #ok
    2929
    3030NET RS485_E_DE LOC  = D20 | IOSTANDARD=LVCMOS33;                #ok
    3131NET RS485_E_RE LOC  = D21 | IOSTANDARD=LVCMOS33;                #ok
    32 #NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;               #ok
    33 #NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;               #ok
     32NET RS485_E_DO LOC  = D22 | IOSTANDARD=LVCMOS33;                #ok
     33NET RS485_E_DI LOC  = D23 | IOSTANDARD=LVCMOS33;                #ok
    3434
    3535
     
    230230NET A1_T<3> LOC  = AC14 | IOSTANDARD=LVCMOS33;          #ok
    231231NET A1_T<4> LOC  = AC15 | IOSTANDARD=LVCMOS33;          #ok
    232 #NET A1_T<5> LOC  = AB16 | IOSTANDARD=LVCMOS33;                 #ok
    233 #NET A1_T<6> LOC  = AC16 | IOSTANDARD=LVCMOS33;         #ok
    234 #NET A1_T<7> LOC  = AB18 | IOSTANDARD=LVCMOS33;         #ok
     232NET A1_T<5> LOC  = AB16 | IOSTANDARD=LVCMOS33;          #ok
     233NET A1_T<6> LOC  = AC16 | IOSTANDARD=LVCMOS33;          #ok
     234NET A1_T<7> LOC  = AB18 | IOSTANDARD=LVCMOS33;          #ok
    235235
    236236
     
    253253# LEDs
    254254#######################################################
    255 NET LED<0> LOC  = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;         
    256 NET LED<1> LOC  = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2;
    257 NET LED<2> LOC  = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;       
    258 
    259 
     255NET AMBER_LED LOC  = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;              #schematic: LED_3 D3 AMBER
     256NET GREEN_LED LOC  = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 1; #schematic: LED_0 D1 GREEN
     257NET RED_LED LOC  = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2  RED
     258
     259
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10073 r10074  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:00:27 03.01.2011
     5--          at - 15:02:56 04.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    2929      W_INT      : IN     std_logic;
    3030      X_50M      : IN     STD_LOGIC;
    31       A0_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (others => '0');
    32       A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0');
     31      A0_T       : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
     32      A1_T       : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     33      AMBER_LED  : OUT    std_logic;
    3334      A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
    3435      D0_SRCLK   : OUT    STD_LOGIC;
     
    3738      D3_SRCLK   : OUT    STD_LOGIC;
    3839      DAC_CS     : OUT    std_logic;
    39       DENABLE    : OUT    std_logic                       := '0';
    40       DWRITE     : OUT    std_logic                       := '0';
    41       D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0');
    42       D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0');
    43       D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0');
     40      DENABLE    : OUT    std_logic                     := '0';
     41      DWRITE     : OUT    std_logic                     := '0';
     42      D_A        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     43      D_T        : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     44      D_T2       : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    4445      EE_CS      : OUT    std_logic;
    45       LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1');
    46       MOSI       : OUT    std_logic                       := '0';
     46      GREEN_LED  : OUT    std_logic;
     47      MOSI       : OUT    std_logic                     := '0';
    4748      OE_ADC     : OUT    STD_LOGIC;
     49      RED_LED    : OUT    std_logic;
    4850      RS485_C_DE : OUT    std_logic;
    4951      RS485_C_DO : OUT    std_logic;
     
    5153      RS485_E_DE : OUT    std_logic;
    5254      RS485_E_RE : OUT    std_logic;
    53       RSRLOAD    : OUT    std_logic                       := '0';
    54       SRIN       : OUT    std_logic                       := '0';
     55      RSRLOAD    : OUT    std_logic                     := '0';
     56      SRIN       : OUT    std_logic                     := '0';
    5557      S_CLK      : OUT    std_logic;
    5658      T0_CS      : OUT    std_logic;
     
    6062      TRG_V      : OUT    std_logic;
    6163      W_A        : OUT    std_logic_vector (9 DOWNTO 0);
    62       W_CS       : OUT    std_logic                       := '1';
    63       W_RD       : OUT    std_logic                       := '1';
    64       W_RES      : OUT    std_logic                       := '1';
    65       W_WR       : OUT    std_logic                       := '1';
     64      W_CS       : OUT    std_logic                     := '1';
     65      W_RD       : OUT    std_logic                     := '1';
     66      W_RES      : OUT    std_logic                     := '1';
     67      W_WR       : OUT    std_logic                     := '1';
    6668      MISO       : INOUT  std_logic;
    6769      W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
     
    7779-- Created:
    7880--          by - dneise.UNKNOWN (E5B-LABOR6)
    79 --          at - 17:00:27 03.01.2011
     81--          at - 15:02:56 04.01.2011
    8082--
    8183-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    159161      adc_clk_en      : OUT    std_logic                     := '0';
    160162      adc_oeb         : OUT    std_logic                     := '1';
     163      amber           : OUT    std_logic ;
    161164      dac_cs          : OUT    std_logic ;
    162165      denable         : OUT    std_logic                     := '0';           -- default domino wave off
    163166      drs_channel_id  : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    164167      drs_dwrite      : OUT    std_logic                     := '1';
     168      green           : OUT    std_logic ;
    165169      led             : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    166170      mosi            : OUT    std_logic                     := '0';
    167171      offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    168172      ready           : OUT    std_logic                     := '0';
     173      red             : OUT    std_logic ;
    169174      sclk            : OUT    std_logic ;
    170175      sensor_cs       : OUT    std_logic_vector (3 DOWNTO 0);
     
    238243   
    239244   EE_CS <= '1';
    240    -- LEDs are low active
    241    LED(0) <= '1';
    242    LED(1) <= '0'; -- on
    243    LED(2) <= '1';
    244                                  
    245    
    246    
    247245
    248246   -- HDL Embedded Text Block 7 eb1
     
    316314         adc_clk_en      => adc_clk_en,
    317315         adc_oeb         => OE_ADC,
     316         amber           => AMBER_LED,
    318317         dac_cs          => dummy,
    319318         denable         => DENABLE,
    320319         drs_channel_id  => drs_channel_id,
    321320         drs_dwrite      => DWRITE,
     321         green           => GREEN_LED,
    322322         led             => D_T,
    323323         mosi            => MOSI,
    324324         offset          => OPEN,
    325325         ready           => ready,
     326         red             => RED_LED,
    326327         sclk            => S_CLK,
    327328         sensor_cs       => sensor_cs,
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10073 r10074  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:00:23 03.01.2011
     5--          at - 15:02:55 04.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    4747      adc_clk_en      : OUT    std_logic                     := '0';
    4848      adc_oeb         : OUT    std_logic                     := '1';
     49      amber           : OUT    std_logic;
    4950      dac_cs          : OUT    std_logic;
    5051      denable         : OUT    std_logic                     := '0';              -- default domino wave off
    5152      drs_channel_id  : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    5253      drs_dwrite      : OUT    std_logic                     := '1';
     54      green           : OUT    std_logic;
    5355      led             : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    5456      mosi            : OUT    std_logic                     := '0';
    5557      offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    5658      ready           : OUT    std_logic                     := '0';
     59      red             : OUT    std_logic;
    5760      sclk            : OUT    std_logic;
    5861      sensor_cs       : OUT    std_logic_vector (3 DOWNTO 0);
     
    7780-- Created:
    7881--          by - dneise.UNKNOWN (E5B-LABOR6)
    79 --          at - 17:00:24 03.01.2011
     82--          at - 15:02:55 04.01.2011
    8083--
    8184-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    157160   SIGNAL sensor_array           : sensor_array_type;
    158161   SIGNAL sensor_ready           : std_logic;
     162   SIGNAL socks_connected        : std_logic;
     163   SIGNAL socks_waiting          : std_logic;
    159164   SIGNAL srclk_enable           : std_logic                                    := '0';
    160165   SIGNAL srin_write_ack         : std_logic                                    := '0';
     
    316321   );
    317322   END COMPONENT;
     323   COMPONENT led_controller
     324   GENERIC (
     325      HEARTBEAT_DIVIDER : integer := 5000;         -- 100kHz @ 50 MHz
     326      WAITING_DIVIDER   : integer := 50000000      -- 10Hz @ 50 MHz
     327   );
     328   PORT (
     329      CLK             : IN     std_logic;
     330      socks_connected : IN     std_logic;
     331      socks_waiting   : IN     std_logic;
     332      trigger         : IN     std_logic;
     333      amber           : OUT    std_logic;
     334      green           : OUT    std_logic;
     335      red             : OUT    std_logic
     336   );
     337   END COMPONENT;
    318338   COMPONENT memory_manager
    319339   GENERIC (
     
    411431      ps_do_phase_shift : OUT    std_logic                      := '0';           --pulse this TO phase shift once
    412432      ps_reset          : OUT    std_logic                      := '0';           -- pulse this TO reset the variable phase shift
    413       srclk_enable      : OUT    std_logic                      := '1'            -- default SRCLK on.
     433      srclk_enable      : OUT    std_logic                      := '1';           -- default SRCLK on.
     434      socks_waiting     : OUT    std_logic ;
     435      socks_connected   : OUT    std_logic
    414436   );
    415437   END COMPONENT;
     
    423445   FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
    424446   FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
     447   FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller;
    425448   FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
    426449   FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
     
    593616         SRCLK                    => SRCLK1
    594617      );
     618   U_10 : led_controller
     619      GENERIC MAP (
     620         HEARTBEAT_DIVIDER => 25000000,         -- 2Hz @ 50 MHz
     621         WAITING_DIVIDER   => 5000000           -- 10Hz @ 50 MHz
     622      )
     623      PORT MAP (
     624         CLK             => CLK_50_internal,
     625         green           => green,
     626         amber           => amber,
     627         red             => red,
     628         trigger         => trigger_out,
     629         socks_waiting   => socks_waiting,
     630         socks_connected => socks_connected
     631      );
    595632   I_main_memory_manager : memory_manager
    596633      GENERIC MAP (
     
    680717         ps_do_phase_shift => ps_do_phase_shift,
    681718         ps_reset          => ps_reset,
    682          srclk_enable      => srclk_enable
     719         srclk_enable      => srclk_enable,
     720         socks_waiting     => socks_waiting,
     721         socks_connected   => socks_connected
    683722      );
    684723
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd.bak

    r9912 r10074  
    138138                PSEN <= '0';
    139139        if (PSDONE = '1') then
    140                         next_state <= READY_STATE;
     140                             next_state <= READY_STATE;
    141141        else
    142                         next_state <= READY_STATE;
     142                             next_state <= WAITINGFORDONE;
    143143        end if;
    144144       
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10072 r10074  
    4949      ram_addr       : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
    5050      data_valid     : IN     std_logic;
    51           data_valid_ack : OUT    std_logic := '0';
     51      data_valid_ack : OUT    std_logic := '0';
    5252      busy           : OUT    std_logic                     := '1';
    5353      write_header_flag, write_end_flag : IN std_logic;
     
    7474      ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
    7575     
    76       srclk_enable : out std_logic := '1' -- default SRCLK on.
     76      srclk_enable : out std_logic := '1'; -- default SRCLK on.
     77     
     78      socks_waiting : out std_logic;
     79      socks_connected: out std_logic
    7780   );
    7881
     
    238241                                          busy <= '1';
    239242                                                zaehler <= zaehler + 1;
     243                                                socks_waiting <= '0';
     244            socks_connected <= '0';
    240245            wiz_reset <= '0';
    241246--            led <= X"FF";
     
    432437                                               
    433438                                        when ESTABLISH =>
     439                                          socks_waiting <= '1';
     440            socks_connected <= '0';
    434441                                                par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
    435442                                                state_init <= READ_REG;
     
    463470          -- main "loop"
    464471                                        when MAIN =>
     472                                          socks_waiting <= '0';
     473            socks_connected <= '1';
     474
    465475                                          ps_do_phase_shift <= '0';
    466476                                          ps_reset <= '0';
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak

    r9912 r10074  
    4949      ram_addr       : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
    5050      data_valid     : IN     std_logic;
    51           data_valid_ack : OUT    std_logic := '0';
     51           data_valid_ack : OUT    std_logic := '0';
    5252      busy           : OUT    std_logic                     := '1';
    5353      write_header_flag, write_end_flag : IN std_logic;
     
    6060      config_wr_en : out std_logic := '0';
    6161      config_rd_en : out std_logic := '0';
     62      -- --
     63      config_rw_ack, config_rw_ready : in std_logic;
     64      -- --
    6265      config_busy : in std_logic;
    6366     
     
    6972      ps_direction : out std_logic := '1'; -- default phase shift upwards
    7073      ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
    71       ps_reset : out std_logic := '0' -- pulse this to reset the variable phase shift
     74      ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
     75     
     76      srclk_enable : out std_logic := '1' -- default SRCLK on.
    7277   );
    7378
     
    8085type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
    8186                         INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
    82                          SI, SI1, SI2, SI3, SI4, SI5, SI6,      ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
    83 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
     87                         SI, SI1, SI2, SI3, SI4, SI5, SI6,      ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
     88type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
    8489                          WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
    8590type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
     
    118123signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
    119124signal chk_recv_cntr : integer range 0 to 10000 := 0;
     125
     126-- --
     127signal wait_cntr : integer range 0 to 10000 := 0;
     128-- --
     129
    120130signal rx_packets_cnt : std_logic_vector (15 downto 0);
    121131signal next_packet_data : std_logic := '0';
     
    131141signal local_fifo_channels : std_logic_vector (3 downto 0);
    132142
     143signal data_valid_int : std_logic := '0';
     144
     145-- only for debugging
     146--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
     147--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
     148
     149
    133150begin
    134151
     
    136153  RST_TIME <= X"00120";
    137154  --synthesis translate_on
     155
    138156
    139157        w5300_init_proc : process (clk, int)
     
    218236                                        -- reset W5300
    219237                                        when RESET =>
     238                                          busy <= '1';
    220239                                                zaehler <= zaehler + 1;
    221240            wiz_reset <= '0';
    222             led <= X"FF";
     241--            led <= X"FF";
    223242                                                if (zaehler >= X"00064") then -- wait 2µs
    224243                                                        wiz_reset <= '1';
     
    354373                                                par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
    355374                                                state_init <= WRITE_REG;
    356                                                 next_state <= TIMEOUT;
    357                                         when TIMEOUT =>
    358                                                 par_addr <=     W5300_RTR;
    359                                                 par_data <= X"07D0"; -- 0x07D0 = 200ms
    360                                                 state_init <= WRITE_REG;
    361                                                 next_state <= RETRY;
    362                                         when RETRY =>
    363                                                 par_addr <=     W5300_RCR;
    364                                                 par_data <= X"0008";
    365                                                 state_init <= WRITE_REG;
    366375                                                next_state <= SI;
     376--                                      when TIMEOUT =>
     377--            par_addr <=       W5300_RTR;
     378--            par_data <= X"07D0"; -- 0x07D0 = 200ms
     379--            state_init <= WRITE_REG;
     380--            next_state <= RETRY;
     381--          when RETRY =>
     382--            par_addr <=       W5300_RCR;
     383--            par_data <= X"0008";
     384--            state_init <= WRITE_REG;
     385--            next_state <= SI;
     386--                                       
    367387
    368388                                        -- Socket Init
     
    416436                                                next_state <= EST1;
    417437                                        when EST1 =>
    418                                                 led <= data_read (7 downto 0);
     438--                                              led <= data_read (7 downto 0);
     439--            led <= X"00";
    419440                                                case data_read (7 downto 0) is
    420441                                                        when X"17" => -- established
     
    432453                                       
    433454                                        when CONFIG =>
    434             led <= X"F0";
     455--                                        led <= X"F0";
    435456                                          new_config <= '1';
    436457                                          if (config_started = '1') then
    437                                             led <= X"0F";
     458--                                          led <= X"0F";
    438459                                            new_config <= '0';
    439                                             busy <= '0';
    440460                                            state_init <= MAIN;
    441461                                          end if;
     
    446466                                          ps_reset <= '0';
    447467            if (trigger_stop = '1') then
    448                                             s_trigger <= '0';
    449                                           end if;
     468              s_trigger <= '0';
     469            end if;
     470            data_valid_ack <= '0';
     471            state_init <= MAIN1;
     472            data_valid_int <= data_valid;
     473                                        when MAIN1 =>
    450474            if (chk_recv_cntr = 1000) then
    451475              chk_recv_cntr <= 0;
     
    454478              busy <= '1';
    455479            else
    456               busy <= '0';
    457               data_valid_ack <= '0';
    458480              chk_recv_cntr <= chk_recv_cntr + 1; 
    459                                                   if (data_valid = '1') then
    460                                                     data_valid_ack <= '1';
    461                 local_write_length <= write_length;
    462                 local_ram_start_addr <= ram_start_addr;
    463                 local_ram_addr <= (others => '0');
    464                 local_write_header_flag <= write_header_flag;
    465                 local_write_end_flag <= write_end_flag;
    466                 local_fifo_channels <= fifo_channels;
    467                                                           next_state <= MAIN;
    468                                                           state_init <= WRITE_DATA;
    469                                                           busy <= '1';
    470               end if;
    471                                                 end if;
     481              state_init <= MAIN2;
     482            end if;
     483          when MAIN2 =>
     484            busy <= '0';
     485                                          if (data_valid = '1') then
     486                                            data_valid_int <= '0';
     487                                            busy <= '1';
     488              local_write_length <= write_length;
     489              local_ram_start_addr <= ram_start_addr;
     490              local_ram_addr <= (others => '0');
     491              local_write_header_flag <= write_header_flag;
     492              local_write_end_flag <= write_end_flag;
     493              local_fifo_channels <= fifo_channels;
     494--                data_valid_ack <= '1';
     495--                next_state <= MAIN;
     496--                state_init <= WRITE_DATA;
     497              state_init <= MAIN3;
     498            else
     499              state_init <= MAIN1;
     500            end if;
     501          when MAIN3 =>
     502--            led <= local_ram_start_addr (7 downto 0);
     503            data_valid_ack <= '1';
     504            next_state <= MAIN;
     505            state_init <= WRITE_DATA;
     506                                         
    472507
    473508                                        -- read data from socket 0 
     
    505540                else
    506541                  state_read_data <= RD_END;
    507 --                  if (new_config_flag = '1') then
    508 --                    new_config_flag <= '0';
    509 --                    state_init <= CONFIG;
    510 --                  else
    511 --                    busy <= '0';
    512 --                    state_init <= MAIN;
    513 --                  end if;
    514542                end if;
    515543              when RD_6 =>
    516                 led <= data_read (15 downto 8);
     544--                led <= data_read (15 downto 8);
    517545                -- read command
    518546                if (next_packet_data = '0') then
     
    521549                      trigger_stop <= '1';
    522550                      s_trigger <= '1';
    523                       state_read_data <= RD_WAIT;
     551                      state_read_data <= RD_5;
    524552                    when CMD_DWRITE_RUN =>
    525553                      dwrite_enable <= '1';
    526                       state_read_data <= RD_WAIT;
     554                      state_read_data <= RD_5;
    527555                    when CMD_DWRITE_STOP =>
    528556                      dwrite_enable <= '0';
    529                       state_read_data <= RD_WAIT;
     557                      state_read_data <= RD_5;
    530558                    when CMD_SCLK_ON =>
    531559                      sclk_enable <= '1';
    532                       state_read_data <= RD_WAIT;
     560                      state_read_data <= RD_5;
    533561                    when CMD_SCLK_OFF =>
    534562                      sclk_enable <= '0';
    535                       state_read_data <= RD_WAIT;
     563                      state_read_data <= RD_5;
    536564                    when CMD_DENABLE =>
    537565                      denable <= '1';
    538                       state_read_data <= RD_WAIT;
     566                      state_read_data <= RD_5;
    539567                    when CMD_DDISABLE =>
    540568                      denable <= '0';
    541                       state_read_data <= RD_WAIT;
     569                      state_read_data <= RD_5;
    542570                    when CMD_TRIGGER_C =>
    543571                      trigger_stop <= '0';
    544572                      s_trigger <= '1';
    545                       state_read_data <= RD_WAIT;
     573                      state_read_data <= RD_5;
    546574                    when CMD_TRIGGER_S =>
    547575                      trigger_stop <= '1';
    548                       state_read_data <= RD_WAIT;
     576                      state_read_data <= RD_5;
    549577                    -- phase shift commands here:
    550578                    when CMD_PS_DO =>
    551579                      ps_do_phase_shift <= '1';
    552                       state_read_data <= RD_WAIT;
     580                      state_read_data <= RD_5;
    553581                    when CMD_PS_DIRINC =>
    554582                      ps_direction <= '1';
    555                       state_read_data <= RD_WAIT;
     583                      state_read_data <= RD_5;
    556584                    when CMD_PS_RESET =>
    557585                      ps_reset <= '1';
    558                       state_read_data <= RD_WAIT;
     586                      state_read_data <= RD_5;
     587                    when CMD_SRCLK_ON =>
     588                      srclk_enable <= '1';
     589                      state_read_data <= RD_5;
     590                    when CMD_SRCLK_OFF =>
     591                      srclk_enable <= '0';
     592                      state_read_data <= RD_5;
    559593                    when CMD_PS_DIRDEC =>
    560594                      ps_direction <= '0';
    561                       state_read_data <= RD_WAIT;
     595                      state_read_data <= RD_5;
    562596                    when CMD_WRITE =>
    563597                      next_packet_data <= '1';
     
    578612                end if;
    579613              when RD_WAIT =>
    580                 state_read_data <= RD_WAIT1;
     614                if (config_rw_ack = '1') then
     615                  state_read_data <= RD_WAIT1;
     616                end if;
    581617              when RD_WAIT1 =>
    582                 config_data <= (others => 'Z');
    583                 config_wr_en <= '0';
    584                 state_read_data <= RD_5;
     618                if (config_rw_ready = '1') then
     619                  config_data <= (others => 'Z');
     620                  config_wr_en <= '0';
     621                  state_read_data <= RD_5;
     622                end if;
    585623              when RD_END =>
    586624                par_addr <= W5300_S0_CR;
     
    591629                  next_state <= CONFIG;
    592630                else
    593 --                busy <= '0';
    594631                  next_state <= MAIN;
    595632                end if;
     
    611648                                                          if (local_write_header_flag = '1') then
    612649                                                            local_socket_nr <= ram_data (2 downto 0);
     650--                                                          local_socket_nr <= "000";
    613651                                                          end if;
    614652                                                                next_state_tmp <= next_state;
     
    632670                                                                state_write <= WR_04;
    633671                                                        when WR_04 =>
    634                                                                 if (socket_tx_free (16 downto 0) < write_length_bytes) then
     672                                                         
     673--                                                        led <= socket_tx_free (15 downto 8);
     674                                                               
     675--                                                              if (socket_tx_free (16 downto 0) < write_length_bytes) then
     676                if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
    635677                                                                        state_write <= WR_01;
    636678                                                                else
     
    743785                state_init <= WRITE_REG;
    744786                next_state <= WRITE_DATA;
    745                 state_write <= WR_05;
     787                state_write <= WR_05a;
    746788             
    747789              -- End Write End Package Flag
     790             
     791              -- Wait????
     792              when WR_05a =>
     793                if (wait_cntr < 10) then -- 3000 works???
     794                  wait_cntr <= wait_cntr + 1;
     795                else
     796                  wait_cntr <= 0;
     797                  state_write <= WR_05b;
     798                end if;
     799              when WR_05b =>
     800                state_write <= WR_05;
    748801
    749802              --Send FIFO
     
    765818                                                                state_write <= WR_08;
    766819                                                        when others =>
    767 --                                                      busy <= '0';
    768820                                                                state_init <= next_state_tmp;
    769821                                                                state_write <= WR_START;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r10073 r10074  
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    262268LIBRARY FACT_FAD_lib
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    522 VIEW @behavioral
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    524 DESIGN data_generator
    525 VIEW @behavioral
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    527 DESIGN data_generator
    528 VIEW @behavioral
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    530 DESIGN data_generator
    531 VIEW @behavioral
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    533 DESIGN data_generator
    534 VIEW @behavioral
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    536 DESIGN data_generator
    537 VIEW @behavioral
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    539 DESIGN data_generator
    540 VIEW @behavioral
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    543 VIEW @behavioral
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    546 VIEW @behavioral
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    549 VIEW @behavioral
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    552 VIEW @behavioral
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    555 VIEW @behavioral
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    558 VIEW @behavioral
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    561 VIEW @behavioral
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    564 VIEW @behavioral
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    573 VIEW @behavioral
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    578 DESIGN data_generator
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    612 VIEW @behavioral
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    615 VIEW @behavioral
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    618 VIEW @behavioral
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    624 VIEW @behavioral
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    627 VIEW @behavioral
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    630 VIEW @behavioral
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    633 VIEW @behavioral
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    636 VIEW @behavioral
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    639 VIEW @behavioral
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    642 VIEW @behavioral
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    645 VIEW @behavioral
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    647 DESIGN @f@a@d_main
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    717 VIEW struct.bd
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     527DESIGN @f@a@d_main
     528VIEW struct.bd
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     530DESIGN data_generator
     531VIEW symbol.sb
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     533DESIGN data_generator
     534VIEW @behavioral
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     536DESIGN data_generator
     537VIEW @behavioral
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     539DESIGN data_generator
     540VIEW @behavioral
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     542DESIGN data_generator
     543VIEW @behavioral
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     545DESIGN data_generator
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     548DESIGN data_generator
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     551DESIGN data_generator
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     554DESIGN data_generator
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     563DESIGN data_generator
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     566DESIGN data_generator
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     581DESIGN data_generator
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     584DESIGN data_generator
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     593DESIGN data_generator
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     605DESIGN data_generator
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     617DESIGN data_generator
     618VIEW @behavioral
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     623DESIGN data_generator
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     627VIEW @behavioral
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     629DESIGN data_generator
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     635DESIGN data_generator
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     641DESIGN data_generator
     642VIEW @behavioral
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     653DESIGN data_generator
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     657VIEW @behavioral
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     659DESIGN data_generator
     660VIEW @behavioral
     661GRAPHIC 811,0 299 0
     662DESIGN @f@a@d_main
     663VIEW struct.bd
     664GRAPHIC 4903,0 302 0
     665DESIGN @f@a@d_main
     666VIEW struct.bd
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     668DESIGN @f@a@d_main
     669VIEW struct.bd
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     671DESIGN @f@a@d_main
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     675VIEW struct.bd
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     681VIEW symbol.sb
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     683DESIGN memory_manager
     684VIEW beha
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     686DESIGN memory_manager
     687VIEW beha
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     689DESIGN memory_manager
     690VIEW beha
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     692DESIGN memory_manager
     693VIEW beha
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     695DESIGN memory_manager
     696VIEW beha
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     698DESIGN memory_manager
     699VIEW beha
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     701DESIGN memory_manager
     702VIEW beha
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     704DESIGN memory_manager
     705VIEW beha
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     707DESIGN memory_manager
     708VIEW beha
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     710DESIGN memory_manager
     711VIEW beha
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     713DESIGN memory_manager
     714VIEW beha
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     716DESIGN memory_manager
     717VIEW beha
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     719DESIGN memory_manager
     720VIEW beha
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     722DESIGN memory_manager
     723VIEW beha
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     725DESIGN memory_manager
     726VIEW beha
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     729VIEW beha
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     731DESIGN memory_manager
     732VIEW beha
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     734DESIGN memory_manager
     735VIEW beha
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     738VIEW beha
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    771 VIEW symbol.sb
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     909VIEW @behavioral
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    881911LIBRARY FACT_FAD_lib
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    883913VIEW struct.bd
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     1483VIEW struct.bd
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     1489VIEW struct.bd
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     1492VIEW struct.bd
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     1495VIEW struct.bd
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     1530DESIGN @f@a@d_main
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     1533DESIGN @f@a@d_main
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     1577NO_GRAPHIC 727
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r10073 r10074  
    149149(vvPair
    150150variable "date"
    151 value "03.01.2011"
     151value "04.01.2011"
    152152)
    153153(vvPair
    154154variable "day"
    155 value "Mo"
     155value "Di"
    156156)
    157157(vvPair
    158158variable "day_long"
    159 value "Montag"
     159value "Dienstag"
    160160)
    161161(vvPair
    162162variable "dd"
    163 value "03"
     163value "04"
    164164)
    165165(vvPair
     
    297297(vvPair
    298298variable "time"
    299 value "16:58:24"
     299value "13:01:09"
    300300)
    301301(vvPair
     
    688688n "wiz_reset"
    689689t "std_logic"
    690 o 44
     690o 47
    691691suid 2,0
    692692i "'1'"
     
    727727b "(7 DOWNTO 0)"
    728728posAdd 0
    729 o 34
     729o 36
    730730suid 7,0
    731731i "(OTHERS => '0')"
     
    909909t "std_logic_vector"
    910910b "(9 DOWNTO 0)"
    911 o 41
     911o 44
    912912suid 26,0
    913913)
     
    945945n "wiz_cs"
    946946t "std_logic"
    947 o 42
     947o 45
    948948suid 28,0
    949949i "'1'"
     
    983983t "std_logic_vector"
    984984b "(15 DOWNTO 0)"
    985 o 47
     985o 50
    986986suid 27,0
    987987)
     
    10541054n "wiz_rd"
    10551055t "std_logic"
    1056 o 43
     1056o 46
    10571057suid 30,0
    10581058i "'1'"
     
    10911091n "wiz_wr"
    10921092t "std_logic"
    1093 o 45
     1093o 48
    10941094suid 29,0
    10951095i "'1'"
     
    13011301t "std_logic_vector"
    13021302b "(3 downto 0)"
    1303 o 32
     1303o 33
    13041304suid 48,0
    13051305i "(others => '0')"
     
    13371337n "drs_dwrite"
    13381338t "std_logic"
    1339 o 33
     1339o 34
    13401340suid 49,0
    13411341i "'1'"
     
    15821582n "dac_cs"
    15831583t "std_logic"
    1584 o 30
     1584o 31
    15851585suid 64,0
    15861586)
     
    16181618n "sclk"
    16191619t "std_logic"
    1620 o 38
     1620o 41
    16211621suid 62,0
    16221622)
     
    16551655t "std_logic_vector"
    16561656b "(3 DOWNTO 0)"
    1657 o 39
     1657o 42
    16581658suid 65,0
    16591659)
     
    16931693preAdd 0
    16941694posAdd 0
    1695 o 46
     1695o 49
    16961696suid 63,0
    16971697)
     
    17291729n "mosi"
    17301730t "std_logic"
    1731 o 35
     1731o 37
    17321732suid 66,0
    17331733i "'0'"
     
    17681768eolc "-- default domino wave off"
    17691769posAdd 0
    1770 o 31
     1770o 32
    17711771suid 67,0
    17721772i "'0'"
     
    19181918preAdd 0
    19191919posAdd 0
    1920 o 36
     1920o 38
    19211921suid 77,0
    19221922i "(OTHERS => '0')"
     
    21732173preAdd 0
    21742174posAdd 0
    2175 o 37
     2175o 39
    21762176suid 79,0
    21772177i "'0'"
     
    22132213preAdd 0
    22142214posAdd 0
    2215 o 40
     2215o 43
    22162216suid 78,0
    22172217i "'0'"
     
    23642364)
    23652365)
     2366*60 (CptPort
     2367uid 12521,0
     2368ps "OnEdgeStrategy"
     2369shape (Triangle
     2370uid 12522,0
     2371ro 90
     2372va (VaSet
     2373vasetType 1
     2374fg "0,65535,0"
     2375)
     2376xt "80000,140625,80750,141375"
     2377)
     2378tg (CPTG
     2379uid 12523,0
     2380ps "CptPortTextPlaceStrategy"
     2381stg "RightVerticalLayoutStrategy"
     2382f (Text
     2383uid 12524,0
     2384va (VaSet
     2385)
     2386xt "76500,140500,79000,141500"
     2387st "amber"
     2388ju 2
     2389blo "79000,141300"
     2390)
     2391)
     2392thePort (LogicalPort
     2393m 1
     2394decl (Decl
     2395n "amber"
     2396t "std_logic"
     2397o 30
     2398suid 87,0
     2399)
     2400)
     2401)
     2402*61 (CptPort
     2403uid 12525,0
     2404ps "OnEdgeStrategy"
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     2407ro 90
     2408va (VaSet
     2409vasetType 1
     2410fg "0,65535,0"
     2411)
     2412xt "80000,141625,80750,142375"
     2413)
     2414tg (CPTG
     2415uid 12527,0
     2416ps "CptPortTextPlaceStrategy"
     2417stg "RightVerticalLayoutStrategy"
     2418f (Text
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     2420va (VaSet
     2421)
     2422xt "76600,141500,79000,142500"
     2423st "green"
     2424ju 2
     2425blo "79000,142300"
     2426)
     2427)
     2428thePort (LogicalPort
     2429m 1
     2430decl (Decl
     2431n "green"
     2432t "std_logic"
     2433o 35
     2434suid 86,0
     2435)
     2436)
     2437)
     2438*62 (CptPort
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     2440ps "OnEdgeStrategy"
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     2442uid 12530,0
     2443ro 90
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     2445vasetType 1
     2446fg "0,65535,0"
     2447)
     2448xt "80000,142625,80750,143375"
     2449)
     2450tg (CPTG
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     2452ps "CptPortTextPlaceStrategy"
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     2454f (Text
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     2456va (VaSet
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     2459st "red"
     2460ju 2
     2461blo "79000,143300"
     2462)
     2463)
     2464thePort (LogicalPort
     2465m 1
     2466decl (Decl
     2467n "red"
     2468t "std_logic"
     2469o 40
     2470suid 88,0
     2471)
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     2473)
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    23732481lineWidth 2
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     2483xt "52000,66000,80000,144000"
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    23772485oxt "15000,-1000,43000,27000"
     
    23812489stg "VerticalLayoutStrategy"
    23822490textVec [
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     2501*64 (Text
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    23952503va (VaSet
     
    24012509tm "CptNameMgr"
    24022510)
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    24052513va (VaSet
     
    24432551fg "49152,49152,49152"
    24442552)
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     2553xt "52250,142250,53750,143750"
    24462554iconName "BlockDiagram.png"
    24472555iconMaskName "BlockDiagram.msk"
     
    24532561archFileType "UNKNOWN"
    24542562)
    2455 *63 (PortIoIn
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    24562564uid 231,0
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    25972705textVec [
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    26332741)
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    2655 *70 (Net
     2758xt "39000,62400,67500,63200"
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    26562763uid 283,0
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    26672774font "Courier New,8,0"
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    2674 *71 (PortIoOut
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    5091 -- LEDs are low active
    5092 LED(0) <= '1';
    5093 LED(1) <= '0'; -- on
    5094 LED(2) <= '1';
    5095                              
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