Changeset 10081 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

Timestamp:

01/05/11 17:19:13 (14 years ago)

Author:

neise

Message:

DRS write shift register & write config register

File:

• firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak (modified) (8 diffs)

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

@@ -67 +67 @@
 
       drs_read_s_cell_ready : in std_logic;
-      drs_s_cell_array : in drs_s_cell_array_type
+      drs_s_cell_array : in drs_s_cell_array_type;
+      
+      drs_readout_started : out std_logic
       );
 end data_generator ;
@@ -73 +75 @@
 architecture Behavioral of data_generator is
 
-type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
+type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
                              WRITE_END_FLAG, WRITE_DATA_STOP,
@@ -93 +95 @@
 signal roi_max_int : roi_max_type;
 
+signal sig_drs_readout_started : std_logic := '0';
+
 begin
   
+  drs_readout_started <= sig_drs_readout_started;
   
         generate_data : process (clk)
@@ -142 +147 @@
         when CONFIG4 =>
           drs_channel_id <= DRS_WRITE_SHIFT_REG;
-          drs_srin_data <= "10101010";
+          drs_srin_data <= "11111111";
           drs_srin_write_8b <= '1';
           if (drs_srin_write_ack = '1') then
@@ -151 +156 @@
           if (drs_srin_write_ready = '1') then
             roi_max_int <= roi_max;
-            state_generate <= WRITE_DATA_IDLE;
-          end if;
+            state_generate <= CONFIG6;
+          end if;
+          when CONFIG6 =>
+            drs_channel_id <= DRS_WRITE_CONFIG_REG;
+            drs_srin_data <= "11111111";
+            drs_srin_write_8b <= '1';
+            if (drs_srin_write_ack = '1') then
+              drs_srin_write_8b <= '0';
+              state_generate <= CONFIG7;
+            end if;
+          when CONFIG7 =>
+            if (drs_srin_write_ready = '1') then
+              roi_max_int <= roi_max;
+              state_generate <= WRITE_DATA_IDLE;
+            end if;
         -- end configure DRS
 
@@ -161 +179 @@
 --          if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then
           if (ram_write_ea = '1' and trigger_flag = '1') then
+            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
             -- stop drs, dwrite low
             drs_dwrite <= '0';
@@ -193 +212 @@
 
         when WRITE_DAC1 =>
+          sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE
           data_out <= conv_std_logic_vector (dac_array (3), 16)
                     & conv_std_logic_vector (dac_array (2), 16)
@@ -252 +272 @@
         when WRITE_ADC_DATA =>
           if (data_cntr < roi_max (channel_id)) then
-            data_out <= "000" & adc_otr(3) & adc_data_array(3)
-                      & "000" & adc_otr(2) & adc_data_array(2)
-                      & "000" & adc_otr(1) & adc_data_array(1)
-                      & "000" & adc_otr(0) & adc_data_array(0);
---              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
---                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
---                          & "00100" & conv_std_logic_vector (data_cntr, 11) 
---                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
+--            data_out <= "000" & adc_otr(3) & adc_data_array(3)
+--                      & "000" & adc_otr(2) & adc_data_array(2)
+--                      & "000" & adc_otr(1) & adc_data_array(1)
+--                      & "000" & adc_otr(0) & adc_data_array(0);
+              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
+                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
+                          & "00100" & conv_std_logic_vector (data_cntr, 11) 
+                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
             addr_cntr <= addr_cntr + 1;
             state_generate <= WRITE_ADC_DATA;