Index: firmware/FTM/test_firmware/FTM_test9/FTM_test9.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test9/FTM_test9.vhd (revision 10104) +++ firmware/FTM/test_firmware/FTM_test9/FTM_test9.vhd (revision 10104) @@ -0,0 +1,501 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 13 January 2011 +-- Design Name: +-- Module Name: FTM_test9 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Test firmware for FTM board: try to contact FTU via RS485 +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FTM_test9 is + port( + +-- Clock + clk : IN STD_LOGIC; -- external clock from + -- oscillator U47 +-- connection to the WIZnet W5300 ethernet controller +-- on IO-Bank 1 +------------------------------------------------------------------------------- + -- W5300 data bus +-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 + + + -- W5300 address bus +-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + -- the W5300 is operated in the + -- 16-bit mode + + -- W5300 controll signals + -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 + -- W_CS is also routed to testpoint JP7 +-- W_CS : out STD_LOGIC; -- W5300 chip select +-- W_INT : IN STD_LOGIC; -- interrupt +-- W_RD : out STD_LOGIC; -- read +-- W_WR : out STD_LOGIC; -- write +-- W_RES : out STD_LOGIC -- reset W5300 chip + + -- W5300 buffer ready indicator +-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + + -- testpoints (T18) associated with the W5300 on IO-bank 1 +-- W_T : inout STD_LOGIC_VECTOR(3 downto 0); + + + +-- SPI Interface +-- connection to the EEPROM U36 (AL25L016M) and +-- temperature sensors U45, U46, U48 and U49 (all MAX6662) +-- on IO-Bank 1 +------------------------------------------------------------------------------- +-- S_CLK : out STD_LOGIC; -- SPI clock + + -- EEPROM +-- MOSI : out STD_LOGIC; -- master out slave in +-- MISO : in STD_LOGIC; -- master in slave out +-- EE_CS : out STD_LOGIC; -- EEPROM chip select + + -- temperature sensors U45, U46, U48 and U49 +-- SIO : inout STD_LOGIC; -- serial IO +-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + + + +-- Trigger primitives inputs +-- on IO-Bank 2 +------------------------------------------------------------------------------- +-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 +-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 +-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 +-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + + + +-- NIM inputs +------------------------------------------------------------------------------ + -- on IO-Bank 3 +-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input +-- Veto : in STD_LOGIC; -- trigger veto input +-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + + -- on IO-Bank 0 +-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + + + +-- LEDs on IO-Banks 0 and 3 +------------------------------------------------------------------------------- + LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red + LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow + LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green + +-- Clock conditioner LMK03000 +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock +-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable +-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + +-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization +-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + +-- various RS-485 Interfaces +-- on IO-Bank 3 +------------------------------------------------------------------------------- + -- Bus 1: FTU slow control + Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable + Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable + + Bus1_RxD_0 : in STD_LOGIC; -- crate 0 + Bus1_TxD_0 : out STD_LOGIC + +-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus1_TxD_1 : out STD_LOGIC; + +-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus1_TxD_2 : out STD_LOGIC; + +-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus1_TxD_3 : out STD_LOGIC; + + + -- Bus 2: Trigger-ID to FAD boards +-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable +-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + +-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 +-- Bus2_TxD_0 : out STD_LOGIC; + +-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 +-- Bus2_TxD_1 : out STD_LOGIC; + +-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 +-- Bus2_TxD_2 : out STD_LOGIC; + +-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 +-- Bus2_TxD_3 : out STD_LOGIC; + + +-- auxiliary access +-- Aux_Rx_D : in STD_LOGIC; -- +-- Aux_Tx_D : out STD_LOGIC; -- +-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable +-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID + + +-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +-- TrID_Rx_D : in STD_LOGIC; -- +-- TrID_Tx_D : out STD_LOGIC -- + + +-- Crate-Resets +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Crate_Res0 : out STD_LOGIC; -- +-- Crate_Res1 : out STD_LOGIC; -- +-- Crate_Res2 : out STD_LOGIC; -- +-- Crate_Res3 : out STD_LOGIC; -- + + +-- Busy signals from the FAD boards +-- on IO-Bank 3 +------------------------------------------------------------------------------- +-- Busy0 : in STD_LOGIC; -- +-- Busy1 : in STD_LOGIC; -- +-- Busy2 : in STD_LOGIC; -- +-- Busy3 : in STD_LOGIC; -- + + + +-- NIM outputs +-- on IO-Bank 0 +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +------------------------------------------------------------------------------- +-- calibration +-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ +-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- +-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ +-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- + +-- auxiliarry / spare NIM outputs +-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ +-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- +-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ +-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- + + + +-- fast control signal outputs +-- LVDS output at the FPGA followed by LVDS to NIM conversion stage +-- conversion stage +------------------------------------------------------------------------------- +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 +-- TIM_Sel : out STD_LOGIC -- Time Marker selector on + -- IO-Bank 2 + +-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA + + + +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- to connector J13 +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; + +-- to connector J12 +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC; + + +-- Testpoints +------------------------------------------------------------------------------- +-- TP : inout STD_LOGIC_VECTOR(32 downto 0) +-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only + +-- Board ID - inputs +-- local board-ID "solder programmable" +-- all on 'input only' pins +------------------------------------------------------------------------------- +-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only + ); +end FTM_test9; + +architecture Behavioral of FTM_test9 is + + COMPONENT FTM_test9_dcm + PORT( + CLKIN_IN : IN std_logic; + RST_IN : IN std_logic; + CLKFX_OUT : OUT std_logic; + CLK0_OUT : OUT std_logic; + LOCKED_OUT : OUT std_logic + ); + END COMPONENT; + + component FTM_test9_rs485_interface + GENERIC( + CLOCK_FREQUENCY : integer; -- Hertz + BAUD_RATE : integer -- bits / sec + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector(7 DOWNTO 0); + -- rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector(7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + end component; + + signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up + signal clk_50M_sig : STD_LOGIC; + + signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '1'); + signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0) := (others => '1'); + signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0) := (others => '1'); + + signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + -- signal rx_busy_sig : STD_LOGIC; + signal rx_valid_sig : STD_LOGIC; + + signal txcnt : integer range 0 to 28 := 0; -- count 28 1-byte frames + + signal tx_start_sig : std_logic := '0'; + signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); + signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface + + + type FTM_test9_StateType is (INIT, SEND, WAIT_FOR_ANSWER, FINISHED); + signal FTM_test9_State : FTM_test9_StateType; + +begin + + Inst_FTM_test9_dcm: FTM_test9_dcm PORT MAP( + CLKIN_IN => clk, + RST_IN => reset_sig, + CLKFX_OUT => clk_50M_sig, + CLK0_OUT => open, + LOCKED_OUT => open + ); + + Inst_FTM_test9_rs485_interface : FTM_test9_rs485_interface + generic map( + CLOCK_FREQUENCY => 50000000, + BAUD_RATE => 250000 + ) + port map( + clk => clk_50M_sig, + -- RS485 + rx_d => Bus1_RxD_0, + rx_en => Bus1_Rx_En, + tx_d => Bus1_TxD_0, + tx_en => Bus1_Tx_En, + -- FPGA + rx_data => rx_data_sig, + -- rx_busy => rx_busy_sig, + rx_valid => rx_valid_sig, + tx_data => tx_data_sig, + tx_busy => tx_busy_sig, + tx_start => tx_start_sig + ); + + --FTM test9 state machine + + FTM_test9_FSM: process (clk_50M_sig) + begin + if Rising_edge(clk_50M_sig) then + case FTM_test9_State is + + when INIT => + LED_red_sig(0) <= '0'; + LED_ye_sig(0) <= '1'; + LED_gn_sig(0) <= '1'; + FTM_test9_State <= SEND; + + when SEND => + LED_red_sig(0) <= '0'; + LED_ye_sig(0) <= '1'; + LED_gn_sig(0) <= '1'; + if tx_busy_sig = '0' then + if txcnt = 0 then -- start delimiter + txcnt <= txcnt + 1; + tx_data_sig <= "01000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 1 then -- FTU address + txcnt <= txcnt + 1; + tx_data_sig <= "00111111"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 2 then -- FTM address + txcnt <= txcnt + 1; + tx_data_sig <= "11000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 3 then -- firmware ID + txcnt <= txcnt + 1; + tx_data_sig <= "00000001"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 4 then -- command + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 5 then -- data: DAC A low + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 6 then -- data: DAC A high + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 7 then -- data: DAC B low + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 8 then -- data: DAC B high + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 9 then -- data: DAC C low + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 10 then -- data: DAC C high + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 11 then -- data: DAC D low + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 12 then -- data: DAC D high + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 13 then -- data: DAC E low + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = 14 then -- data: DAC E high + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt < (28 - 2) then -- data: not used + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = (28 - 2) then -- CRC error counter + txcnt <= txcnt + 1; + tx_data_sig <= "00000000"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + elsif txcnt = (28 - 1) then -- check sum + txcnt <= txcnt + 1; + tx_data_sig <= "00011101"; + tx_start_sig <= '1'; + FTM_test9_State <= SEND; + else -- transmission finished + txcnt <= 0; + LED_red_sig(0) <= '1'; + LED_ye_sig(0) <= '0'; + LED_gn_sig(0) <= '1'; + FTM_test9_State <= WAIT_FOR_ANSWER; + end if; + else + tx_start_sig <= '0'; + FTM_test9_State <= SEND; + end if; + + when WAIT_FOR_ANSWER => + LED_red_sig(0) <= '1'; + LED_ye_sig(0) <= '0'; + LED_gn_sig(0) <= '1'; + if rx_valid_sig = '1' then + LED_red_sig(0) <= '1'; + LED_ye_sig(0) <= '1'; + LED_gn_sig(0) <= '0'; + FTM_test9_State <= FINISHED; + else + FTM_test9_State <= WAIT_FOR_ANSWER; + end if; + + when FINISHED => + LED_red_sig(0) <= '1'; + LED_ye_sig(0) <= '1'; + LED_gn_sig(0) <= '0'; + + end case; + end if; + end process FTM_test9_FSM; + + LED_red <= LED_red_sig; + LED_ye <= LED_ye_sig; + LED_gn <= LED_gn_sig; + + LED_red_sig(3 downto 1) <= "111"; + LED_ye_sig(1) <= '1'; + LED_gn_sig(1) <= '1'; + +end Behavioral; Index: firmware/FTM/test_firmware/FTM_test9/FTM_test9_dcm.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test9/FTM_test9_dcm.vhd (revision 10104) +++ firmware/FTM/test_firmware/FTM_test9/FTM_test9_dcm.vhd (revision 10104) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_test9_dcm.vhd +-- /___/ /\ Timestamp : 01/13/2011 (copy from FTM_Test8_dcm) +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test8/FTM_Test8/ipcore_dir/FTM_Test8_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test8/FTM_Test8/ipcore_dir/FTM_Test8_dcm +--Design Name: FTM_Test8_dcm +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_test9_dcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_test9_dcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_test9_dcm; + +architecture BEHAVIORAL of FTM_test9_dcm is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; Index: firmware/FTM/test_firmware/FTM_test9/FTM_test9_rs485_interface.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test9/FTM_test9_rs485_interface.vhd (revision 10104) +++ firmware/FTM/test_firmware/FTM_test9/FTM_test9_rs485_interface.vhd (revision 10104) @@ -0,0 +1,126 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified for FTU design by Q. Weitzel, 30 July 2010 +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +-- library ftu_definitions; +-- USE ftu_definitions.ftu_array_types.all; +-- USE ftu_definitions.ftu_constants.all; + +ENTITY FTM_test9_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := 50000000; + BAUD_RATE : integer := 250000 + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + --rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +END FTM_test9_rs485_interface; + +ARCHITECTURE beha OF FTM_test9_rs485_interface IS + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + --transmit + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bits + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + --receive + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + --rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; Index: firmware/FTM/test_firmware/FTM_test9/FTM_test9_tb.vhd =================================================================== --- firmware/FTM/test_firmware/FTM_test9/FTM_test9_tb.vhd (revision 10104) +++ firmware/FTM/test_firmware/FTM_test9/FTM_test9_tb.vhd (revision 10104) @@ -0,0 +1,138 @@ +-------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel, P. Vogler +-- +-- Create Date: 13.01.2011 +-- Design Name: +-- Module Name: FTM_test9_tb.vhd +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: Testbench for FTM - FTU RS485 test +-- +-- VHDL Test Bench Created by ISE for module: FTM_test9 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity FTU_test9_tb is +end FTU_test9_tb; + +architecture behavior of FTU_test9_tb is + + -- Component Declaration for the Unit Under Test (UUT) + + component FTM_test9 + port( + clk : in STD_LOGIC; + LED_red : out STD_LOGIC_VECTOR(3 downto 0); + LED_ye : out STD_LOGIC_VECTOR(1 downto 0); + LED_gn : out STD_LOGIC_VECTOR(1 downto 0); + Bus1_Tx_En : out STD_LOGIC; + Bus1_Rx_En : out STD_LOGIC; + Bus1_RxD_0 : in STD_LOGIC; + Bus1_TxD_0 : out STD_LOGIC + ); + end component; + + --Inputs + signal clk_sig : STD_LOGIC := '0'; + signal Bus1_RxD_0_sig : STD_LOGIC := '1'; + + --Outputs + signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0); + signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0); + signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0); + signal Bus1_Tx_En_sig : STD_LOGIC; + signal Bus1_Rx_En_sig : STD_LOGIC; + signal Bus1_TxD_0_sig : STD_LOGIC; + + -- Clock period definitions + constant clk_period : TIME := 25 ns; + constant baud_rate_period : TIME := 4 us; + +begin + + -- Instantiate the Unit Under Test (UUT) + uut: FTM_test9 + port map( + clk => clk_sig, + LED_red => LED_red_sig, + LED_ye => LED_ye_sig, + LED_gn => LED_gn_sig, + Bus1_Tx_En => Bus1_Tx_En_sig, + Bus1_Rx_En => Bus1_Rx_En_sig, + Bus1_RxD_0 => Bus1_RxD_0_sig, + Bus1_TxD_0 => Bus1_TxD_0_sig + ); + + -- Stimulus process for clock + clk_proc: process + begin + clk_sig <= '0'; + wait for clk_period/2; + clk_sig <= '1'; + wait for clk_period/2; + end process clk_proc; + + -- Stimulus process for RS485 + rs485_proc: process + + procedure assign_rs485 (data: std_logic_vector(7 downto 0)) is + begin + Bus1_RxD_0_sig <= '0'; --start bit + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(0); --bit 0 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(1); --bit 1 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(2); --bit 2 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(3); --bit 3 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(4); --bit 4 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(5); --bit 5 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(6); --bit 6 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(7); --bit 7 + wait for baud_rate_period; + Bus1_RxD_0_sig <= '1'; --stop bit + wait for baud_rate_period; + Bus1_RxD_0_sig <= '1'; --stop bit + wait for baud_rate_period; + end assign_rs485; + + begin + wait for 1500us; + --------------------------------------------------------------------------- + -- send a '@' character + --------------------------------------------------------------------------- + assign_rs485("01000000"); + --------------------------------------------------------------------------- + -- don't forget final wait! + --------------------------------------------------------------------------- + wait; + + end process rs485_proc; + +end; Index: firmware/FTM/test_firmware/FTM_test9/ftm_board_test9.ucf =================================================================== --- firmware/FTM/test_firmware/FTM_test9/ftm_board_test9.ucf (revision 10104) +++ firmware/FTM/test_firmware/FTM_test9/ftm_board_test9.ucf (revision 10104) @@ -0,0 +1,407 @@ +######################################################## +# FTM Board +# FACT Trigger Master +# +# Pin location constraints +# +# by Patrick Vogler +# 18 October 2010 +# +# Pin location for FTM test 7 : RS-485 Transmitter +######################################################## + + +#Clock +####################################################### + NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47 + + +# Ethernet Interface +# connection to the WIZnet W5300 ethernet controller (U37) +# on IO-Bank 1 +####################################################### +# data bus +# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300 +# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; # +# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; # +# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; # +# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; # +# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; # +# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; # +# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; # +# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; # +# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; # +# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; # +# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; # +# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; # +# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; # +# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; # +# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; # + +# W5300 address bus +# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because +# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # +# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # +# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; # +# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; # +# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; # +# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; # + +# W5300 controll signals +# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 +# W_CS is also routed to testpoint JP7 +# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select +# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt +# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read +# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write +# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip + +# W5300 buffer ready indicator +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # + +# W5300 associated testpoints +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # + + +# SPI Interface +# connection to the EEPROM U36 (AL25L016M) and the temperature +# sensors U45, U46, U48 and U49 (all MAX6662) +# on IO-Bank 1 +####################################################### +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock + +# EEPROM +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in + +# temperature sensors +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 + + +# Trigger primitives inputs +# on IO-Bank 2 +####################################################### +# crate 0 +# crate A +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> + +# crate 1 +# crate B +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> + +# crate 2 +# crate C +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> + +# crate 3 +# crate D +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> + + +# NIM inputs +####################################################### +# on IO-Bank 3 +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # + +# on IO-Bank 0 +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer + # available + + +# LEDs +# on IO-Banks 0 and 3 +####################################################### +# red + NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + +# yellow + NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + +# green + NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0 + + +# Clock conditioner LMK03000 +# on IO-Bank 3 +####################################################### +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 + + +# various RS-485 Interfaces +# on IO-Bank 3 +####################################################### +# Bus 1: FTU slow control + NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 + NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Bus 2: Trigger-ID to FAD boards +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 0 +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 1 +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 2 +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + +# crate 3 +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# auxiliary access +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary + # Trigger-ID + +# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Crate-Resets +# on IO-Bank 3 +####################################################### +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# Busy signals from the FAD boards +# on IO-Bank 3 +####################################################### +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # + + +# NIM outputs +# on IO-Bank 0 +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# calibration +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2- + +# auxiliarry / spare NIM outputs +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1- + + +# fast control signal outputs +# LVDS output at the FPGA followed by LVDS to NIM +# conversion stage +####################################################### +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33; # TIM_Run- + # on IO-Bank2 +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # Time Marker selector + # IO-Bank 2 +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA + + +# LVDS calibration outputs +# on IO-Bank 0 +####################################################### +# to connector J13 +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- + +# to connector J12 +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- + + +# Testpoints +###################################################### +# Connector T7 +# IO-Bank 0 +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # + +# Connector T10 +# IO-Bank 0 +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # + +# on Connector T12 +# IO-Bank 0 +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # + +# on Connector T14 +# IO-Bank 0 +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # + +# on Connector T16 +# IO-Bank 0 +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # + +# on Connector T8 +# IO-Bank 0 +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # + +# on Connector T9 +# IO-Bank 0 +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # + +# on Connector T11 +# IO-Bank 3 +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # + +# on Connector T13 +# IO-Bank 3 +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # + +# on Connector T15 +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only + + +# Board ID - inputs +# local board-ID "solder programmable" +# all on 'input only' pins +####################################################### +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # +