Changeset 10121


Ignore:
Timestamp:
01/27/11 08:32:16 (14 years ago)
Author:
neise
Message:
synchronous trigger handling added
continous soft trigger generation.
---> control frequency via 'send 0x21??'
each step increases trigger delay by 12.5ms
0x2100 = 40Hz
0x21FF = 0.3Hz
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS
Files:
1 added
39 edited

Legend:

Unmodified
Added
Removed

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

    r9912 r10121  
    44FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
    55FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
    6 secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
    7 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
    8 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
    9 unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
    10 XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
     6secureip = D:\unisim/secureip
     7simprim = D:\unisim/simprim
     8unimacro = D:\unisim/unimacro
     9unisim = D:\unisim/unisim
     10XilinxCoreLib = D:\unisim/xilinxcorelib
    1111[QuestaSim]
    12 secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
    13 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
    14 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
    15 unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
    16 XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
     12secureip = D:\unisim/secureip
     13simprim = D:\unisim/simprim
     14unimacro = D:\unisim/unimacro
     15unisim = D:\unisim/unisim
     16XilinxCoreLib = D:\unisim/xilinxcorelib
    1717[XilinxISE]
    1818FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10074 r10121  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 12:35:56 04.01.2011
     5--          at - 11:57:15 26.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    2424      PSCLK_OUT       : OUT    std_logic;
    2525      PSDONE_extraOUT : OUT    std_logic;
    26       PSEN_OUT        : OUT    std_logic;
    2726      PSINCDEC_OUT    : OUT    std_logic;
    2827      offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    … …  
    4140-- Created:
    4241--          by - dneise.UNKNOWN (E5B-LABOR6)
    43 --          at - 12:35:56 04.01.2011
     42--          at - 11:57:15 26.01.2011
    4443--
    4544-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    5049USE ieee.numeric_std.all;
    5150LIBRARY UNISIM;
    52 USE UNISIM.Vcomponents.all;
     51--USE UNISIM.Vcomponents.all;
    5352
    5453LIBRARY FACT_FAD_lib;
    … …  
    131130   PSCLK_OUT <= PSCLK_IN;
    132131
    133    -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
    134    PSEN_OUT <= PSEN_IN;
    135 
    136132   -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
    137133   PSINCDEC_OUT <= PSINCDEC_IN;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd

    r10073 r10121  
    22--
    33-- Created:
    4 --          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:00:23 03.01.2011
     4--          by - daqct3.UNKNOWN (IHP110)
     5--          at - 12:52:19 06.01.2011
    66--
    7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    88--
    99LIBRARY ieee;
    … …  
    4141--
    4242-- Created:
    43 --          by - dneise.UNKNOWN (E5B-LABOR6)
    44 --          at - 17:00:23 03.01.2011
     43--          by - daqct3.UNKNOWN (IHP110)
     44--          at - 12:52:20 06.01.2011
    4545--
    46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     46-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    4747--
    4848LIBRARY ieee;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10081 r10121  
    5858      adc_otr : in std_logic_vector (3 downto 0);
    5959      drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
    60       drs_dwrite : out std_logic := '1';
     60      -- --
     61--      drs_dwrite : out std_logic := '1';
     62      drs_readout_ready : out std_logic := '0';
     63      drs_readout_ready_ack : in std_logic;
     64      -- --
    6165      drs_clk_en, drs_read_s_cell : out std_logic := '0';
    6266
    … …  
    6973      drs_s_cell_array : in drs_s_cell_array_type;
    7074     
    71       drs_readout_started : out std_logic
     75      drs_readout_started : out std_logic := '0'
    7276      );
    7377end data_generator ;
    … …  
    7781type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    7882                             WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    79                              WRITE_END_FLAG, WRITE_DATA_STOP,
     83                             WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1,
    8084                             WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
    8185
    … …  
    181185            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
    182186            -- stop drs, dwrite low
    183             drs_dwrite <= '0';
     187            -- drs_dwrite <= '0';
    184188            -- start reading of drs stop cell
    185189            drs_read_s_cell <= '1';
    … …  
    329333                  if (ram_write_ready_ack = '0') then
    330334                  -- --
    331             drs_dwrite <= '1';
     335--            drs_dwrite <= '1';
     336            drs_readout_ready <= '1';
    332337                                          data_cntr <= 0;
    333338                                          addr_cntr <= 0;
    334339                                          channel_id <= 0;
    335                                           state_generate <= WRITE_DATA_IDLE;
     340                                          state_generate <= WRITE_DATA_STOP1;
    336341                                        -- --
    337342                                        end if;
    338343                                  -- --
     344                                when WRITE_DATA_STOP1 =>
     345                                  if (drs_readout_ready_ack = '1') then
     346                                    drs_readout_ready <= '0';
     347                                    state_generate <= WRITE_DATA_IDLE;
     348                                  end if;
    339349                                when others =>
    340350                                        null;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

    r10081 r10121  
    5858      adc_otr : in std_logic_vector (3 downto 0);
    5959      drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
    60       drs_dwrite : out std_logic := '1';
     60      -- --
     61--      drs_dwrite : out std_logic := '1';
     62      drs_readout_ready : out std_logic := '0';
     63      -- --
    6164      drs_clk_en, drs_read_s_cell : out std_logic := '0';
    6265
    … …  
    6972      drs_s_cell_array : in drs_s_cell_array_type;
    7073     
    71       drs_readout_started : out std_logic
     74      drs_readout_started : out std_logic := '0'
    7275      );
    7376end data_generator ;
    … …  
    7780type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
    7881                             WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
    79                              WRITE_END_FLAG, WRITE_DATA_STOP,
     82                             WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1,
    8083                             WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
    8184
    … …  
    181184            sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
    182185            -- stop drs, dwrite low
    183             drs_dwrite <= '0';
     186            -- drs_dwrite <= '0';
    184187            -- start reading of drs stop cell
    185188            drs_read_s_cell <= '1';
    … …  
    272275        when WRITE_ADC_DATA =>
    273276          if (data_cntr < roi_max (channel_id)) then
    274 --            data_out <= "000" & adc_otr(3) & adc_data_array(3)
    275 --                      & "000" & adc_otr(2) & adc_data_array(2)
    276 --                      & "000" & adc_otr(1) & adc_data_array(1)
    277 --                      & "000" & adc_otr(0) & adc_data_array(0);
    278               data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
    279                           & "00010" & conv_std_logic_vector (data_cntr, 11)
    280                           & "00100" & conv_std_logic_vector (data_cntr, 11)
    281                           & "00110" & conv_std_logic_vector (data_cntr, 11) ;
     277            data_out <= "000" & adc_otr(3) & adc_data_array(3)
     278                      & "000" & adc_otr(2) & adc_data_array(2)
     279                      & "000" & adc_otr(1) & adc_data_array(1)
     280                      & "000" & adc_otr(0) & adc_data_array(0);
     281 --             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11)
     282--                          & "00010" & conv_std_logic_vector (data_cntr, 11)
     283--                          & "00100" & conv_std_logic_vector (data_cntr, 11)
     284--                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
    282285            addr_cntr <= addr_cntr + 1;
    283286            state_generate <= WRITE_ADC_DATA;
    … …  
    329332                  if (ram_write_ready_ack = '0') then
    330333                  -- --
    331             drs_dwrite <= '1';
     334--            drs_dwrite <= '1';
     335            drs_readout_ready <= '1';
    332336                                          data_cntr <= 0;
    333337                                          addr_cntr <= 0;
    334338                                          channel_id <= 0;
    335                                           state_generate <= WRITE_DATA_IDLE;
     339                                          state_generate <= WRITE_DATA_STOP1;
    336340                                        -- --
    337341                                        end if;
    338342                                  -- --
     343                                when WRITE_DATA_STOP1 =>
     344                                  if (drs_readout_ready_ack = '1') then
     345                                    drs_readout_ready <= '0';
     346                                    state_generate <= WRITE_DATA_IDLE;
     347                                  end if;
    339348                                when others =>
    340349                                        null;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf

    r10074 r10121  
    3535
    3636# BOARD ID  - inputs
    37 #NET LINE<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;           #ok
    38 #NET LINE<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;           #ok
    39 #NET LINE<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;          #ok
    40 #NET LINE<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;          #ok
    41 #NET LINE<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;          #ok
    42 #NET LINE<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;          #ok
     37NET POSITION_ID<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;             #ok  name was LINE befoer i changed it
     38NET POSITION_ID<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;             #ok
     39NET POSITION_ID<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;            #ok
     40NET POSITION_ID<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;            #ok
     41NET POSITION_ID<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;            #ok
     42NET POSITION_ID<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;            #ok
    4343
    4444# W5300
    … …  
    9999
    100100NET SRIN LOC  = E1 | IOSTANDARD=LVCMOS25;                       #ok -- nur fuer vollauslese noetig; auf Z legen.
    101 #NET REFCLK LOC  = AC11 | IOSTANDARD=LVCMOS25;          #ok -- listen to REFCLK possible
     101NET REFCLK LOC  = AC11 | IOSTANDARD=LVCMOS25;           #ok -- listen to REFCLK possible
    102102
    103103

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak

    r10074 r10121  
    3535
    3636# BOARD ID  - inputs
    37 #NET LINE<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;           #ok
    38 #NET LINE<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;           #ok
    39 #NET LINE<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;          #ok
    40 #NET LINE<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;          #ok
    41 #NET LINE<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;          #ok
    42 #NET LINE<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;          #ok
     37NET POSITION_ID<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;             #ok  name was LINE befoer i changed it
     38NET POSITION_ID<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;             #ok
     39NET POSITION_ID<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;            #ok
     40NET POSITION_ID<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;            #ok
     41NET POSITION_ID<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;            #ok
     42NET POSITION_ID<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;            #ok
    4343
    4444# W5300
    … …  
    254254#######################################################
    255255NET AMBER_LED LOC  = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2;              #schematic: LED_3 D3 AMBER
    256 NET GREEN_LED LOC  = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 1; #schematic: LED_0 D1 GREEN
     256NET GREEN_LED LOC  = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; #schematic: LED_0 D1 GREEN
    257257NET RED_LED LOC  = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2  RED
    258258

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10081 r10121  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:46:34 05.01.2011
     5--          at - 16:46:19 26.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    1313ENTITY FAD_Board IS
    1414   PORT(
    15       A0_D       : IN     std_logic_vector (11 DOWNTO 0);
    16       A1_D       : IN     std_logic_vector (11 DOWNTO 0);
    17       A2_D       : IN     std_logic_vector (11 DOWNTO 0);
    18       A3_D       : IN     std_logic_vector (11 DOWNTO 0);
    19       A_OTR      : IN     std_logic_vector (3 DOWNTO 0);
    20       D0_SROUT   : IN     std_logic;
    21       D1_SROUT   : IN     std_logic;
    22       D2_SROUT   : IN     std_logic;
    23       D3_SROUT   : IN     std_logic;
    24       D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0);
    25       RS485_C_DI : IN     std_logic;
    26       RS485_E_DI : IN     std_logic;
    27       RS485_E_DO : IN     std_logic;
    28       TRG        : IN     STD_LOGIC;
    29       W_INT      : IN     std_logic;
    30       X_50M      : IN     STD_LOGIC;
    31       A0_T       : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
    32       A1_T       : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    33       AMBER_LED  : OUT    std_logic;
    34       A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
    35       D0_SRCLK   : OUT    STD_LOGIC;
    36       D1_SRCLK   : OUT    STD_LOGIC;
    37       D2_SRCLK   : OUT    STD_LOGIC;
    38       D3_SRCLK   : OUT    STD_LOGIC;
    39       DAC_CS     : OUT    std_logic;
    40       DENABLE    : OUT    std_logic                     := '0';
    41       DWRITE     : OUT    std_logic                     := '0';
    42       D_A        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    43       D_T        : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    44       D_T2       : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    45       EE_CS      : OUT    std_logic;
    46       GREEN_LED  : OUT    std_logic;
    47       MOSI       : OUT    std_logic                     := '0';
    48       OE_ADC     : OUT    STD_LOGIC;
    49       RED_LED    : OUT    std_logic;
    50       RS485_C_DE : OUT    std_logic;
    51       RS485_C_DO : OUT    std_logic;
    52       RS485_C_RE : OUT    std_logic;
    53       RS485_E_DE : OUT    std_logic;
    54       RS485_E_RE : OUT    std_logic;
    55       RSRLOAD    : OUT    std_logic                     := '0';
    56       SRIN       : OUT    std_logic                     := '0';
    57       S_CLK      : OUT    std_logic;
    58       T0_CS      : OUT    std_logic;
    59       T1_CS      : OUT    std_logic;
    60       T2_CS      : OUT    std_logic;
    61       T3_CS      : OUT    std_logic;
    62       TRG_V      : OUT    std_logic;
    63       W_A        : OUT    std_logic_vector (9 DOWNTO 0);
    64       W_CS       : OUT    std_logic                     := '1';
    65       W_RD       : OUT    std_logic                     := '1';
    66       W_RES      : OUT    std_logic                     := '1';
    67       W_WR       : OUT    std_logic                     := '1';
    68       MISO       : INOUT  std_logic;
    69       W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
     15      A0_D        : IN     std_logic_vector (11 DOWNTO 0);
     16      A1_D        : IN     std_logic_vector (11 DOWNTO 0);
     17      A2_D        : IN     std_logic_vector (11 DOWNTO 0);
     18      A3_D        : IN     std_logic_vector (11 DOWNTO 0);
     19      A_OTR       : IN     std_logic_vector (3 DOWNTO 0);
     20      D0_SROUT    : IN     std_logic;
     21      D1_SROUT    : IN     std_logic;
     22      D2_SROUT    : IN     std_logic;
     23      D3_SROUT    : IN     std_logic;
     24      D_PLLLCK    : IN     std_logic_vector (3 DOWNTO 0);
     25      POSITION_ID : IN     std_logic_vector ( 5 DOWNTO 0 );
     26      REFCLK      : IN     std_logic;
     27      RS485_C_DI  : IN     std_logic;
     28      RS485_E_DI  : IN     std_logic;
     29      RS485_E_DO  : IN     std_logic;
     30      TRG         : IN     STD_LOGIC;
     31      W_INT       : IN     std_logic;
     32      X_50M       : IN     STD_LOGIC;
     33      A0_T        : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
     34      A1_T        : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     35      AMBER_LED   : OUT    std_logic;
     36      A_CLK       : OUT    std_logic_vector (3 DOWNTO 0);
     37      D0_SRCLK    : OUT    STD_LOGIC;
     38      D1_SRCLK    : OUT    STD_LOGIC;
     39      D2_SRCLK    : OUT    STD_LOGIC;
     40      D3_SRCLK    : OUT    STD_LOGIC;
     41      DAC_CS      : OUT    std_logic;
     42      DENABLE     : OUT    std_logic                     := '0';
     43      DWRITE      : OUT    std_logic                     := '0';
     44      D_A         : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     45      D_T         : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     46      D_T2        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     47      EE_CS       : OUT    std_logic;
     48      GREEN_LED   : OUT    std_logic;
     49      MOSI        : OUT    std_logic                     := '0';
     50      OE_ADC      : OUT    STD_LOGIC;
     51      RED_LED     : OUT    std_logic;
     52      RS485_C_DE  : OUT    std_logic;
     53      RS485_C_DO  : OUT    std_logic;
     54      RS485_C_RE  : OUT    std_logic;
     55      RS485_E_DE  : OUT    std_logic;
     56      RS485_E_RE  : OUT    std_logic;
     57      RSRLOAD     : OUT    std_logic                     := '0';
     58      SRIN        : OUT    std_logic                     := '0';
     59      S_CLK       : OUT    std_logic;
     60      T0_CS       : OUT    std_logic;
     61      T1_CS       : OUT    std_logic;
     62      T2_CS       : OUT    std_logic;
     63      T3_CS       : OUT    std_logic;
     64      TRG_V       : OUT    std_logic;
     65      W_A         : OUT    std_logic_vector (9 DOWNTO 0);
     66      W_CS        : OUT    std_logic                     := '1';
     67      W_RD        : OUT    std_logic                     := '1';
     68      W_RES       : OUT    std_logic                     := '1';
     69      W_WR        : OUT    std_logic                     := '1';
     70      MISO        : INOUT  std_logic;
     71      W_D         : INOUT  std_logic_vector (15 DOWNTO 0)
    7072   );
    7173
    … …  
    7981-- Created:
    8082--          by - dneise.UNKNOWN (E5B-LABOR6)
    81 --          at - 17:46:35 05.01.2011
     83--          at - 16:46:20 26.01.2011
    8284--
    8385-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    109111   SIGNAL PSCLK_OUT       : std_logic;
    110112   SIGNAL PSDONE_extraOUT : std_logic;
    111    SIGNAL PSEN_OUT        : std_logic;
    112113   SIGNAL PSINCDEC_OUT    : std_logic;
    113114   SIGNAL PS_DIR_IN       : std_logic;
    114    SIGNAL PS_DO_IN        : std_logic;
    115115   SIGNAL SRCLK           : std_logic                    := '0';
    116116   SIGNAL adc_clk_en      : std_logic                    := '0';
    … …  
    135135   );
    136136   PORT (
    137       CLK             : IN     std_logic ;
    138       SROUT_in_0      : IN     std_logic ;
    139       SROUT_in_1      : IN     std_logic ;
    140       SROUT_in_2      : IN     std_logic ;
    141       SROUT_in_3      : IN     std_logic ;
    142       adc_data_array  : IN     adc_data_array_type ;
    143       adc_otr_array   : IN     std_logic_vector (3 DOWNTO 0);
    144       board_id        : IN     std_logic_vector (3 DOWNTO 0);
    145       crate_id        : IN     std_logic_vector (1 DOWNTO 0);
    146       trigger         : IN     std_logic ;
    147       wiz_int         : IN     std_logic ;
    148       CLK25_OUT       : OUT    std_logic ;
    149       CLK25_PSOUT     : OUT    std_logic ;
    150       CLK50_OUT       : OUT    std_logic ;
    151       CLK_25_PS       : OUT    std_logic ;
    152       CLK_50          : OUT    std_logic ;
    153       DCM_locked      : OUT    std_logic ;
    154       LOCKED_extraOUT : OUT    std_logic ;
    155       PSCLK_OUT       : OUT    std_logic ;
    156       PSDONE_extraOUT : OUT    std_logic ;
    157       PSEN_OUT        : OUT    std_logic ;
    158       PSINCDEC_OUT    : OUT    std_logic ;
    159       PS_DIR_IN       : OUT    std_logic ;
    160       PS_DO_IN        : OUT    std_logic ;
    161       RSRLOAD         : OUT    std_logic                     := '0';
    162       SRCLK           : OUT    std_logic                     := '0';
    163       SRIN_out        : OUT    std_logic                     := '0';
    164       adc_clk_en      : OUT    std_logic                     := '0';
    165       adc_oeb         : OUT    std_logic                     := '1';
    166       amber           : OUT    std_logic ;
    167       dac_cs          : OUT    std_logic ;
    168       denable         : OUT    std_logic                     := '0';           -- default domino wave off
    169       drs_channel_id  : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    170       drs_dwrite      : OUT    std_logic                     := '1';
    171       green           : OUT    std_logic ;
    172       led             : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    173       mosi            : OUT    std_logic                     := '0';
    174       offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    175       ready           : OUT    std_logic                     := '0';
    176       red             : OUT    std_logic ;
    177       sclk            : OUT    std_logic ;
    178       sensor_cs       : OUT    std_logic_vector (3 DOWNTO 0);
     137      CLK                    : IN     std_logic ;
     138      SROUT_in_0             : IN     std_logic ;
     139      SROUT_in_1             : IN     std_logic ;
     140      SROUT_in_2             : IN     std_logic ;
     141      SROUT_in_3             : IN     std_logic ;
     142      adc_data_array         : IN     adc_data_array_type ;
     143      adc_otr_array          : IN     std_logic_vector (3 DOWNTO 0);
     144      board_id               : IN     std_logic_vector (3 DOWNTO 0);
     145      crate_id               : IN     std_logic_vector (1 DOWNTO 0);
     146      trigger                : IN     std_logic ;
     147      wiz_int                : IN     std_logic ;
     148      CLK25_OUT              : OUT    std_logic ;
     149      CLK25_PSOUT            : OUT    std_logic ;
     150      CLK50_OUT              : OUT    std_logic ;
     151      CLK_25_PS              : OUT    std_logic ;
     152      CLK_50                 : OUT    std_logic ;
     153      DCM_locked             : OUT    std_logic ;
     154      LOCKED_extraOUT        : OUT    std_logic ;
     155      PSCLK_OUT              : OUT    std_logic ;
     156      PSDONE_extraOUT        : OUT    std_logic ;
     157      PSINCDEC_OUT           : OUT    std_logic ;
     158      PS_DIR_IN              : OUT    std_logic ;
     159      RSRLOAD                : OUT    std_logic                     := '0';
     160      SRCLK                  : OUT    std_logic                     := '0';
     161      SRIN_out               : OUT    std_logic                     := '0';
     162      adc_clk_en             : OUT    std_logic                     := '0';
     163      adc_oeb                : OUT    std_logic                     := '1';
     164      additional_flasher_out : OUT    std_logic ;
     165      amber                  : OUT    std_logic ;
     166      dac_cs                 : OUT    std_logic ;
     167      denable                : OUT    std_logic                     := '0';           -- default domino wave off
     168      drs_channel_id         : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     169      drs_dwrite             : OUT    std_logic                     := '1';
     170      green                  : OUT    std_logic ;
     171      led                    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     172      mosi                   : OUT    std_logic                     := '0';
     173      offset                 : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     174      ready                  : OUT    std_logic                     := '0';
     175      red                    : OUT    std_logic ;
     176      sclk                   : OUT    std_logic ;
     177      sensor_cs              : OUT    std_logic_vector (3 DOWNTO 0);
    179178      -- status:
    180       shifting        : OUT    std_logic                     := '0';
    181       wiz_addr        : OUT    std_logic_vector (9 DOWNTO 0);
    182       wiz_cs          : OUT    std_logic                     := '1';
    183       wiz_rd          : OUT    std_logic                     := '1';
    184       wiz_reset       : OUT    std_logic                     := '1';
    185       wiz_wr          : OUT    std_logic                     := '1';
    186       sio             : INOUT  std_logic ;
    187       wiz_data        : INOUT  std_logic_vector (15 DOWNTO 0)
     179      shifting               : OUT    std_logic                     := '0';
     180      wiz_addr               : OUT    std_logic_vector (9 DOWNTO 0);
     181      wiz_cs                 : OUT    std_logic                     := '1';
     182      wiz_rd                 : OUT    std_logic                     := '1';
     183      wiz_reset              : OUT    std_logic                     := '1';
     184      wiz_wr                 : OUT    std_logic                     := '1';
     185      sio                    : INOUT  std_logic ;
     186      wiz_data               : INOUT  std_logic_vector (15 DOWNTO 0)
    188187   );
    189188   END COMPONENT;
    … …  
    232231   -- HDL Embedded Text Block 6 MISC
    233232   -- MISC 6     
    234    TRG_V <= '0';
     233   
    235234   RS485_C_RE <= '0';
    236235   RS485_C_DE <= '0';   
    237236   RS485_C_DO <= RS485_C_DI;
    238237   
    239    RS485_E_RE <= '0';     
    240    RS485_E_DE <= '0';
    241    --RS485_E_DO <= RS485_E_DI;
     238   
    242239   
    243240   -- DENABLE <= '0'; -- domino wave stopped
    … …  
    246243   
    247244   EE_CS <= '1';
    248 
    249    -- HDL Embedded Text Block 7 eb1
    250    D_T2 <= D_PLLLCK;
    251245
    252246   -- HDL Embedded Text Block 8 eb2
    … …  
    256250   -- HDL Embedded Text Block 9 eb3
    257251   -- eb3 9                         
    258    A0_T(0) <= ready;
    259    A0_T(1) <= shifting;
    260    A0_T(2) <= CLK25_PSOUT;
    261    A0_T(3) <= PS_DIR_IN;
    262    A0_T(4) <= PS_DO_IN;
    263    A0_T(5) <= PSINCDEC_OUT;
    264    A0_T(6) <= PSEN_OUT;
    265    A0_T(7) <= DCM_locked;
     252   --A0_T(0) <= ready;
     253   --A0_T(1) <= shifting;
     254   --A0_T(2) <= CLK25_PSOUT;
     255   --A0_T(3) <= PS_DIR_IN;
     256   --A0_T(4) <= PS_DO_IN;
     257   --A0_T(5) <= PSINCDEC_OUT;
     258   
     259   
    266260   
    267261   A1_T(0) <= SRIN_internal;
    … …  
    274268   A1_T(6) <= drs_channel_id(2);
    275269   A1_T(7) <= drs_channel_id(3);
     270   
     271   A0_T(5 downto 0) <= POSITION_ID;
     272   A0_T(6) <= REFCLK;
     273   A0_T(7) <= RS485_E_DI;
     274   RS485_E_RE <= '0';
     275   RS485_E_DE <= '0';
     276   
     277   D_T2 <= D_PLLLCK;
    276278
    277279
    … …  
    288290      )
    289291      PORT MAP (
    290          CLK             => X_50M,
    291          SROUT_in_0      => D0_SROUT,
    292          SROUT_in_1      => D1_SROUT,
    293          SROUT_in_2      => D2_SROUT,
    294          SROUT_in_3      => D3_SROUT,
    295          adc_data_array  => adc_data_array,
    296          adc_otr_array   => A_OTR,
    297          board_id        => board_id,
    298          crate_id        => crate_id,
    299          trigger         => TRG,
    300          wiz_int         => W_INT,
    301          CLK25_OUT       => CLK25_OUT,
    302          CLK25_PSOUT     => CLK25_PSOUT,
    303          CLK50_OUT       => CLK50_OUT,
    304          CLK_25_PS       => CLK_25_PS1,
    305          CLK_50          => CLK_50,
    306          DCM_locked      => DCM_locked,
    307          LOCKED_extraOUT => LOCKED_extraOUT,
    308          PSCLK_OUT       => PSCLK_OUT,
    309          PSDONE_extraOUT => PSDONE_extraOUT,
    310          PSEN_OUT        => PSEN_OUT,
    311          PSINCDEC_OUT    => PSINCDEC_OUT,
    312          PS_DIR_IN       => PS_DIR_IN,
    313          PS_DO_IN        => PS_DO_IN,
    314          RSRLOAD         => RSRLOAD,
    315          SRCLK           => SRCLK,
    316          SRIN_out        => SRIN_internal,
    317          adc_clk_en      => adc_clk_en,
    318          adc_oeb         => OE_ADC,
    319          amber           => AMBER_LED,
    320          dac_cs          => dummy,
    321          denable         => DENABLE,
    322          drs_channel_id  => drs_channel_id,
    323          drs_dwrite      => DWRITE,
    324          green           => RED_LED,
    325          led             => D_T,
    326          mosi            => MOSI,
    327          offset          => OPEN,
    328          ready           => ready,
    329          red             => GREEN_LED,
    330          sclk            => S_CLK,
    331          sensor_cs       => sensor_cs,
    332          shifting        => shifting,
    333          wiz_addr        => W_A,
    334          wiz_cs          => W_CS,
    335          wiz_rd          => W_RD,
    336          wiz_reset       => W_RES,
    337          wiz_wr          => W_WR,
    338          sio             => MISO,
    339          wiz_data        => W_D
     292         CLK                    => X_50M,
     293         SROUT_in_0             => D0_SROUT,
     294         SROUT_in_1             => D1_SROUT,
     295         SROUT_in_2             => D2_SROUT,
     296         SROUT_in_3             => D3_SROUT,
     297         adc_data_array         => adc_data_array,
     298         adc_otr_array          => A_OTR,
     299         board_id               => board_id,
     300         crate_id               => crate_id,
     301         trigger                => TRG,
     302         wiz_int                => W_INT,
     303         CLK25_OUT              => CLK25_OUT,
     304         CLK25_PSOUT            => CLK25_PSOUT,
     305         CLK50_OUT              => CLK50_OUT,
     306         CLK_25_PS              => CLK_25_PS1,
     307         CLK_50                 => CLK_50,
     308         DCM_locked             => DCM_locked,
     309         LOCKED_extraOUT        => LOCKED_extraOUT,
     310         PSCLK_OUT              => PSCLK_OUT,
     311         PSDONE_extraOUT        => PSDONE_extraOUT,
     312         PSINCDEC_OUT           => PSINCDEC_OUT,
     313         PS_DIR_IN              => PS_DIR_IN,
     314         RSRLOAD                => RSRLOAD,
     315         SRCLK                  => SRCLK,
     316         SRIN_out               => SRIN_internal,
     317         adc_clk_en             => adc_clk_en,
     318         adc_oeb                => OE_ADC,
     319         additional_flasher_out => TRG_V,
     320         amber                  => AMBER_LED,
     321         dac_cs                 => dummy,
     322         denable                => DENABLE,
     323         drs_channel_id         => drs_channel_id,
     324         drs_dwrite             => DWRITE,
     325         green                  => RED_LED,
     326         led                    => D_T,
     327         mosi                   => MOSI,
     328         offset                 => OPEN,
     329         ready                  => ready,
     330         red                    => GREEN_LED,
     331         sclk                   => S_CLK,
     332         sensor_cs              => sensor_cs,
     333         shifting               => shifting,
     334         wiz_addr               => W_A,
     335         wiz_cs                 => W_CS,
     336         wiz_rd                 => W_RD,
     337         wiz_reset              => W_RES,
     338         wiz_wr                 => W_WR,
     339         sio                    => MISO,
     340         wiz_data               => W_D
    340341      );
    341342

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10081 r10121  
    2323 
    2424  -- @ ETH zurich
    25 --    constant NETMASK : ip_type := (255, 255, 248, 0);
    26 --    constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
    27 --    constant GATEWAY : ip_type := (192, 33, 96, 1);
     25--   constant NETMASK : ip_type := (255, 255, 248, 0);
     26--   constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
     27--   constant GATEWAY : ip_type := (192, 33, 96, 1);
    2828
    2929  -- @ TU Dortmund
    … …  
    138138constant CMD_SRCLK_OFF : std_logic_vector     := X"16";
    139139
     140constant CMD_TRIGGERS_ON : std_logic_vector     := X"18";
     141constant CMD_TRIGGERS_OFF : std_logic_vector     := X"19";
     142
    140143constant CMD_PS_RESET : std_logic_vector     := X"17";
     144
     145constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21";
     146
    141147-- DRS Registers
    142148  constant DRS_CONFIG_REG : std_logic_vector := "1100"; 

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak

    r10081 r10121  
    2323 
    2424  -- @ ETH zurich
    25 --    constant NETMASK : ip_type := (255, 255, 248, 0);
    26 --    constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
    27 --    constant GATEWAY : ip_type := (192, 33, 96, 1);
     25--   constant NETMASK : ip_type := (255, 255, 248, 0);
     26--   constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
     27--   constant GATEWAY : ip_type := (192, 33, 96, 1);
    2828
    2929  -- @ TU Dortmund
    … …  
    138138constant CMD_SRCLK_OFF : std_logic_vector     := X"16";
    139139
     140constant CMD_TRIGGERS_ON : std_logic_vector     := X"18";
     141constant CMD_TRIGGERS_OFF : std_logic_vector     := X"19";
     142
    140143constant CMD_PS_RESET : std_logic_vector     := X"17";
    141144-- DRS Registers
     145  constant DRS_CONFIG_REG : std_logic_vector := "1100"; 
    142146  constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; 
    143  
     147  constant DRS_WRITE_CONFIG_REG : std_logic_vector := "1110"; 
     148  constant DRS_DISABLE_ALL_OUTS : std_logic_vector := "1111"; 
    144149 
    145150-- Declare functions and procedure

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10081 r10121  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:46:33 05.01.2011
     5--          at - 16:46:18 26.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    1818   );
    1919   PORT(
    20       CLK             : IN     std_logic;
    21       SROUT_in_0      : IN     std_logic;
    22       SROUT_in_1      : IN     std_logic;
    23       SROUT_in_2      : IN     std_logic;
    24       SROUT_in_3      : IN     std_logic;
    25       adc_data_array  : IN     adc_data_array_type;
    26       adc_otr_array   : IN     std_logic_vector (3 DOWNTO 0);
    27       board_id        : IN     std_logic_vector (3 DOWNTO 0);
    28       crate_id        : IN     std_logic_vector (1 DOWNTO 0);
    29       trigger         : IN     std_logic;
    30       wiz_int         : IN     std_logic;
    31       CLK25_OUT       : OUT    std_logic;
    32       CLK25_PSOUT     : OUT    std_logic;
    33       CLK50_OUT       : OUT    std_logic;
    34       CLK_25_PS       : OUT    std_logic;
    35       CLK_50          : OUT    std_logic;
    36       DCM_locked      : OUT    std_logic;
    37       LOCKED_extraOUT : OUT    std_logic;
    38       PSCLK_OUT       : OUT    std_logic;
    39       PSDONE_extraOUT : OUT    std_logic;
    40       PSEN_OUT        : OUT    std_logic;
    41       PSINCDEC_OUT    : OUT    std_logic;
    42       PS_DIR_IN       : OUT    std_logic;
    43       PS_DO_IN        : OUT    std_logic;
    44       RSRLOAD         : OUT    std_logic                     := '0';
    45       SRCLK           : OUT    std_logic                     := '0';
    46       SRIN_out        : OUT    std_logic                     := '0';
    47       adc_clk_en      : OUT    std_logic                     := '0';
    48       adc_oeb         : OUT    std_logic                     := '1';
    49       amber           : OUT    std_logic;
    50       dac_cs          : OUT    std_logic;
    51       denable         : OUT    std_logic                     := '0';              -- default domino wave off
    52       drs_channel_id  : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    53       drs_dwrite      : OUT    std_logic                     := '1';
    54       green           : OUT    std_logic;
    55       led             : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    56       mosi            : OUT    std_logic                     := '0';
    57       offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    58       ready           : OUT    std_logic                     := '0';
    59       red             : OUT    std_logic;
    60       sclk            : OUT    std_logic;
    61       sensor_cs       : OUT    std_logic_vector (3 DOWNTO 0);
     20      CLK                    : IN     std_logic;
     21      SROUT_in_0             : IN     std_logic;
     22      SROUT_in_1             : IN     std_logic;
     23      SROUT_in_2             : IN     std_logic;
     24      SROUT_in_3             : IN     std_logic;
     25      adc_data_array         : IN     adc_data_array_type;
     26      adc_otr_array          : IN     std_logic_vector (3 DOWNTO 0);
     27      board_id               : IN     std_logic_vector (3 DOWNTO 0);
     28      crate_id               : IN     std_logic_vector (1 DOWNTO 0);
     29      trigger                : IN     std_logic;
     30      wiz_int                : IN     std_logic;
     31      CLK25_OUT              : OUT    std_logic;
     32      CLK25_PSOUT            : OUT    std_logic;
     33      CLK50_OUT              : OUT    std_logic;
     34      CLK_25_PS              : OUT    std_logic;
     35      CLK_50                 : OUT    std_logic;
     36      DCM_locked             : OUT    std_logic;
     37      LOCKED_extraOUT        : OUT    std_logic;
     38      PSCLK_OUT              : OUT    std_logic;
     39      PSDONE_extraOUT        : OUT    std_logic;
     40      PSINCDEC_OUT           : OUT    std_logic;
     41      PS_DIR_IN              : OUT    std_logic;
     42      RSRLOAD                : OUT    std_logic                     := '0';
     43      SRCLK                  : OUT    std_logic                     := '0';
     44      SRIN_out               : OUT    std_logic                     := '0';
     45      adc_clk_en             : OUT    std_logic                     := '0';
     46      adc_oeb                : OUT    std_logic                     := '1';
     47      additional_flasher_out : OUT    std_logic;
     48      amber                  : OUT    std_logic;
     49      dac_cs                 : OUT    std_logic;
     50      denable                : OUT    std_logic                     := '0';              -- default domino wave off
     51      drs_channel_id         : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     52      drs_dwrite             : OUT    std_logic                     := '1';
     53      green                  : OUT    std_logic;
     54      led                    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     55      mosi                   : OUT    std_logic                     := '0';
     56      offset                 : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     57      ready                  : OUT    std_logic                     := '0';
     58      red                    : OUT    std_logic;
     59      sclk                   : OUT    std_logic;
     60      sensor_cs              : OUT    std_logic_vector (3 DOWNTO 0);
    6261      -- status:
    63       shifting        : OUT    std_logic                     := '0';
    64       wiz_addr        : OUT    std_logic_vector (9 DOWNTO 0);
    65       wiz_cs          : OUT    std_logic                     := '1';
    66       wiz_rd          : OUT    std_logic                     := '1';
    67       wiz_reset       : OUT    std_logic                     := '1';
    68       wiz_wr          : OUT    std_logic                     := '1';
    69       sio             : INOUT  std_logic;
    70       wiz_data        : INOUT  std_logic_vector (15 DOWNTO 0)
     62      shifting               : OUT    std_logic                     := '0';
     63      wiz_addr               : OUT    std_logic_vector (9 DOWNTO 0);
     64      wiz_cs                 : OUT    std_logic                     := '1';
     65      wiz_rd                 : OUT    std_logic                     := '1';
     66      wiz_reset              : OUT    std_logic                     := '1';
     67      wiz_wr                 : OUT    std_logic                     := '1';
     68      sio                    : INOUT  std_logic;
     69      wiz_data               : INOUT  std_logic_vector (15 DOWNTO 0)
    7170   );
    7271
    … …  
    8079-- Created:
    8180--          by - dneise.UNKNOWN (E5B-LABOR6)
    82 --          at - 17:46:34 05.01.2011
     81--          at - 16:46:19 26.01.2011
    8382--
    8483-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    9392
    9493library UNISIM;
    95 use UNISIM.VComponents.all;
     94--use UNISIM.VComponents.all;
    9695USE IEEE.NUMERIC_STD.all;
    9796USE IEEE.std_logic_signed.all;
    … …  
    109108   SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0);
    110109   SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
     110   SIGNAL c_trigger_enable       : std_logic                                    := '0';
     111   SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1');    --subject to changes
    111112   SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0);
    112113   SIGNAL config_busy            : std_logic;
    … …  
    131132   SIGNAL dac_array              : dac_array_type;
    132133   SIGNAL data_out               : std_logic_vector(63 DOWNTO 0);
     134   SIGNAL dout                   : std_logic;
     135   SIGNAL dout1                  : std_logic;
    133136   SIGNAL drs_address            : std_logic_vector(3 DOWNTO 0)                 := (others => '0');
    134137   SIGNAL drs_address_mode       : std_logic;
    … …  
    137140   SIGNAL drs_read_s_cell        : std_logic                                    := '0';
    138141   SIGNAL drs_read_s_cell_ready  : std_logic;
     142   -- --
     143--      drs_dwrite : out std_logic := '1';
     144   SIGNAL drs_readout_ready      : std_logic                                    := '0';
     145   SIGNAL drs_readout_ready_ack  : std_logic;
    139146   SIGNAL drs_readout_started    : std_logic;
    140147   SIGNAL drs_s_cell_array       : drs_s_cell_array_type;
    … …  
    157164   SIGNAL roi_max                : roi_max_type;
    158165   SIGNAL s_trigger              : std_logic;
     166   SIGNAL s_trigger_0            : std_logic;
    159167   SIGNAL sclk1                  : std_logic;
    160168   SIGNAL sclk_enable            : std_logic;
    … …  
    167175   SIGNAL srin_write_ready       : std_logic                                    := '0';
    168176   SIGNAL start_srin_write_8b    : std_logic;
     177   SIGNAL trigger1               : std_logic;
     178   SIGNAL trigger_enable         : std_logic;
    169179   SIGNAL trigger_id             : std_logic_vector(47 DOWNTO 0);
    170180   SIGNAL trigger_out            : std_logic;
    … …  
    207217      PSCLK_OUT       : OUT    std_logic ;
    208218      PSDONE_extraOUT : OUT    std_logic ;
    209       PSEN_OUT        : OUT    std_logic ;
    210219      PSINCDEC_OUT    : OUT    std_logic ;
    211220      offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    … …  
    213222      -- status:
    214223      shifting        : OUT    std_logic                     := '0'
     224   );
     225   END COMPONENT;
     226   COMPONENT continous_pulser
     227   GENERIC (
     228      MINIMAL_TRIGGER_WAIT_TIME : integer := 250000
     229   );
     230   PORT (
     231      CLK        : IN     std_logic;
     232      enable     : IN     std_logic;
     233      multiplier : IN     std_logic_vector (7 DOWNTO 0);
     234      trigger    : OUT    std_logic
    215235   );
    216236   END COMPONENT;
    … …  
    291311      adc_otr               : IN     std_logic_vector (3 DOWNTO 0);
    292312      drs_channel_id        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    293       drs_dwrite            : OUT    std_logic                     := '1';
     313      -- --
     314      --      drs_dwrite : out std_logic := '1';
     315      drs_readout_ready     : OUT    std_logic                     := '0';
     316      drs_readout_ready_ack : IN     std_logic ;
     317      -- --
    294318      drs_clk_en            : OUT    std_logic                     := '0';
     319      -- --
    295320      drs_read_s_cell       : OUT    std_logic                     := '0';
    296321      drs_srin_write_8b     : OUT    std_logic                     := '0';
    … …  
    300325      drs_read_s_cell_ready : IN     std_logic ;
    301326      drs_s_cell_array      : IN     drs_s_cell_array_type ;
    302       drs_readout_started   : OUT    std_logic
     327      drs_readout_started   : OUT    std_logic                     := '0'
    303328   );
    304329   END COMPONENT;
    … …  
    325350   COMPONENT led_controller
    326351   GENERIC (
    327       HEARTBEAT_PWM_DIVIDER : integer := 500;           -- 1kHz @ 50 MHz
    328       MAX_DELAY             : integer := 100;
    329       WAITING_DIVIDER       : integer := 500000000      -- 1Hz @ 50 MHz
    330    );
    331    PORT (
    332       CLK             : IN     std_logic;
    333       socks_connected : IN     std_logic;
    334       socks_waiting   : IN     std_logic;
    335       trigger         : IN     std_logic;
    336       amber           : OUT    std_logic;
    337       green           : OUT    std_logic;
    338       red             : OUT    std_logic
     352      HEARTBEAT_PWM_DIVIDER : integer := 500;
     353      MAX_DELAY             : integer := 100;      --not used anymore at all :-(
     354      WAITING_DIVIDER       : integer := 500000000
     355   );
     356   PORT (
     357      CLK                    : IN     std_logic;
     358      socks_connected        : IN     std_logic;
     359      socks_waiting          : IN     std_logic;
     360      trigger                : IN     std_logic;
     361      additional_flasher_out : OUT    std_logic;
     362      amber                  : OUT    std_logic;
     363      green                  : OUT    std_logic;
     364      red                    : OUT    std_logic
    339365   );
    340366   END COMPONENT;
    … …  
    389415      trigger    : IN     std_logic ;
    390416      clk        : IN     std_logic
     417   );
     418   END COMPONENT;
     419   COMPONENT trigger_manager
     420   PORT (
     421      clk                   : IN     std_logic;
     422      drs_readout_ready     : IN     std_logic;
     423      trigger_in            : IN     std_logic;
     424      drs_readout_ready_ack : OUT    std_logic  := '0';
     425      drs_write             : OUT    std_logic  := '1';
     426      trigger_out           : OUT    std_logic  := '0'
    391427   );
    392428   END COMPONENT;
    … …  
    415451      write_end_flag    : IN     std_logic ;
    416452      fifo_channels     : IN     std_logic_vector (3 DOWNTO 0);
     453      -- softtrigger:
    417454      s_trigger         : OUT    std_logic                      := '0';
     455      c_trigger_enable  : OUT    std_logic                      := '0';
     456      c_trigger_mult    : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '1'); --subject TO changes
     457      --
    418458      new_config        : OUT    std_logic                      := '0';
    419459      config_started    : IN     std_logic ;
    … …  
    428468      -- --
    429469      config_busy       : IN     std_logic ;
    430       denable           : OUT    std_logic                      := '0';           -- default domino wave off
    431       dwrite_enable     : OUT    std_logic                      := '0';           -- default DWRITE low.
    432       sclk_enable       : OUT    std_logic                      := '1';           -- default DWRITE HIGH.
    433       ps_direction      : OUT    std_logic                      := '1';           -- default phase shift upwards
    434       ps_do_phase_shift : OUT    std_logic                      := '0';           --pulse this TO phase shift once
    435       ps_reset          : OUT    std_logic                      := '0';           -- pulse this TO reset the variable phase shift
    436       srclk_enable      : OUT    std_logic                      := '1';           -- default SRCLK on.
     470      denable           : OUT    std_logic                      := '0';             -- default domino wave off
     471      dwrite_enable     : OUT    std_logic                      := '0';             -- default DWRITE low.
     472      sclk_enable       : OUT    std_logic                      := '1';             -- default DWRITE HIGH.
     473      ps_direction      : OUT    std_logic                      := '1';             -- default phase shift upwards
     474      ps_do_phase_shift : OUT    std_logic                      := '0';             --pulse this TO phase shift once
     475      ps_reset          : OUT    std_logic                      := '0';             -- pulse this TO reset the variable phase shift
     476      srclk_enable      : OUT    std_logic                      := '1';             -- default SRCLK on.
     477      trigger_enable    : OUT    std_logic                      := '0';             -- default triggers are NOT accepted
    437478      socks_waiting     : OUT    std_logic ;
    438479      socks_connected   : OUT    std_logic
    … …  
    444485   FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
    445486   FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
     487   FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser;
    446488   FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
    447489   FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
    … …  
    452494   FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
    453495   FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
     496   FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager;
    454497   FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
    455498   -- pragma synthesis_on
    … …  
    467510   sclk <= sclk_enable AND sclk1;
    468511
    469    -- ModuleWare code(v1.9) for instance 'U_3' of 'assignment'
    470    PS_DO_IN <= ps_do_phase_shift;
     512   -- ModuleWare code(v1.9) for instance 'U_11' of 'and'
     513   dout1 <= dout AND trigger_enable;
    471514
    472515   -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
    … …  
    494537
    495538   -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
    496    trigger_out <= s_trigger OR trigger;
     539   dout <= s_trigger OR trigger;
     540
     541   -- ModuleWare code(v1.9) for instance 'U_13' of 'or'
     542   s_trigger <= s_trigger_0 OR trigger1;
    497543
    498544   -- Instance port mappings.
    … …  
    518564         PSCLK_OUT       => PSCLK_OUT,
    519565         PSDONE_extraOUT => PSDONE_extraOUT,
    520          PSEN_OUT        => PSEN_OUT,
    521566         PSINCDEC_OUT    => PSINCDEC_OUT,
    522567         offset          => offset,
    523568         ready           => ready,
    524569         shifting        => shifting
     570      );
     571   U_3 : continous_pulser
     572      GENERIC MAP (
     573         MINIMAL_TRIGGER_WAIT_TIME => 250000
     574      )
     575      PORT MAP (
     576         CLK        => CLK_25,
     577         enable     => c_trigger_enable,
     578         multiplier => c_trigger_mult,
     579         trigger    => trigger1
    525580      );
    526581   I_main_control_unit : control_unit
    … …  
    590645         adc_otr               => adc_otr,
    591646         drs_channel_id        => drs_channel_internal,
    592          drs_dwrite            => dwrite,
     647         drs_readout_ready     => drs_readout_ready,
     648         drs_readout_ready_ack => drs_readout_ready_ack,
    593649         drs_clk_en            => drs_clk_en,
    594650         drs_read_s_cell       => drs_read_s_cell,
    … …  
    627683      )
    628684      PORT MAP (
    629          CLK             => CLK_50_internal,
    630          green           => green,
    631          amber           => amber,
    632          red             => red,
    633          trigger         => drs_readout_started,
    634          socks_waiting   => socks_waiting,
    635          socks_connected => socks_connected
     685         CLK                    => CLK_50_internal,
     686         green                  => green,
     687         amber                  => amber,
     688         red                    => red,
     689         additional_flasher_out => additional_flasher_out,
     690         trigger                => drs_readout_started,
     691         socks_waiting          => socks_waiting,
     692         socks_connected        => socks_connected
    636693      );
    637694   I_main_memory_manager : memory_manager
    … …  
    682739         clk        => CLK_25_PS_internal
    683740      );
     741   U_12 : trigger_manager
     742      PORT MAP (
     743         clk                   => CLK_25,
     744         trigger_in            => dout1,
     745         trigger_out           => trigger_out,
     746         drs_write             => dwrite,
     747         drs_readout_ready     => drs_readout_ready,
     748         drs_readout_ready_ack => drs_readout_ready_ack
     749      );
    684750   I_main_ethernet : w5300_modul
    685751      GENERIC MAP (
    … …  
    706772         write_end_flag    => wiz_write_end,
    707773         fifo_channels     => wiz_number_of_channels,
    708          s_trigger         => s_trigger,
     774         s_trigger         => s_trigger_0,
     775         c_trigger_enable  => c_trigger_enable,
     776         c_trigger_mult    => c_trigger_mult,
    709777         new_config        => new_config,
    710778         config_started    => config_started,
    … …  
    723791         ps_reset          => ps_reset,
    724792         srclk_enable      => srclk_enable,
     793         trigger_enable    => trigger_enable,
    725794         socks_waiting     => socks_waiting,
    726795         socks_connected   => socks_connected

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd

    r10075 r10121  
    2121ENTITY led_controller IS
    2222GENERIC(
    23   HEARTBEAT_PWM_DIVIDER : integer := 500;   -- 1kHz @ 50 MHz
    24   MAX_DELAY : integer := 100;
    25   WAITING_DIVIDER : integer := 500000000   -- 1Hz @ 50 MHz
     23  HEARTBEAT_PWM_DIVIDER : integer := 500;   
     24  MAX_DELAY : integer := 100;  --not used anymore at all :-(
     25  WAITING_DIVIDER : integer := 500000000 
    2626);
    2727PORT(
    … …  
    3232    amber : OUT std_logic;
    3333    red : OUT std_logic;
     34    additional_flasher_out : OUT std_logic;
    3435   
    3536   
    … …  
    6162  amber <= not amber_loc;
    6263  red <= not red_loc;
     64  additional_flasher_out <= flasher;
    6365 
    6466  -- MAIN FSM: go to next state if rising edge

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd

    r10073 r10121  
    22--
    33-- Created:
    4 --          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 14:00:24 01.10.2010
     4--          by - daqct3.UNKNOWN (IHP110)
     5--          at - 12:52:20 06.01.2011
    66--
    7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    88--
    99LIBRARY ieee;
    … …  
    3737--
    3838-- Created:
    39 --          by - dneise.UNKNOWN (E5B-LABOR6)
    40 --          at - 14:00:25 01.10.2010
     39--          by - daqct3.UNKNOWN (IHP110)
     40--          at - 12:52:20 06.01.2011
    4141--
    42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     42-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    4343--
    4444LIBRARY ieee;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10078 r10121  
    5353      write_header_flag, write_end_flag : IN std_logic;
    5454      fifo_channels : IN std_logic_vector (3 downto 0);
     55      -- softtrigger:
    5556      s_trigger : OUT std_logic := '0';
     57      c_trigger_enable: out std_logic := '0';
     58      c_trigger_mult: out std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject to changes
     59      --
    5660      new_config : OUT std_logic := '0';
    5761      config_started : in std_logic;
    … …  
    7579     
    7680      srclk_enable : out std_logic := '1'; -- default SRCLK on.
     81     
     82      trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted
    7783     
    7884      socks_waiting : out std_logic;
    … …  
    593599                      state_read_data <= RD_5;
    594600                    when CMD_TRIGGER_C =>
    595                       trigger_stop <= '0';
    596                       s_trigger <= '1';
     601                      c_trigger_enable <= '1';
     602                      --trigger_stop <= '0';
     603                      --s_trigger <= '1';
    597604                      state_read_data <= RD_5;
    598605                    when CMD_TRIGGER_S =>
    599                       trigger_stop <= '1';
    600                       state_read_data <= RD_5;
     606                      c_trigger_enable <= '0';
     607                      --trigger_stop <= '1';
     608                      state_read_data <= RD_5;
     609                    when CMD_SET_TRIGGER_MULT =>
     610                      c_trigger_mult <= data_read (7 downto 0);
     611                      state_read_data <= RD_5;
     612
    601613                    -- phase shift commands here:
    602614                    when CMD_PS_DO =>
    … …  
    609621                      ps_reset <= '1';
    610622                      state_read_data <= RD_5;
     623
    611624                    when CMD_SRCLK_ON =>
    612625                      srclk_enable <= '1';
    … …  
    615628                      srclk_enable <= '0';
    616629                      state_read_data <= RD_5;
     630
     631                    when CMD_TRIGGERS_ON =>
     632                      trigger_enable <= '1';
     633                      state_read_data <= RD_5;
     634                    when CMD_TRIGGERS_OFF =>
     635                      trigger_enable <= '0';
     636                      state_read_data <= RD_5;
     637
     638
    617639                    when CMD_PS_DIRDEC =>
    618640                      ps_direction <= '0';

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak

    r10078 r10121  
    5353      write_header_flag, write_end_flag : IN std_logic;
    5454      fifo_channels : IN std_logic_vector (3 downto 0);
     55      -- softtrigger:
    5556      s_trigger : OUT std_logic := '0';
     57      c_trigger_enable: out std_logic := '0';
     58      c_trigger_mult: out std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject to changes
     59      --
    5660      new_config : OUT std_logic := '0';
    5761      config_started : in std_logic;
    … …  
    7579     
    7680      srclk_enable : out std_logic := '1'; -- default SRCLK on.
     81     
     82      trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted
    7783     
    7884      socks_waiting : out std_logic;
    … …  
    243249                                        -- reset W5300
    244250                                        when RESET =>
     251                                          socket_send_mode <= '0';
    245252                                          busy <= '1';
    246253                                                zaehler <= zaehler + 1;
    … …  
    561568                  case data_read (15 downto 8) is
    562569                   
    563                     when CMD_START => -- all data will be send via socket 0
     570                    when CMD_START => -- all data will be send via socket 1..7
    564571                        socket_send_mode <= '1';
    565572                        state_read_data <= RD_5;
    566                     when CMD_STOP => -- all data will be send via socket 1..7
     573                    when CMD_STOP => -- all data will be send via socket 0
    567574                        socket_send_mode <= '0';
    568575                        state_read_data <= RD_5;                   
    … …  
    592599                      state_read_data <= RD_5;
    593600                    when CMD_TRIGGER_C =>
    594                       trigger_stop <= '0';
    595                       s_trigger <= '1';
     601                      c_trigger_enable <= '1';
     602                      --trigger_stop <= '0';
     603                      --s_trigger <= '1';
    596604                      state_read_data <= RD_5;
    597605                    when CMD_TRIGGER_S =>
    598                       trigger_stop <= '1';
     606                      c_trigger_enable <= '0';
     607                      --trigger_stop <= '1';
    599608                      state_read_data <= RD_5;
    600609                    -- phase shift commands here:
    … …  
    608617                      ps_reset <= '1';
    609618                      state_read_data <= RD_5;
     619
    610620                    when CMD_SRCLK_ON =>
    611621                      srclk_enable <= '1';
    … …  
    614624                      srclk_enable <= '0';
    615625                      state_read_data <= RD_5;
     626
     627                    when CMD_TRIGGERS_ON =>
     628                      trigger_enable <= '1';
     629                      state_read_data <= RD_5;
     630                    when CMD_TRIGGERS_OFF =>
     631                      trigger_enable <= '0';
     632                      state_read_data <= RD_5;
     633
     634
    616635                    when CMD_PS_DIRDEC =>
    617636                      ps_direction <= '0';

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/_DCM_25MHz_38nsPS_BEHAVIORAL.vhd._fpf

    r9912 r10121  
    88}
    99DONT_TOUCH atom XSTDataPrep
     10INCLUDE list {
     11 DEFAULT atom 1
     12}

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/_DCM_25MHz_noPS_BEHAVIORAL.vhd._fpf

    r9912 r10121  
    88}
    99DONT_TOUCH atom XSTDataPrep
     10INCLUDE list {
     11 DEFAULT atom 1
     12}

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/_dataRAM_64b_16b_width14_5_dataRAM_64b_16b_width14_5_a.vhd._fpf

    r9912 r10121  
    1212 }
    1313}
     14INCLUDE list {
     15 DEFAULT atom 1
     16}

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/_dataRAM_64b_16b_width15_dataRAM_64b_16b_width15_a.vhd._fpf

    r9912 r10121  
    1212 }
    1313}
     14INCLUDE list {
     15 DEFAULT atom 1
     16}

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/_dataRM_64b_16b_width14_dataRM_64b_16b_width14_a.vhd._fpf

    r9912 r10121  
    1212 }
    1313}
     14INCLUDE list {
     15 DEFAULT atom 1
     16}

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.hdlsidedata/_dcm_var_ps_38ns_BEHAVIORAL.vhd._fpf

    r9912 r10121  
    77 }
    88}
     9INCLUDE list {
     10 DEFAULT atom 1
     11}

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf

    r9912 r10121  
    4040DESIGN clock_generator_var_ps
    4141VIEW symbol.sb
    42 GRAPHIC 529,0 25 0
    43 DESIGN clock_generator_var_ps
    44 VIEW symbol.sb
    45 GRAPHIC 534,0 26 0
    46 DESIGN clock_generator_var_ps
    47 VIEW symbol.sb
    48 GRAPHIC 475,0 27 0
    49 DESIGN clock_generator_var_ps
    50 VIEW symbol.sb
    51 GRAPHIC 463,0 28 0
    52 DESIGN clock_generator_var_ps
    53 VIEW symbol.sb
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     42GRAPHIC 534,0 25 0
     43DESIGN clock_generator_var_ps
     44VIEW symbol.sb
     45GRAPHIC 475,0 26 0
     46DESIGN clock_generator_var_ps
     47VIEW symbol.sb
     48GRAPHIC 463,0 27 0
     49DESIGN clock_generator_var_ps
     50VIEW symbol.sb
     51GRAPHIC 469,0 29 0
     52DESIGN clock_generator_var_ps
     53VIEW symbol.sb
     54GRAPHIC 1,0 32 0
    5555DESIGN clock_generator_var_ps
    5656VIEW symbol.sb
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    5858DESIGN clock_generator_var_ps
    59 VIEW symbol.sb
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    61 DESIGN clock_generator_var_ps
    62 VIEW struct.bd
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    64 DESIGN clock_generator_var_ps
    65 VIEW struct.bd
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    67 DESIGN clock_generator_var_ps
    68 VIEW struct.bd
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    70 DESIGN clock_generator_var_ps
    71 VIEW struct.bd
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    73 DESIGN clock_generator_var_ps
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    76 DESIGN clock_generator_var_ps
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    79 DESIGN clock_generator_var_ps
    80 VIEW struct.bd
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    82 DESIGN clock_generator_var_ps
    83 VIEW struct.bd
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    85 DESIGN clock_generator_var_ps
    86 VIEW struct.bd
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    88 DESIGN clock_generator_var_ps
    89 VIEW struct.bd
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    91 DESIGN clock_generator_var_ps
    92 VIEW struct.bd
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    94 DESIGN clock_generator_var_ps
    95 VIEW struct.bd
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    97 DESIGN clock_generator_var_ps
    98 VIEW struct.bd
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     59VIEW struct.bd
     60NO_GRAPHIC 36
     61DESIGN clock_generator_var_ps
     62VIEW struct.bd
     63GRAPHIC 41,0 45 0
     64DESIGN clock_generator_var_ps
     65VIEW struct.bd
     66NO_GRAPHIC 51
     67DESIGN clock_generator_var_ps
     68VIEW struct.bd
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     70DESIGN clock_generator_var_ps
     71VIEW struct.bd
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     73DESIGN clock_generator_var_ps
     74VIEW struct.bd
     75GRAPHIC 600,0 60 0
     76DESIGN clock_generator_var_ps
     77VIEW struct.bd
     78GRAPHIC 530,0 61 0
     79DESIGN clock_generator_var_ps
     80VIEW struct.bd
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     82DESIGN clock_generator_var_ps
     83VIEW struct.bd
     84GRAPHIC 544,0 63 0
     85DESIGN clock_generator_var_ps
     86VIEW struct.bd
     87GRAPHIC 558,0 64 0
     88DESIGN clock_generator_var_ps
     89VIEW struct.bd
     90NO_GRAPHIC 65
     91DESIGN clock_generator_var_ps
     92VIEW struct.bd
     93GRAPHIC 229,0 67 0
     94DESIGN clock_generator_var_ps
     95VIEW struct.bd
     96NO_GRAPHIC 69
    10097LIBRARY FACT_FAD_lib
    10198DESIGN dcm_50_to_25
    10299VIEW @b@e@h@a@v@i@o@r@a@l
    103 GRAPHIC 403,0 72 0
    104 DESIGN clock_generator_var_ps
    105 VIEW struct.bd
    106 NO_GRAPHIC 78
    107 DESIGN clock_generator_var_ps
    108 VIEW struct.bd
    109 GRAPHIC 354,0 80 0
    110 DESIGN clock_generator_var_ps
    111 VIEW struct.bd
    112 NO_GRAPHIC 84
    113 DESIGN clock_generator_var_ps
    114 VIEW struct.bd
    115 GRAPHIC 514,0 86 0
    116 DESIGN clock_generator_var_ps
    117 VIEW struct.bd
    118 NO_GRAPHIC 96
    119 DESIGN clock_generator_var_ps
    120 VIEW struct.bd
    121 GRAPHIC 826,0 98 0
    122 DESIGN phase_shifter
    123 VIEW first_behave
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    125 DESIGN phase_shifter
    126 VIEW first_behave
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    128 DESIGN phase_shifter
    129 VIEW first_behave
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    131 DESIGN phase_shifter
    132 VIEW first_behave
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    135 VIEW first_behave
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    137 DESIGN phase_shifter
    138 VIEW first_behave
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    140 DESIGN phase_shifter
    141 VIEW first_behave
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    143 DESIGN phase_shifter
    144 VIEW first_behave
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    146 DESIGN phase_shifter
    147 VIEW first_behave
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    149 DESIGN phase_shifter
    150 VIEW first_behave
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    152 DESIGN phase_shifter
    153 VIEW first_behave
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    155 DESIGN phase_shifter
    156 VIEW first_behave
    157 GRAPHIC 108,0 114 0
     100GRAPHIC 403,0 71 0
     101DESIGN clock_generator_var_ps
     102VIEW struct.bd
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     104DESIGN clock_generator_var_ps
     105VIEW struct.bd
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     107DESIGN clock_generator_var_ps
     108VIEW struct.bd
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     110DESIGN clock_generator_var_ps
     111VIEW struct.bd
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     113DESIGN clock_generator_var_ps
     114VIEW struct.bd
     115NO_GRAPHIC 95
     116DESIGN clock_generator_var_ps
     117VIEW struct.bd
     118GRAPHIC 826,0 97 0
     119DESIGN phase_shifter
     120VIEW first_behave
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     122DESIGN phase_shifter
     123VIEW first_behave
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     125DESIGN phase_shifter
     126VIEW first_behave
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     128DESIGN phase_shifter
     129VIEW first_behave
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     131DESIGN phase_shifter
     132VIEW first_behave
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     134DESIGN phase_shifter
     135VIEW first_behave
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     137DESIGN phase_shifter
     138VIEW first_behave
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     140DESIGN phase_shifter
     141VIEW first_behave
     142GRAPHIC 88,0 108 0
     143DESIGN phase_shifter
     144VIEW first_behave
     145GRAPHIC 93,0 109 0
     146DESIGN phase_shifter
     147VIEW first_behave
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     149DESIGN phase_shifter
     150VIEW first_behave
     151GRAPHIC 103,0 112 0
     152DESIGN phase_shifter
     153VIEW first_behave
     154GRAPHIC 108,0 113 0
    158155LIBRARY FACT_FAD_lib
    159156DESIGN clock_generator_var_ps
    160157VIEW struct.bd
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    162 DESIGN clock_generator_var_ps
    163 VIEW struct.bd
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    165 DESIGN clock_generator_var_ps
    166 VIEW struct.bd
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    168 DESIGN clock_generator_var_ps
    169 VIEW struct.bd
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    171 DESIGN clock_generator_var_ps
    172 VIEW struct.bd
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    174 DESIGN clock_generator_var_ps
    175 VIEW struct.bd
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    177 DESIGN clock_generator_var_ps
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    180 DESIGN clock_generator_var_ps
    181 VIEW struct.bd
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    183 DESIGN clock_generator_var_ps
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    186 DESIGN clock_generator_var_ps
    187 VIEW struct.bd
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    189 DESIGN clock_generator_var_ps
    190 VIEW struct.bd
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    192 DESIGN clock_generator_var_ps
    193 VIEW struct.bd
    194 NO_GRAPHIC 143
    195 DESIGN clock_generator_var_ps
    196 VIEW struct.bd
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    198 DESIGN clock_generator_var_ps
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    201 DESIGN clock_generator_var_ps
    202 VIEW struct.bd
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    204 DESIGN clock_generator_var_ps
    205 VIEW struct.bd
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    207 DESIGN clock_generator_var_ps
    208 VIEW struct.bd
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    210 DESIGN clock_generator_var_ps
    211 VIEW struct.bd
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     159DESIGN clock_generator_var_ps
     160VIEW struct.bd
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     162DESIGN clock_generator_var_ps
     163VIEW struct.bd
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     165DESIGN clock_generator_var_ps
     166VIEW struct.bd
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     168DESIGN clock_generator_var_ps
     169VIEW struct.bd
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     171DESIGN clock_generator_var_ps
     172VIEW struct.bd
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     174DESIGN clock_generator_var_ps
     175VIEW struct.bd
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     177DESIGN clock_generator_var_ps
     178VIEW struct.bd
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     180DESIGN clock_generator_var_ps
     181VIEW struct.bd
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     183DESIGN clock_generator_var_ps
     184VIEW struct.bd
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     186DESIGN clock_generator_var_ps
     187VIEW struct.bd
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     189DESIGN clock_generator_var_ps
     190VIEW struct.bd
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     192DESIGN clock_generator_var_ps
     193VIEW struct.bd
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     195DESIGN clock_generator_var_ps
     196VIEW struct.bd
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     198DESIGN clock_generator_var_ps
     199VIEW struct.bd
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     201DESIGN clock_generator_var_ps
     202VIEW struct.bd
     203GRAPHIC 354,0 148 0
     204DESIGN clock_generator_var_ps
     205VIEW struct.bd
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     207DESIGN clock_generator_var_ps
     208VIEW struct.bd
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     210DESIGN clock_generator_var_ps
     211VIEW struct.bd
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    213213DESIGN clock_generator_var_ps
    214214VIEW struct.bd
    … …  
    216216DESIGN clock_generator_var_ps
    217217VIEW struct.bd
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    219 DESIGN clock_generator_var_ps
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    246 DESIGN clock_generator_var_ps
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     220VIEW struct.bd
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     223VIEW struct.bd
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     225DESIGN clock_generator_var_ps
     226VIEW struct.bd
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     234DESIGN clock_generator_var_ps
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     237DESIGN clock_generator_var_ps
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     241VIEW struct.bd
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     246DESIGN clock_generator_var_ps
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     249DESIGN clock_generator_var_ps
     250VIEW struct.bd
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     252DESIGN clock_generator_var_ps
     253VIEW struct.bd
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     255DESIGN clock_generator_var_ps
     256VIEW struct.bd
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     258DESIGN clock_generator_var_ps
     259VIEW struct.bd
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     261DESIGN clock_generator_var_ps
     262VIEW struct.bd
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     264DESIGN clock_generator_var_ps
     265VIEW struct.bd
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     267DESIGN clock_generator_var_ps
     268VIEW struct.bd
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     271VIEW struct.bd
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     277VIEW struct.bd
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     280VIEW struct.bd
     281NO_GRAPHIC 183

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r10081 r10121  
    3737DESIGN @f@a@d_@board
    3838VIEW symbol.sb
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

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     214DESIGN @f@a@d_main
     215VIEW struct.bd
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     217DESIGN @f@a@d_main
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     220DESIGN @f@a@d_main
     221VIEW struct.bd
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     223DESIGN @f@a@d_main
     224VIEW struct.bd
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     226DESIGN @f@a@d_main
     227VIEW struct.bd
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     229DESIGN @f@a@d_main
     230VIEW struct.bd
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     232DESIGN @f@a@d_main
     233VIEW struct.bd
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     235DESIGN @f@a@d_main
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     241DESIGN @f@a@d_main
     242VIEW struct.bd
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     244DESIGN @f@a@d_main
     245VIEW struct.bd
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     247DESIGN @f@a@d_main
     248VIEW struct.bd
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     250DESIGN @f@a@d_main
     251VIEW struct.bd
     252GRAPHIC 5144,0 131 0
     253DESIGN @f@a@d_main
     254VIEW struct.bd
     255GRAPHIC 332,0 132 0
     256DESIGN @f@a@d_main
     257VIEW struct.bd
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     259DESIGN @f@a@d_main
     260VIEW struct.bd
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     262DESIGN @f@a@d_main
     263VIEW struct.bd
     264GRAPHIC 8508,0 135 0
     265DESIGN @f@a@d_main
     266VIEW struct.bd
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     268DESIGN @f@a@d_main
     269VIEW struct.bd
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     271DESIGN @f@a@d_main
     272VIEW struct.bd
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     274DESIGN @f@a@d_main
     275VIEW struct.bd
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     277DESIGN @f@a@d_main
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     280DESIGN @f@a@d_main
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     283DESIGN @f@a@d_main
     284VIEW struct.bd
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     286DESIGN @f@a@d_main
     287VIEW struct.bd
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     289DESIGN @f@a@d_main
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     292DESIGN @f@a@d_main
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     295DESIGN @f@a@d_main
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     298DESIGN @f@a@d_main
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     301DESIGN @f@a@d_main
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     304DESIGN @f@a@d_main
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     307DESIGN @f@a@d_main
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     310DESIGN @f@a@d_main
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     313DESIGN @f@a@d_main
     314VIEW struct.bd
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     316DESIGN @f@a@d_main
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     319DESIGN @f@a@d_main
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     322DESIGN @f@a@d_main
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     325DESIGN @f@a@d_main
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     328DESIGN @f@a@d_main
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     331DESIGN @f@a@d_main
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     334DESIGN @f@a@d_main
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     340DESIGN @f@a@d_main
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     343DESIGN @f@a@d_main
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     346DESIGN @f@a@d_main
     347VIEW struct.bd
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     349DESIGN @f@a@d_main
     350VIEW struct.bd
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     352DESIGN @f@a@d_main
     353VIEW struct.bd
     354GRAPHIC 5478,0 168 0
     355DESIGN @f@a@d_main
     356VIEW struct.bd
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     358DESIGN @f@a@d_main
     359VIEW struct.bd
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     361DESIGN @f@a@d_main
     362VIEW struct.bd
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     364DESIGN @f@a@d_main
     365VIEW struct.bd
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     367DESIGN @f@a@d_main
     368VIEW struct.bd
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     370DESIGN @f@a@d_main
     371VIEW struct.bd
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     373DESIGN @f@a@d_main
     374VIEW struct.bd
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     376DESIGN @f@a@d_main
     377VIEW struct.bd
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     379DESIGN @f@a@d_main
     380VIEW struct.bd
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     382DESIGN @f@a@d_main
     383VIEW struct.bd
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     385DESIGN @f@a@d_main
     386VIEW struct.bd
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     388DESIGN @f@a@d_main
     389VIEW struct.bd
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     391DESIGN @f@a@d_main
     392VIEW struct.bd
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     394DESIGN @f@a@d_main
     395VIEW struct.bd
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     400DESIGN @f@a@d_main
     401VIEW struct.bd
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     403DESIGN @f@a@d_main
     404VIEW struct.bd
     405GRAPHIC 2498,0 185 0
     406DESIGN @f@a@d_main
     407VIEW struct.bd
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     409DESIGN @f@a@d_main
     410VIEW struct.bd
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     412DESIGN @f@a@d_main
     413VIEW struct.bd
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     415DESIGN @f@a@d_main
     416VIEW struct.bd
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     418DESIGN @f@a@d_main
     419VIEW struct.bd
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     421DESIGN @f@a@d_main
     422VIEW struct.bd
     423GRAPHIC 3888,0 192 0
     424DESIGN @f@a@d_main
     425VIEW struct.bd
     426NO_GRAPHIC 194
    403427LIBRARY FACT_FAD_lib
    404428DESIGN adc_buffer
    405429VIEW beha
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    407 DESIGN @f@a@d_main
    408 VIEW struct.bd
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    410 DESIGN @f@a@d_main
    411 VIEW struct.bd
    412 GRAPHIC 9175,0 195 0
     430GRAPHIC 5678,0 196 0
     431DESIGN @f@a@d_main
     432VIEW struct.bd
     433NO_GRAPHIC 203
     434DESIGN @f@a@d_main
     435VIEW struct.bd
     436GRAPHIC 9175,0 205 0
    413437DESIGN clock_generator_var_ps
    414438VIEW symbol.sb
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     439GRAPHIC 168,0 207 0
    416440DESIGN clock_generator_var_ps
    417441VIEW symbol.sb
    418 GRAPHIC 848,0 198 0
     442GRAPHIC 848,0 208 0
    419443DESIGN clock_generator_var_ps
    420444VIEW symbol.sb
    421 GRAPHIC 703,0 199 0
     445GRAPHIC 703,0 209 0
    422446DESIGN clock_generator_var_ps
    423447VIEW symbol.sb
    424 GRAPHIC 698,0 200 0
     448GRAPHIC 698,0 210 0
    425449DESIGN clock_generator_var_ps
    426450VIEW symbol.sb
    427 GRAPHIC 126,0 201 0
     451GRAPHIC 126,0 211 0
    428452DESIGN clock_generator_var_ps
    429453VIEW symbol.sb
    430 GRAPHIC 643,0 202 0
     454GRAPHIC 643,0 212 0
    431455DESIGN clock_generator_var_ps
    432456VIEW symbol.sb
    433 GRAPHIC 121,0 203 0
     457GRAPHIC 121,0 213 0
    434458DESIGN clock_generator_var_ps
    435459VIEW symbol.sb
    436 GRAPHIC 481,0 204 0
     460GRAPHIC 481,0 214 0
    437461DESIGN clock_generator_var_ps
    438462VIEW symbol.sb
    439 GRAPHIC 544,0 205 0
     463GRAPHIC 544,0 215 0
    440464DESIGN clock_generator_var_ps
    441465VIEW symbol.sb
    442 GRAPHIC 524,0 206 0
     466GRAPHIC 524,0 216 0
    443467DESIGN clock_generator_var_ps
    444468VIEW symbol.sb
    445 GRAPHIC 539,0 207 0
     469GRAPHIC 539,0 217 0
    446470DESIGN clock_generator_var_ps
    447471VIEW symbol.sb
    448 GRAPHIC 529,0 208 0
     472GRAPHIC 534,0 218 0
    449473DESIGN clock_generator_var_ps
    450474VIEW symbol.sb
    451 GRAPHIC 534,0 209 0
     475GRAPHIC 475,0 219 0
    452476DESIGN clock_generator_var_ps
    453477VIEW symbol.sb
    454 GRAPHIC 475,0 210 0
     478GRAPHIC 463,0 220 0
    455479DESIGN clock_generator_var_ps
    456480VIEW symbol.sb
    457 GRAPHIC 463,0 211 0
    458 DESIGN clock_generator_var_ps
    459 VIEW symbol.sb
    460 GRAPHIC 469,0 212 0
    461 DESIGN @f@a@d_main
    462 VIEW struct.bd
    463 GRAPHIC 5072,0 216 0
     481GRAPHIC 469,0 221 0
     482DESIGN @f@a@d_main
     483VIEW struct.bd
     484GRAPHIC 13117,0 225 0
     485DESIGN @f@a@d_main
     486VIEW struct.bd
     487GRAPHIC 13124,0 226 1
     488DESIGN @f@a@d_main
     489VIEW struct.bd
     490NO_GRAPHIC 234
     491DESIGN @f@a@d_main
     492VIEW struct.bd
     493GRAPHIC 5072,0 236 0
    464494DESIGN control_unit
    465495VIEW symbol.sb
    466 GRAPHIC 130,0 218 0
     496GRAPHIC 130,0 238 0
    467497DESIGN control_unit
    468498VIEW symbol.sb
    469 GRAPHIC 135,0 219 0
     499GRAPHIC 135,0 239 0
    470500DESIGN control_unit
    471501VIEW symbol.sb
    472 GRAPHIC 170,0 220 0
     502GRAPHIC 170,0 240 0
    473503DESIGN control_unit
    474504VIEW symbol.sb
    475 GRAPHIC 175,0 221 0
     505GRAPHIC 175,0 241 0
    476506DESIGN control_unit
    477507VIEW symbol.sb
    478 GRAPHIC 160,0 222 0
     508GRAPHIC 160,0 242 0
    479509DESIGN control_unit
    480510VIEW symbol.sb
    481 GRAPHIC 145,0 223 0
     511GRAPHIC 145,0 243 0
    482512DESIGN control_unit
    483513VIEW symbol.sb
    484 GRAPHIC 140,0 224 0
     514GRAPHIC 140,0 244 0
    485515DESIGN control_unit
    486516VIEW symbol.sb
    487 GRAPHIC 180,0 225 0
     517GRAPHIC 180,0 245 0
    488518DESIGN control_unit
    489519VIEW symbol.sb
    490 GRAPHIC 558,0 226 0
     520GRAPHIC 558,0 246 0
    491521DESIGN control_unit
    492522VIEW symbol.sb
    493 GRAPHIC 564,0 228 0
     523GRAPHIC 564,0 248 0
    494524DESIGN control_unit
    495525VIEW symbol.sb
    496 GRAPHIC 350,0 230 0
     526GRAPHIC 350,0 250 0
    497527DESIGN control_unit
    498528VIEW symbol.sb
    499 GRAPHIC 165,0 231 0
     529GRAPHIC 165,0 251 0
    500530DESIGN control_unit
    501531VIEW symbol.sb
    502 GRAPHIC 155,0 232 0
     532GRAPHIC 155,0 252 0
    503533DESIGN control_unit
    504534VIEW symbol.sb
    505 GRAPHIC 150,0 233 0
    506 DESIGN @f@a@d_main
    507 VIEW struct.bd
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     535GRAPHIC 150,0 253 0
     536DESIGN @f@a@d_main
     537VIEW struct.bd
     538GRAPHIC 8277,0 256 0
    509539DESIGN data@r@a@m_64b_16b_width14_5
    510540VIEW data@r@a@m_64b_16b_width14_5_a
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     541GRAPHIC 48,0 258 0
    512542DESIGN data@r@a@m_64b_16b_width14_5
    513543VIEW data@r@a@m_64b_16b_width14_5_a
    514 GRAPHIC 53,0 239 0
     544GRAPHIC 53,0 259 0
    515545DESIGN data@r@a@m_64b_16b_width14_5
    516546VIEW data@r@a@m_64b_16b_width14_5_a
    517 GRAPHIC 58,0 240 0
     547GRAPHIC 58,0 260 0
    518548DESIGN data@r@a@m_64b_16b_width14_5
    519549VIEW data@r@a@m_64b_16b_width14_5_a
    520 GRAPHIC 63,0 241 0
     550GRAPHIC 63,0 261 0
    521551DESIGN data@r@a@m_64b_16b_width14_5
    522552VIEW data@r@a@m_64b_16b_width14_5_a
    523 GRAPHIC 68,0 242 0
     553GRAPHIC 68,0 262 0
    524554DESIGN data@r@a@m_64b_16b_width14_5
    525555VIEW data@r@a@m_64b_16b_width14_5_a
    526 GRAPHIC 73,0 243 0
     556GRAPHIC 73,0 263 0
    527557DESIGN data@r@a@m_64b_16b_width14_5
    528558VIEW data@r@a@m_64b_16b_width14_5_a
    529 GRAPHIC 78,0 244 0
    530 DESIGN @f@a@d_main
    531 VIEW struct.bd
    532 GRAPHIC 1399,0 247 0
    533 DESIGN data_generator
    534 VIEW symbol.sb
    535 GRAPHIC 14,0 248 1
    536 DESIGN data_generator
    537 VIEW @behavioral
    538 GRAPHIC 48,0 252 0
    539 DESIGN data_generator
    540 VIEW @behavioral
    541 GRAPHIC 53,0 254 0
    542 DESIGN data_generator
    543 VIEW @behavioral
    544 GRAPHIC 58,0 255 0
    545 DESIGN data_generator
    546 VIEW @behavioral
    547 GRAPHIC 73,0 256 0
    548 DESIGN data_generator
    549 VIEW @behavioral
    550 GRAPHIC 78,0 257 0
    551 DESIGN data_generator
    552 VIEW @behavioral
    553 GRAPHIC 402,0 258 0
    554 DESIGN data_generator
    555 VIEW @behavioral
    556 GRAPHIC 407,0 259 0
    557 DESIGN data_generator
    558 VIEW @behavioral
    559 GRAPHIC 1479,0 260 0
    560 DESIGN data_generator
    561 VIEW @behavioral
    562 GRAPHIC 1122,0 262 0
    563 DESIGN data_generator
    564 VIEW @behavioral
    565 GRAPHIC 963,0 264 0
    566 DESIGN data_generator
    567 VIEW @behavioral
    568 GRAPHIC 1127,0 266 0
    569 DESIGN data_generator
    570 VIEW @behavioral
    571 GRAPHIC 1048,0 268 0
    572 DESIGN data_generator
    573 VIEW @behavioral
    574 GRAPHIC 958,0 269 0
    575 DESIGN data_generator
    576 VIEW @behavioral
    577 GRAPHIC 1053,0 270 0
    578 DESIGN data_generator
    579 VIEW @behavioral
    580 GRAPHIC 1201,0 271 0
    581 DESIGN data_generator
    582 VIEW @behavioral
    583 GRAPHIC 1196,0 272 0
    584 DESIGN data_generator
    585 VIEW @behavioral
    586 GRAPHIC 1206,0 273 0
    587 DESIGN data_generator
    588 VIEW @behavioral
    589 GRAPHIC 473,0 274 0
    590 DESIGN data_generator
    591 VIEW @behavioral
    592 GRAPHIC 412,0 275 0
    593 DESIGN data_generator
    594 VIEW @behavioral
    595 GRAPHIC 1085,0 276 0
    596 DESIGN data_generator
    597 VIEW @behavioral
    598 GRAPHIC 1090,0 277 0
    599 DESIGN data_generator
    600 VIEW @behavioral
    601 GRAPHIC 1240,0 278 0
    602 DESIGN data_generator
    603 VIEW @behavioral
    604 GRAPHIC 526,0 279 0
    605 DESIGN data_generator
    606 VIEW @behavioral
    607 GRAPHIC 88,0 280 0
    608 DESIGN data_generator
    609 VIEW @behavioral
    610 GRAPHIC 285,0 281 0
    611 DESIGN data_generator
    612 VIEW @behavioral
    613 GRAPHIC 93,0 282 0
    614 DESIGN data_generator
    615 VIEW @behavioral
    616 GRAPHIC 98,0 283 0
    617 DESIGN data_generator
    618 VIEW @behavioral
    619 GRAPHIC 1164,0 284 0
    620 DESIGN data_generator
    621 VIEW @behavioral
    622 GRAPHIC 1159,0 286 0
    623 DESIGN data_generator
    624 VIEW @behavioral
    625 GRAPHIC 898,0 287 0
    626 DESIGN data_generator
    627 VIEW @behavioral
    628 GRAPHIC 637,0 288 0
    629 DESIGN data_generator
    630 VIEW @behavioral
    631 GRAPHIC 1395,0 289 0
    632 DESIGN data_generator
    633 VIEW @behavioral
    634 GRAPHIC 1427,0 290 0
    635 DESIGN data_generator
    636 VIEW @behavioral
    637 GRAPHIC 676,0 291 0
    638 DESIGN data_generator
    639 VIEW @behavioral
    640 GRAPHIC 845,0 292 0
    641 DESIGN data_generator
    642 VIEW @behavioral
    643 GRAPHIC 681,0 293 0
    644 DESIGN data_generator
    645 VIEW @behavioral
    646 GRAPHIC 801,0 294 0
    647 DESIGN data_generator
    648 VIEW @behavioral
    649 GRAPHIC 1464,0 295 0
    650 DESIGN data_generator
    651 VIEW @behavioral
    652 GRAPHIC 1469,0 296 0
    653 DESIGN data_generator
    654 VIEW @behavioral
    655 GRAPHIC 1459,0 297 0
    656 DESIGN data_generator
    657 VIEW @behavioral
    658 GRAPHIC 1474,0 298 0
    659 DESIGN data_generator
    660 VIEW @behavioral
    661 GRAPHIC 806,0 299 0
    662 DESIGN data_generator
    663 VIEW @behavioral
    664 GRAPHIC 811,0 300 0
    665 DESIGN data_generator
    666 VIEW @behavioral
    667 GRAPHIC 1519,0 301 0
    668 DESIGN @f@a@d_main
    669 VIEW struct.bd
    670 GRAPHIC 4903,0 304 0
    671 DESIGN @f@a@d_main
    672 VIEW struct.bd
    673 NO_GRAPHIC 322
    674 DESIGN @f@a@d_main
    675 VIEW struct.bd
    676 GRAPHIC 11209,0 324 0
    677 DESIGN @f@a@d_main
    678 VIEW struct.bd
    679 GRAPHIC 11216,0 325 1
    680 DESIGN @f@a@d_main
    681 VIEW struct.bd
    682 NO_GRAPHIC 338
    683 DESIGN @f@a@d_main
    684 VIEW struct.bd
    685 GRAPHIC 2311,0 340 0
    686 DESIGN memory_manager
    687 VIEW symbol.sb
    688 GRAPHIC 14,0 341 1
    689 DESIGN memory_manager
    690 VIEW beha
    691 GRAPHIC 138,0 346 0
    692 DESIGN memory_manager
    693 VIEW beha
    694 GRAPHIC 194,0 347 0
    695 DESIGN memory_manager
    696 VIEW beha
    697 GRAPHIC 349,0 348 0
    698 DESIGN memory_manager
    699 VIEW beha
    700 GRAPHIC 949,0 349 0
    701 DESIGN memory_manager
    702 VIEW beha
    703 GRAPHIC 569,0 351 0
    704 DESIGN memory_manager
    705 VIEW beha
    706 GRAPHIC 224,0 353 0
    707 DESIGN memory_manager
    708 VIEW beha
    709 GRAPHIC 254,0 354 0
    710 DESIGN memory_manager
    711 VIEW beha
    712 GRAPHIC 804,0 355 0
    713 DESIGN memory_manager
    714 VIEW beha
    715 GRAPHIC 433,0 356 0
    716 DESIGN memory_manager
    717 VIEW beha
    718 GRAPHIC 622,0 357 0
    719 DESIGN memory_manager
    720 VIEW beha
    721 GRAPHIC 289,0 358 0
    722 DESIGN memory_manager
    723 VIEW beha
    724 GRAPHIC 309,0 359 0
    725 DESIGN memory_manager
    726 VIEW beha
    727 GRAPHIC 284,0 360 0
    728 DESIGN memory_manager
    729 VIEW beha
    730 GRAPHIC 294,0 361 0
    731 DESIGN memory_manager
    732 VIEW beha
    733 GRAPHIC 304,0 362 0
    734 DESIGN memory_manager
    735 VIEW beha
    736 GRAPHIC 299,0 363 0
    737 DESIGN memory_manager
    738 VIEW beha
    739 GRAPHIC 379,0 364 0
    740 DESIGN memory_manager
    741 VIEW beha
    742 GRAPHIC 915,0 365 0
    743 DESIGN memory_manager
    744 VIEW beha
    745 GRAPHIC 51,0 366 0
    746 DESIGN @f@a@d_main
    747 VIEW struct.bd
    748 GRAPHIC 5793,0 369 0
     559GRAPHIC 78,0 264 0
     560DESIGN @f@a@d_main
     561VIEW struct.bd
     562GRAPHIC 1399,0 267 0
     563DESIGN data_generator
     564VIEW symbol.sb
     565GRAPHIC 14,0 268 1
     566DESIGN data_generator
     567VIEW @behavioral
     568GRAPHIC 48,0 272 0
     569DESIGN data_generator
     570VIEW @behavioral
     571GRAPHIC 53,0 274 0
     572DESIGN data_generator
     573VIEW @behavioral
     574GRAPHIC 58,0 275 0
     575DESIGN data_generator
     576VIEW @behavioral
     577GRAPHIC 73,0 276 0
     578DESIGN data_generator
     579VIEW @behavioral
     580GRAPHIC 78,0 277 0
     581DESIGN data_generator
     582VIEW @behavioral
     583GRAPHIC 402,0 278 0
     584DESIGN data_generator
     585VIEW @behavioral
     586GRAPHIC 407,0 279 0
     587DESIGN data_generator
     588VIEW @behavioral
     589GRAPHIC 1479,0 280 0
     590DESIGN data_generator
     591VIEW @behavioral
     592GRAPHIC 1122,0 282 0
     593DESIGN data_generator
     594VIEW @behavioral
     595GRAPHIC 963,0 284 0
     596DESIGN data_generator
     597VIEW @behavioral
     598GRAPHIC 1127,0 286 0
     599DESIGN data_generator
     600VIEW @behavioral
     601GRAPHIC 1048,0 288 0
     602DESIGN data_generator
     603VIEW @behavioral
     604GRAPHIC 958,0 289 0
     605DESIGN data_generator
     606VIEW @behavioral
     607GRAPHIC 1053,0 290 0
     608DESIGN data_generator
     609VIEW @behavioral
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     1658GRAPHIC 6362,0 785 0
     1659DESIGN @f@a@d_main
     1660VIEW struct.bd
     1661GRAPHIC 6452,0 786 0
     1662DESIGN @f@a@d_main
     1663VIEW struct.bd
     1664GRAPHIC 8752,0 787 0
     1665DESIGN @f@a@d_main
     1666VIEW struct.bd
     1667GRAPHIC 9233,0 788 0
     1668DESIGN @f@a@d_main
     1669VIEW struct.bd
     1670GRAPHIC 9241,0 789 0
     1671DESIGN @f@a@d_main
     1672VIEW struct.bd
     1673GRAPHIC 9943,0 790 0
     1674DESIGN @f@a@d_main
     1675VIEW struct.bd
     1676GRAPHIC 9951,0 791 0
     1677DESIGN @f@a@d_main
     1678VIEW struct.bd
     1679GRAPHIC 11858,0 792 0
     1680DESIGN @f@a@d_main
     1681VIEW struct.bd
     1682GRAPHIC 10637,0 793 0
     1683DESIGN @f@a@d_main
     1684VIEW struct.bd
     1685GRAPHIC 10629,0 794 0
     1686DESIGN @f@a@d_main
     1687VIEW struct.bd
     1688GRAPHIC 6276,0 798 0
     1689DESIGN @f@a@d_main
     1690VIEW struct.bd
     1691GRAPHIC 3888,0 799 0
     1692DESIGN @f@a@d_main
     1693VIEW struct.bd
     1694NO_GRAPHIC 801

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r10081 r10121  
    8484)
    8585(EmbeddedInstance
    86 name "eb1"
    87 number "7"
    88 )
    89 (EmbeddedInstance
    9086name "eb2"
    9187number "8"
    … …  
    109105(vvPair
    110106variable "HDLDir"
    111 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
     107value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
    112108)
    113109(vvPair
    114110variable "HDSDir"
    115 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
     111value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    116112)
    117113(vvPair
    118114variable "SideDataDesignDir"
    119 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     115value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    120116)
    121117(vvPair
    122118variable "SideDataUserDir"
    123 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     119value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    124120)
    125121(vvPair
    126122variable "SourceDir"
    127 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
     123value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    128124)
    129125(vvPair
    … …  
    141137(vvPair
    142138variable "d"
    143 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     139value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    144140)
    145141(vvPair
    146142variable "d_logical"
    147 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
     143value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
    148144)
    149145(vvPair
    150146variable "date"
    151 value "05.01.2011"
     147value "26.01.2011"
    152148)
    153149(vvPair
    … …  
    161157(vvPair
    162158variable "dd"
    163 value "05"
     159value "26"
    164160)
    165161(vvPair
    … …  
    237233(vvPair
    238234variable "p"
    239 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     235value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    240236)
    241237(vvPair
    242238variable "p_logical"
    243 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     239value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    244240)
    245241(vvPair
    … …  
    297293(vvPair
    298294variable "time"
    299 value "17:34:20"
     295value "11:50:58"
    300296)
    301297(vvPair
    … …  
    688684n "wiz_reset"
    689685t "std_logic"
    690 o 47
     686o 46
    691687suid 2,0
    692688i "'1'"
    … …  
    727723b "(7 DOWNTO 0)"
    728724posAdd 0
    729 o 36
     725o 35
    730726suid 7,0
    731727i "(OTHERS => '0')"
    … …  
    799795n "adc_oeb"
    800796t "std_logic"
    801 o 29
     797o 27
    802798suid 21,0
    803799i "'1'"
    … …  
    909905t "std_logic_vector"
    910906b "(9 DOWNTO 0)"
    911 o 44
     907o 43
    912908suid 26,0
    913909)
    … …  
    945941n "wiz_cs"
    946942t "std_logic"
    947 o 45
     943o 44
    948944suid 28,0
    949945i "'1'"
    … …  
    983979t "std_logic_vector"
    984980b "(15 DOWNTO 0)"
    985 o 50
     981o 49
    986982suid 27,0
    987983)
    … …  
    10541050n "wiz_rd"
    10551051t "std_logic"
    1056 o 46
     1052o 45
    10571053suid 30,0
    10581054i "'1'"
    … …  
    10911087n "wiz_wr"
    10921088t "std_logic"
    1093 o 48
     1089o 47
    10941090suid 29,0
    10951091i "'1'"
    … …  
    13011297t "std_logic_vector"
    13021298b "(3 downto 0)"
    1303 o 33
     1299o 32
    13041300suid 48,0
    13051301i "(others => '0')"
    … …  
    13371333n "drs_dwrite"
    13381334t "std_logic"
    1339 o 34
     1335o 33
    13401336suid 49,0
    13411337i "'1'"
    … …  
    15091505n "RSRLOAD"
    15101506t "std_logic"
    1511 o 25
     1507o 23
    15121508suid 56,0
    15131509i "'0'"
    … …  
    15451541n "SRCLK"
    15461542t "std_logic"
    1547 o 26
     1543o 24
    15481544suid 57,0
    15491545i "'0'"
    … …  
    15821578n "dac_cs"
    15831579t "std_logic"
    1584 o 31
     1580o 30
    15851581suid 64,0
    15861582)
    … …  
    16181614n "sclk"
    16191615t "std_logic"
    1620 o 41
     1616o 40
    16211617suid 62,0
    16221618)
    … …  
    16551651t "std_logic_vector"
    16561652b "(3 DOWNTO 0)"
    1657 o 42
     1653o 41
    16581654suid 65,0
    16591655)
    … …  
    16931689preAdd 0
    16941690posAdd 0
    1695 o 49
     1691o 48
    16961692suid 63,0
    16971693)
    … …  
    17291725n "mosi"
    17301726t "std_logic"
    1731 o 37
     1727o 36
    17321728suid 66,0
    17331729i "'0'"
    … …  
    17681764eolc "-- default domino wave off"
    17691765posAdd 0
    1770 o 32
     1766o 31
    17711767suid 67,0
    17721768i "'0'"
    … …  
    18041800n "adc_clk_en"
    18051801t "std_logic"
    1806 o 28
     1802o 26
    18071803suid 69,0
    18081804i "'0'"
    … …  
    19181914preAdd 0
    19191915posAdd 0
    1920 o 38
     1916o 37
    19211917suid 77,0
    19221918i "(OTHERS => '0')"
    … …  
    19551951n "PS_DIR_IN"
    19561952t "std_logic"
    1957 o 23
     1953o 22
    19581954suid 80,0
    19591955)
    … …  
    19611957)
    19621958*49 (CptPort
    1963 uid 10266,0
    1964 ps "OnEdgeStrategy"
    1965 shape (Triangle
    1966 uid 10267,0
    1967 ro 90
    1968 va (VaSet
    1969 vasetType 1
    1970 fg "0,65535,0"
    1971 )
    1972 xt "80000,126625,80750,127375"
    1973 )
    1974 tg (CPTG
    1975 uid 10268,0
    1976 ps "CptPortTextPlaceStrategy"
    1977 stg "RightVerticalLayoutStrategy"
    1978 f (Text
    1979 uid 10269,0
    1980 va (VaSet
    1981 )
    1982 xt "74800,126500,79000,127500"
    1983 st "PS_DO_IN"
    1984 ju 2
    1985 blo "79000,127300"
    1986 )
    1987 )
    1988 thePort (LogicalPort
    1989 m 1
    1990 decl (Decl
    1991 n "PS_DO_IN"
    1992 t "std_logic"
    1993 o 24
    1994 suid 81,0
    1995 )
    1996 )
    1997 )
    1998 *50 (CptPort
    19991959uid 10270,0
    20001960ps "OnEdgeStrategy"
    … …  
    20321992)
    20331993)
    2034 *51 (CptPort
     1994*50 (CptPort
    20351995uid 10274,0
    20361996ps "OnEdgeStrategy"
    … …  
    20682028)
    20692029)
    2070 *52 (CptPort
    2071 uid 10278,0
    2072 ps "OnEdgeStrategy"
    2073 shape (Triangle
    2074 uid 10279,0
    2075 ro 90
    2076 va (VaSet
    2077 vasetType 1
    2078 fg "0,65535,0"
    2079 )
    2080 xt "80000,128625,80750,129375"
    2081 )
    2082 tg (CPTG
    2083 uid 10280,0
    2084 ps "CptPortTextPlaceStrategy"
    2085 stg "RightVerticalLayoutStrategy"
    2086 f (Text
    2087 uid 10281,0
    2088 va (VaSet
    2089 )
    2090 xt "74400,128500,79000,129500"
    2091 st "PSEN_OUT"
    2092 ju 2
    2093 blo "79000,129300"
    2094 )
    2095 )
    2096 thePort (LogicalPort
    2097 m 1
    2098 decl (Decl
    2099 n "PSEN_OUT"
    2100 t "std_logic"
    2101 o 21
    2102 suid 73,0
    2103 )
    2104 )
    2105 )
    2106 *53 (CptPort
     2030*51 (CptPort
    21072031uid 10282,0
    21082032ps "OnEdgeStrategy"
    … …  
    21352059n "PSINCDEC_OUT"
    21362060t "std_logic"
    2137 o 22
     2061o 21
    21382062suid 72,0
    21392063)
    21402064)
    21412065)
    2142 *54 (CptPort
     2066*52 (CptPort
    21432067uid 10286,0
    21442068ps "OnEdgeStrategy"
    … …  
    21732097preAdd 0
    21742098posAdd 0
    2175 o 39
     2099o 38
    21762100suid 79,0
    21772101i "'0'"
    … …  
    21792103)
    21802104)
    2181 *55 (CptPort
     2105*53 (CptPort
    21822106uid 10290,0
    21832107ps "OnEdgeStrategy"
    … …  
    22132137preAdd 0
    22142138posAdd 0
    2215 o 43
     2139o 42
    22162140suid 78,0
    22172141i "'0'"
    … …  
    22192143)
    22202144)
    2221 *56 (CptPort
     2145*54 (CptPort
    22222146uid 10320,0
    22232147ps "OnEdgeStrategy"
    … …  
    22552179)
    22562180)
    2257 *57 (CptPort
     2181*55 (CptPort
    22582182uid 10324,0
    22592183ps "OnEdgeStrategy"
    … …  
    22912215)
    22922216)
    2293 *58 (CptPort
     2217*56 (CptPort
    22942218uid 10328,0
    22952219ps "OnEdgeStrategy"
    … …  
    23272251)
    23282252)
    2329 *59 (CptPort
     2253*57 (CptPort
    23302254uid 12314,0
    23312255ps "OnEdgeStrategy"
    … …  
    23582282n "SRIN_out"
    23592283t "std_logic"
    2360 o 27
     2284o 25
    23612285suid 85,0
    23622286i "'0'"
    … …  
    23642288)
    23652289)
    2366 *60 (CptPort
     2290*58 (CptPort
    23672291uid 12521,0
    23682292ps "OnEdgeStrategy"
    … …  
    23952319n "amber"
    23962320t "std_logic"
    2397 o 30
     2321o 29
    23982322suid 87,0
    23992323)
    24002324)
    24012325)
    2402 *61 (CptPort
     2326*59 (CptPort
    24032327uid 12525,0
    24042328ps "OnEdgeStrategy"
    … …  
    24312355n "green"
    24322356t "std_logic"
    2433 o 35
     2357o 34
    24342358suid 86,0
    24352359)
    24362360)
    24372361)
    2438 *62 (CptPort
     2362*60 (CptPort
    24392363uid 12529,0
    24402364ps "OnEdgeStrategy"
    … …  
    24672391n "red"
    24682392t "std_logic"
    2469 o 40
     2393o 39
    24702394suid 88,0
     2395)
     2396)
     2397)
     2398*61 (CptPort
     2399uid 13843,0
     2400ps "OnEdgeStrategy"
     2401shape (Triangle
     2402uid 13844,0
     2403ro 90
     2404va (VaSet
     2405vasetType 1
     2406fg "0,65535,0"
     2407)
     2408xt "80000,143625,80750,144375"
     2409)
     2410tg (CPTG
     2411uid 13845,0
     2412ps "CptPortTextPlaceStrategy"
     2413stg "RightVerticalLayoutStrategy"
     2414f (Text
     2415uid 13846,0
     2416va (VaSet
     2417)
     2418xt "70500,143500,79000,144500"
     2419st "additional_flasher_out"
     2420ju 2
     2421blo "79000,144300"
     2422)
     2423)
     2424thePort (LogicalPort
     2425m 1
     2426decl (Decl
     2427n "additional_flasher_out"
     2428t "std_logic"
     2429o 28
     2430suid 90,0
    24712431)
    24722432)
    … …  
    24812441lineWidth 2
    24822442)
    2483 xt "52000,66000,80000,144000"
     2443xt "52000,66000,80000,145000"
    24842444)
    24852445oxt "15000,-1000,43000,27000"
    … …  
    24892449stg "VerticalLayoutStrategy"
    24902450textVec [
     2451*62 (Text
     2452uid 172,0
     2453va (VaSet
     2454font "Arial,8,1"
     2455)
     2456xt "55200,141000,61400,142000"
     2457st "FACT_FAD_lib"
     2458blo "55200,141800"
     2459tm "BdLibraryNameMgr"
     2460)
    24912461*63 (Text
    2492 uid 172,0
     2462uid 173,0
    24932463va (VaSet
    24942464font "Arial,8,1"
    24952465)
    2496 xt "52200,123000,58400,124000"
    2497 st "FACT_FAD_lib"
    2498 blo "52200,123800"
    2499 tm "BdLibraryNameMgr"
     2466xt "55200,142000,59400,143000"
     2467st "FAD_main"
     2468blo "55200,142800"
     2469tm "CptNameMgr"
    25002470)
    25012471*64 (Text
    2502 uid 173,0
     2472uid 174,0
    25032473va (VaSet
    25042474font "Arial,8,1"
    25052475)
    2506 xt "52200,124000,56400,125000"
    2507 st "FAD_main"
    2508 blo "52200,124800"
    2509 tm "CptNameMgr"
    2510 )
    2511 *65 (Text
    2512 uid 174,0
    2513 va (VaSet
    2514 font "Arial,8,1"
    2515 )
    2516 xt "52200,125000,58000,126000"
     2476xt "55200,143000,61000,144000"
    25172477st "I_board_main"
    2518 blo "52200,125800"
     2478blo "55200,143800"
    25192479tm "InstanceNameMgr"
    25202480)
    … …  
    25512511fg "49152,49152,49152"
    25522512)
    2553 xt "52250,142250,53750,143750"
     2513xt "52250,143250,53750,144750"
    25542514iconName "BlockDiagram.png"
    25552515iconMaskName "BlockDiagram.msk"
    … …  
    25612521archFileType "UNKNOWN"
    25622522)
    2563 *66 (PortIoIn
     2523*65 (PortIoIn
    25642524uid 231,0
    25652525shape (CompositeShape
    … …  
    26062566)
    26072567)
    2608 *67 (PortIoIn
     2568*66 (PortIoIn
    26092569uid 251,0
    26102570shape (CompositeShape
    … …  
    26512611)
    26522612)
    2653 *68 (HdlText
     2613*67 (HdlText
    26542614uid 265,0
    26552615optionalChildren [
    2656 *69 (EmbeddedText
     2616*68 (EmbeddedText
    26572617uid 271,0
    26582618commentText (CommentText
    … …  
    27042664stg "VerticalLayoutStrategy"
    27052665textVec [
    2706 *70 (Text
     2666*69 (Text
    27072667uid 268,0
    27082668va (VaSet
    … …  
    27142674tm "HdlTextNameMgr"
    27152675)
    2716 *71 (Text
     2676*70 (Text
    27172677uid 269,0
    27182678va (VaSet
    … …  
    27402700viewiconposition 0
    27412701)
    2742 *72 (Net
     2702*71 (Net
    27432703uid 275,0
    27442704decl (Decl
    … …  
    27482708preAdd 0
    27492709posAdd 0
    2750 o 73
     2710o 75
    27512711suid 5,0
    27522712)
    … …  
    27572717)
    27582718xt "39000,62400,67500,63200"
    2759 st "SIGNAL board_id        : std_logic_vector(3 downto 0)"
    2760 )
    2761 )
    2762 *73 (Net
     2719st "SIGNAL board_id        : std_logic_vector(3 downto 0)
     2720"
     2721)
     2722)
     2723*72 (Net
    27632724uid 283,0
    27642725decl (Decl
    … …  
    27662727t "std_logic_vector"
    27672728b "(1 downto 0)"
    2768 o 74
     2729o 76
    27692730suid 6,0
    27702731)
    … …  
    27752736)
    27762737xt "39000,63200,67500,64000"
    2777 st "SIGNAL crate_id        : std_logic_vector(1 downto 0)"
    2778 )
    2779 )
    2780 *74 (PortIoOut
     2738st "SIGNAL crate_id        : std_logic_vector(1 downto 0)
     2739"
     2740)
     2741)
     2742*73 (PortIoOut
    27812743uid 472,0
    27822744shape (CompositeShape
    … …  
    28222784)
    28232785)
    2824 *75 (PortIoOut
     2786*74 (PortIoOut
    28252787uid 478,0
    28262788shape (CompositeShape
    … …  
    28662828)
    28672829)
    2868 *76 (PortIoOut
     2830*75 (PortIoOut
    28692831uid 484,0
    28702832shape (CompositeShape
    … …  
    29102872)
    29112873)
    2912 *77 (PortIoInOut
     2874*76 (PortIoInOut
    29132875uid 490,0
    29142876shape (CompositeShape
    … …  
    29522914)
    29532915)
    2954 *78 (PortIoIn
     2916*77 (PortIoIn
    29552917uid 496,0
    29562918shape (CompositeShape
    … …  
    29962958)
    29972959)
    2998 *79 (PortIoOut
     2960*78 (PortIoOut
    29992961uid 502,0
    30002962shape (CompositeShape
    … …  
    30403002)
    30413003)
    3042 *80 (PortIoOut
     3004*79 (PortIoOut
    30433005uid 508,0
    30443006shape (CompositeShape
    … …  
    30843046)
    30853047)
    3086 *81 (Net
     3048*80 (Net
    30873049uid 1465,0
    30883050decl (Decl
    30893051n "adc_data_array"
    30903052t "adc_data_array_type"
    3091 o 72
     3053o 74
    30923054suid 29,0
    30933055)
    … …  
    30983060)
    30993061xt "39000,61600,63000,62400"
    3100 st "SIGNAL adc_data_array  : adc_data_array_type"
    3101 )
    3102 )
    3103 *82 (Net
     3062st "SIGNAL adc_data_array  : adc_data_array_type
     3063"
     3064)
     3065)
     3066*81 (Net
    31043067uid 2407,0
    31053068decl (Decl
    31063069n "RSRLOAD"
    31073070t "std_logic"
    3108 o 41
     3071o 43
    31093072suid 57,0
    31103073i "'0'"
    … …  
    31153078font "Courier New,8,0"
    31163079)
    3117 xt "39000,35800,67500,36600"
    3118 st "RSRLOAD         : std_logic                    := '0'"
    3119 )
    3120 )
    3121 *83 (PortIoOut
     3080xt "39000,37400,67500,38200"
     3081st "RSRLOAD         : std_logic                    := '0'
     3082"
     3083)
     3084)
     3085*82 (PortIoOut
    31223086uid 2415,0
    31233087shape (CompositeShape
    … …  
    31643128)
    31653129)
    3166 *84 (Net
     3130*83 (Net
    31673131uid 2421,0
    31683132decl (Decl
    31693133n "SRCLK"
    31703134t "std_logic"
    3171 o 70
     3135o 72
    31723136suid 58,0
    31733137i "'0'"
    … …  
    31793143)
    31803144xt "39000,60000,71000,60800"
    3181 st "SIGNAL SRCLK           : std_logic                    := '0'"
    3182 )
    3183 )
    3184 *85 (Net
     3145st "SIGNAL SRCLK           : std_logic                    := '0'
     3146"
     3147)
     3148)
     3149*84 (Net
    31853150uid 3019,0
    31863151decl (Decl
    … …  
    31883153t "std_logic_vector"
    31893154b "(3 DOWNTO 0)"
    3190 o 78
     3155o 80
    31913156suid 65,0
    31923157)
    … …  
    31973162)
    31983163xt "39000,66400,67500,67200"
    3199 st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)"
    3200 )
    3201 )
    3202 *86 (Net
     3164st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)
     3165"
     3166)
     3167)
     3168*85 (Net
    32033169uid 3025,0
    32043170decl (Decl
    32053171n "DAC_CS"
    32063172t "std_logic"
    3207 o 24
     3173o 27
    32083174suid 66,0
    32093175)
    … …  
    32133179font "Courier New,8,0"
    32143180)
    3215 xt "39000,23000,54000,23800"
    3216 st "DAC_CS          : std_logic"
    3217 )
    3218 )
    3219 *87 (PortIoOut
     3181xt "39000,24600,54000,25400"
     3182st "DAC_CS          : std_logic
     3183"
     3184)
     3185)
     3186*86 (PortIoOut
    32203187uid 3153,0
    32213188shape (CompositeShape
    … …  
    32623229)
    32633230)
    3264 *88 (Net
     3231*87 (Net
    32653232uid 3216,0
    32663233decl (Decl
    … …  
    32693236preAdd 0
    32703237posAdd 0
    3271 o 16
     3238o 18
    32723239suid 67,0
    32733240)
    … …  
    32773244font "Courier New,8,0"
    32783245)
    3279 xt "39000,15800,54000,16600"
    3280 st "X_50M           : STD_LOGIC"
    3281 )
    3282 )
    3283 *89 (Net
     3246xt "39000,17400,54000,18200"
     3247st "X_50M           : STD_LOGIC
     3248"
     3249)
     3250)
     3251*88 (Net
    32843252uid 3226,0
    32853253decl (Decl
    32863254n "TRG"
    32873255t "STD_LOGIC"
    3288 o 14
     3256o 16
    32893257suid 68,0
    32903258)
    … …  
    32943262font "Courier New,8,0"
    32953263)
    3296 xt "39000,14200,54000,15000"
    3297 st "TRG             : STD_LOGIC"
    3298 )
    3299 )
    3300 *90 (HdlText
     3264xt "39000,15800,54000,16600"
     3265st "TRG             : STD_LOGIC
     3266"
     3267)
     3268)
     3269*89 (HdlText
    33013270uid 3248,0
    33023271optionalChildren [
    3303 *91 (EmbeddedText
     3272*90 (EmbeddedText
    33043273uid 3254,0
    33053274commentText (CommentText
    … …  
    33533322stg "VerticalLayoutStrategy"
    33543323textVec [
    3355 *92 (Text
     3324*91 (Text
    33563325uid 3251,0
    33573326va (VaSet
    … …  
    33633332tm "HdlTextNameMgr"
    33643333)
    3365 *93 (Text
     3334*92 (Text
    33663335uid 3252,0
    33673336va (VaSet
    … …  
    33893358viewiconposition 0
    33903359)
    3391 *94 (Net
     3360*93 (Net
    33923361uid 3266,0
    33933362decl (Decl
    … …  
    33953364t "std_logic_vector"
    33963365b "(3 downto 0)"
    3397 o 19
     3366o 22
    33983367suid 71,0
    33993368)
    … …  
    34033372font "Courier New,8,0"
    34043373)
    3405 xt "39000,19000,64000,19800"
    3406 st "A_CLK           : std_logic_vector(3 downto 0)"
    3407 )
    3408 )
    3409 *95 (Net
     3374xt "39000,20600,64000,21400"
     3375st "A_CLK           : std_logic_vector(3 downto 0)
     3376"
     3377)
     3378)
     3379*94 (Net
    34103380uid 3268,0
    34113381decl (Decl
    34123382n "CLK_25_PS"
    34133383t "std_logic"
    3414 o 59
     3384o 61
    34153385suid 72,0
    34163386)
    … …  
    34203390font "Courier New,8,0"
    34213391)
    3422 xt "39000,51200,57500,52000"
    3423 st "SIGNAL CLK_25_PS       : std_logic"
    3424 )
    3425 )
    3426 *96 (PortIoOut
     3392xt "39000,52800,57500,53600"
     3393st "SIGNAL CLK_25_PS       : std_logic
     3394"
     3395)
     3396)
     3397*95 (PortIoOut
    34273398uid 3284,0
    34283399shape (CompositeShape
    … …  
    34693440)
    34703441)
    3471 *97 (Net
     3442*96 (Net
    34723443uid 3290,0
    34733444decl (Decl
    … …  
    34763447preAdd 0
    34773448posAdd 0
    3478 o 35
     3449o 36
    34793450suid 73,0
    34803451)
    … …  
    34843455font "Courier New,8,0"
    34853456)
    3486 xt "39000,30200,54000,31000"
    3487 st "OE_ADC          : STD_LOGIC"
    3488 )
    3489 )
    3490 *98 (PortIoIn
     3457xt "39000,31800,54000,32600"
     3458st "OE_ADC          : STD_LOGIC
     3459"
     3460)
     3461)
     3462*97 (PortIoIn