Ignore:
Timestamp:
01/27/11 08:32:16 (13 years ago)
Author:
neise
Message:
synchronous trigger handling added
continous soft trigger generation.
---> control frequency via 'send 0x21??'
each step increases trigger delay by 12.5ms
0x2100 = 40Hz
0x21FF = 0.3Hz
File:
1 edited

Legend:

Unmodified
Added
Removed

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

    r9912 r10121  
    44FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
    55FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
    6 secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
    7 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
    8 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
    9 unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
    10 XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
     6secureip = D:\unisim/secureip
     7simprim = D:\unisim/simprim
     8unimacro = D:\unisim/unimacro
     9unisim = D:\unisim/unisim
     10XilinxCoreLib = D:\unisim/xilinxcorelib
    1111[QuestaSim]
    12 secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
    13 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
    14 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
    15 unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
    16 XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
     12secureip = D:\unisim/secureip
     13simprim = D:\unisim/simprim
     14unimacro = D:\unisim/unimacro
     15unisim = D:\unisim/unisim
     16XilinxCoreLib = D:\unisim/xilinxcorelib
    1717[XilinxISE]
    1818FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
Note: See TracChangeset for help on using the changeset viewer.