Ignore:
Timestamp:
01/27/11 08:32:16 (13 years ago)
Author:
neise
Message:
synchronous trigger handling added
continous soft trigger generation.
---> control frequency via 'send 0x21??'
each step increases trigger delay by 12.5ms
0x2100 = 40Hz
0x21FF = 0.3Hz
File:
1 edited

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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10074 r10121  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 12:35:56 04.01.2011
     5--          at - 11:57:15 26.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    2424      PSCLK_OUT       : OUT    std_logic;
    2525      PSDONE_extraOUT : OUT    std_logic;
    26       PSEN_OUT        : OUT    std_logic;
    2726      PSINCDEC_OUT    : OUT    std_logic;
    2827      offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     
    4140-- Created:
    4241--          by - dneise.UNKNOWN (E5B-LABOR6)
    43 --          at - 12:35:56 04.01.2011
     42--          at - 11:57:15 26.01.2011
    4443--
    4544-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    5049USE ieee.numeric_std.all;
    5150LIBRARY UNISIM;
    52 USE UNISIM.Vcomponents.all;
     51--USE UNISIM.Vcomponents.all;
    5352
    5453LIBRARY FACT_FAD_lib;
     
    131130   PSCLK_OUT <= PSCLK_IN;
    132131
    133    -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
    134    PSEN_OUT <= PSEN_IN;
    135 
    136132   -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
    137133   PSINCDEC_OUT <= PSINCDEC_IN;
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