Changeset 10121 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
- Timestamp:
- 01/27/11 08:32:16 (13 years ago)
- File:
-
- 1 edited
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10074 r10121 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 2:35:56 04.01.20115 -- at - 11:57:15 26.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 24 24 PSCLK_OUT : OUT std_logic; 25 25 PSDONE_extraOUT : OUT std_logic; 26 PSEN_OUT : OUT std_logic;27 26 PSINCDEC_OUT : OUT std_logic; 28 27 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); … … 41 40 -- Created: 42 41 -- by - dneise.UNKNOWN (E5B-LABOR6) 43 -- at - 1 2:35:56 04.01.201142 -- at - 11:57:15 26.01.2011 44 43 -- 45 44 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 50 49 USE ieee.numeric_std.all; 51 50 LIBRARY UNISIM; 52 USE UNISIM.Vcomponents.all;51 --USE UNISIM.Vcomponents.all; 53 52 54 53 LIBRARY FACT_FAD_lib; … … 131 130 PSCLK_OUT <= PSCLK_IN; 132 131 133 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'134 PSEN_OUT <= PSEN_IN;135 136 132 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment' 137 133 PSINCDEC_OUT <= PSINCDEC_IN;
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