Changeset 10121 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

Timestamp:

01/27/11 08:32:16 (13 years ago)

Author:

neise

Message:

synchronous trigger handling added
continous soft trigger generation.
---> control frequency via 'send 0x21??'
each step increases trigger delay by 12.5ms
0x2100 = 40Hz
0x21FF = 0.3Hz

File:

• firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak (modified) (6 diffs)

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak

@@ -58 +58 @@
       adc_otr : in std_logic_vector (3 downto 0);
       drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
-      drs_dwrite : out std_logic := '1';
+      -- --
+--      drs_dwrite : out std_logic := '1';
+      drs_readout_ready : out std_logic := '0';
+      -- --
       drs_clk_en, drs_read_s_cell : out std_logic := '0';
 
@@ -69 +72 @@
       drs_s_cell_array : in drs_s_cell_array_type;
       
-      drs_readout_started : out std_logic
+      drs_readout_started : out std_logic := '0'
       );
 end data_generator ;
@@ -77 +80 @@
 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
                              WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
-                             WRITE_END_FLAG, WRITE_DATA_STOP,
+                             WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1, 
                              WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
 
@@ -181 +184 @@
             sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1
             -- stop drs, dwrite low
-            drs_dwrite <= '0';
+            -- drs_dwrite <= '0';
             -- start reading of drs stop cell
             drs_read_s_cell <= '1';
@@ -272 +275 @@
         when WRITE_ADC_DATA =>
           if (data_cntr < roi_max (channel_id)) then
---            data_out <= "000" & adc_otr(3) & adc_data_array(3)
---                      & "000" & adc_otr(2) & adc_data_array(2)
---                      & "000" & adc_otr(1) & adc_data_array(1)
---                      & "000" & adc_otr(0) & adc_data_array(0);
-              data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
-                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
-                          & "00100" & conv_std_logic_vector (data_cntr, 11) 
-                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
+            data_out <= "000" & adc_otr(3) & adc_data_array(3)
+                      & "000" & adc_otr(2) & adc_data_array(2)
+                      & "000" & adc_otr(1) & adc_data_array(1)
+                      & "000" & adc_otr(0) & adc_data_array(0);
+ --             data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 
+--                          & "00010" & conv_std_logic_vector (data_cntr, 11) 
+--                          & "00100" & conv_std_logic_vector (data_cntr, 11) 
+--                          & "00110" & conv_std_logic_vector (data_cntr, 11) ;
             addr_cntr <= addr_cntr + 1;
             state_generate <= WRITE_ADC_DATA;
@@ -329 +332 @@
                   if (ram_write_ready_ack = '0') then
                   -- --
-            drs_dwrite <= '1';
+--            drs_dwrite <= '1';
+            drs_readout_ready <= '1';
                                           data_cntr <= 0;
                                           addr_cntr <= 0;
                                           channel_id <= 0;
-                                          state_generate <= WRITE_DATA_IDLE;
+                                          state_generate <= WRITE_DATA_STOP1;
                                         -- --
                                         end if;
                                   -- --
+                                when WRITE_DATA_STOP1 =>
+                                  if (drs_readout_ready_ack = '1') then
+                                    drs_readout_ready <= '0';
+                                    state_generate <= WRITE_DATA_IDLE;
+                                  end if;
                                 when others =>
                                         null;