Changeset 10123


Ignore:
Timestamp:
01/27/11 17:10:41 (12 years ago)
Author:
neise
Message:
jumper selectable MAC and IP address choice.
D_T7 jumper selects if in_can (no jumper) or not in cam(jumper set)
D_T6 jumper selects if in Dortmund (jumper set) or at ETHZ (jumper not set)
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
19 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10121 r10123  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 11:57:15 26.01.2011
     5--          at - 09:36:36 27.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    4040-- Created:
    4141--          by - dneise.UNKNOWN (E5B-LABOR6)
    42 --          at - 11:57:15 26.01.2011
     42--          at - 09:36:36 27.01.2011
    4343--
    4444-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf

    r10121 r10123  
    3535
    3636# BOARD ID  - inputs
    37 NET POSITION_ID<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;             #ok  name was LINE befoer i changed it
    38 NET POSITION_ID<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;             #ok
    39 NET POSITION_ID<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;            #ok
    40 NET POSITION_ID<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;            #ok
    41 NET POSITION_ID<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;            #ok
    42 NET POSITION_ID<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;            #ok
     37NET LINE<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;            #ok 
     38NET LINE<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;            #ok
     39NET LINE<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;           #ok
     40NET LINE<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;           #ok
     41NET LINE<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;           #ok
     42NET LINE<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;           #ok
    4343
    4444# W5300
     
    138138NET D_T<4> LOC  = K5 | IOSTANDARD=LVCMOS25;                     #ok
    139139NET D_T<5> LOC  = L4 | IOSTANDARD=LVCMOS25;                     #ok
    140 NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;                     #ok
    141 NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;                     #ok
     140NET D_T_in<0> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                 #ok was: NET D_T<6> LOC  = M3
     141NET D_T_in<1> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                 #ok was: NET D_T<7> LOC  = T3
     142#NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;                    #ok
     143#NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;                    #ok
    142144NET D_T2<0> LOC  = U2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<8>
    143145NET D_T2<1> LOC  = V2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<9>
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak

    r10121 r10123  
    3535
    3636# BOARD ID  - inputs
    37 NET POSITION_ID<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;             #ok  name was LINE befoer i changed it
    38 NET POSITION_ID<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;             #ok
    39 NET POSITION_ID<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;            #ok
    40 NET POSITION_ID<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;            #ok
    41 NET POSITION_ID<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;            #ok
    42 NET POSITION_ID<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;            #ok
     37NET LINE<0> LOC  = Y1 | IOSTANDARD=LVCMOS33;            #ok 
     38NET LINE<1> LOC  = Y2 | IOSTANDARD=LVCMOS33;            #ok
     39NET LINE<2> LOC  = AB1 | IOSTANDARD=LVCMOS33;           #ok
     40NET LINE<3> LOC  = AC1 | IOSTANDARD=LVCMOS33;           #ok
     41NET LINE<4> LOC  = AD1 | IOSTANDARD=LVCMOS33;           #ok
     42NET LINE<5> LOC  = AD2 | IOSTANDARD=LVCMOS33;           #ok
    4343
    4444# W5300
     
    9999
    100100NET SRIN LOC  = E1 | IOSTANDARD=LVCMOS25;                       #ok -- nur fuer vollauslese noetig; auf Z legen.
    101 #NET REFCLK LOC  = AC11 | IOSTANDARD=LVCMOS25;          #ok -- listen to REFCLK possible
     101NET REFCLK LOC  = AC11 | IOSTANDARD=LVCMOS25;           #ok -- listen to REFCLK possible
    102102
    103103
     
    138138NET D_T<4> LOC  = K5 | IOSTANDARD=LVCMOS25;                     #ok
    139139NET D_T<5> LOC  = L4 | IOSTANDARD=LVCMOS25;                     #ok
    140 NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;                     #ok
    141 NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;                     #ok
     140#NET D_T_in<0> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                        #ok was: NET D_T<6> LOC  = M3
     141#NET D_T_in<1> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                        #ok was: NET D_T<7> LOC  = T3
     142NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                    #ok
     143NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                    #ok
    142144NET D_T2<0> LOC  = U2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<8>
    143145NET D_T2<1> LOC  = V2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<9>
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10121 r10123  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 16:46:19 26.01.2011
     5--          at - 17:58:59 27.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    1313ENTITY FAD_Board IS
    1414   PORT(
    15       A0_D        : IN     std_logic_vector (11 DOWNTO 0);
    16       A1_D        : IN     std_logic_vector (11 DOWNTO 0);
    17       A2_D        : IN     std_logic_vector (11 DOWNTO 0);
    18       A3_D        : IN     std_logic_vector (11 DOWNTO 0);
    19       A_OTR       : IN     std_logic_vector (3 DOWNTO 0);
    20       D0_SROUT    : IN     std_logic;
    21       D1_SROUT    : IN     std_logic;
    22       D2_SROUT    : IN     std_logic;
    23       D3_SROUT    : IN     std_logic;
    24       D_PLLLCK    : IN     std_logic_vector (3 DOWNTO 0);
    25       POSITION_ID : IN     std_logic_vector ( 5 DOWNTO 0 );
    26       REFCLK      : IN     std_logic;
    27       RS485_C_DI  : IN     std_logic;
    28       RS485_E_DI  : IN     std_logic;
    29       RS485_E_DO  : IN     std_logic;
    30       TRG         : IN     STD_LOGIC;
    31       W_INT       : IN     std_logic;
    32       X_50M       : IN     STD_LOGIC;
    33       A0_T        : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
    34       A1_T        : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    35       AMBER_LED   : OUT    std_logic;
    36       A_CLK       : OUT    std_logic_vector (3 DOWNTO 0);
    37       D0_SRCLK    : OUT    STD_LOGIC;
    38       D1_SRCLK    : OUT    STD_LOGIC;
    39       D2_SRCLK    : OUT    STD_LOGIC;
    40       D3_SRCLK    : OUT    STD_LOGIC;
    41       DAC_CS      : OUT    std_logic;
    42       DENABLE     : OUT    std_logic                     := '0';
    43       DWRITE      : OUT    std_logic                     := '0';
    44       D_A         : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    45       D_T         : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    46       D_T2        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    47       EE_CS       : OUT    std_logic;
    48       GREEN_LED   : OUT    std_logic;
    49       MOSI        : OUT    std_logic                     := '0';
    50       OE_ADC      : OUT    STD_LOGIC;
    51       RED_LED     : OUT    std_logic;
    52       RS485_C_DE  : OUT    std_logic;
    53       RS485_C_DO  : OUT    std_logic;
    54       RS485_C_RE  : OUT    std_logic;
    55       RS485_E_DE  : OUT    std_logic;
    56       RS485_E_RE  : OUT    std_logic;
    57       RSRLOAD     : OUT    std_logic                     := '0';
    58       SRIN        : OUT    std_logic                     := '0';
    59       S_CLK       : OUT    std_logic;
    60       T0_CS       : OUT    std_logic;
    61       T1_CS       : OUT    std_logic;
    62       T2_CS       : OUT    std_logic;
    63       T3_CS       : OUT    std_logic;
    64       TRG_V       : OUT    std_logic;
    65       W_A         : OUT    std_logic_vector (9 DOWNTO 0);
    66       W_CS        : OUT    std_logic                     := '1';
    67       W_RD        : OUT    std_logic                     := '1';
    68       W_RES       : OUT    std_logic                     := '1';
    69       W_WR        : OUT    std_logic                     := '1';
    70       MISO        : INOUT  std_logic;
    71       W_D         : INOUT  std_logic_vector (15 DOWNTO 0)
     15      A0_D       : IN     std_logic_vector (11 DOWNTO 0);
     16      A1_D       : IN     std_logic_vector (11 DOWNTO 0);
     17      A2_D       : IN     std_logic_vector (11 DOWNTO 0);
     18      A3_D       : IN     std_logic_vector (11 DOWNTO 0);
     19      A_OTR      : IN     std_logic_vector (3 DOWNTO 0);
     20      D0_SROUT   : IN     std_logic;
     21      D1_SROUT   : IN     std_logic;
     22      D2_SROUT   : IN     std_logic;
     23      D3_SROUT   : IN     std_logic;
     24      D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0);
     25      D_T_in     : IN     std_logic_vector (1 DOWNTO 0);
     26      LINE       : IN     std_logic_vector ( 5 DOWNTO 0 );
     27      REFCLK     : IN     std_logic;
     28      RS485_C_DI : IN     std_logic;
     29      RS485_E_DI : IN     std_logic;
     30      RS485_E_DO : IN     std_logic;
     31      TRG        : IN     STD_LOGIC;
     32      W_INT      : IN     std_logic;
     33      X_50M      : IN     STD_LOGIC;
     34      A0_T       : OUT    std_logic_vector (7 DOWNTO 0) := (others => '0');
     35      A1_T       : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     36      AMBER_LED  : OUT    std_logic;
     37      A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
     38      D0_SRCLK   : OUT    STD_LOGIC;
     39      D1_SRCLK   : OUT    STD_LOGIC;
     40      D2_SRCLK   : OUT    STD_LOGIC;
     41      D3_SRCLK   : OUT    STD_LOGIC;
     42      DAC_CS     : OUT    std_logic;
     43      DENABLE    : OUT    std_logic                     := '0';
     44      DWRITE     : OUT    std_logic                     := '0';
     45      D_A        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     46      D_T        : OUT    std_logic_vector (5 DOWNTO 0) := (OTHERS => '0');
     47      D_T2       : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     48      EE_CS      : OUT    std_logic;
     49      GREEN_LED  : OUT    std_logic;
     50      MOSI       : OUT    std_logic                     := '0';
     51      OE_ADC     : OUT    STD_LOGIC;
     52      RED_LED    : OUT    std_logic;
     53      RS485_C_DE : OUT    std_logic;
     54      RS485_C_DO : OUT    std_logic;
     55      RS485_C_RE : OUT    std_logic;
     56      RS485_E_DE : OUT    std_logic;
     57      RS485_E_RE : OUT    std_logic;
     58      RSRLOAD    : OUT    std_logic                     := '0';
     59      SRIN       : OUT    std_logic                     := '0';
     60      S_CLK      : OUT    std_logic;
     61      T0_CS      : OUT    std_logic;
     62      T1_CS      : OUT    std_logic;
     63      T2_CS      : OUT    std_logic;
     64      T3_CS      : OUT    std_logic;
     65      TRG_V      : OUT    std_logic;
     66      W_A        : OUT    std_logic_vector (9 DOWNTO 0);
     67      W_CS       : OUT    std_logic                     := '1';
     68      W_RD       : OUT    std_logic                     := '1';
     69      W_RES      : OUT    std_logic                     := '1';
     70      W_WR       : OUT    std_logic                     := '1';
     71      MISO       : INOUT  std_logic;
     72      W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
    7273   );
    7374
     
    8182-- Created:
    8283--          by - dneise.UNKNOWN (E5B-LABOR6)
    83 --          at - 16:46:20 26.01.2011
     84--          at - 17:58:59 27.01.2011
    8485--
    8586-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    120121   SIGNAL drs_channel_id  : std_logic_vector(3 DOWNTO 0) := (others => '0');
    121122   SIGNAL dummy           : std_logic;
     123   SIGNAL led             : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
    122124   SIGNAL ready           : std_logic                    := '0';
    123125   SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0);
     
    136138   PORT (
    137139      CLK                    : IN     std_logic ;
     140      D_T_in                 : IN     std_logic_vector (1 DOWNTO 0);
    138141      SROUT_in_0             : IN     std_logic ;
    139142      SROUT_in_1             : IN     std_logic ;
     
    198201   -- HDL Embedded Text Block 1 eb_ID
    199202   -- hard-wired IDs
    200    board_id <= "0101";
    201    crate_id <= "01";
     203   board_id <= LINE(5 downto 2);
     204   crate_id <= LINE(1 downto 0);
    202205
    203206   -- HDL Embedded Text Block 2 ADC_CLK
     
    243246   
    244247   EE_CS <= '1';
     248
     249   -- HDL Embedded Text Block 7 eb1
     250   D_T(5 downto 0) <= (others => '0');
    245251
    246252   -- HDL Embedded Text Block 8 eb2
     
    269275   A1_T(7) <= drs_channel_id(3);
    270276   
    271    A0_T(5 downto 0) <= POSITION_ID;
     277   A0_T(5 downto 0) <= (others => '0');
    272278   A0_T(6) <= REFCLK;
    273279   A0_T(7) <= RS485_E_DI;
     
    291297      PORT MAP (
    292298         CLK                    => X_50M,
     299         D_T_in                 => D_T_in,
    293300         SROUT_in_0             => D0_SROUT,
    294301         SROUT_in_1             => D1_SROUT,
     
    324331         drs_dwrite             => DWRITE,
    325332         green                  => RED_LED,
    326          led                    => D_T,
     333         led                    => led,
    327334         mosi                   => MOSI,
    328335         offset                 => OPEN,
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10121 r10123  
    1818  type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
    1919  type ip_type is array (0 to 3) of integer;
     20 
     21  type mac_list_type is array (0 to 2) of mac_type;
     22  type ip_list_type is array (0 to 2) of ip_type;
    2023-- Network Settings
    2124
    22   constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4");
     25  constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1);
     26  constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --???????????????
     27  constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); 
    2328 
    24   -- @ ETH zurich
    25 --   constant NETMASK : ip_type := (255, 255, 248, 0);
    26 --   constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
    27 --   constant GATEWAY : ip_type := (192, 33, 96, 1);
     29  constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0);
     30  constant CAM_NETMASK : ip_type := (255, 255, 248, 0);  --???????????????
     31  constant TUDO_NETMASK : ip_type := (255, 255, 255, 0);
    2832
    29   -- @ TU Dortmund
    30   constant NETMASK : ip_type := (255, 255, 255, 0);
    31   constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
    32   constant GATEWAY : ip_type := (129, 217, 160, 1);
     33  --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000");
     34  constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4");
     35  constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001");
     36  constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002");
     37 
     38  --constant IP_ZERO : ip_type := (0,0,0,0);
     39  constant IP_TUDO : ip_type := (129, 217, 160, 119);
     40  constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225);
     41  constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226);
     42  constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237);
     43
     44  -- IP lookup table used to convert CID,BID into IP, if not in camera.
     45  constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2);   
     46  constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2);
    3347
    3448  constant FIRST_PORT : integer := 5000;
     49  constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0);
     50  constant IP_offset : integer := 128;
     51  constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000");
    3552-- Network Settings End 
    3653 
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak

    r10121 r10123  
    1717
    1818  type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
     19  type mac_list_type is array (0 to 3) of mac_type;
    1920  type ip_type is array (0 to 3) of integer;
     21  type ip_list_type is array (0 to 3) of ip_type;
    2022-- Network Settings
    2123
    22   constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4");
     24  constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1);
     25  constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --???????????????
     26  constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); 
    2327 
    24   -- @ ETH zurich
    25 --   constant NETMASK : ip_type := (255, 255, 248, 0);
    26 --   constant IP_ADDRESS : ip_type := (192, 33, 99, 225);
    27 --   constant GATEWAY : ip_type := (192, 33, 96, 1);
     28  constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0);
     29  constant CAM_NETMASK : ip_type := (255, 255, 248, 0);  --???????????????
     30  constant TUDO_NETMASK : ip_type := (255, 255, 255, 0);
    2831
    29   -- @ TU Dortmund
    30   constant NETMASK : ip_type := (255, 255, 255, 0);
    31   constant IP_ADDRESS : ip_type := (129, 217, 160, 119);
    32   constant GATEWAY : ip_type := (129, 217, 160, 1);
     32  --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000");
     33  constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4");
     34  constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001");
     35  constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002");
     36 
     37  --constant IP_ZERO : ip_type := (0,0,0,0);
     38  constant IP_TUDO : ip_type := (129, 217, 160, 119);
     39  constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225);
     40  constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226);
     41  constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237);
     42
     43  -- IP lookup table used to convert CID,BID into IP, if not in camera.
     44  constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2);   
     45  constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2);
    3346
    3447  constant FIRST_PORT : integer := 5000;
     48  constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0);
     49  constant IP_offset : integer := 128;
     50  constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000");
    3551-- Network Settings End 
    3652 
     
    142158
    143159constant CMD_PS_RESET : std_logic_vector     := X"17";
     160
     161constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21";
     162
    144163-- DRS Registers
    145164  constant DRS_CONFIG_REG : std_logic_vector := "1100"; 
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10121 r10123  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 16:46:18 26.01.2011
     5--          at - 17:58:58 27.01.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    1919   PORT(
    2020      CLK                    : IN     std_logic;
     21      D_T_in                 : IN     std_logic_vector (1 DOWNTO 0);
    2122      SROUT_in_0             : IN     std_logic;
    2223      SROUT_in_1             : IN     std_logic;
     
    7980-- Created:
    8081--          by - dneise.UNKNOWN (E5B-LABOR6)
    81 --          at - 16:46:19 26.01.2011
     82--          at - 17:58:58 27.01.2011
    8283--
    8384-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    468469      -- --
    469470      config_busy       : IN     std_logic ;
     471      MAC_jumper        : IN     std_logic_vector (1 DOWNTO 0);
     472      BoardID           : IN     std_logic_vector (3 DOWNTO 0);
     473      CrateID           : IN     std_logic_vector (1 DOWNTO 0);
    470474      denable           : OUT    std_logic                      := '0';             -- default domino wave off
    471475      dwrite_enable     : OUT    std_logic                      := '0';             -- default DWRITE low.
     
    784788         config_rw_ready   => config_rw_ready,
    785789         config_busy       => config_busy,
     790         MAC_jumper        => D_T_in,
     791         BoardID           => board_id,
     792         CrateID           => crate_id,
    786793         denable           => denable,
    787794         dwrite_enable     => dwrite_enable,
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10121 r10123  
    6969      config_busy : in std_logic;
    7070     
    71 
     71      MAC_jumper : in std_logic_vector (1 downto 0);
     72      BoardID : in std_logic_vector (3 downto 0);
     73      CrateID : in std_logic_vector (1 downto 0);
    7274     
    7375      denable : out std_logic := '0'; -- default domino wave off
     
    9395
    9496type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
    95                          INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
     97                         INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
    9698                         SI, SI1, SI2, SI3, SI4, SI5, SI6,      ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
    9799type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
     
    152154signal data_valid_int : std_logic := '0';
    153155
     156signal FAD_in_cam : std_logic := '0';
     157signal FAD_at_ETHZ : std_logic := '0';
     158signal bid : std_logic_vector (3 downto 0);
     159signal cid : std_logic_vector (1 downto 0);
     160
     161
    154162-- only for debugging
    155163--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
     
    160168signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
    161169signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
     170
     171signal mac_loc : mac_type;
     172signal ip_loc : ip_type;
     173signal gateway_loc : ip_type;
     174signal netmask_loc : ip_type;
     175
    162176
    163177begin
     
    274288                                        -- Init
    275289                                        when INIT =>
     290                                          -- status of MAC jumpers is synched in
     291                                          -- and Board- and CrateID are synched in
     292                                          FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook
     293            FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was;
     294            bid <= BoardID;
     295            cid <= CrateID;
     296            --
    276297                                                par_addr <= W5300_MR;
    277298                                                par_data <= X"0000";
    278299                                                state_init <= WRITE_REG;
    279                                                 next_state <= IM;
     300                                                next_state <= LOCATE;
     301                                       
     302                                        when LOCATE =>                                   
     303                                          state_init <= IM;
     304                                         
     305                                          if (FAD_in_cam = '1') then
     306                                            -- if BID = "1111" and CID="11" then FAD is not really in cam
     307              -- back to INIT !! endless loop
     308              if (bid = "1111" and cid="11") then
     309               -- this should never happen!!!!!
     310               -- impossible to find this out, if in cam
     311                state_init <= INIT;
     312              else -- everything is fine
     313                -- IP & MAC are calculated from BID & CID
     314                -- code here
     315                gateway_loc <= CAM_GATEWAY;
     316                netmask_loc <= CAM_NETMASK;                                             
     317                mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1)  , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid)  , 16)   );
     318                ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) );
     319              end if;
     320                                          else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without.
     321                                            if ( FAD_at_ETHZ = '0' ) then
     322                                             -- easy FAD is at TUDO -> only one choice.
     323                                             mac_loc <= MAC_FAD0;
     324               ip_loc <= IP_TUDO;
     325               gateway_loc <= TUDO_GATEWAY;
     326               netmask_loc <= TUDO_NETMASK;
     327                                            else -- FAD is at ETHZ but not in cam --> IP lookup table is needed.
     328                                              if (bid = "1111" and cid="11") then -- FAD is not in crate
     329                  mac_loc <= MAC_FAD0;
     330                  ip_loc <= IP_ETHZ_FAD0;
     331                  gateway_loc <= ETHZ_GATEWAY;
     332                  netmask_loc <= ETHZ_NETMASK;                                         
     333                                              else
     334                                                -- FAD is at ETHZ and in crate:
     335                                                -- crate ID is not of importance.
     336                                                -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed.
     337                                                if ( conv_integer(bid) < MAC_LIST'length) then
     338                    gateway_loc <= ETHZ_GATEWAY;
     339                    netmask_loc <= ETHZ_NETMASK;                                               
     340                    mac_loc <= MAC_LIST(conv_integer(bid));
     341                                                ip_loc <= IP_LIST(conv_integer(bid));
     342                                                end if; -- conv_integer
     343                                              end if; -- bid=1111 & cid=11
     344                                            end if; --FAD_at_ETHZ = 0
     345                                          end if; --FAD_in_cam = 1
    280346                                               
    281347                                        -- Interrupt Mask
     
    336402                                        when MAC =>
    337403                                                par_addr <= W5300_SHAR;
    338                                                 par_data <= MAC_ADDRESS (0);
     404                                                par_data <= mac_loc(0);
    339405                                                state_init <= WRITE_REG;
    340406                                                next_state <= MAC1;
    341407                                        when MAC1 =>
    342408                                                par_addr <= W5300_SHAR + 2;
    343                                                 par_data <= MAC_ADDRESS (1);
     409                                                par_data <= mac_loc(1);
    344410                                                state_init <= WRITE_REG;
    345411                                                next_state <= MAC2;
    346412                                        when MAC2 =>
    347413                                                par_addr <= W5300_SHAR + 4;
    348                                                 par_data <= MAC_ADDRESS (2);
     414                                                par_data <= mac_loc(2);
    349415                                                state_init <= WRITE_REG;
    350416                                                next_state <= GW;
     
    353419                                        when GW =>
    354420                                                par_addr <= W5300_GAR;
    355                                                 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
    356                                                 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
     421                                                par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8);
     422                                                par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8);
    357423                                                state_init <= WRITE_REG;
    358424                                                next_state <= GW1;
    359425                                        when GW1 =>
    360426                                                par_addr <= W5300_GAR + 2;
    361                                                 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
    362                                                 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
     427                                                par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8);
     428                                                par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8);
    363429                                                state_init <= WRITE_REG;
    364430                                                next_state <= SNM;
     
    367433                                        when SNM =>
    368434                                                par_addr <= W5300_SUBR;
    369                                                 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
    370                                                 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
     435                                                par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8);
     436                                                par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8);
    371437                                                state_init <= WRITE_REG;
    372438                                                next_state <= SNM1;
    373439                                        when SNM1 =>
    374440                                                par_addr <= W5300_SUBR + 2;
    375                                                 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
    376                                                 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
     441                                                par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8);
     442                                                par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8);
    377443                                                state_init <= WRITE_REG;
    378444                                                next_state <= IP;
     
    380446                                        when IP =>
    381447                                                par_addr <= W5300_SIPR;
    382                                                 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
    383                                                 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
     448                                                par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);
     449                                                par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8);
    384450                                                state_init <= WRITE_REG;
    385451                                                next_state <= IP1;
    386452                                        when IP1 =>
    387453                                                par_addr <= W5300_SIPR + 2;
    388                                                 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
    389                                                 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
     454                                                par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8);
     455                                                par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8);
    390456                                                state_init <= WRITE_REG;
    391457                                                next_state <= SI;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak

    r10121 r10123  
    6969      config_busy : in std_logic;
    7070     
    71 
     71      MAC_jumper : in std_logic_vector (1 downto 0);
     72      BoardID : in std_logic_vector (3 downto 0);
     73      CrateID : in std_logic_vector (1 downto 0);
    7274     
    7375      denable : out std_logic := '0'; -- default domino wave off
     
    9395
    9496type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
    95                          INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
     97                         INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
    9698                         SI, SI1, SI2, SI3, SI4, SI5, SI6,      ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
    9799type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
     
    152154signal data_valid_int : std_logic := '0';
    153155
     156signal FAD_in_cam : std_logic := '0';
     157signal FAD_at_ETHZ : std_logic := '0';
     158signal bid : std_logic_vector (3 downto 0);
     159signal cid : std_logic_vector (1 downto 0);
     160
     161
    154162-- only for debugging
    155163--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
     
    160168signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending
    161169signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
     170
     171signal mac_loc : mac_type;
     172signal ip_loc : ip_type;
     173signal gateway_loc : ip_type;
     174signal netmask_loc : ip_type;
     175
    162176
    163177begin
     
    274288                                        -- Init
    275289                                        when INIT =>
     290                                          -- status of MAC jumpers is synched in
     291                                          -- and Board- and CrateID are synched in
     292                                          FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook
     293            FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was;
     294            bid <= BoardID;
     295            cid <= CrateID;
     296            --
    276297                                                par_addr <= W5300_MR;
    277298                                                par_data <= X"0000";
    278299                                                state_init <= WRITE_REG;
    279                                                 next_state <= IM;
     300                                                next_state <= LOCATE;
     301                                       
     302                                        when LOCATE =>                                   
     303                                          state_init <= IM;
     304                                         
     305                                          if (FAD_in_cam = '1') then
     306                                            -- if BID = "1111" and CID="11" then FAD is not really in cam
     307              -- back to INIT !! endless loop
     308              if (bid = "1111" and cid="11") then
     309               -- this should never happen!!!!!
     310               -- impossible to find this out, if in cam
     311                state_init <= INIT;
     312              else -- everything is fine
     313                -- IP & MAC are calculated from BID & CID
     314                -- code here
     315                gateway_loc <= CAM_GATEWAY;
     316                netmask_loc <= CAM_NETMASK;                                             
     317                mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1)  , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid)  , 16)   );
     318                ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) );
     319              end if;
     320                                          else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without.
     321                                            if ( FAD_at_ETHZ = '0' ) then
     322                                             -- easy FAD is at TUDO -> only one choice.
     323                                             mac_loc <= MAC_FAD0;
     324               ip_loc <= IP_TUDO;
     325               gateway_loc <= TUDO_GATEWAY;
     326               netmask_loc <= TUDO_NETMASK;
     327                                            else -- FAD is at ETHZ but not in cam --> IP lookup table is needed.
     328                                              if (bid = "1111" and cid="11") then -- FAD is not in crate
     329                  mac_loc <= MAC_FAD0;
     330                  ip_loc <= IP_ETHZ_FAD0;
     331                  gateway_loc <= ETHZ_GATEWAY;
     332                  netmask_loc <= ETHZ_NETMASK;                                         
     333                                              else
     334                                                -- FAD is at ETHZ and in crate:
     335                                                -- crate ID is not of importance.
     336                                                -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed.
     337                                                if ( conv_integer(bid) < MAC_LIST'length) then
     338                    gateway_loc <= ETHZ_GATEWAY;
     339                    netmask_loc <= ETHZ_NETMASK;                                               
     340                    mac_loc <= MAC_LIST(conv_integer(bid));
     341                                                ip_loc <= IP_LIST(conv_integer(bid));
     342                                                end if; -- conv_integer
     343                                              end if; -- bid=1111 & cid=11
     344                                            end if; --FAD_at_ETHZ = 0
     345                                          end if; --FAD_in_cam = 1
    280346                                               
    281347                                        -- Interrupt Mask
     
    336402                                        when MAC =>
    337403                                                par_addr <= W5300_SHAR;
    338                                                 par_data <= MAC_ADDRESS (0);
     404                                                par_data <= mac_loc(0);
    339405                                                state_init <= WRITE_REG;
    340406                                                next_state <= MAC1;
    341407                                        when MAC1 =>
    342408                                                par_addr <= W5300_SHAR + 2;
    343                                                 par_data <= MAC_ADDRESS (1);
     409                                                par_data <= mac_loc(1);
    344410                                                state_init <= WRITE_REG;
    345411                                                next_state <= MAC2;
    346412                                        when MAC2 =>
    347413                                                par_addr <= W5300_SHAR + 4;
    348                                                 par_data <= MAC_ADDRESS (2);
     414                                                par_data <= mac_loc(2);
    349415                                                state_init <= WRITE_REG;
    350416                                                next_state <= GW;
     
    353419                                        when GW =>
    354420                                                par_addr <= W5300_GAR;
    355                                                 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
    356                                                 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
     421                                                par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8);
     422                                                par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8);
    357423                                                state_init <= WRITE_REG;
    358424                                                next_state <= GW1;
    359425                                        when GW1 =>
    360426                                                par_addr <= W5300_GAR + 2;
    361                                                 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
    362                                                 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
     427                                                par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8);
     428                                                par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8);
    363429                                                state_init <= WRITE_REG;
    364430                                                next_state <= SNM;
     
    367433                                        when SNM =>
    368434                                                par_addr <= W5300_SUBR;
    369                                                 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
    370                                                 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
     435                                                par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8);
     436                                                par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8);
    371437                                                state_init <= WRITE_REG;
    372438                                                next_state <= SNM1;
    373439                                        when SNM1 =>
    374440                                                par_addr <= W5300_SUBR + 2;
    375                                                 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
    376                                                 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
     441                                                par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8);
     442                                                par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8);
    377443                                                state_init <= WRITE_REG;
    378444                                                next_state <= IP;
    379445                                        -- Own IP-Address
    380446                                        when IP =>
     447                                          led(0) <= '1';
     448          led(1) <= '1';
     449          led(2) <= '1';
     450
    381451                                                par_addr <= W5300_SIPR;
    382                                                 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
    383                                                 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
     452                                                par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);
     453                                                par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8);
    384454                                                state_init <= WRITE_REG;
    385455                                                next_state <= IP1;
    386456                                        when IP1 =>
    387457                                                par_addr <= W5300_SIPR + 2;
    388                                                 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
    389                                                 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
     458                                                par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8);
     459                                                par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8);
    390460                                                state_init <= WRITE_REG;
    391461                                                next_state <= SI;
     
    404474                                        -- Socket Init
    405475                                        when SI =>
     476                                          led(3) <= '1';
    406477                                                par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
    407478                                                par_data <= X"0101"; -- ALIGN, TCP
     
    435506                                                end if;
    436507                                        when SI6 =>
     508                                          led(4) <= '1';
    437509                                                par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
    438510                                                par_data <= X"0002"; -- LISTEN
     
    448520                                               
    449521                                        when ESTABLISH =>
     522                                          led(5) <= '1';
    450523                                          socks_waiting <= '1';
    451524            socks_connected <= '0';
     
    607680                      --trigger_stop <= '1';
    608681                      state_read_data <= RD_5;
     682                    when CMD_SET_TRIGGER_MULT =>
     683                      c_trigger_mult <= data_read (7 downto 0);
     684                      state_read_data <= RD_5;
     685
    609686                    -- phase shift commands here:
    610687                    when CMD_PS_DO =>
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

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     421DESIGN @f@a@d_main
     422VIEW struct.bd
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     424DESIGN @f@a@d_main
     425VIEW struct.bd
     426GRAPHIC 3888,0 193 0
     427DESIGN @f@a@d_main
     428VIEW struct.bd
     429NO_GRAPHIC 195
    427430LIBRARY FACT_FAD_lib
    428431DESIGN adc_buffer
    429432VIEW beha
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    431 DESIGN @f@a@d_main
    432 VIEW struct.bd
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    434 DESIGN @f@a@d_main
    435 VIEW struct.bd
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     433GRAPHIC 5678,0 197 0
     434DESIGN @f@a@d_main
     435VIEW struct.bd
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     437DESIGN @f@a@d_main
     438VIEW struct.bd
     439GRAPHIC 9175,0 206 0
    437440DESIGN clock_generator_var_ps
    438441VIEW symbol.sb
    439 GRAPHIC 168,0 207 0
     442GRAPHIC 168,0 208 0
    440443DESIGN clock_generator_var_ps
    441444VIEW symbol.sb
    442 GRAPHIC 848,0 208 0
     445GRAPHIC 848,0 209 0
    443446DESIGN clock_generator_var_ps
    444447VIEW symbol.sb
    445 GRAPHIC 703,0 209 0
     448GRAPHIC 703,0 210 0
    446449DESIGN clock_generator_var_ps
    447450VIEW symbol.sb
    448 GRAPHIC 698,0 210 0
     451GRAPHIC 698,0 211 0
    449452DESIGN clock_generator_var_ps
    450453VIEW symbol.sb
    451 GRAPHIC 126,0 211 0
     454GRAPHIC 126,0 212 0
    452455DESIGN clock_generator_var_ps
    453456VIEW symbol.sb
    454 GRAPHIC 643,0 212 0
     457GRAPHIC 643,0 213 0
    455458DESIGN clock_generator_var_ps
    456459VIEW symbol.sb
    457 GRAPHIC 121,0 213 0
     460GRAPHIC 121,0 214 0
    458461DESIGN clock_generator_var_ps
    459462VIEW symbol.sb
    460 GRAPHIC 481,0 214 0
     463GRAPHIC 481,0 215 0
    461464DESIGN clock_generator_var_ps
    462465VIEW symbol.sb
    463 GRAPHIC 544,0 215 0
     466GRAPHIC 544,0 216 0
    464467DESIGN clock_generator_var_ps
    465468VIEW symbol.sb
    466 GRAPHIC 524,0 216 0
     469GRAPHIC 524,0 217 0
    467470DESIGN clock_generator_var_ps
    468471VIEW symbol.sb
    469 GRAPHIC 539,0 217 0
     472GRAPHIC 539,0 218 0
    470473DESIGN clock_generator_var_ps
    471474VIEW symbol.sb
    472 GRAPHIC 534,0 218 0
     475GRAPHIC 534,0 219 0
    473476DESIGN clock_generator_var_ps
    474477VIEW symbol.sb
    475 GRAPHIC 475,0 219 0
     478GRAPHIC 475,0 220 0
    476479DESIGN clock_generator_var_ps
    477480VIEW symbol.sb
    478 GRAPHIC 463,0 220 0
     481GRAPHIC 463,0 221 0
    479482DESIGN clock_generator_var_ps
    480483VIEW symbol.sb
    481 GRAPHIC 469,0 221 0
    482 DESIGN @f@a@d_main
    483 VIEW struct.bd
    484 GRAPHIC 13117,0 225 0
    485 DESIGN @f@a@d_main
    486 VIEW struct.bd
    487 GRAPHIC 13124,0 226 1
    488 DESIGN @f@a@d_main
    489 VIEW struct.bd
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    491 DESIGN @f@a@d_main
    492 VIEW struct.bd
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     484GRAPHIC 469,0 222 0
     485DESIGN @f@a@d_main
     486VIEW struct.bd
     487GRAPHIC 13117,0 226 0
     488DESIGN @f@a@d_main
     489VIEW struct.bd
     490GRAPHIC 13124,0 227 1
     491DESIGN @f@a@d_main
     492VIEW struct.bd
     493NO_GRAPHIC 235
     494DESIGN @f@a@d_main
     495VIEW struct.bd
     496GRAPHIC 5072,0 237 0
    494497DESIGN control_unit
    495498VIEW symbol.sb
    496 GRAPHIC 130,0 238 0
     499GRAPHIC 130,0 239 0
    497500DESIGN control_unit
    498501VIEW symbol.sb
    499 GRAPHIC 135,0 239 0
     502GRAPHIC 135,0 240 0
    500503DESIGN control_unit
    501504VIEW symbol.sb
    502 GRAPHIC 170,0 240 0
     505GRAPHIC 170,0 241 0
    503506DESIGN control_unit
    504507VIEW symbol.sb
    505 GRAPHIC 175,0 241 0
     508GRAPHIC 175,0 242 0
    506509DESIGN control_unit
    507510VIEW symbol.sb
    508 GRAPHIC 160,0 242 0
     511GRAPHIC 160,0 243 0
    509512DESIGN control_unit
    510513VIEW symbol.sb
    511 GRAPHIC 145,0 243 0
     514GRAPHIC 145,0 244 0
    512515DESIGN control_unit
    513516VIEW symbol.sb
    514 GRAPHIC 140,0 244 0
     517GRAPHIC 140,0 245 0
    515518DESIGN control_unit
    516519VIEW symbol.sb
    517 GRAPHIC 180,0 245 0
     520GRAPHIC 180,0 246 0
    518521DESIGN control_unit
    519522VIEW symbol.sb
    520 GRAPHIC 558,0 246 0
     523GRAPHIC 558,0 247 0
    521524DESIGN control_unit
    522525VIEW symbol.sb
    523 GRAPHIC 564,0 248 0
     526GRAPHIC 564,0 249 0
    524527DESIGN control_unit
    525528VIEW symbol.sb
    526 GRAPHIC 350,0 250 0
     529GRAPHIC 350,0 251 0
    527530DESIGN control_unit
    528531VIEW symbol.sb
    529 GRAPHIC 165,0 251 0
     532GRAPHIC 165,0 252 0
    530533DESIGN control_unit
    531534VIEW symbol.sb
    532 GRAPHIC 155,0 252 0
     535GRAPHIC 155,0 253 0
    533536DESIGN control_unit
    534537VIEW symbol.sb
    535 GRAPHIC 150,0 253 0
    536 DESIGN @f@a@d_main
    537 VIEW struct.bd
    538 GRAPHIC 8277,0 256 0
     538GRAPHIC 150,0 254 0
     539DESIGN @f@a@d_main
     540VIEW struct.bd
     541GRAPHIC 8277,0 257 0
    539542DESIGN data@r@a@m_64b_16b_width14_5
    540543VIEW data@r@a@m_64b_16b_width14_5_a
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     544GRAPHIC 48,0 259 0
    542545DESIGN data@r@a@m_64b_16b_width14_5
    543546VIEW data@r@a@m_64b_16b_width14_5_a
    544 GRAPHIC 53,0 259 0
     547GRAPHIC 53,0 260 0
    545548DESIGN data@r@a@m_64b_16b_width14_5
    546549VIEW data@r@a@m_64b_16b_width14_5_a
    547 GRAPHIC 58,0 260 0
     550GRAPHIC 58,0 261 0
    548551DESIGN data@r@a@m_64b_16b_width14_5
    549552VIEW data@r@a@m_64b_16b_width14_5_a
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     553GRAPHIC 63,0 262 0
    551554DESIGN data@r@a@m_64b_16b_width14_5
    552555VIEW data@r@a@m_64b_16b_width14_5_a
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     556GRAPHIC 68,0 263 0
    554557DESIGN data@r@a@m_64b_16b_width14_5
    555558VIEW data@r@a@m_64b_16b_width14_5_a
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     559GRAPHIC 73,0 264 0
    557560DESIGN data@r@a@m_64b_16b_width14_5
    558561VIEW data@r@a@m_64b_16b_width14_5_a
    559 GRAPHIC 78,0 264 0
    560 DESIGN @f@a@d_main
    561 VIEW struct.bd
    562 GRAPHIC 1399,0 267 0
    563 DESIGN data_generator
    564 VIEW symbol.sb
    565 GRAPHIC 14,0 268 1
    566 DESIGN data_generator
    567 VIEW @behavioral
    568 GRAPHIC 48,0 272 0
    569 DESIGN data_generator
    570 VIEW @behavioral
    571 GRAPHIC 53,0 274 0
    572 DESIGN data_generator
    573 VIEW @behavioral
    574 GRAPHIC 58,0 275 0
    575 DESIGN data_generator
    576 VIEW @behavioral
    577 GRAPHIC 73,0 276 0
    578 DESIGN data_generator
    579 VIEW @behavioral
    580 GRAPHIC 78,0 277 0
    581 DESIGN data_generator
    582 VIEW @behavioral
    583 GRAPHIC 402,0 278 0
    584 DESIGN data_generator
    585 VIEW @behavioral
    586 GRAPHIC 407,0 279 0
    587 DESIGN data_generator
    588 VIEW @behavioral
    589 GRAPHIC 1479,0 280 0
    590 DESIGN data_generator
    591 VIEW @behavioral
    592 GRAPHIC 1122,0 282 0
    593 DESIGN data_generator
    594 VIEW @behavioral
    595 GRAPHIC 963,0 284 0
    596 DESIGN data_generator
    597 VIEW @behavioral
    598 GRAPHIC 1127,0 286 0
    599 DESIGN data_generator
    600 VIEW @behavioral
    601 GRAPHIC 1048,0 288 0
    602 DESIGN data_generator
    603 VIEW @behavioral
    604 GRAPHIC 958,0 289 0
    605 DESIGN data_generator
    606 VIEW @behavioral
    607 GRAPHIC 1053,0 290 0
    608 DESIGN data_generator
    609 VIEW @behavioral
    610 GRAPHIC 1201,0 291 0
    611 DESIGN data_generator
    612 VIEW @behavioral
    613 GRAPHIC 1196,0 292 0
    614 DESIGN data_generator
    615 VIEW @behavioral
    616 GRAPHIC 1206,0 293 0
    617 DESIGN data_generator
    618 VIEW @behavioral
    619 GRAPHIC 473,0 294 0
    620 DESIGN data_generator
    621 VIEW @behavioral
    622 GRAPHIC 412,0 295 0
    623 DESIGN data_generator
    624 VIEW @behavioral
    625 GRAPHIC 1085,0 296 0
    626 DESIGN data_generator
    627 VIEW @behavioral
    628 GRAPHIC 1090,0 297 0
    629 DESIGN data_generator
    630 VIEW @behavioral
    631 GRAPHIC 1240,0 298 0
    632 DESIGN data_generator
    633 VIEW @behavioral
    634 GRAPHIC 526,0 299 0
    635 DESIGN data_generator
    636 VIEW @behavioral
    637 GRAPHIC 88,0 300 0
    638 DESIGN data_generator
    639 VIEW @behavioral
    640 GRAPHIC 285,0 301 0
    641 DESIGN data_generator
    642 VIEW @behavioral
    643 GRAPHIC 93,0 302 0
    644 DESIGN data_generator
    645 VIEW @behavioral
    646 GRAPHIC 98,0 303 0
    647 DESIGN data_generator
    648 VIEW @behavioral
    649 GRAPHIC 1164,0 304 0
    650 DESIGN data_generator
    651 VIEW @behavioral
    652 GRAPHIC 1159,0 306 0
    653 DESIGN data_generator
    654 VIEW @behavioral
    655 GRAPHIC 898,0 307 0
    656 DESIGN data_generator
    657 VIEW @behavioral
    658 GRAPHIC 637,0 308 0
    659 DESIGN data_generator
    660 VIEW @behavioral
    661 GRAPHIC 1395,0 309 0
    662 DESIGN data_generator
    663 VIEW @behavioral
    664 GRAPHIC 1427,0 310 0
    665 DESIGN data_generator
    666 VIEW @behavioral
    667 GRAPHIC 676,0 311 0
    668 DESIGN data_generator
    669 VIEW @behavioral
    670 GRAPHIC 1551,0 312 0
    671 DESIGN data_generator
    672 VIEW @behavioral
    673 GRAPHIC 1583,0 315 0
    674 DESIGN data_generator
    675 VIEW @behavioral
    676 GRAPHIC 681,0 316 0
    677 DESIGN data_generator
    678 VIEW @behavioral
    679 GRAPHIC 801,0 318 0
    680 DESIGN data_generator
    681 VIEW @behavioral
    682 GRAPHIC 1464,0 320 0
    683 DESIGN data_generator
    684 VIEW @behavioral
    685 GRAPHIC 1469,0 321 0
    686 DESIGN data_generator
    687 VIEW @behavioral
    688 GRAPHIC 1459,0 322 0
    689 DESIGN data_generator
    690 VIEW @behavioral
    691 GRAPHIC 1474,0 323 0
    692 DESIGN data_generator
    693 VIEW @behavioral
    694 GRAPHIC 806,0 324 0
    695 DESIGN data_generator
    696 VIEW @behavioral
    697 GRAPHIC 811,0 325 0
    698 DESIGN data_generator
    699 VIEW @behavioral
    700 GRAPHIC 1519,0 326 0
    701 DESIGN @f@a@d_main
    702 VIEW struct.bd
    703 GRAPHIC 4903,0 329 0
    704 DESIGN @f@a@d_main
    705 VIEW struct.bd
    706 NO_GRAPHIC 347
    707 DESIGN @f@a@d_main
    708 VIEW struct.bd
    709 GRAPHIC 11209,0 349 0
    710 DESIGN @f@a@d_main
    711 VIEW struct.bd
    712 GRAPHIC 11216,0 350 1
    713 DESIGN @f@a@d_main
    714 VIEW struct.bd
    715 NO_GRAPHIC 364
    716 DESIGN @f@a@d_main
    717 VIEW struct.bd
    718 GRAPHIC 2311,0 366 0
    719 DESIGN memory_manager
    720 VIEW symbol.sb
    721 GRAPHIC 14,0 367 1
    722 DESIGN memory_manager
    723 VIEW beha
    724 GRAPHIC 138,0 372 0
    725 DESIGN memory_manager
    726 VIEW beha
    727 GRAPHIC 194,0 373 0
    728 DESIGN memory_manager
    729 VIEW beha
    730 GRAPHIC 349,0 374 0
    731 DESIGN memory_manager
    732 VIEW beha
    733 GRAPHIC 949,0 375 0
    734 DESIGN memory_manager
    735 VIEW beha
    736 GRAPHIC 569,0 377 0
    737 DESIGN memory_manager
    738 VIEW beha
    739 GRAPHIC 224,0 379 0
    740 DESIGN memory_manager
    741 VIEW beha
    742 GRAPHIC 254,0 380 0
    743 DESIGN memory_manager
    744 VIEW beha
    745 GRAPHIC 804,0 381 0
    746 DESIGN memory_manager
    747 VIEW beha
    748 GRAPHIC 433,0 382 0
    749 DESIGN memory_manager
    750 VIEW beha
    751 GRAPHIC 622,0 383 0
    752 DESIGN memory_manager
    753 VIEW beha
    754 GRAPHIC 289,0 384 0
    755 DESIGN memory_manager
    756 VIEW beha
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    758 DESIGN memory_manager
    759 VIEW beha
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    761 DESIGN memory_manager
    762 VIEW beha
    763 GRAPHIC 294,0 387 0
    764 DESIGN memory_manager
    765 VIEW beha
    766 GRAPHIC 304,0 388 0
    767 DESIGN memory_manager
    768 VIEW beha
    769 GRAPHIC 299,0 389 0
    770 DESIGN memory_manager
    771 VIEW beha
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    773 DESIGN memory_manager
    774 VIEW beha
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    776 DESIGN memory_manager
    777 VIEW beha
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    779 DESIGN @f@a@d_main
    780 VIEW struct.bd
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     562GRAPHIC 78,0 265 0
     563DESIGN @f@a@d_main
     564VIEW struct.bd
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     566DESIGN data_generator
     567VIEW symbol.sb
     568GRAPHIC 14,0 269 1
     569DESIGN data_generator
     570VIEW @behavioral
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     572DESIGN data_generator
     573VIEW @behavioral
     574GRAPHIC 53,0 275 0
     575DESIGN data_generator
     576VIEW @behavioral
     577GRAPHIC 58,0 276 0
     578DESIGN data_generator
     579VIEW @behavioral
     580GRAPHIC 73,0 277 0
     581DESIGN data_generator
     582VIEW @behavioral
     583GRAPHIC 78,0 278 0
     584DESIGN data_generator
     585VIEW @behavioral
     586GRAPHIC 402,0 279 0
     587DESIGN data_generator
     588VIEW @behavioral
     589GRAPHIC 407,0 280 0
     590DESIGN data_generator
     591VIEW @behavioral
     592GRAPHIC 1479,0 281 0
     593DESIGN data_generator
     594VIEW @behavioral
     595GRAPHIC 1122,0 283 0
     596DESIGN data_generator
     597VIEW @behavioral
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     599DESIGN data_generator
     600VIEW @behavioral
     601GRAPHIC 1127,0 287 0
     602DESIGN data_generator
     603VIEW @behavioral
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     605DESIGN data_generator
     606VIEW @behavioral
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     608DESIGN data_generator
     609VIEW @behavioral
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     611DESIGN data_generator
     612VIEW @behavioral
     613GRAPHIC 1201,0 292 0
     614DESIGN data_generator
     615VIEW @behavioral
     616GRAPHIC 1196,0 293 0
     617DESIGN data_generator
     618VIEW @behavioral
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     620DESIGN data_generator
     621VIEW @behavioral
     622GRAPHIC 473,0 295 0
     623DESIGN data_generator
     624VIEW @behavioral
     625GRAPHIC 412,0 296 0
     626DESIGN data_generator
     627VIEW @behavioral
     628GRAPHIC 1085,0 297 0
     629DESIGN data_generator
     630VIEW @behavioral
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     632DESIGN data_generator
     633VIEW @behavioral
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     635DESIGN data_generator
     636VIEW @behavioral
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     638DESIGN data_generator
     639VIEW @behavioral
     640GRAPHIC 88,0 301 0
     641DESIGN data_generator
     642VIEW @behavioral
     643GRAPHIC 285,0 302 0
     644DESIGN data_generator
     645VIEW @behavioral
     646GRAPHIC 93,0 303 0
     647DESIGN data_generator
     648VIEW @behavioral
     649GRAPHIC 98,0 304 0
     650DESIGN data_generator
     651VIEW @behavioral
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     653DESIGN data_generator
     654VIEW @behavioral
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     656DESIGN data_generator
     657VIEW @behavioral
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     659DESIGN data_generator
     660VIEW @behavioral
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     662DESIGN data_generator
     663VIEW @behavioral
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     665DESIGN data_generator
     666VIEW @behavioral
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     668DESIGN data_generator
     669VIEW @behavioral
     670GRAPHIC 676,0 312 0
     671DESIGN data_generator
     672VIEW @behavioral
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     674DESIGN data_generator
     675VIEW @behavioral
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     677DESIGN data_generator
     678VIEW @behavioral
     679GRAPHIC 681,0 317 0
     680DESIGN data_generator
     681VIEW @behavioral
     682GRAPHIC 801,0 319 0
     683DESIGN data_generator
     684VIEW @behavioral
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     686DESIGN data_generator
     687VIEW @behavioral
     688GRAPHIC 1469,0 322 0
     689DESIGN data_generator
     690VIEW @behavioral
     691GRAPHIC 1459,0 323 0
     692DESIGN data_generator
     693VIEW @behavioral
     694GRAPHIC 1474,0 324 0
     695DESIGN data_generator
     696VIEW @behavioral
     697GRAPHIC 806,0 325 0
     698DESIGN data_generator
     699VIEW @behavioral
     700GRAPHIC 811,0 326 0
     701DESIGN data_generator
     702VIEW @behavioral
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     704DESIGN @f@a@d_main
     705VIEW struct.bd
     706GRAPHIC 4903,0 330 0
     707DESIGN @f@a@d_main
     708VIEW struct.bd
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     710DESIGN @f@a@d_main
     711VIEW struct.bd
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     713DESIGN @f@a@d_main
     714VIEW struct.bd
     715GRAPHIC 11216,0 351 1
     716DESIGN @f@a@d_main
     717VIEW struct.bd
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     719DESIGN @f@a@d_main
     720VIEW struct.bd
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     722DESIGN memory_manager
     723VIEW symbol.sb
     724GRAPHIC 14,0 368 1
     725DESIGN memory_manager
     726VIEW beha
     727GRAPHIC 138,0 373 0
     728DESIGN memory_manager
     729VIEW beha
     730GRAPHIC 194,0 374 0
     731DESIGN memory_manager
     732VIEW beha
     733GRAPHIC 349,0 375 0
     734DESIGN memory_manager
     735VIEW beha
     736GRAPHIC 949,0 376 0
     737DESIGN memory_manager
     738VIEW beha
     739GRAPHIC 569,0 378 0
     740DESIGN memory_manager
     741VIEW beha
     742GRAPHIC 224,0 380 0
     743DESIGN memory_manager
     744VIEW beha
     745GRAPHIC 254,0 381 0
     746DESIGN memory_manager
     747VIEW beha
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     749DESIGN memory_manager
     750VIEW beha
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     752DESIGN memory_manager
     753VIEW beha
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     755DESIGN memory_manager
     756VIEW beha
     757GRAPHIC 289,0 385 0
     758DESIGN memory_manager
     759VIEW beha
     760GRAPHIC 309,0 386 0
     761DESIGN memory_manager
     762VIEW beha
     763GRAPHIC 284,0 387 0
     764DESIGN memory_manager
     765VIEW beha
     766GRAPHIC 294,0 388 0
     767DESIGN memory_manager
     768VIEW beha
     769GRAPHIC 304,0 389 0
     770DESIGN memory_manager
     771VIEW beha
     772GRAPHIC 299,0 390 0
     773DESIGN memory_manager
     774VIEW beha
     775GRAPHIC 379,0 391 0
     776DESIGN memory_manager
     777VIEW beha
     778GRAPHIC 915,0 392 0
     779DESIGN memory_manager
     780VIEW beha
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     782DESIGN @f@a@d_main
     783VIEW struct.bd
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    782785DESIGN spi_interface
    783786VIEW symbol.sb
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     787GRAPHIC 1121,0 398 0
    785788DESIGN spi_interface
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    788791DESIGN spi_interface
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    791794DESIGN spi_interface
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    797800DESIGN spi_interface
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     1715NO_GRAPHIC 808
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r10121 r10123  
    9191number "9"
    9292)
     93(EmbeddedInstance
     94name "eb1"
     95number "7"
     96)
    9397]
    9498libraryRefs [
     
    105109(vvPair
    106110variable "HDLDir"
    107 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
     111value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
    108112)
    109113(vvPair
    110114variable "HDSDir"
    111 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
     115value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    112116)
    113117(vvPair
    114118variable "SideDataDesignDir"
    115 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     119value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    116120)
    117121(vvPair
    118122variable "SideDataUserDir"
    119 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     123value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    120124)
    121125(vvPair
    122126variable "SourceDir"
    123 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
     127value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
    124128)
    125129(vvPair
     
    137141(vvPair
    138142variable "d"
    139 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     143value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    140144)
    141145(vvPair
    142146variable "d_logical"
    143 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
     147value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"
    144148)
    145149(vvPair
    146150variable "date"
    147 value "26.01.2011"
     151value "27.01.2011"
    148152)
    149153(vvPair
    150154variable "day"
    151 value "Mi"
     155value "Do"
    152156)
    153157(vvPair
    154158variable "day_long"
    155 value "Mittwoch"
     159value "Donnerstag"
    156160)
    157161(vvPair
    158162variable "dd"
    159 value "26"
     163value "27"
    160164)
    161165(vvPair
     
    233237(vvPair
    234238variable "p"
    235 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     239value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    236240)
    237241(vvPair
    238242variable "p_logical"
    239 value "C:\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     243value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    240244)
    241245(vvPair
     
    293297(vvPair
    294298variable "time"
    295 value "11:50:58"
     299value "17:58:52"
    296300)
    297301(vvPair
     
    684688n "wiz_reset"
    685689t "std_logic"
    686 o 46
     690o 47
    687691suid 2,0
    688692i "'1'"
     
    723727b "(7 DOWNTO 0)"
    724728posAdd 0
    725 o 35
     729o 36
    726730suid 7,0
    727731i "(OTHERS => '0')"
     
    760764preAdd 0
    761765posAdd 0
    762 o 10
     766o 11
    763767suid 18,0
    764768)
     
    795799n "adc_oeb"
    796800t "std_logic"
    797 o 27
     801o 28
    798802suid 21,0
    799803i "'1'"
     
    833837preAdd 0
    834838posAdd 0
    835 o 8
     839o 9
    836840suid 24,0
    837841)
     
    868872t "std_logic_vector"
    869873b "(1 downto 0)"
    870 o 9
     874o 10
    871875suid 25,0
    872876)
     
    905909t "std_logic_vector"
    906910b "(9 DOWNTO 0)"
    907 o 43
     911o 44
    908912suid 26,0
    909913)
     
    941945n "wiz_cs"
    942946t "std_logic"
    943 o 44
     947o 45
    944948suid 28,0
    945949i "'1'"
     
    979983t "std_logic_vector"
    980984b "(15 DOWNTO 0)"
    981 o 49
     985o 50
    982986suid 27,0
    983987)
     
    10141018n "wiz_int"
    10151019t "std_logic"
    1016 o 11
     1020o 12
    10171021suid 31,0
    10181022)
     
    10501054n "wiz_rd"
    10511055t "std_logic"
    1052 o 45
     1056o 46
    10531057suid 30,0
    10541058i "'1'"
     
    10871091n "wiz_wr"
    10881092t "std_logic"
    1089 o 47
     1093o 48
    10901094suid 29,0
    10911095i "'1'"
     
    11231127n "CLK_25_PS"
    11241128t "std_logic"
    1125 o 15
     1129o 16
    11261130suid 35,0
    11271131)
     
    11581162n "CLK_50"
    11591163t "std_logic"
    1160 o 16
     1164o 17
    11611165suid 37,0
    11621166)
     
    12261230n "adc_data_array"
    12271231t "adc_data_array_type"
    1228 o 6
     1232o 7
    12291233suid 39,0
    12301234)
     
    12611265t "std_logic_vector"
    12621266b "(3 DOWNTO 0)"
    1263 o 7
     1267o 8
    12641268suid 40,0
    12651269)
     
    12971301t "std_logic_vector"
    12981302b "(3 downto 0)"
    1299 o 32
     1303o 33
    13001304suid 48,0
    13011305i "(others => '0')"
     
    13331337n "drs_dwrite"
    13341338t "std_logic"
    1335 o 33
     1339o 34
    13361340suid 49,0
    13371341i "'1'"
     
    13681372n "SROUT_in_0"
    13691373t "std_logic"
    1370 o 2
     1374o 3
    13711375suid 42,0
    13721376)
     
    14021406n "SROUT_in_1"
    14031407t "std_logic"
    1404 o 3
     1408o 4
    14051409suid 43,0
    14061410)
     
    14361440n "SROUT_in_2"
    14371441t "std_logic"
    1438 o 4
     1442o 5
    14391443suid 44,0
    14401444)
     
    14701474n "SROUT_in_3"
    14711475t "std_logic"
    1472 o 5
     1476o 6
    14731477suid 45,0
    14741478)
     
    15051509n "RSRLOAD"
    15061510t "std_logic"
    1507 o 23
     1511o 24
    15081512suid 56,0
    15091513i "'0'"
     
    15411545n "SRCLK"
    15421546t "std_logic"
    1543 o 24
     1547o 25
    15441548suid 57,0
    15451549i "'0'"
     
    15781582n "dac_cs"
    15791583t "std_logic"
    1580 o 30
     1584o 31
    15811585suid 64,0
    15821586)
     
    16141618n "sclk"
    16151619t "std_logic"
    1616 o 40
     1620o 41
    16171621suid 62,0
    16181622)
     
    16511655t "std_logic_vector"
    16521656b "(3 DOWNTO 0)"
    1653 o 41
     1657o 42
    16541658suid 65,0
    16551659)
     
    16891693preAdd 0
    16901694posAdd 0
    1691 o 48
     1695o 49
    16921696suid 63,0
    16931697)
     
    17251729n "mosi"
    17261730t "std_logic"
    1727 o 36
     1731o 37
    17281732suid 66,0
    17291733i "'0'"
     
    17641768eolc "-- default domino wave off"
    17651769posAdd 0
    1766 o 31
     1770o 32
    17671771suid 67,0
    17681772i "'0'"
     
    18001804n "adc_clk_en"
    18011805t "std_logic"
    1802 o 26
     1806o 27
    18031807suid 69,0
    18041808i "'0'"
     
    18391843preAdd 0
    18401844posAdd 0
    1841 o 17
     1845o 18
    18421846suid 76,0
    18431847)
     
    18751879n "LOCKED_extraOUT"
    18761880t "std_logic"
    1877 o 18
     1881o 19
    18781882suid 70,0
    18791883)
     
    19141918preAdd 0
    19151919posAdd 0
    1916 o 37
     1920o 38
    19171921suid 77,0
    19181922i "(OTHERS => '0')"
     
    19511955n "PS_DIR_IN"
    19521956t "std_logic"
    1953 o 22
     1957o 23
    19541958suid 80,0
    19551959)
     
    19871991n "PSCLK_OUT"
    19881992t "std_logic"
    1989 o 19
     1993o 20
    19901994suid 74,0
    19911995)
     
    20232027n "PSDONE_extraOUT"
    20242028t "std_logic"
    2025 o 20
     2029o 21
    20262030suid 71,0
    20272031)
     
    20592063n "PSINCDEC_OUT"
    20602064t "std_logic"
    2061 o 21
     2065o 22
    20622066suid 72,0
    20632067)
     
    20972101preAdd 0
    20982102posAdd 0
    2099 o 38
     2103o 39
    21002104suid 79,0
    21012105i "'0'"
     
    21372141preAdd 0
    21382142posAdd 0
    2139 o 42
     2143o 43
    21402144suid 78,0
    21412145i "'0'"
     
    21742178n "CLK25_OUT"
    21752179t "std_logic"
    2176 o 12
     2180o 13
    21772181suid 83,0
    21782182)
     
    22102214n "CLK25_PSOUT"
    22112215t "std_logic"
    2212 o 13
     2216o 14
    22132217suid 84,0
    22142218)
     
    22462250n "CLK50_OUT"
    22472251t "std_logic"
    2248 o 14
     2252o 15
    22492253suid 82,0
    22502254)
     
    22822286n "SRIN_out"
    22832287t "std_logic"
    2284 o 25
     2288o 26
    22852289suid 85,0
    22862290i "'0'"
     
    23192323n "amber"
    23202324t "std_logic"
    2321 o 29
     2325o 30
    23222326suid 87,0
    23232327)
     
    23552359n "green"
    23562360t "std_logic"
    2357 o 34
     2361o 35
    23582362suid 86,0
    23592363)
     
    23912395n "red"
    23922396t "std_logic"
    2393 o 39
     2397o 40
    23942398suid 88,0
    23952399)
     
    24272431n "additional_flasher_out"
    24282432t "std_logic"
    2429 o 28
     2433o 29
    24302434suid 90,0
     2435)
     2436)
     2437)
     2438*62 (CptPort
     2439uid 14682,0
     2440ps "OnEdgeStrategy"
     2441shape (Triangle
     2442uid 14683,0
     2443ro 90
     2444va (VaSet
     2445vasetType 1
     2446fg "0,65535,0"
     2447)
     2448xt "51250,138625,52000,139375"
     2449)
     2450tg (CPTG
     2451uid 14684,0
     2452ps "CptPortTextPlaceStrategy"
     2453stg "VerticalLayoutStrategy"
     2454f (Text
     2455uid 14685,0
     2456va (VaSet
     2457)
     2458xt "53000,138500,58500,139500"
     2459st "D_T_in : (1:0)"
     2460blo "53000,139300"
     2461)
     2462)
     2463thePort (LogicalPort
     2464decl (Decl
     2465n "D_T_in"
     2466t "std_logic_vector"
     2467b "(1 DOWNTO 0)"
     2468o 2
     2469suid 91,0
    24312470)
    24322471)
     
    24492488stg "VerticalLayoutStrategy"
    24502489textVec [
    2451 *62 (Text
     2490*63 (Text
    24522491uid 172,0
    24532492va (VaSet
     
    24592498tm "BdLibraryNameMgr"
    24602499)
    2461 *63 (Text
     2500*64 (Text
    24622501uid 173,0
    24632502va (VaSet
     
    24692508tm "CptNameMgr"
    24702509)
    2471 *64 (Text
     2510*65 (Text
    24722511uid 174,0
    24732512va (VaSet
     
    25212560archFileType "UNKNOWN"
    25222561)
    2523 *65 (PortIoIn
     2562*66 (PortIoIn
    25242563uid 231,0
    25252564shape (CompositeShape
     
    25662605)
    25672606)
    2568 *66 (PortIoIn
     2607*67 (PortIoIn
    25692608uid 251,0
    25702609shape (CompositeShape
     
    26112650)
    26122651)
    2613 *67 (HdlText
     2652*68 (HdlText
    26142653uid 265,0
    26152654optionalChildren [
    2616 *68 (EmbeddedText
     2655*69 (EmbeddedText
    26172656uid 271,0
    26182657commentText (CommentText
     
    26342673va (VaSet
    26352674)
    2636 xt "32200,83200,39700,86200"
     2675xt "32200,83200,43700,86200"
    26372676st "
    26382677-- hard-wired IDs
    2639 board_id <= \"0101\";
    2640 crate_id <= \"01\";
     2678board_id <= LINE(5 downto 2);
     2679crate_id <= LINE(1 downto 0);
    26412680"
    26422681tm "HdlTextMgr"
     
    26642703stg "VerticalLayoutStrategy"
    26652704textVec [
    2666 *69 (Text
     2705*70 (Text
    26672706uid 268,0
    26682707va (VaSet
     
    26742713tm "HdlTextNameMgr"
    26752714)
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     2715*71 (Text
    26772716uid 269,0
    26782717va (VaSet
     
    27002739viewiconposition 0
    27012740)
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     2741*72 (Net
    27032742uid 275,0
    27042743decl (Decl
     
    27162755font "Courier New,8,0"
    27172756)
    2718 xt "39000,62400,67500,63200"
    2719 st "SIGNAL board_id        : std_logic_vector(3 downto 0)
    2720 "
    2721 )
    2722 )
    2723 *72 (Net
     2757xt "39000,63200,67500,64000"
     2758st "SIGNAL board_id        : std_logic_vector(3 downto 0)"
     2759)
     2760)
     2761*73 (Net
    27242762uid 283,0
    27252763decl (Decl
     
    27352773font "Courier New,8,0"
    27362774)
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    2738 st "SIGNAL crate_id        : std_logic_vector(1 downto 0)
    2739 "
    2740 )
    2741 )
    2742 *73 (PortIoOut
     2775xt "39000,64000,67500,64800"
     2776st "SIGNAL crate_id        : std_logic_vector(1 downto 0)"
     2777)
     2778)
     2779*74 (PortIoOut
    27432780uid 472,0
    27442781shape (CompositeShape
     
    27842821)
    27852822)
    2786 *74 (PortIoOut
     2823*75 (PortIoOut
    27872824uid 478,0
    27882825shape (CompositeShape
     
    28282865)
    28292866)
    2830 *75 (PortIoOut
     2867*76 (PortIoOut
    28312868uid 484,0
    28322869shape (CompositeShape
     
    28722909)
    28732910)
    2874 *76 (PortIoInOut
     2911*77 (PortIoInOut
    28752912uid 490,0
    28762913shape (CompositeShape
     
    29142951)
    29152952)
    2916 *77 (PortIoIn
     2953*78 (PortIoIn
    29172954uid 496,0
    29182955shape (CompositeShape
     
    29582995)
    29592996)
    2960 *78 (PortIoOut
     2997*79 (PortIoOut
    29612998uid 502,0
    29622999shape (CompositeShape
     
    30023039)
    30033040)
    3004 *79 (PortIoOut
     3041*80 (PortIoOut
    30053042uid 508,0
    30063043shape (CompositeShape
     
    30463083)
    30473084)
    3048 *80 (Net
     3085*81 (Net
    30493086uid 1465,0
    30503087decl (Decl
     
    30593096font "Courier New,8,0"
    30603097)
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    3062 st "SIGNAL adc_data_array  : adc_data_array_type
    3063 "
    3064 )
    3065 )
    3066 *81 (Net
     3098xt "39000,62400,63000,63200"
     3099st "SIGNAL adc_data_array  : adc_data_array_type"
     3100)
     3101)
     3102*82 (Net
    30673103uid 2407,0
    30683104decl (Decl
     
    30783114font "Courier New,8,0"
    30793115)
    3080 xt "39000,37400,67500,38200"
    3081 st "RSRLOAD         : std_logic                    := '0'
    3082 "
    3083 )
    3084 )
    3085 *82 (PortIoOut
     3116xt "39000,38200,67500,39000"
     3117st "RSRLOAD         : std_logic                    := '0'"
     3118)
     3119)
     3120*83 (PortIoOut
    30863121uid 2415,0
    30873122shape (CompositeShape
     
    31283163)
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     3165*84 (Net
    31313166uid 2421,0
    31323167decl (Decl
     
    31423177font "Courier New,8,0"
    31433178)
    3144 xt "39000,60000,71000,60800"
    3145 st "SIGNAL SRCLK           : std_logic                    := '0'
    3146 "
    3147 )
    3148 )
    3149 *84 (Net
     3179xt "39000,60800,71000,61600"
     3180st "SIGNAL SRCLK           : std_logic                    := '0'"
     3181)
     3182)
     3183*85 (Net
    31503184uid 3019,0
    31513185decl (Decl
     
    31613195font "Courier New,8,0"
    31623196)
    3163 xt "39000,66400,67500,67200"
    3164 st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)
    3165 "
    3166 )
    3167 )
    3168 *85 (Net
     3197xt "39000,68000,67500,68800"
     3198st "SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0)"
     3199)
     3200)
     3201*86 (Net
    31693202uid 3025,0
    31703203decl (Decl
     
    31793212font "Courier New,8,0"
    31803213)
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    3184 )
    3185 )
    3186 *86 (PortIoOut
     3214xt "39000,25400,54000,26200"
     3215st "DAC_CS          : std_logic"
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     3217)
     3218*87 (PortIoOut
    31873219uid 3153,0
    31883220shape (CompositeShape
     
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     3263*88 (Net
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    3251 *88 (Net
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     3279st "X_50M           : STD_LOGIC"
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     3281)
     3282*89 (Net
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    32623293font "Courier New,8,0"
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    3269 *89 (HdlText
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    33733403)
    3374 xt "39000,20600,64000,21400"
    3375 st "A_CLK           : std_logic_vector(3 downto 0)
    3376 "
    3377 )
    3378 )
    3379 *94 (Net
     3404xt "39000,21400,64000,22200"
     3405st "A_CLK           : std_logic_vector(3 downto 0)"
     3406)
     3407)
     3408*95 (Net
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    33813410decl (Decl
     
    33903419font "Courier New,8,0"
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    3395 )
    3396 )
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