Changeset 10123
- Timestamp:
- 01/27/11 17:10:41 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
- Files:
-
- 19 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10121 r10123 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 11:57:15 26.01.20115 -- at - 09:36:36 27.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 40 40 -- Created: 41 41 -- by - dneise.UNKNOWN (E5B-LABOR6) 42 -- at - 11:57:15 26.01.201142 -- at - 09:36:36 27.01.2011 43 43 -- 44 44 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r10121 r10123 35 35 36 36 # BOARD ID - inputs 37 NET POSITION_ID<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok name was LINE befoer i changed it38 NET POSITION_ID<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok39 NET POSITION_ID<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok40 NET POSITION_ID<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok41 NET POSITION_ID<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok42 NET POSITION_ID<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok37 NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok 38 NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok 39 NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok 40 NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok 41 NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok 42 NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok 43 43 44 44 # W5300 … … 138 138 NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok 139 139 NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok 140 NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok 141 NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok 140 NET D_T_in<0> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<6> LOC = M3 141 NET D_T_in<1> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<7> LOC = T3 142 #NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok 143 #NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok 142 144 NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> 143 145 NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak
r10121 r10123 35 35 36 36 # BOARD ID - inputs 37 NET POSITION_ID<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok name was LINE befoer i changed it38 NET POSITION_ID<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok39 NET POSITION_ID<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok40 NET POSITION_ID<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok41 NET POSITION_ID<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok42 NET POSITION_ID<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok37 NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok 38 NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok 39 NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok 40 NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok 41 NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok 42 NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok 43 43 44 44 # W5300 … … 99 99 100 100 NET SRIN LOC = E1 | IOSTANDARD=LVCMOS25; #ok -- nur fuer vollauslese noetig; auf Z legen. 101 #NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible101 NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible 102 102 103 103 … … 138 138 NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok 139 139 NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok 140 NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok 141 NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok 140 #NET D_T_in<0> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<6> LOC = M3 141 #NET D_T_in<1> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<7> LOC = T3 142 NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok 143 NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok 142 144 NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> 143 145 NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10121 r10123 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 6:46:19 26.01.20115 -- at - 17:58:59 27.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 13 13 ENTITY FAD_Board IS 14 14 PORT( 15 A0_D : IN std_logic_vector (11 DOWNTO 0); 16 A1_D : IN std_logic_vector (11 DOWNTO 0); 17 A2_D : IN std_logic_vector (11 DOWNTO 0); 18 A3_D : IN std_logic_vector (11 DOWNTO 0); 19 A_OTR : IN std_logic_vector (3 DOWNTO 0); 20 D0_SROUT : IN std_logic; 21 D1_SROUT : IN std_logic; 22 D2_SROUT : IN std_logic; 23 D3_SROUT : IN std_logic; 24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); 25 POSITION_ID : IN std_logic_vector ( 5 DOWNTO 0 ); 26 REFCLK : IN std_logic; 27 RS485_C_DI : IN std_logic; 28 RS485_E_DI : IN std_logic; 29 RS485_E_DO : IN std_logic; 30 TRG : IN STD_LOGIC; 31 W_INT : IN std_logic; 32 X_50M : IN STD_LOGIC; 33 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 34 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 35 AMBER_LED : OUT std_logic; 36 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 37 D0_SRCLK : OUT STD_LOGIC; 38 D1_SRCLK : OUT STD_LOGIC; 39 D2_SRCLK : OUT STD_LOGIC; 40 D3_SRCLK : OUT STD_LOGIC; 41 DAC_CS : OUT std_logic; 42 DENABLE : OUT std_logic := '0'; 43 DWRITE : OUT std_logic := '0'; 44 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 45 D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 46 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 47 EE_CS : OUT std_logic; 48 GREEN_LED : OUT std_logic; 49 MOSI : OUT std_logic := '0'; 50 OE_ADC : OUT STD_LOGIC; 51 RED_LED : OUT std_logic; 52 RS485_C_DE : OUT std_logic; 53 RS485_C_DO : OUT std_logic; 54 RS485_C_RE : OUT std_logic; 55 RS485_E_DE : OUT std_logic; 56 RS485_E_RE : OUT std_logic; 57 RSRLOAD : OUT std_logic := '0'; 58 SRIN : OUT std_logic := '0'; 59 S_CLK : OUT std_logic; 60 T0_CS : OUT std_logic; 61 T1_CS : OUT std_logic; 62 T2_CS : OUT std_logic; 63 T3_CS : OUT std_logic; 64 TRG_V : OUT std_logic; 65 W_A : OUT std_logic_vector (9 DOWNTO 0); 66 W_CS : OUT std_logic := '1'; 67 W_RD : OUT std_logic := '1'; 68 W_RES : OUT std_logic := '1'; 69 W_WR : OUT std_logic := '1'; 70 MISO : INOUT std_logic; 71 W_D : INOUT std_logic_vector (15 DOWNTO 0) 15 A0_D : IN std_logic_vector (11 DOWNTO 0); 16 A1_D : IN std_logic_vector (11 DOWNTO 0); 17 A2_D : IN std_logic_vector (11 DOWNTO 0); 18 A3_D : IN std_logic_vector (11 DOWNTO 0); 19 A_OTR : IN std_logic_vector (3 DOWNTO 0); 20 D0_SROUT : IN std_logic; 21 D1_SROUT : IN std_logic; 22 D2_SROUT : IN std_logic; 23 D3_SROUT : IN std_logic; 24 D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); 25 D_T_in : IN std_logic_vector (1 DOWNTO 0); 26 LINE : IN std_logic_vector ( 5 DOWNTO 0 ); 27 REFCLK : IN std_logic; 28 RS485_C_DI : IN std_logic; 29 RS485_E_DI : IN std_logic; 30 RS485_E_DO : IN std_logic; 31 TRG : IN STD_LOGIC; 32 W_INT : IN std_logic; 33 X_50M : IN STD_LOGIC; 34 A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 35 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 36 AMBER_LED : OUT std_logic; 37 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 38 D0_SRCLK : OUT STD_LOGIC; 39 D1_SRCLK : OUT STD_LOGIC; 40 D2_SRCLK : OUT STD_LOGIC; 41 D3_SRCLK : OUT STD_LOGIC; 42 DAC_CS : OUT std_logic; 43 DENABLE : OUT std_logic := '0'; 44 DWRITE : OUT std_logic := '0'; 45 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 46 D_T : OUT std_logic_vector (5 DOWNTO 0) := (OTHERS => '0'); 47 D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 48 EE_CS : OUT std_logic; 49 GREEN_LED : OUT std_logic; 50 MOSI : OUT std_logic := '0'; 51 OE_ADC : OUT STD_LOGIC; 52 RED_LED : OUT std_logic; 53 RS485_C_DE : OUT std_logic; 54 RS485_C_DO : OUT std_logic; 55 RS485_C_RE : OUT std_logic; 56 RS485_E_DE : OUT std_logic; 57 RS485_E_RE : OUT std_logic; 58 RSRLOAD : OUT std_logic := '0'; 59 SRIN : OUT std_logic := '0'; 60 S_CLK : OUT std_logic; 61 T0_CS : OUT std_logic; 62 T1_CS : OUT std_logic; 63 T2_CS : OUT std_logic; 64 T3_CS : OUT std_logic; 65 TRG_V : OUT std_logic; 66 W_A : OUT std_logic_vector (9 DOWNTO 0); 67 W_CS : OUT std_logic := '1'; 68 W_RD : OUT std_logic := '1'; 69 W_RES : OUT std_logic := '1'; 70 W_WR : OUT std_logic := '1'; 71 MISO : INOUT std_logic; 72 W_D : INOUT std_logic_vector (15 DOWNTO 0) 72 73 ); 73 74 … … 81 82 -- Created: 82 83 -- by - dneise.UNKNOWN (E5B-LABOR6) 83 -- at - 1 6:46:20 26.01.201184 -- at - 17:58:59 27.01.2011 84 85 -- 85 86 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 120 121 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 121 122 SIGNAL dummy : std_logic; 123 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 122 124 SIGNAL ready : std_logic := '0'; 123 125 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); … … 136 138 PORT ( 137 139 CLK : IN std_logic ; 140 D_T_in : IN std_logic_vector (1 DOWNTO 0); 138 141 SROUT_in_0 : IN std_logic ; 139 142 SROUT_in_1 : IN std_logic ; … … 198 201 -- HDL Embedded Text Block 1 eb_ID 199 202 -- hard-wired IDs 200 board_id <= "0101";201 crate_id <= "01";203 board_id <= LINE(5 downto 2); 204 crate_id <= LINE(1 downto 0); 202 205 203 206 -- HDL Embedded Text Block 2 ADC_CLK … … 243 246 244 247 EE_CS <= '1'; 248 249 -- HDL Embedded Text Block 7 eb1 250 D_T(5 downto 0) <= (others => '0'); 245 251 246 252 -- HDL Embedded Text Block 8 eb2 … … 269 275 A1_T(7) <= drs_channel_id(3); 270 276 271 A0_T(5 downto 0) <= POSITION_ID;277 A0_T(5 downto 0) <= (others => '0'); 272 278 A0_T(6) <= REFCLK; 273 279 A0_T(7) <= RS485_E_DI; … … 291 297 PORT MAP ( 292 298 CLK => X_50M, 299 D_T_in => D_T_in, 293 300 SROUT_in_0 => D0_SROUT, 294 301 SROUT_in_1 => D1_SROUT, … … 324 331 drs_dwrite => DWRITE, 325 332 green => RED_LED, 326 led => D_T,333 led => led, 327 334 mosi => MOSI, 328 335 offset => OPEN, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10121 r10123 18 18 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); 19 19 type ip_type is array (0 to 3) of integer; 20 21 type mac_list_type is array (0 to 2) of mac_type; 22 type ip_list_type is array (0 to 2) of ip_type; 20 23 -- Network Settings 21 24 22 constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); 25 constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1); 26 constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --??????????????? 27 constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); 23 28 24 -- @ ETH zurich 25 -- constant NETMASK : ip_type := (255, 255, 248, 0); 26 -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); 27 -- constant GATEWAY : ip_type := (192, 33, 96, 1); 29 constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0); 30 constant CAM_NETMASK : ip_type := (255, 255, 248, 0); --??????????????? 31 constant TUDO_NETMASK : ip_type := (255, 255, 255, 0); 28 32 29 -- @ TU Dortmund 30 constant NETMASK : ip_type := (255, 255, 255, 0); 31 constant IP_ADDRESS : ip_type := (129, 217, 160, 119); 32 constant GATEWAY : ip_type := (129, 217, 160, 1); 33 --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000"); 34 constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4"); 35 constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001"); 36 constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002"); 37 38 --constant IP_ZERO : ip_type := (0,0,0,0); 39 constant IP_TUDO : ip_type := (129, 217, 160, 119); 40 constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225); 41 constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226); 42 constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237); 43 44 -- IP lookup table used to convert CID,BID into IP, if not in camera. 45 constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2); 46 constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2); 33 47 34 48 constant FIRST_PORT : integer := 5000; 49 constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0); 50 constant IP_offset : integer := 128; 51 constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000"); 35 52 -- Network Settings End 36 53 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak
r10121 r10123 17 17 18 18 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); 19 type mac_list_type is array (0 to 3) of mac_type; 19 20 type ip_type is array (0 to 3) of integer; 21 type ip_list_type is array (0 to 3) of ip_type; 20 22 -- Network Settings 21 23 22 constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4"); 24 constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1); 25 constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --??????????????? 26 constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); 23 27 24 -- @ ETH zurich 25 -- constant NETMASK : ip_type := (255, 255, 248, 0); 26 -- constant IP_ADDRESS : ip_type := (192, 33, 99, 225); 27 -- constant GATEWAY : ip_type := (192, 33, 96, 1); 28 constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0); 29 constant CAM_NETMASK : ip_type := (255, 255, 248, 0); --??????????????? 30 constant TUDO_NETMASK : ip_type := (255, 255, 255, 0); 28 31 29 -- @ TU Dortmund 30 constant NETMASK : ip_type := (255, 255, 255, 0); 31 constant IP_ADDRESS : ip_type := (129, 217, 160, 119); 32 constant GATEWAY : ip_type := (129, 217, 160, 1); 32 --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000"); 33 constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4"); 34 constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001"); 35 constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002"); 36 37 --constant IP_ZERO : ip_type := (0,0,0,0); 38 constant IP_TUDO : ip_type := (129, 217, 160, 119); 39 constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225); 40 constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226); 41 constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237); 42 43 -- IP lookup table used to convert CID,BID into IP, if not in camera. 44 constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2); 45 constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2); 33 46 34 47 constant FIRST_PORT : integer := 5000; 48 constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0); 49 constant IP_offset : integer := 128; 50 constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000"); 35 51 -- Network Settings End 36 52 … … 142 158 143 159 constant CMD_PS_RESET : std_logic_vector := X"17"; 160 161 constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; 162 144 163 -- DRS Registers 145 164 constant DRS_CONFIG_REG : std_logic_vector := "1100"; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10121 r10123 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 6:46:18 26.01.20115 -- at - 17:58:58 27.01.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 19 19 PORT( 20 20 CLK : IN std_logic; 21 D_T_in : IN std_logic_vector (1 DOWNTO 0); 21 22 SROUT_in_0 : IN std_logic; 22 23 SROUT_in_1 : IN std_logic; … … 79 80 -- Created: 80 81 -- by - dneise.UNKNOWN (E5B-LABOR6) 81 -- at - 1 6:46:19 26.01.201182 -- at - 17:58:58 27.01.2011 82 83 -- 83 84 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 468 469 -- -- 469 470 config_busy : IN std_logic ; 471 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 472 BoardID : IN std_logic_vector (3 DOWNTO 0); 473 CrateID : IN std_logic_vector (1 DOWNTO 0); 470 474 denable : OUT std_logic := '0'; -- default domino wave off 471 475 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. … … 784 788 config_rw_ready => config_rw_ready, 785 789 config_busy => config_busy, 790 MAC_jumper => D_T_in, 791 BoardID => board_id, 792 CrateID => crate_id, 786 793 denable => denable, 787 794 dwrite_enable => dwrite_enable, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10121 r10123 69 69 config_busy : in std_logic; 70 70 71 71 MAC_jumper : in std_logic_vector (1 downto 0); 72 BoardID : in std_logic_vector (3 downto 0); 73 CrateID : in std_logic_vector (1 downto 0); 72 74 73 75 denable : out std_logic := '0'; -- default domino wave off … … 93 95 94 96 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 95 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,97 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 96 98 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 97 99 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, … … 152 154 signal data_valid_int : std_logic := '0'; 153 155 156 signal FAD_in_cam : std_logic := '0'; 157 signal FAD_at_ETHZ : std_logic := '0'; 158 signal bid : std_logic_vector (3 downto 0); 159 signal cid : std_logic_vector (1 downto 0); 160 161 154 162 -- only for debugging 155 163 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); … … 160 168 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending 161 169 signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. 170 171 signal mac_loc : mac_type; 172 signal ip_loc : ip_type; 173 signal gateway_loc : ip_type; 174 signal netmask_loc : ip_type; 175 162 176 163 177 begin … … 274 288 -- Init 275 289 when INIT => 290 -- status of MAC jumpers is synched in 291 -- and Board- and CrateID are synched in 292 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook 293 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was; 294 bid <= BoardID; 295 cid <= CrateID; 296 -- 276 297 par_addr <= W5300_MR; 277 298 par_data <= X"0000"; 278 299 state_init <= WRITE_REG; 279 next_state <= IM; 300 next_state <= LOCATE; 301 302 when LOCATE => 303 state_init <= IM; 304 305 if (FAD_in_cam = '1') then 306 -- if BID = "1111" and CID="11" then FAD is not really in cam 307 -- back to INIT !! endless loop 308 if (bid = "1111" and cid="11") then 309 -- this should never happen!!!!! 310 -- impossible to find this out, if in cam 311 state_init <= INIT; 312 else -- everything is fine 313 -- IP & MAC are calculated from BID & CID 314 -- code here 315 gateway_loc <= CAM_GATEWAY; 316 netmask_loc <= CAM_NETMASK; 317 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) ); 318 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) ); 319 end if; 320 else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without. 321 if ( FAD_at_ETHZ = '0' ) then 322 -- easy FAD is at TUDO -> only one choice. 323 mac_loc <= MAC_FAD0; 324 ip_loc <= IP_TUDO; 325 gateway_loc <= TUDO_GATEWAY; 326 netmask_loc <= TUDO_NETMASK; 327 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed. 328 if (bid = "1111" and cid="11") then -- FAD is not in crate 329 mac_loc <= MAC_FAD0; 330 ip_loc <= IP_ETHZ_FAD0; 331 gateway_loc <= ETHZ_GATEWAY; 332 netmask_loc <= ETHZ_NETMASK; 333 else 334 -- FAD is at ETHZ and in crate: 335 -- crate ID is not of importance. 336 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed. 337 if ( conv_integer(bid) < MAC_LIST'length) then 338 gateway_loc <= ETHZ_GATEWAY; 339 netmask_loc <= ETHZ_NETMASK; 340 mac_loc <= MAC_LIST(conv_integer(bid)); 341 ip_loc <= IP_LIST(conv_integer(bid)); 342 end if; -- conv_integer 343 end if; -- bid=1111 & cid=11 344 end if; --FAD_at_ETHZ = 0 345 end if; --FAD_in_cam = 1 280 346 281 347 -- Interrupt Mask … … 336 402 when MAC => 337 403 par_addr <= W5300_SHAR; 338 par_data <= MAC_ADDRESS(0);404 par_data <= mac_loc(0); 339 405 state_init <= WRITE_REG; 340 406 next_state <= MAC1; 341 407 when MAC1 => 342 408 par_addr <= W5300_SHAR + 2; 343 par_data <= MAC_ADDRESS(1);409 par_data <= mac_loc(1); 344 410 state_init <= WRITE_REG; 345 411 next_state <= MAC2; 346 412 when MAC2 => 347 413 par_addr <= W5300_SHAR + 4; 348 par_data <= MAC_ADDRESS(2);414 par_data <= mac_loc(2); 349 415 state_init <= WRITE_REG; 350 416 next_state <= GW; … … 353 419 when GW => 354 420 par_addr <= W5300_GAR; 355 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(0),8);356 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(1),8);421 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); 422 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); 357 423 state_init <= WRITE_REG; 358 424 next_state <= GW1; 359 425 when GW1 => 360 426 par_addr <= W5300_GAR + 2; 361 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(2),8);362 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(3),8);427 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); 428 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); 363 429 state_init <= WRITE_REG; 364 430 next_state <= SNM; … … 367 433 when SNM => 368 434 par_addr <= W5300_SUBR; 369 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(0),8);370 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(1),8);435 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); 436 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); 371 437 state_init <= WRITE_REG; 372 438 next_state <= SNM1; 373 439 when SNM1 => 374 440 par_addr <= W5300_SUBR + 2; 375 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(2),8);376 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(3),8);441 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); 442 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); 377 443 state_init <= WRITE_REG; 378 444 next_state <= IP; … … 380 446 when IP => 381 447 par_addr <= W5300_SIPR; 382 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(0),8);383 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(1),8);448 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); 449 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); 384 450 state_init <= WRITE_REG; 385 451 next_state <= IP1; 386 452 when IP1 => 387 453 par_addr <= W5300_SIPR + 2; 388 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(2),8);389 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(3),8);454 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); 455 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); 390 456 state_init <= WRITE_REG; 391 457 next_state <= SI; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak
r10121 r10123 69 69 config_busy : in std_logic; 70 70 71 71 MAC_jumper : in std_logic_vector (1 downto 0); 72 BoardID : in std_logic_vector (3 downto 0); 73 CrateID : in std_logic_vector (1 downto 0); 72 74 73 75 denable : out std_logic := '0'; -- default domino wave off … … 93 95 94 96 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 95 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,97 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 96 98 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); 97 99 type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, … … 152 154 signal data_valid_int : std_logic := '0'; 153 155 156 signal FAD_in_cam : std_logic := '0'; 157 signal FAD_at_ETHZ : std_logic := '0'; 158 signal bid : std_logic_vector (3 downto 0); 159 signal cid : std_logic_vector (1 downto 0); 160 161 154 162 -- only for debugging 155 163 --signal error_cnt : std_logic_vector (7 downto 0) := (others => '0'); … … 160 168 signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending 161 169 signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. 170 171 signal mac_loc : mac_type; 172 signal ip_loc : ip_type; 173 signal gateway_loc : ip_type; 174 signal netmask_loc : ip_type; 175 162 176 163 177 begin … … 274 288 -- Init 275 289 when INIT => 290 -- status of MAC jumpers is synched in 291 -- and Board- and CrateID are synched in 292 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook 293 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was; 294 bid <= BoardID; 295 cid <= CrateID; 296 -- 276 297 par_addr <= W5300_MR; 277 298 par_data <= X"0000"; 278 299 state_init <= WRITE_REG; 279 next_state <= IM; 300 next_state <= LOCATE; 301 302 when LOCATE => 303 state_init <= IM; 304 305 if (FAD_in_cam = '1') then 306 -- if BID = "1111" and CID="11" then FAD is not really in cam 307 -- back to INIT !! endless loop 308 if (bid = "1111" and cid="11") then 309 -- this should never happen!!!!! 310 -- impossible to find this out, if in cam 311 state_init <= INIT; 312 else -- everything is fine 313 -- IP & MAC are calculated from BID & CID 314 -- code here 315 gateway_loc <= CAM_GATEWAY; 316 netmask_loc <= CAM_NETMASK; 317 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) ); 318 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) ); 319 end if; 320 else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without. 321 if ( FAD_at_ETHZ = '0' ) then 322 -- easy FAD is at TUDO -> only one choice. 323 mac_loc <= MAC_FAD0; 324 ip_loc <= IP_TUDO; 325 gateway_loc <= TUDO_GATEWAY; 326 netmask_loc <= TUDO_NETMASK; 327 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed. 328 if (bid = "1111" and cid="11") then -- FAD is not in crate 329 mac_loc <= MAC_FAD0; 330 ip_loc <= IP_ETHZ_FAD0; 331 gateway_loc <= ETHZ_GATEWAY; 332 netmask_loc <= ETHZ_NETMASK; 333 else 334 -- FAD is at ETHZ and in crate: 335 -- crate ID is not of importance. 336 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed. 337 if ( conv_integer(bid) < MAC_LIST'length) then 338 gateway_loc <= ETHZ_GATEWAY; 339 netmask_loc <= ETHZ_NETMASK; 340 mac_loc <= MAC_LIST(conv_integer(bid)); 341 ip_loc <= IP_LIST(conv_integer(bid)); 342 end if; -- conv_integer 343 end if; -- bid=1111 & cid=11 344 end if; --FAD_at_ETHZ = 0 345 end if; --FAD_in_cam = 1 280 346 281 347 -- Interrupt Mask … … 336 402 when MAC => 337 403 par_addr <= W5300_SHAR; 338 par_data <= MAC_ADDRESS(0);404 par_data <= mac_loc(0); 339 405 state_init <= WRITE_REG; 340 406 next_state <= MAC1; 341 407 when MAC1 => 342 408 par_addr <= W5300_SHAR + 2; 343 par_data <= MAC_ADDRESS(1);409 par_data <= mac_loc(1); 344 410 state_init <= WRITE_REG; 345 411 next_state <= MAC2; 346 412 when MAC2 => 347 413 par_addr <= W5300_SHAR + 4; 348 par_data <= MAC_ADDRESS(2);414 par_data <= mac_loc(2); 349 415 state_init <= WRITE_REG; 350 416 next_state <= GW; … … 353 419 when GW => 354 420 par_addr <= W5300_GAR; 355 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(0),8);356 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(1),8);421 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); 422 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); 357 423 state_init <= WRITE_REG; 358 424 next_state <= GW1; 359 425 when GW1 => 360 426 par_addr <= W5300_GAR + 2; 361 par_data (15 downto 8) <= conv_std_logic_vector( GATEWAY(2),8);362 par_data (7 downto 0) <= conv_std_logic_vector( GATEWAY(3),8);427 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); 428 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); 363 429 state_init <= WRITE_REG; 364 430 next_state <= SNM; … … 367 433 when SNM => 368 434 par_addr <= W5300_SUBR; 369 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(0),8);370 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(1),8);435 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); 436 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); 371 437 state_init <= WRITE_REG; 372 438 next_state <= SNM1; 373 439 when SNM1 => 374 440 par_addr <= W5300_SUBR + 2; 375 par_data (15 downto 8) <= conv_std_logic_vector( NETMASK(2),8);376 par_data (7 downto 0) <= conv_std_logic_vector( NETMASK(3),8);441 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); 442 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); 377 443 state_init <= WRITE_REG; 378 444 next_state <= IP; 379 445 -- Own IP-Address 380 446 when IP => 447 led(0) <= '1'; 448 led(1) <= '1'; 449 led(2) <= '1'; 450 381 451 par_addr <= W5300_SIPR; 382 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(0),8);383 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(1),8);452 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); 453 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); 384 454 state_init <= WRITE_REG; 385 455 next_state <= IP1; 386 456 when IP1 => 387 457 par_addr <= W5300_SIPR + 2; 388 par_data (15 downto 8) <= conv_std_logic_vector( IP_ADDRESS(2),8);389 par_data (7 downto 0) <= conv_std_logic_vector( IP_ADDRESS(3),8);458 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); 459 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); 390 460 state_init <= WRITE_REG; 391 461 next_state <= SI; … … 404 474 -- Socket Init 405 475 when SI => 476 led(3) <= '1'; 406 477 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; 407 478 par_data <= X"0101"; -- ALIGN, TCP … … 435 506 end if; 436 507 when SI6 => 508 led(4) <= '1'; 437 509 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 438 510 par_data <= X"0002"; -- LISTEN … … 448 520 449 521 when ESTABLISH => 522 led(5) <= '1'; 450 523 socks_waiting <= '1'; 451 524 socks_connected <= '0'; … … 607 680 --trigger_stop <= '1'; 608 681 state_read_data <= RD_5; 682 when CMD_SET_TRIGGER_MULT => 683 c_trigger_mult <= data_read (7 downto 0); 684 state_read_data <= RD_5; 685 609 686 -- phase shift commands here: 610 687 when CMD_PS_DO => -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf
r10121 r10123 37 37 DESIGN @f@a@d_@board 38 38 VIEW symbol.sb 39 GRAPHIC 4 165,0 24 040 DESIGN @f@a@d_@board 41 VIEW symbol.sb 42 GRAPHIC 42 64,0 25 043 DESIGN @f@a@d_@board 44 VIEW symbol.sb 45 GRAPHIC 3581,0 26 046 DESIGN @f@a@d_@board 47 VIEW symbol.sb 48 GRAPHIC 3 687,0 27 049 DESIGN @f@a@d_@board 50 VIEW symbol.sb 51 GRAPHIC 36 92,0 28 052 DESIGN @f@a@d_@board 53 VIEW symbol.sb 54 GRAPHIC 1121,0 29 055 DESIGN @f@a@d_@board 56 VIEW symbol.sb 57 GRAPHIC 1 421,0 30 058 DESIGN @f@a@d_@board 59 VIEW symbol.sb 60 GRAPHIC 1 116,0 31 061 DESIGN @f@a@d_@board 62 VIEW symbol.sb 63 GRAPHIC 3456,0 32 064 DESIGN @f@a@d_@board 65 VIEW symbol.sb 66 GRAPHIC 3 026,0 33 067 DESIGN @f@a@d_@board 68 VIEW symbol.sb 69 GRAPHIC 4033,0 34 070 DESIGN @f@a@d_@board 71 VIEW symbol.sb 72 GRAPHIC 1126,0 35 073 DESIGN @f@a@d_@board 74 VIEW symbol.sb 75 GRAPHIC 1 227,0 36 076 DESIGN @f@a@d_@board 77 VIEW symbol.sb 78 GRAPHIC 12 32,0 37 079 DESIGN @f@a@d_@board 80 VIEW symbol.sb 81 GRAPHIC 123 7,0 38 082 DESIGN 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symbol.sb 165 GRAPHIC 1426,0 66 0 166 DESIGN @f@a@d_@board 167 VIEW symbol.sb 168 GRAPHIC 1409,0 67 0 169 DESIGN @f@a@d_@board 170 VIEW symbol.sb 171 GRAPHIC 1403,0 68 0 172 DESIGN @f@a@d_@board 173 VIEW symbol.sb 174 GRAPHIC 1415,0 69 0 175 DESIGN @f@a@d_@board 176 VIEW symbol.sb 177 GRAPHIC 1626,0 70 0 178 DESIGN @f@a@d_@board 179 VIEW symbol.sb 180 GRAPHIC 1398,0 71 0 181 181 DESIGN @f@a@d_@board 182 182 VIEW symbol.sb 183 183 GRAPHIC 1,0 74 0 184 184 DESIGN @f@a@d_@board 185 VIEW struct.bd 186 NO_GRAPHIC 77 187 DESIGN @f@a@d_@board 188 VIEW struct.bd 189 GRAPHIC 41,0 86 0 190 DESIGN @f@a@d_@board 191 VIEW struct.bd 192 NO_GRAPHIC 94 193 DESIGN @f@a@d_@board 194 VIEW struct.bd 195 GRAPHIC 0,0 97 2 196 DESIGN @f@a@d_@board 197 VIEW struct.bd 198 GRAPHIC 10504,0 102 0 199 DESIGN @f@a@d_@board 200 VIEW struct.bd 201 GRAPHIC 10512,0 103 0 202 DESIGN @f@a@d_@board 203 VIEW struct.bd 204 GRAPHIC 10496,0 104 0 205 DESIGN @f@a@d_@board 206 VIEW struct.bd 207 GRAPHIC 3268,0 105 0 208 DESIGN @f@a@d_@board 209 VIEW struct.bd 210 GRAPHIC 10032,0 106 0 211 DESIGN @f@a@d_@board 212 VIEW struct.bd 213 GRAPHIC 9500,0 107 0 214 DESIGN @f@a@d_@board 215 VIEW struct.bd 216 GRAPHIC 10552,0 108 0 217 DESIGN @f@a@d_@board 218 VIEW struct.bd 219 GRAPHIC 10592,0 109 0 220 DESIGN @f@a@d_@board 221 VIEW struct.bd 222 GRAPHIC 10584,0 110 0 223 DESIGN @f@a@d_@board 224 VIEW struct.bd 225 GRAPHIC 10576,0 111 0 226 DESIGN @f@a@d_@board 227 VIEW struct.bd 228 GRAPHIC 10544,0 112 0 229 DESIGN @f@a@d_@board 230 VIEW struct.bd 231 GRAPHIC 10520,0 113 0 232 DESIGN @f@a@d_@board 233 VIEW struct.bd 234 GRAPHIC 2421,0 114 0 235 DESIGN @f@a@d_@board 236 VIEW struct.bd 237 GRAPHIC 10050,0 115 0 238 DESIGN @f@a@d_@board 239 VIEW struct.bd 240 GRAPHIC 1465,0 116 0 241 DESIGN @f@a@d_@board 242 VIEW struct.bd 243 GRAPHIC 275,0 117 0 244 DESIGN @f@a@d_@board 245 VIEW struct.bd 246 GRAPHIC 283,0 118 0 247 DESIGN @f@a@d_@board 248 VIEW struct.bd 249 GRAPHIC 8851,0 119 0 250 DESIGN @f@a@d_@board 251 VIEW struct.bd 252 GRAPHIC 7485,0 120 0 253 DESIGN @f@a@d_@board 254 VIEW struct.bd 255 GRAPHIC 10560,0 121 0 256 DESIGN @f@a@d_@board 257 VIEW struct.bd 258 GRAPHIC 3019,0 122 0 259 DESIGN @f@a@d_@board 260 VIEW struct.bd 261 GRAPHIC 10568,0 124 0 262 DESIGN @f@a@d_@board 263 VIEW struct.bd 264 NO_GRAPHIC 125 265 DESIGN @f@a@d_@board 266 VIEW struct.bd 267 GRAPHIC 13570,0 127 0 268 DESIGN @f@a@d_@board 269 VIEW struct.bd 270 NO_GRAPHIC 129 185 VIEW symbol.sb 186 GRAPHIC 1,0 75 0 187 DESIGN @f@a@d_@board 188 VIEW struct.bd 189 NO_GRAPHIC 78 190 DESIGN @f@a@d_@board 191 VIEW struct.bd 192 GRAPHIC 41,0 87 0 193 DESIGN @f@a@d_@board 194 VIEW struct.bd 195 NO_GRAPHIC 95 196 DESIGN @f@a@d_@board 197 VIEW struct.bd 198 GRAPHIC 0,0 98 2 199 DESIGN @f@a@d_@board 200 VIEW struct.bd 201 GRAPHIC 10504,0 103 0 202 DESIGN @f@a@d_@board 203 VIEW struct.bd 204 GRAPHIC 10512,0 104 0 205 DESIGN @f@a@d_@board 206 VIEW struct.bd 207 GRAPHIC 10496,0 105 0 208 DESIGN @f@a@d_@board 209 VIEW struct.bd 210 GRAPHIC 3268,0 106 0 211 DESIGN @f@a@d_@board 212 VIEW struct.bd 213 GRAPHIC 10032,0 107 0 214 DESIGN @f@a@d_@board 215 VIEW struct.bd 216 GRAPHIC 9500,0 108 0 217 DESIGN @f@a@d_@board 218 VIEW struct.bd 219 GRAPHIC 10552,0 109 0 220 DESIGN @f@a@d_@board 221 VIEW struct.bd 222 GRAPHIC 10592,0 110 0 223 DESIGN @f@a@d_@board 224 VIEW struct.bd 225 GRAPHIC 10584,0 111 0 226 DESIGN @f@a@d_@board 227 VIEW struct.bd 228 GRAPHIC 10576,0 112 0 229 DESIGN @f@a@d_@board 230 VIEW struct.bd 231 GRAPHIC 10544,0 113 0 232 DESIGN @f@a@d_@board 233 VIEW struct.bd 234 GRAPHIC 10520,0 114 0 235 DESIGN @f@a@d_@board 236 VIEW struct.bd 237 GRAPHIC 2421,0 115 0 238 DESIGN @f@a@d_@board 239 VIEW struct.bd 240 GRAPHIC 10050,0 116 0 241 DESIGN @f@a@d_@board 242 VIEW struct.bd 243 GRAPHIC 1465,0 117 0 244 DESIGN @f@a@d_@board 245 VIEW struct.bd 246 GRAPHIC 275,0 118 0 247 DESIGN @f@a@d_@board 248 VIEW struct.bd 249 GRAPHIC 283,0 119 0 250 DESIGN @f@a@d_@board 251 VIEW struct.bd 252 GRAPHIC 8851,0 120 0 253 DESIGN @f@a@d_@board 254 VIEW struct.bd 255 GRAPHIC 7485,0 121 0 256 DESIGN @f@a@d_@board 257 VIEW struct.bd 258 GRAPHIC 15173,0 122 0 259 DESIGN @f@a@d_@board 260 VIEW struct.bd 261 GRAPHIC 10560,0 123 0 262 DESIGN @f@a@d_@board 263 VIEW struct.bd 264 GRAPHIC 3019,0 124 0 265 DESIGN @f@a@d_@board 266 VIEW struct.bd 267 GRAPHIC 10568,0 126 0 268 DESIGN @f@a@d_@board 269 VIEW struct.bd 270 NO_GRAPHIC 127 271 DESIGN @f@a@d_@board 272 VIEW struct.bd 273 GRAPHIC 13570,0 129 0 274 DESIGN @f@a@d_@board 275 VIEW struct.bd 276 NO_GRAPHIC 131 271 277 LIBRARY FACT_FAD_lib 272 278 DESIGN @f@a@d_main 273 279 VIEW struct 274 GRAPHIC 169,0 131 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 14,0 132 1 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 1755,0 136 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 2710,0 137 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 2715,0 138 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 2720,0 139 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 2725,0 140 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 2282,0 141 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 1976,0 142 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 923,0 143 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 928,0 144 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 464,0 145 0 308 DESIGN @f@a@d_main 309 VIEW symbol.sb 310 GRAPHIC 1062,0 146 0 311 DESIGN @f@a@d_main 312 VIEW symbol.sb 313 GRAPHIC 4584,0 147 0 314 DESIGN @f@a@d_main 315 VIEW symbol.sb 316 GRAPHIC 4589,0 148 0 317 DESIGN @f@a@d_main 318 VIEW symbol.sb 319 GRAPHIC 4579,0 149 0 320 DESIGN @f@a@d_main 321 VIEW symbol.sb 322 GRAPHIC 1389,0 150 0 323 DESIGN @f@a@d_main 324 VIEW symbol.sb 325 GRAPHIC 1725,0 151 0 326 DESIGN @f@a@d_main 327 VIEW symbol.sb 328 GRAPHIC 4497,0 152 0 329 DESIGN @f@a@d_main 330 VIEW symbol.sb 331 GRAPHIC 4467,0 153 0 332 DESIGN @f@a@d_main 333 VIEW symbol.sb 334 GRAPHIC 4487,0 154 0 335 DESIGN @f@a@d_main 336 VIEW symbol.sb 337 GRAPHIC 4472,0 155 0 338 DESIGN @f@a@d_main 339 VIEW symbol.sb 340 GRAPHIC 4477,0 156 0 341 DESIGN @f@a@d_main 342 VIEW symbol.sb 343 GRAPHIC 4517,0 157 0 344 DESIGN @f@a@d_main 345 VIEW symbol.sb 346 GRAPHIC 2987,0 158 0 347 DESIGN @f@a@d_main 348 VIEW symbol.sb 349 GRAPHIC 2992,0 159 0 350 DESIGN @f@a@d_main 351 VIEW symbol.sb 352 GRAPHIC 4780,0 160 0 353 DESIGN @f@a@d_main 354 VIEW symbol.sb 355 GRAPHIC 4323,0 161 0 356 DESIGN @f@a@d_main 357 VIEW symbol.sb 358 GRAPHIC 833,0 162 0 359 DESIGN @f@a@d_main 360 VIEW symbol.sb 361 GRAPHIC 5206,0 163 0 362 DESIGN @f@a@d_main 363 VIEW symbol.sb 364 GRAPHIC 4911,0 164 0 365 DESIGN @f@a@d_main 366 VIEW symbol.sb 367 GRAPHIC 3641,0 165 0 368 DESIGN @f@a@d_main 369 VIEW symbol.sb 370 GRAPHIC 4144,0 166 0 371 DESIGN @f@a@d_main 372 VIEW symbol.sb 373 GRAPHIC 2448,0 167 0 374 DESIGN @f@a@d_main 375 VIEW symbol.sb 376 GRAPHIC 2453,0 168 0 377 DESIGN @f@a@d_main 378 VIEW symbol.sb 379 GRAPHIC 4906,0 169 0 380 DESIGN @f@a@d_main 381 VIEW symbol.sb 382 GRAPHIC 163,0 170 0 383 DESIGN @f@a@d_main 384 VIEW symbol.sb 385 GRAPHIC 4067,0 171 0 386 DESIGN @f@a@d_main 387 VIEW symbol.sb 388 GRAPHIC 4502,0 172 0 389 DESIGN @f@a@d_main 390 VIEW symbol.sb 391 GRAPHIC 4512,0 173 0 392 DESIGN @f@a@d_main 393 VIEW symbol.sb 394 GRAPHIC 4916,0 174 0 395 DESIGN @f@a@d_main 396 VIEW symbol.sb 397 GRAPHIC 3631,0 175 0 398 DESIGN @f@a@d_main 399 VIEW symbol.sb 400 GRAPHIC 3646,0 176 0 401 DESIGN @f@a@d_main 402 VIEW symbol.sb 403 GRAPHIC 4507,0 177 0 404 DESIGN @f@a@d_main 405 VIEW symbol.sb 406 GRAPHIC 1037,0 179 0 407 DESIGN @f@a@d_main 408 VIEW symbol.sb 409 GRAPHIC 1047,0 180 0 410 DESIGN @f@a@d_main 411 VIEW symbol.sb 412 GRAPHIC 1057,0 181 0 413 DESIGN @f@a@d_main 414 VIEW symbol.sb 415 GRAPHIC 135,0 182 0 416 DESIGN @f@a@d_main 417 VIEW symbol.sb 418 GRAPHIC 1052,0 183 0 419 DESIGN @f@a@d_main 420 VIEW symbol.sb 421 GRAPHIC 3636,0 184 0 422 DESIGN @f@a@d_main 423 VIEW symbol.sb 424 GRAPHIC 1042,0 185 0 280 GRAPHIC 169,0 133 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 14,0 134 1 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 1755,0 138 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 5328,0 139 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 2710,0 140 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 2715,0 141 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 2720,0 142 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 2725,0 143 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 2282,0 144 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 1976,0 145 0 308 DESIGN @f@a@d_main 309 VIEW symbol.sb 310 GRAPHIC 923,0 146 0 311 DESIGN @f@a@d_main 312 VIEW symbol.sb 313 GRAPHIC 928,0 147 0 314 DESIGN @f@a@d_main 315 VIEW symbol.sb 316 GRAPHIC 464,0 148 0 317 DESIGN @f@a@d_main 318 VIEW symbol.sb 319 GRAPHIC 1062,0 149 0 320 DESIGN @f@a@d_main 321 VIEW symbol.sb 322 GRAPHIC 4584,0 150 0 323 DESIGN @f@a@d_main 324 VIEW symbol.sb 325 GRAPHIC 4589,0 151 0 326 DESIGN @f@a@d_main 327 VIEW symbol.sb 328 GRAPHIC 4579,0 152 0 329 DESIGN @f@a@d_main 330 VIEW symbol.sb 331 GRAPHIC 1389,0 153 0 332 DESIGN @f@a@d_main 333 VIEW symbol.sb 334 GRAPHIC 1725,0 154 0 335 DESIGN @f@a@d_main 336 VIEW symbol.sb 337 GRAPHIC 4497,0 155 0 338 DESIGN @f@a@d_main 339 VIEW symbol.sb 340 GRAPHIC 4467,0 156 0 341 DESIGN @f@a@d_main 342 VIEW symbol.sb 343 GRAPHIC 4487,0 157 0 344 DESIGN @f@a@d_main 345 VIEW symbol.sb 346 GRAPHIC 4472,0 158 0 347 DESIGN @f@a@d_main 348 VIEW symbol.sb 349 GRAPHIC 4477,0 159 0 350 DESIGN @f@a@d_main 351 VIEW symbol.sb 352 GRAPHIC 4517,0 160 0 353 DESIGN @f@a@d_main 354 VIEW symbol.sb 355 GRAPHIC 2987,0 161 0 356 DESIGN @f@a@d_main 357 VIEW symbol.sb 358 GRAPHIC 2992,0 162 0 359 DESIGN @f@a@d_main 360 VIEW symbol.sb 361 GRAPHIC 4780,0 163 0 362 DESIGN @f@a@d_main 363 VIEW symbol.sb 364 GRAPHIC 4323,0 164 0 365 DESIGN @f@a@d_main 366 VIEW symbol.sb 367 GRAPHIC 833,0 165 0 368 DESIGN @f@a@d_main 369 VIEW symbol.sb 370 GRAPHIC 5206,0 166 0 371 DESIGN @f@a@d_main 372 VIEW symbol.sb 373 GRAPHIC 4911,0 167 0 374 DESIGN @f@a@d_main 375 VIEW symbol.sb 376 GRAPHIC 3641,0 168 0 377 DESIGN @f@a@d_main 378 VIEW symbol.sb 379 GRAPHIC 4144,0 169 0 380 DESIGN @f@a@d_main 381 VIEW symbol.sb 382 GRAPHIC 2448,0 170 0 383 DESIGN @f@a@d_main 384 VIEW symbol.sb 385 GRAPHIC 2453,0 171 0 386 DESIGN @f@a@d_main 387 VIEW symbol.sb 388 GRAPHIC 4906,0 172 0 389 DESIGN @f@a@d_main 390 VIEW symbol.sb 391 GRAPHIC 163,0 173 0 392 DESIGN @f@a@d_main 393 VIEW symbol.sb 394 GRAPHIC 4067,0 174 0 395 DESIGN @f@a@d_main 396 VIEW symbol.sb 397 GRAPHIC 4502,0 175 0 398 DESIGN @f@a@d_main 399 VIEW symbol.sb 400 GRAPHIC 4512,0 176 0 401 DESIGN @f@a@d_main 402 VIEW symbol.sb 403 GRAPHIC 4916,0 177 0 404 DESIGN @f@a@d_main 405 VIEW symbol.sb 406 GRAPHIC 3631,0 178 0 407 DESIGN @f@a@d_main 408 VIEW symbol.sb 409 GRAPHIC 3646,0 179 0 410 DESIGN @f@a@d_main 411 VIEW symbol.sb 412 GRAPHIC 4507,0 180 0 413 DESIGN @f@a@d_main 414 VIEW symbol.sb 415 GRAPHIC 1037,0 182 0 416 DESIGN @f@a@d_main 417 VIEW symbol.sb 418 GRAPHIC 1047,0 183 0 419 DESIGN @f@a@d_main 420 VIEW symbol.sb 421 GRAPHIC 1057,0 184 0 422 DESIGN @f@a@d_main 423 VIEW symbol.sb 424 GRAPHIC 135,0 185 0 425 DESIGN @f@a@d_main 426 VIEW symbol.sb 427 GRAPHIC 1052,0 186 0 428 DESIGN @f@a@d_main 429 VIEW symbol.sb 430 GRAPHIC 3636,0 187 0 431 DESIGN @f@a@d_main 432 VIEW symbol.sb 433 GRAPHIC 1042,0 188 0 425 434 LIBRARY FACT_FAD_lib 426 435 DESIGN @f@a@d_@board 427 436 VIEW struct.bd 428 NO_GRAPHIC 188 429 DESIGN @f@a@d_@board 430 VIEW struct.bd 431 GRAPHIC 169,0 191 0 432 DESIGN @f@a@d_@board 433 VIEW struct.bd 434 NO_GRAPHIC 194 435 DESIGN @f@a@d_@board 436 VIEW struct.bd 437 GRAPHIC 265,0 197 0 438 DESIGN @f@a@d_@board 439 VIEW struct.bd 440 NO_GRAPHIC 201 441 DESIGN @f@a@d_@board 442 VIEW struct.bd 443 GRAPHIC 3248,0 202 0 444 DESIGN @f@a@d_@board 445 VIEW struct.bd 446 NO_GRAPHIC 208 447 DESIGN @f@a@d_@board 448 VIEW struct.bd 449 GRAPHIC 3300,0 209 0 450 DESIGN @f@a@d_@board 451 VIEW struct.bd 452 NO_GRAPHIC 215 453 DESIGN @f@a@d_@board 454 VIEW struct.bd 455 GRAPHIC 3394,0 216 0 456 DESIGN @f@a@d_@board 457 VIEW struct.bd 458 NO_GRAPHIC 222 459 DESIGN @f@a@d_@board 460 VIEW struct.bd 461 GRAPHIC 3542,0 223 0 462 DESIGN @f@a@d_@board 463 VIEW struct.bd 464 NO_GRAPHIC 229 465 DESIGN @f@a@d_@board 466 VIEW struct.bd 467 GRAPHIC 3700,0 230 0 468 DESIGN @f@a@d_@board 469 VIEW struct.bd 470 NO_GRAPHIC 244 471 DESIGN @f@a@d_@board 472 VIEW struct.bd 473 GRAPHIC 7092,0 245 0 474 DESIGN @f@a@d_@board 475 VIEW struct.bd 476 NO_GRAPHIC 248 477 DESIGN @f@a@d_@board 478 VIEW struct.bd 479 GRAPHIC 10310,0 249 0 480 DESIGN @f@a@d_@board 481 VIEW struct.bd 482 NO_GRAPHIC 277 483 DESIGN @f@a@d_@board 484 VIEW struct.bd 485 GRAPHIC 10023,0 278 0 486 DESIGN @f@a@d_@board 487 VIEW struct.bd 488 GRAPHIC 7652,0 281 0 489 DESIGN @f@a@d_@board 490 VIEW struct.bd 491 NO_GRAPHIC 284 492 DESIGN @f@a@d_@board 493 VIEW struct.bd 494 GRAPHIC 169,0 286 0 495 DESIGN @f@a@d_@board 496 VIEW struct.bd 497 GRAPHIC 176,0 287 1 498 DESIGN @f@a@d_@board 499 VIEW struct.bd 500 GRAPHIC 245,0 291 0 501 DESIGN @f@a@d_@board 502 VIEW struct.bd 503 GRAPHIC 1865,0 292 0 504 DESIGN @f@a@d_@board 505 VIEW struct.bd 506 GRAPHIC 1873,0 293 0 507 DESIGN @f@a@d_@board 508 VIEW struct.bd 509 GRAPHIC 1881,0 294 0 510 DESIGN @f@a@d_@board 511 VIEW struct.bd 512 GRAPHIC 1889,0 295 0 513 DESIGN @f@a@d_@board 514 VIEW struct.bd 515 GRAPHIC 1467,0 296 0 516 DESIGN @f@a@d_@board 517 VIEW struct.bd 518 GRAPHIC 1730,0 297 0 519 DESIGN @f@a@d_@board 520 VIEW struct.bd 521 GRAPHIC 277,0 298 0 522 DESIGN @f@a@d_@board 523 VIEW struct.bd 524 GRAPHIC 285,0 299 0 525 DESIGN @f@a@d_@board 526 VIEW struct.bd 527 GRAPHIC 3218,0 300 0 528 DESIGN @f@a@d_@board 529 VIEW struct.bd 530 GRAPHIC 450,0 301 0 531 DESIGN @f@a@d_@board 532 VIEW struct.bd 533 GRAPHIC 10506,0 302 0 534 DESIGN @f@a@d_@board 535 VIEW struct.bd 536 GRAPHIC 10514,0 303 0 537 DESIGN @f@a@d_@board 538 VIEW struct.bd 539 GRAPHIC 10498,0 304 0 540 DESIGN @f@a@d_@board 541 VIEW struct.bd 542 GRAPHIC 10034,0 305 0 543 DESIGN @f@a@d_@board 544 VIEW struct.bd 545 GRAPHIC 9502,0 306 0 546 DESIGN @f@a@d_@board 547 VIEW struct.bd 548 GRAPHIC 10554,0 307 0 549 DESIGN @f@a@d_@board 550 VIEW struct.bd 551 GRAPHIC 10594,0 308 0 552 DESIGN @f@a@d_@board 553 VIEW struct.bd 554 GRAPHIC 10586,0 309 0 555 DESIGN @f@a@d_@board 556 VIEW struct.bd 557 GRAPHIC 10578,0 310 0 558 DESIGN @f@a@d_@board 559 VIEW struct.bd 560 GRAPHIC 10546,0 311 0 561 DESIGN @f@a@d_@board 562 VIEW struct.bd 563 GRAPHIC 10522,0 312 0 564 DESIGN @f@a@d_@board 565 VIEW struct.bd 566 GRAPHIC 2409,0 313 0 567 DESIGN @f@a@d_@board 568 VIEW struct.bd 569 GRAPHIC 2423,0 314 0 570 DESIGN @f@a@d_@board 571 VIEW struct.bd 572 GRAPHIC 12320,0 315 0 573 DESIGN @f@a@d_@board 574 VIEW struct.bd 575 GRAPHIC 10052,0 316 0 576 DESIGN @f@a@d_@board 577 VIEW struct.bd 578 GRAPHIC 362,0 317 0 579 DESIGN @f@a@d_@board 580 VIEW struct.bd 581 GRAPHIC 3778,0 318 0 582 DESIGN @f@a@d_@board 583 VIEW struct.bd 584 GRAPHIC 12545,0 319 0 585 DESIGN @f@a@d_@board 586 VIEW struct.bd 587 GRAPHIC 7477,0 320 0 588 DESIGN @f@a@d_@board 589 VIEW struct.bd 590 GRAPHIC 6431,0 321 0 591 DESIGN @f@a@d_@board 592 VIEW struct.bd 593 GRAPHIC 8853,0 322 0 594 DESIGN @f@a@d_@board 595 VIEW struct.bd 596 GRAPHIC 1841,0 323 0 597 DESIGN @f@a@d_@board 598 VIEW struct.bd 599 GRAPHIC 12573,0 324 0 600 DESIGN @f@a@d_@board 601 VIEW struct.bd 602 GRAPHIC 4942,0 325 0 603 DESIGN @f@a@d_@board 604 VIEW struct.bd 605 GRAPHIC 3682,0 326 0 606 DESIGN @f@a@d_@board 607 VIEW struct.bd 608 GRAPHIC 10562,0 328 0 609 DESIGN @f@a@d_@board 610 VIEW struct.bd 611 GRAPHIC 12559,0 329 0 612 DESIGN @f@a@d_@board 613 VIEW struct.bd 614 GRAPHIC 3009,0 330 0 615 DESIGN @f@a@d_@board 616 VIEW struct.bd 617 GRAPHIC 3021,0 331 0 618 DESIGN @f@a@d_@board 619 VIEW struct.bd 620 GRAPHIC 10570,0 332 0 621 DESIGN @f@a@d_@board 622 VIEW struct.bd 623 GRAPHIC 426,0 333 0 624 DESIGN @f@a@d_@board 625 VIEW struct.bd 626 GRAPHIC 434,0 334 0 627 DESIGN @f@a@d_@board 628 VIEW struct.bd 629 GRAPHIC 458,0 335 0 630 DESIGN @f@a@d_@board 631 VIEW struct.bd 632 GRAPHIC 418,0 336 0 633 DESIGN @f@a@d_@board 634 VIEW struct.bd 635 GRAPHIC 466,0 337 0 636 DESIGN @f@a@d_@board 637 VIEW struct.bd 638 GRAPHIC 3015,0 338 0 639 DESIGN @f@a@d_@board 640 VIEW struct.bd 641 GRAPHIC 442,0 339 0 642 DESIGN @f@a@d_@board 643 VIEW struct.bd 644 GRAPHIC 13570,0 343 0 645 DESIGN @f@a@d_@board 646 VIEW struct.bd 647 NO_GRAPHIC 345 437 NO_GRAPHIC 191 438 DESIGN @f@a@d_@board 439 VIEW struct.bd 440 GRAPHIC 169,0 194 0 441 DESIGN @f@a@d_@board 442 VIEW struct.bd 443 NO_GRAPHIC 197 444 DESIGN @f@a@d_@board 445 VIEW struct.bd 446 GRAPHIC 265,0 200 0 447 DESIGN @f@a@d_@board 448 VIEW struct.bd 449 NO_GRAPHIC 204 450 DESIGN @f@a@d_@board 451 VIEW struct.bd 452 GRAPHIC 3248,0 205 0 453 DESIGN @f@a@d_@board 454 VIEW struct.bd 455 NO_GRAPHIC 211 456 DESIGN @f@a@d_@board 457 VIEW struct.bd 458 GRAPHIC 3300,0 212 0 459 DESIGN @f@a@d_@board 460 VIEW struct.bd 461 NO_GRAPHIC 218 462 DESIGN @f@a@d_@board 463 VIEW struct.bd 464 GRAPHIC 3394,0 219 0 465 DESIGN @f@a@d_@board 466 VIEW struct.bd 467 NO_GRAPHIC 225 468 DESIGN @f@a@d_@board 469 VIEW struct.bd 470 GRAPHIC 3542,0 226 0 471 DESIGN @f@a@d_@board 472 VIEW struct.bd 473 NO_GRAPHIC 232 474 DESIGN @f@a@d_@board 475 VIEW struct.bd 476 GRAPHIC 3700,0 233 0 477 DESIGN @f@a@d_@board 478 VIEW struct.bd 479 NO_GRAPHIC 247 480 DESIGN @f@a@d_@board 481 VIEW struct.bd 482 GRAPHIC 14346,0 248 0 483 DESIGN @f@a@d_@board 484 VIEW struct.bd 485 NO_GRAPHIC 250 486 DESIGN @f@a@d_@board 487 VIEW struct.bd 488 GRAPHIC 7092,0 251 0 489 DESIGN @f@a@d_@board 490 VIEW struct.bd 491 NO_GRAPHIC 254 492 DESIGN @f@a@d_@board 493 VIEW struct.bd 494 GRAPHIC 10310,0 255 0 495 DESIGN @f@a@d_@board 496 VIEW struct.bd 497 NO_GRAPHIC 283 498 DESIGN @f@a@d_@board 499 VIEW struct.bd 500 GRAPHIC 10023,0 284 0 501 DESIGN @f@a@d_@board 502 VIEW struct.bd 503 GRAPHIC 7652,0 287 0 504 DESIGN @f@a@d_@board 505 VIEW struct.bd 506 NO_GRAPHIC 290 507 DESIGN @f@a@d_@board 508 VIEW struct.bd 509 GRAPHIC 169,0 292 0 510 DESIGN @f@a@d_@board 511 VIEW struct.bd 512 GRAPHIC 176,0 293 1 513 DESIGN @f@a@d_@board 514 VIEW struct.bd 515 GRAPHIC 245,0 297 0 516 DESIGN @f@a@d_@board 517 VIEW struct.bd 518 GRAPHIC 14328,0 298 0 519 DESIGN @f@a@d_@board 520 VIEW struct.bd 521 GRAPHIC 1865,0 299 0 522 DESIGN @f@a@d_@board 523 VIEW struct.bd 524 GRAPHIC 1873,0 300 0 525 DESIGN @f@a@d_@board 526 VIEW struct.bd 527 GRAPHIC 1881,0 301 0 528 DESIGN @f@a@d_@board 529 VIEW struct.bd 530 GRAPHIC 1889,0 302 0 531 DESIGN @f@a@d_@board 532 VIEW struct.bd 533 GRAPHIC 1467,0 303 0 534 DESIGN @f@a@d_@board 535 VIEW struct.bd 536 GRAPHIC 1730,0 304 0 537 DESIGN @f@a@d_@board 538 VIEW struct.bd 539 GRAPHIC 277,0 305 0 540 DESIGN @f@a@d_@board 541 VIEW struct.bd 542 GRAPHIC 285,0 306 0 543 DESIGN @f@a@d_@board 544 VIEW struct.bd 545 GRAPHIC 3218,0 307 0 546 DESIGN @f@a@d_@board 547 VIEW struct.bd 548 GRAPHIC 450,0 308 0 549 DESIGN @f@a@d_@board 550 VIEW struct.bd 551 GRAPHIC 10506,0 309 0 552 DESIGN @f@a@d_@board 553 VIEW struct.bd 554 GRAPHIC 10514,0 310 0 555 DESIGN @f@a@d_@board 556 VIEW struct.bd 557 GRAPHIC 10498,0 311 0 558 DESIGN @f@a@d_@board 559 VIEW struct.bd 560 GRAPHIC 10034,0 312 0 561 DESIGN @f@a@d_@board 562 VIEW struct.bd 563 GRAPHIC 9502,0 313 0 564 DESIGN @f@a@d_@board 565 VIEW struct.bd 566 GRAPHIC 10554,0 314 0 567 DESIGN @f@a@d_@board 568 VIEW struct.bd 569 GRAPHIC 10594,0 315 0 570 DESIGN @f@a@d_@board 571 VIEW struct.bd 572 GRAPHIC 10586,0 316 0 573 DESIGN @f@a@d_@board 574 VIEW struct.bd 575 GRAPHIC 10578,0 317 0 576 DESIGN @f@a@d_@board 577 VIEW struct.bd 578 GRAPHIC 10546,0 318 0 579 DESIGN @f@a@d_@board 580 VIEW struct.bd 581 GRAPHIC 10522,0 319 0 582 DESIGN @f@a@d_@board 583 VIEW struct.bd 584 GRAPHIC 2409,0 320 0 585 DESIGN @f@a@d_@board 586 VIEW struct.bd 587 GRAPHIC 2423,0 321 0 588 DESIGN @f@a@d_@board 589 VIEW struct.bd 590 GRAPHIC 12320,0 322 0 591 DESIGN @f@a@d_@board 592 VIEW struct.bd 593 GRAPHIC 10052,0 323 0 594 DESIGN @f@a@d_@board 595 VIEW struct.bd 596 GRAPHIC 362,0 324 0 597 DESIGN @f@a@d_@board 598 VIEW struct.bd 599 GRAPHIC 3778,0 325 0 600 DESIGN @f@a@d_@board 601 VIEW struct.bd 602 GRAPHIC 12545,0 326 0 603 DESIGN @f@a@d_@board 604 VIEW struct.bd 605 GRAPHIC 7477,0 327 0 606 DESIGN @f@a@d_@board 607 VIEW struct.bd 608 GRAPHIC 6431,0 328 0 609 DESIGN @f@a@d_@board 610 VIEW struct.bd 611 GRAPHIC 8853,0 329 0 612 DESIGN @f@a@d_@board 613 VIEW struct.bd 614 GRAPHIC 1841,0 330 0 615 DESIGN @f@a@d_@board 616 VIEW struct.bd 617 GRAPHIC 12573,0 331 0 618 DESIGN @f@a@d_@board 619 VIEW struct.bd 620 GRAPHIC 15175,0 332 0 621 DESIGN @f@a@d_@board 622 VIEW struct.bd 623 GRAPHIC 3682,0 333 0 624 DESIGN @f@a@d_@board 625 VIEW struct.bd 626 GRAPHIC 10562,0 335 0 627 DESIGN @f@a@d_@board 628 VIEW struct.bd 629 GRAPHIC 12559,0 336 0 630 DESIGN @f@a@d_@board 631 VIEW struct.bd 632 GRAPHIC 3009,0 337 0 633 DESIGN @f@a@d_@board 634 VIEW struct.bd 635 GRAPHIC 3021,0 338 0 636 DESIGN @f@a@d_@board 637 VIEW struct.bd 638 GRAPHIC 10570,0 339 0 639 DESIGN @f@a@d_@board 640 VIEW struct.bd 641 GRAPHIC 426,0 340 0 642 DESIGN @f@a@d_@board 643 VIEW struct.bd 644 GRAPHIC 434,0 341 0 645 DESIGN @f@a@d_@board 646 VIEW struct.bd 647 GRAPHIC 458,0 342 0 648 DESIGN @f@a@d_@board 649 VIEW struct.bd 650 GRAPHIC 418,0 343 0 651 DESIGN @f@a@d_@board 652 VIEW struct.bd 653 GRAPHIC 466,0 344 0 654 DESIGN @f@a@d_@board 655 VIEW struct.bd 656 GRAPHIC 3015,0 345 0 657 DESIGN @f@a@d_@board 658 VIEW struct.bd 659 GRAPHIC 442,0 346 0 660 DESIGN @f@a@d_@board 661 VIEW struct.bd 662 GRAPHIC 13570,0 350 0 663 DESIGN @f@a@d_@board 664 VIEW struct.bd 665 NO_GRAPHIC 352 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r10121 r10123 13 13 DESIGN @f@a@d_main 14 14 VIEW symbol.sb 15 GRAPHIC 2710,0 20 016 DESIGN @f@a@d_main 17 VIEW symbol.sb 18 GRAPHIC 271 5,0 21 019 DESIGN @f@a@d_main 20 VIEW symbol.sb 21 GRAPHIC 27 20,0 22 022 DESIGN @f@a@d_main 23 VIEW symbol.sb 24 GRAPHIC 272 5,0 23 025 DESIGN @f@a@d_main 26 VIEW symbol.sb 27 GRAPHIC 2 282,0 24 028 DESIGN @f@a@d_main 29 VIEW symbol.sb 30 GRAPHIC 1976,0 25 031 DESIGN @f@a@d_main 32 VIEW symbol.sb 33 GRAPHIC 923,0 26 034 DESIGN @f@a@d_main 35 VIEW symbol.sb 36 GRAPHIC 92 8,0 27 037 DESIGN @f@a@d_main 38 VIEW symbol.sb 39 GRAPHIC 464,0 28 040 DESIGN @f@a@d_main 41 VIEW symbol.sb 42 GRAPHIC 1062,0 29 043 DESIGN @f@a@d_main 44 VIEW symbol.sb 45 GRAPHIC 4584,0 30 046 DESIGN @f@a@d_main 47 VIEW symbol.sb 48 GRAPHIC 458 9,0 31 049 DESIGN @f@a@d_main 50 VIEW symbol.sb 51 GRAPHIC 45 79,0 32 052 DESIGN @f@a@d_main 53 VIEW symbol.sb 54 GRAPHIC 1389,0 33 055 DESIGN @f@a@d_main 56 VIEW symbol.sb 57 GRAPHIC 1 725,0 34 058 DESIGN @f@a@d_main 59 VIEW symbol.sb 60 GRAPHIC 4497,0 35 061 DESIGN @f@a@d_main 62 VIEW symbol.sb 63 GRAPHIC 44 67,0 36 064 DESIGN @f@a@d_main 65 VIEW symbol.sb 66 GRAPHIC 44 87,0 37 067 DESIGN @f@a@d_main 68 VIEW symbol.sb 69 GRAPHIC 44 72,0 38 070 DESIGN @f@a@d_main 71 VIEW symbol.sb 72 GRAPHIC 447 7,0 39 073 DESIGN @f@a@d_main 74 VIEW symbol.sb 75 GRAPHIC 4 517,0 40 076 DESIGN @f@a@d_main 77 VIEW symbol.sb 78 GRAPHIC 2987,0 41 079 DESIGN @f@a@d_main 80 VIEW symbol.sb 81 GRAPHIC 29 92,0 42 082 DESIGN @f@a@d_main 83 VIEW symbol.sb 84 GRAPHIC 4780,0 43 085 DESIGN @f@a@d_main 86 VIEW symbol.sb 87 GRAPHIC 4 323,0 44 088 DESIGN @f@a@d_main 89 VIEW symbol.sb 90 GRAPHIC 833,0 45 091 DESIGN @f@a@d_main 92 VIEW symbol.sb 93 GRAPHIC 5206,0 46 094 DESIGN @f@a@d_main 95 VIEW symbol.sb 96 GRAPHIC 4911,0 47 097 DESIGN @f@a@d_main 98 VIEW symbol.sb 99 GRAPHIC 3641,0 48 0100 DESIGN @f@a@d_main 101 VIEW symbol.sb 102 GRAPHIC 4144,0 49 0103 DESIGN @f@a@d_main 104 VIEW symbol.sb 105 GRAPHIC 2448,0 50 0106 DESIGN @f@a@d_main 107 VIEW symbol.sb 108 GRAPHIC 24 53,0 51 0109 DESIGN @f@a@d_main 110 VIEW symbol.sb 111 GRAPHIC 4906,0 52 0112 DESIGN @f@a@d_main 113 VIEW symbol.sb 114 GRAPHIC 163,0 53 0115 DESIGN @f@a@d_main 116 VIEW symbol.sb 117 GRAPHIC 4067,0 54 0118 DESIGN @f@a@d_main 119 VIEW symbol.sb 120 GRAPHIC 4 502,0 55 0121 DESIGN @f@a@d_main 122 VIEW symbol.sb 123 GRAPHIC 45 12,0 56 0124 DESIGN @f@a@d_main 125 VIEW symbol.sb 126 GRAPHIC 4 916,0 57 0127 DESIGN @f@a@d_main 128 VIEW symbol.sb 129 GRAPHIC 3631,0 58 0130 DESIGN @f@a@d_main 131 VIEW symbol.sb 132 GRAPHIC 36 46,0 59 0133 DESIGN @f@a@d_main 134 VIEW symbol.sb 135 GRAPHIC 4507,0 610136 DESIGN @f@a@d_main 137 VIEW symbol.sb 138 GRAPHIC 1037,0 62 0139 DESIGN @f@a@d_main 140 VIEW symbol.sb 141 GRAPHIC 10 47,0 63 0142 DESIGN @f@a@d_main 143 VIEW symbol.sb 144 GRAPHIC 10 57,0 64 0145 DESIGN @f@a@d_main 146 VIEW symbol.sb 147 GRAPHIC 1 35,0 65 0148 DESIGN @f@a@d_main 149 VIEW symbol.sb 150 GRAPHIC 1 052,0 66 0151 DESIGN @f@a@d_main 152 VIEW symbol.sb 153 GRAPHIC 3636,0 67 0154 DESIGN @f@a@d_main 155 VIEW symbol.sb 156 GRAPHIC 1042,0 68 0157 DESIGN @f@a@d_main 158 VIEW symbol.sb 159 GRAPHIC 1 ,0 71015 GRAPHIC 5328,0 20 0 16 DESIGN @f@a@d_main 17 VIEW symbol.sb 18 GRAPHIC 2710,0 21 0 19 DESIGN @f@a@d_main 20 VIEW symbol.sb 21 GRAPHIC 2715,0 22 0 22 DESIGN @f@a@d_main 23 VIEW symbol.sb 24 GRAPHIC 2720,0 23 0 25 DESIGN @f@a@d_main 26 VIEW symbol.sb 27 GRAPHIC 2725,0 24 0 28 DESIGN @f@a@d_main 29 VIEW symbol.sb 30 GRAPHIC 2282,0 25 0 31 DESIGN @f@a@d_main 32 VIEW symbol.sb 33 GRAPHIC 1976,0 26 0 34 DESIGN @f@a@d_main 35 VIEW symbol.sb 36 GRAPHIC 923,0 27 0 37 DESIGN @f@a@d_main 38 VIEW symbol.sb 39 GRAPHIC 928,0 28 0 40 DESIGN @f@a@d_main 41 VIEW symbol.sb 42 GRAPHIC 464,0 29 0 43 DESIGN @f@a@d_main 44 VIEW symbol.sb 45 GRAPHIC 1062,0 30 0 46 DESIGN @f@a@d_main 47 VIEW symbol.sb 48 GRAPHIC 4584,0 31 0 49 DESIGN @f@a@d_main 50 VIEW symbol.sb 51 GRAPHIC 4589,0 32 0 52 DESIGN @f@a@d_main 53 VIEW symbol.sb 54 GRAPHIC 4579,0 33 0 55 DESIGN @f@a@d_main 56 VIEW symbol.sb 57 GRAPHIC 1389,0 34 0 58 DESIGN @f@a@d_main 59 VIEW symbol.sb 60 GRAPHIC 1725,0 35 0 61 DESIGN @f@a@d_main 62 VIEW symbol.sb 63 GRAPHIC 4497,0 36 0 64 DESIGN @f@a@d_main 65 VIEW symbol.sb 66 GRAPHIC 4467,0 37 0 67 DESIGN @f@a@d_main 68 VIEW symbol.sb 69 GRAPHIC 4487,0 38 0 70 DESIGN @f@a@d_main 71 VIEW symbol.sb 72 GRAPHIC 4472,0 39 0 73 DESIGN @f@a@d_main 74 VIEW symbol.sb 75 GRAPHIC 4477,0 40 0 76 DESIGN @f@a@d_main 77 VIEW symbol.sb 78 GRAPHIC 4517,0 41 0 79 DESIGN @f@a@d_main 80 VIEW symbol.sb 81 GRAPHIC 2987,0 42 0 82 DESIGN @f@a@d_main 83 VIEW symbol.sb 84 GRAPHIC 2992,0 43 0 85 DESIGN @f@a@d_main 86 VIEW symbol.sb 87 GRAPHIC 4780,0 44 0 88 DESIGN @f@a@d_main 89 VIEW symbol.sb 90 GRAPHIC 4323,0 45 0 91 DESIGN @f@a@d_main 92 VIEW symbol.sb 93 GRAPHIC 833,0 46 0 94 DESIGN @f@a@d_main 95 VIEW symbol.sb 96 GRAPHIC 5206,0 47 0 97 DESIGN @f@a@d_main 98 VIEW symbol.sb 99 GRAPHIC 4911,0 48 0 100 DESIGN @f@a@d_main 101 VIEW symbol.sb 102 GRAPHIC 3641,0 49 0 103 DESIGN @f@a@d_main 104 VIEW symbol.sb 105 GRAPHIC 4144,0 50 0 106 DESIGN @f@a@d_main 107 VIEW symbol.sb 108 GRAPHIC 2448,0 51 0 109 DESIGN @f@a@d_main 110 VIEW symbol.sb 111 GRAPHIC 2453,0 52 0 112 DESIGN @f@a@d_main 113 VIEW symbol.sb 114 GRAPHIC 4906,0 53 0 115 DESIGN @f@a@d_main 116 VIEW symbol.sb 117 GRAPHIC 163,0 54 0 118 DESIGN @f@a@d_main 119 VIEW symbol.sb 120 GRAPHIC 4067,0 55 0 121 DESIGN @f@a@d_main 122 VIEW symbol.sb 123 GRAPHIC 4502,0 56 0 124 DESIGN @f@a@d_main 125 VIEW symbol.sb 126 GRAPHIC 4512,0 57 0 127 DESIGN @f@a@d_main 128 VIEW symbol.sb 129 GRAPHIC 4916,0 58 0 130 DESIGN @f@a@d_main 131 VIEW symbol.sb 132 GRAPHIC 3631,0 59 0 133 DESIGN @f@a@d_main 134 VIEW symbol.sb 135 GRAPHIC 3646,0 60 0 136 DESIGN @f@a@d_main 137 VIEW symbol.sb 138 GRAPHIC 4507,0 62 0 139 DESIGN @f@a@d_main 140 VIEW symbol.sb 141 GRAPHIC 1037,0 63 0 142 DESIGN @f@a@d_main 143 VIEW symbol.sb 144 GRAPHIC 1047,0 64 0 145 DESIGN @f@a@d_main 146 VIEW symbol.sb 147 GRAPHIC 1057,0 65 0 148 DESIGN @f@a@d_main 149 VIEW symbol.sb 150 GRAPHIC 135,0 66 0 151 DESIGN @f@a@d_main 152 VIEW symbol.sb 153 GRAPHIC 1052,0 67 0 154 DESIGN @f@a@d_main 155 VIEW symbol.sb 156 GRAPHIC 3636,0 68 0 157 DESIGN @f@a@d_main 158 VIEW symbol.sb 159 GRAPHIC 1042,0 69 0 160 160 DESIGN @f@a@d_main 161 161 VIEW symbol.sb 162 162 GRAPHIC 1,0 72 0 163 163 DESIGN @f@a@d_main 164 VIEW struct.bd 165 NO_GRAPHIC 75 166 DESIGN @f@a@d_main 167 VIEW struct.bd 168 GRAPHIC 41,0 84 0 169 DESIGN @f@a@d_main 170 VIEW struct.bd 171 NO_GRAPHIC 96 172 DESIGN @f@a@d_main 173 VIEW struct.bd 174 GRAPHIC 0,0 99 2 175 DESIGN @f@a@d_main 176 VIEW struct.bd 177 GRAPHIC 4204,0 104 0 178 DESIGN @f@a@d_main 179 VIEW struct.bd 180 GRAPHIC 10008,0 105 0 181 DESIGN @f@a@d_main 182 VIEW struct.bd 183 GRAPHIC 5640,0 106 0 184 DESIGN @f@a@d_main 185 VIEW struct.bd 186 GRAPHIC 5632,0 107 0 187 DESIGN @f@a@d_main 188 VIEW struct.bd 189 GRAPHIC 326,0 108 0 190 DESIGN @f@a@d_main 191 VIEW struct.bd 192 GRAPHIC 13157,0 109 0 193 DESIGN @f@a@d_main 194 VIEW struct.bd 195 GRAPHIC 13163,0 110 0 196 DESIGN @f@a@d_main 197 VIEW struct.bd 198 GRAPHIC 5088,0 111 0 199 DESIGN @f@a@d_main 200 VIEW struct.bd 201 GRAPHIC 5104,0 112 0 202 DESIGN @f@a@d_main 203 VIEW struct.bd 204 GRAPHIC 5112,0 113 0 205 DESIGN @f@a@d_main 206 VIEW struct.bd 207 GRAPHIC 5096,0 114 0 208 DESIGN @f@a@d_main 209 VIEW struct.bd 210 GRAPHIC 5128,0 115 0 211 DESIGN @f@a@d_main 212 VIEW struct.bd 213 GRAPHIC 2592,0 116 0 214 DESIGN @f@a@d_main 215 VIEW struct.bd 216 GRAPHIC 5196,0 117 0 217 DESIGN @f@a@d_main 218 VIEW struct.bd 219 GRAPHIC 5588,0 118 0 220 DESIGN @f@a@d_main 221 VIEW struct.bd 222 GRAPHIC 10192,0 120 0 223 DESIGN @f@a@d_main 224 VIEW struct.bd 225 GRAPHIC 10200,0 122 0 226 DESIGN @f@a@d_main 227 VIEW struct.bd 228 GRAPHIC 2586,0 123 0 229 DESIGN @f@a@d_main 230 VIEW struct.bd 231 GRAPHIC 5194,0 124 0 232 DESIGN @f@a@d_main 233 VIEW struct.bd 234 GRAPHIC 5743,0 125 0 235 DESIGN @f@a@d_main 236 VIEW struct.bd 237 GRAPHIC 5960,0 126 0 238 DESIGN @f@a@d_main 239 VIEW struct.bd 240 GRAPHIC 6014,0 127 0 241 DESIGN @f@a@d_main 242 VIEW struct.bd 243 GRAPHIC 6016,0 128 0 244 DESIGN @f@a@d_main 245 VIEW struct.bd 246 GRAPHIC 6012,0 129 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 5120,0 130 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 5144,0 131 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 332,0 132 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 12304,0 133 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 12641,0 134 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 8508,0 135 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 8516,0 136 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 8583,0 137 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 4399,0 138 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 4417,0 139 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 4741,0 140 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 GRAPHIC 12647,0 143 0 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 12653,0 144 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 GRAPHIC 11403,0 145 0 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 GRAPHIC 4405,0 146 0 292 DESIGN @f@a@d_main 293 VIEW struct.bd 294 GRAPHIC 10314,0 147 0 295 DESIGN @f@a@d_main 296 VIEW struct.bd 297 GRAPHIC 6544,0 148 0 298 DESIGN @f@a@d_main 299 VIEW struct.bd 300 GRAPHIC 6450,0 149 0 301 DESIGN @f@a@d_main 302 VIEW struct.bd 303 GRAPHIC 5948,0 150 0 304 DESIGN @f@a@d_main 305 VIEW struct.bd 306 GRAPHIC 2640,0 151 0 307 DESIGN @f@a@d_main 308 VIEW struct.bd 309 GRAPHIC 9231,0 152 0 310 DESIGN @f@a@d_main 311 VIEW struct.bd 312 GRAPHIC 9239,0 153 0 313 DESIGN @f@a@d_main 314 VIEW struct.bd 315 GRAPHIC 9941,0 154 0 316 DESIGN @f@a@d_main 317 VIEW struct.bd 318 GRAPHIC 362,0 155 0 319 DESIGN @f@a@d_main 320 VIEW struct.bd 321 GRAPHIC 368,0 156 0 322 DESIGN @f@a@d_main 323 VIEW struct.bd 324 GRAPHIC 2297,0 157 0 325 DESIGN @f@a@d_main 326 VIEW struct.bd 327 GRAPHIC 2574,0 158 0 328 DESIGN @f@a@d_main 329 VIEW struct.bd 330 GRAPHIC 2580,0 159 0 331 DESIGN @f@a@d_main 332 VIEW struct.bd 333 GRAPHIC 10465,0 161 0 334 DESIGN @f@a@d_main 335 VIEW struct.bd 336 GRAPHIC 2924,0 162 0 337 DESIGN @f@a@d_main 338 VIEW struct.bd 339 GRAPHIC 2598,0 163 0 340 DESIGN @f@a@d_main 341 VIEW struct.bd 342 GRAPHIC 10264,0 164 0 343 DESIGN @f@a@d_main 344 VIEW struct.bd 345 GRAPHIC 13206,0 165 0 346 DESIGN @f@a@d_main 347 VIEW struct.bd 348 GRAPHIC 8730,0 166 0 349 DESIGN @f@a@d_main 350 VIEW struct.bd 351 GRAPHIC 8746,0 167 0 352 DESIGN @f@a@d_main 353 VIEW struct.bd 354 GRAPHIC 5478,0 168 0 355 DESIGN @f@a@d_main 356 VIEW struct.bd 357 GRAPHIC 5472,0 169 0 358 DESIGN @f@a@d_main 359 VIEW struct.bd 360 GRAPHIC 10627,0 170 0 361 DESIGN @f@a@d_main 362 VIEW struct.bd 363 GRAPHIC 10635,0 171 0 364 DESIGN @f@a@d_main 365 VIEW struct.bd 366 GRAPHIC 9949,0 172 0 367 DESIGN @f@a@d_main 368 VIEW struct.bd 369 GRAPHIC 10302,0 173 0 370 DESIGN @f@a@d_main 371 VIEW struct.bd 372 GRAPHIC 10308,0 174 0 373 DESIGN @f@a@d_main 374 VIEW struct.bd 375 GRAPHIC 10296,0 175 0 376 DESIGN @f@a@d_main 377 VIEW struct.bd 378 GRAPHIC 13208,0 176 0 379 DESIGN @f@a@d_main 380 VIEW struct.bd 381 GRAPHIC 11856,0 177 0 382 DESIGN @f@a@d_main 383 VIEW struct.bd 384 GRAPHIC 1981,0 178 0 385 DESIGN @f@a@d_main 386 VIEW struct.bd 387 GRAPHIC 10449,0 179 0 388 DESIGN @f@a@d_main 389 VIEW struct.bd 390 GRAPHIC 8414,0 180 0 391 DESIGN @f@a@d_main 392 VIEW struct.bd 393 GRAPHIC 2468,0 181 0 394 DESIGN @f@a@d_main 395 VIEW struct.bd 396 GRAPHIC 2492,0 182 0 397 DESIGN @f@a@d_main 398 VIEW struct.bd 399 GRAPHIC 2486,0 183 0 400 DESIGN @f@a@d_main 401 VIEW struct.bd 402 GRAPHIC 2474,0 184 0 403 DESIGN @f@a@d_main 404 VIEW struct.bd 405 GRAPHIC 2498,0 185 0 406 DESIGN @f@a@d_main 407 VIEW struct.bd 408 GRAPHIC 2504,0 186 0 409 DESIGN @f@a@d_main 410 VIEW struct.bd 411 GRAPHIC 2480,0 187 0 412 DESIGN @f@a@d_main 413 VIEW struct.bd 414 GRAPHIC 320,0 188 0 415 DESIGN @f@a@d_main 416 VIEW struct.bd 417 NO_GRAPHIC 189 418 DESIGN @f@a@d_main 419 VIEW struct.bd 420 GRAPHIC 6276,0 191 0 421 DESIGN @f@a@d_main 422 VIEW struct.bd 423 GRAPHIC 3888,0 192 0 424 DESIGN @f@a@d_main 425 VIEW struct.bd 426 NO_GRAPHIC 194 164 VIEW symbol.sb 165 GRAPHIC 1,0 73 0 166 DESIGN @f@a@d_main 167 VIEW struct.bd 168 NO_GRAPHIC 76 169 DESIGN @f@a@d_main 170 VIEW struct.bd 171 GRAPHIC 41,0 85 0 172 DESIGN @f@a@d_main 173 VIEW struct.bd 174 NO_GRAPHIC 97 175 DESIGN @f@a@d_main 176 VIEW struct.bd 177 GRAPHIC 0,0 100 2 178 DESIGN @f@a@d_main 179 VIEW struct.bd 180 GRAPHIC 4204,0 105 0 181 DESIGN @f@a@d_main 182 VIEW struct.bd 183 GRAPHIC 10008,0 106 0 184 DESIGN @f@a@d_main 185 VIEW struct.bd 186 GRAPHIC 5640,0 107 0 187 DESIGN @f@a@d_main 188 VIEW struct.bd 189 GRAPHIC 5632,0 108 0 190 DESIGN @f@a@d_main 191 VIEW struct.bd 192 GRAPHIC 326,0 109 0 193 DESIGN @f@a@d_main 194 VIEW struct.bd 195 GRAPHIC 13157,0 110 0 196 DESIGN @f@a@d_main 197 VIEW struct.bd 198 GRAPHIC 13163,0 111 0 199 DESIGN @f@a@d_main 200 VIEW struct.bd 201 GRAPHIC 5088,0 112 0 202 DESIGN @f@a@d_main 203 VIEW struct.bd 204 GRAPHIC 5104,0 113 0 205 DESIGN @f@a@d_main 206 VIEW struct.bd 207 GRAPHIC 5112,0 114 0 208 DESIGN @f@a@d_main 209 VIEW struct.bd 210 GRAPHIC 5096,0 115 0 211 DESIGN @f@a@d_main 212 VIEW struct.bd 213 GRAPHIC 5128,0 116 0 214 DESIGN @f@a@d_main 215 VIEW struct.bd 216 GRAPHIC 2592,0 117 0 217 DESIGN @f@a@d_main 218 VIEW struct.bd 219 GRAPHIC 5196,0 118 0 220 DESIGN @f@a@d_main 221 VIEW struct.bd 222 GRAPHIC 5588,0 119 0 223 DESIGN @f@a@d_main 224 VIEW struct.bd 225 GRAPHIC 10192,0 121 0 226 DESIGN @f@a@d_main 227 VIEW struct.bd 228 GRAPHIC 10200,0 123 0 229 DESIGN @f@a@d_main 230 VIEW struct.bd 231 GRAPHIC 2586,0 124 0 232 DESIGN @f@a@d_main 233 VIEW struct.bd 234 GRAPHIC 5194,0 125 0 235 DESIGN @f@a@d_main 236 VIEW struct.bd 237 GRAPHIC 5743,0 126 0 238 DESIGN @f@a@d_main 239 VIEW struct.bd 240 GRAPHIC 5960,0 127 0 241 DESIGN @f@a@d_main 242 VIEW struct.bd 243 GRAPHIC 6014,0 128 0 244 DESIGN @f@a@d_main 245 VIEW struct.bd 246 GRAPHIC 6016,0 129 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 6012,0 130 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 5120,0 131 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 5144,0 132 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 332,0 133 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 12304,0 134 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 12641,0 135 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 8508,0 136 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 8516,0 137 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 8583,0 138 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 4399,0 139 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 4417,0 140 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 GRAPHIC 4741,0 141 0 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 12647,0 144 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 GRAPHIC 12653,0 145 0 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 GRAPHIC 11403,0 146 0 292 DESIGN @f@a@d_main 293 VIEW struct.bd 294 GRAPHIC 4405,0 147 0 295 DESIGN @f@a@d_main 296 VIEW struct.bd 297 GRAPHIC 10314,0 148 0 298 DESIGN @f@a@d_main 299 VIEW struct.bd 300 GRAPHIC 6544,0 149 0 301 DESIGN @f@a@d_main 302 VIEW struct.bd 303 GRAPHIC 6450,0 150 0 304 DESIGN @f@a@d_main 305 VIEW struct.bd 306 GRAPHIC 5948,0 151 0 307 DESIGN @f@a@d_main 308 VIEW struct.bd 309 GRAPHIC 2640,0 152 0 310 DESIGN @f@a@d_main 311 VIEW struct.bd 312 GRAPHIC 9231,0 153 0 313 DESIGN @f@a@d_main 314 VIEW struct.bd 315 GRAPHIC 9239,0 154 0 316 DESIGN @f@a@d_main 317 VIEW struct.bd 318 GRAPHIC 9941,0 155 0 319 DESIGN @f@a@d_main 320 VIEW struct.bd 321 GRAPHIC 362,0 156 0 322 DESIGN @f@a@d_main 323 VIEW struct.bd 324 GRAPHIC 368,0 157 0 325 DESIGN @f@a@d_main 326 VIEW struct.bd 327 GRAPHIC 2297,0 158 0 328 DESIGN @f@a@d_main 329 VIEW struct.bd 330 GRAPHIC 2574,0 159 0 331 DESIGN @f@a@d_main 332 VIEW struct.bd 333 GRAPHIC 2580,0 160 0 334 DESIGN @f@a@d_main 335 VIEW struct.bd 336 GRAPHIC 10465,0 162 0 337 DESIGN @f@a@d_main 338 VIEW struct.bd 339 GRAPHIC 2924,0 163 0 340 DESIGN @f@a@d_main 341 VIEW struct.bd 342 GRAPHIC 2598,0 164 0 343 DESIGN @f@a@d_main 344 VIEW struct.bd 345 GRAPHIC 10264,0 165 0 346 DESIGN @f@a@d_main 347 VIEW struct.bd 348 GRAPHIC 13206,0 166 0 349 DESIGN @f@a@d_main 350 VIEW struct.bd 351 GRAPHIC 8730,0 167 0 352 DESIGN @f@a@d_main 353 VIEW struct.bd 354 GRAPHIC 8746,0 168 0 355 DESIGN @f@a@d_main 356 VIEW struct.bd 357 GRAPHIC 5478,0 169 0 358 DESIGN @f@a@d_main 359 VIEW struct.bd 360 GRAPHIC 5472,0 170 0 361 DESIGN @f@a@d_main 362 VIEW struct.bd 363 GRAPHIC 10627,0 171 0 364 DESIGN @f@a@d_main 365 VIEW struct.bd 366 GRAPHIC 10635,0 172 0 367 DESIGN @f@a@d_main 368 VIEW struct.bd 369 GRAPHIC 9949,0 173 0 370 DESIGN @f@a@d_main 371 VIEW struct.bd 372 GRAPHIC 10302,0 174 0 373 DESIGN @f@a@d_main 374 VIEW struct.bd 375 GRAPHIC 10308,0 175 0 376 DESIGN @f@a@d_main 377 VIEW struct.bd 378 GRAPHIC 10296,0 176 0 379 DESIGN @f@a@d_main 380 VIEW struct.bd 381 GRAPHIC 13208,0 177 0 382 DESIGN @f@a@d_main 383 VIEW struct.bd 384 GRAPHIC 11856,0 178 0 385 DESIGN @f@a@d_main 386 VIEW struct.bd 387 GRAPHIC 1981,0 179 0 388 DESIGN @f@a@d_main 389 VIEW struct.bd 390 GRAPHIC 10449,0 180 0 391 DESIGN @f@a@d_main 392 VIEW struct.bd 393 GRAPHIC 8414,0 181 0 394 DESIGN @f@a@d_main 395 VIEW struct.bd 396 GRAPHIC 2468,0 182 0 397 DESIGN @f@a@d_main 398 VIEW struct.bd 399 GRAPHIC 2492,0 183 0 400 DESIGN @f@a@d_main 401 VIEW struct.bd 402 GRAPHIC 2486,0 184 0 403 DESIGN @f@a@d_main 404 VIEW struct.bd 405 GRAPHIC 2474,0 185 0 406 DESIGN @f@a@d_main 407 VIEW struct.bd 408 GRAPHIC 2498,0 186 0 409 DESIGN @f@a@d_main 410 VIEW struct.bd 411 GRAPHIC 2504,0 187 0 412 DESIGN @f@a@d_main 413 VIEW struct.bd 414 GRAPHIC 2480,0 188 0 415 DESIGN @f@a@d_main 416 VIEW struct.bd 417 GRAPHIC 320,0 189 0 418 DESIGN @f@a@d_main 419 VIEW struct.bd 420 NO_GRAPHIC 190 421 DESIGN @f@a@d_main 422 VIEW struct.bd 423 GRAPHIC 6276,0 192 0 424 DESIGN @f@a@d_main 425 VIEW struct.bd 426 GRAPHIC 3888,0 193 0 427 DESIGN @f@a@d_main 428 VIEW struct.bd 429 NO_GRAPHIC 195 427 430 LIBRARY FACT_FAD_lib 428 431 DESIGN adc_buffer 429 432 VIEW beha 430 GRAPHIC 5678,0 19 60431 DESIGN @f@a@d_main 432 VIEW struct.bd 433 NO_GRAPHIC 20 3434 DESIGN @f@a@d_main 435 VIEW struct.bd 436 GRAPHIC 9175,0 20 50433 GRAPHIC 5678,0 197 0 434 DESIGN @f@a@d_main 435 VIEW struct.bd 436 NO_GRAPHIC 204 437 DESIGN @f@a@d_main 438 VIEW struct.bd 439 GRAPHIC 9175,0 206 0 437 440 DESIGN clock_generator_var_ps 438 441 VIEW symbol.sb 439 GRAPHIC 168,0 20 70442 GRAPHIC 168,0 208 0 440 443 DESIGN clock_generator_var_ps 441 444 VIEW symbol.sb 442 GRAPHIC 848,0 20 80445 GRAPHIC 848,0 209 0 443 446 DESIGN clock_generator_var_ps 444 447 VIEW symbol.sb 445 GRAPHIC 703,0 2 090448 GRAPHIC 703,0 210 0 446 449 DESIGN clock_generator_var_ps 447 450 VIEW symbol.sb 448 GRAPHIC 698,0 21 00451 GRAPHIC 698,0 211 0 449 452 DESIGN clock_generator_var_ps 450 453 VIEW symbol.sb 451 GRAPHIC 126,0 21 10454 GRAPHIC 126,0 212 0 452 455 DESIGN clock_generator_var_ps 453 456 VIEW symbol.sb 454 GRAPHIC 643,0 21 20457 GRAPHIC 643,0 213 0 455 458 DESIGN clock_generator_var_ps 456 459 VIEW symbol.sb 457 GRAPHIC 121,0 21 30460 GRAPHIC 121,0 214 0 458 461 DESIGN clock_generator_var_ps 459 462 VIEW symbol.sb 460 GRAPHIC 481,0 21 40463 GRAPHIC 481,0 215 0 461 464 DESIGN clock_generator_var_ps 462 465 VIEW symbol.sb 463 GRAPHIC 544,0 21 50466 GRAPHIC 544,0 216 0 464 467 DESIGN clock_generator_var_ps 465 468 VIEW symbol.sb 466 GRAPHIC 524,0 21 60469 GRAPHIC 524,0 217 0 467 470 DESIGN clock_generator_var_ps 468 471 VIEW symbol.sb 469 GRAPHIC 539,0 21 70472 GRAPHIC 539,0 218 0 470 473 DESIGN clock_generator_var_ps 471 474 VIEW symbol.sb 472 GRAPHIC 534,0 21 80475 GRAPHIC 534,0 219 0 473 476 DESIGN clock_generator_var_ps 474 477 VIEW symbol.sb 475 GRAPHIC 475,0 2 190478 GRAPHIC 475,0 220 0 476 479 DESIGN clock_generator_var_ps 477 480 VIEW symbol.sb 478 GRAPHIC 463,0 22 00481 GRAPHIC 463,0 221 0 479 482 DESIGN clock_generator_var_ps 480 483 VIEW symbol.sb 481 GRAPHIC 469,0 22 10482 DESIGN @f@a@d_main 483 VIEW struct.bd 484 GRAPHIC 13117,0 22 50485 DESIGN @f@a@d_main 486 VIEW struct.bd 487 GRAPHIC 13124,0 22 61488 DESIGN @f@a@d_main 489 VIEW struct.bd 490 NO_GRAPHIC 23 4491 DESIGN @f@a@d_main 492 VIEW struct.bd 493 GRAPHIC 5072,0 23 60484 GRAPHIC 469,0 222 0 485 DESIGN @f@a@d_main 486 VIEW struct.bd 487 GRAPHIC 13117,0 226 0 488 DESIGN @f@a@d_main 489 VIEW struct.bd 490 GRAPHIC 13124,0 227 1 491 DESIGN @f@a@d_main 492 VIEW struct.bd 493 NO_GRAPHIC 235 494 DESIGN @f@a@d_main 495 VIEW struct.bd 496 GRAPHIC 5072,0 237 0 494 497 DESIGN control_unit 495 498 VIEW symbol.sb 496 GRAPHIC 130,0 23 80499 GRAPHIC 130,0 239 0 497 500 DESIGN control_unit 498 501 VIEW symbol.sb 499 GRAPHIC 135,0 2 390502 GRAPHIC 135,0 240 0 500 503 DESIGN control_unit 501 504 VIEW symbol.sb 502 GRAPHIC 170,0 24 00505 GRAPHIC 170,0 241 0 503 506 DESIGN control_unit 504 507 VIEW symbol.sb 505 GRAPHIC 175,0 24 10508 GRAPHIC 175,0 242 0 506 509 DESIGN control_unit 507 510 VIEW symbol.sb 508 GRAPHIC 160,0 24 20511 GRAPHIC 160,0 243 0 509 512 DESIGN control_unit 510 513 VIEW symbol.sb 511 GRAPHIC 145,0 24 30514 GRAPHIC 145,0 244 0 512 515 DESIGN control_unit 513 516 VIEW symbol.sb 514 GRAPHIC 140,0 24 40517 GRAPHIC 140,0 245 0 515 518 DESIGN control_unit 516 519 VIEW symbol.sb 517 GRAPHIC 180,0 24 50520 GRAPHIC 180,0 246 0 518 521 DESIGN control_unit 519 522 VIEW symbol.sb 520 GRAPHIC 558,0 24 60523 GRAPHIC 558,0 247 0 521 524 DESIGN control_unit 522 525 VIEW symbol.sb 523 GRAPHIC 564,0 24 80526 GRAPHIC 564,0 249 0 524 527 DESIGN control_unit 525 528 VIEW symbol.sb 526 GRAPHIC 350,0 25 00529 GRAPHIC 350,0 251 0 527 530 DESIGN control_unit 528 531 VIEW symbol.sb 529 GRAPHIC 165,0 25 10532 GRAPHIC 165,0 252 0 530 533 DESIGN control_unit 531 534 VIEW symbol.sb 532 GRAPHIC 155,0 25 20535 GRAPHIC 155,0 253 0 533 536 DESIGN control_unit 534 537 VIEW symbol.sb 535 GRAPHIC 150,0 25 30536 DESIGN @f@a@d_main 537 VIEW struct.bd 538 GRAPHIC 8277,0 25 60538 GRAPHIC 150,0 254 0 539 DESIGN @f@a@d_main 540 VIEW struct.bd 541 GRAPHIC 8277,0 257 0 539 542 DESIGN data@r@a@m_64b_16b_width14_5 540 543 VIEW data@r@a@m_64b_16b_width14_5_a 541 GRAPHIC 48,0 25 80544 GRAPHIC 48,0 259 0 542 545 DESIGN data@r@a@m_64b_16b_width14_5 543 546 VIEW data@r@a@m_64b_16b_width14_5_a 544 GRAPHIC 53,0 2 590547 GRAPHIC 53,0 260 0 545 548 DESIGN data@r@a@m_64b_16b_width14_5 546 549 VIEW data@r@a@m_64b_16b_width14_5_a 547 GRAPHIC 58,0 26 00550 GRAPHIC 58,0 261 0 548 551 DESIGN data@r@a@m_64b_16b_width14_5 549 552 VIEW data@r@a@m_64b_16b_width14_5_a 550 GRAPHIC 63,0 26 10553 GRAPHIC 63,0 262 0 551 554 DESIGN data@r@a@m_64b_16b_width14_5 552 555 VIEW data@r@a@m_64b_16b_width14_5_a 553 GRAPHIC 68,0 26 20556 GRAPHIC 68,0 263 0 554 557 DESIGN data@r@a@m_64b_16b_width14_5 555 558 VIEW data@r@a@m_64b_16b_width14_5_a 556 GRAPHIC 73,0 26 30559 GRAPHIC 73,0 264 0 557 560 DESIGN data@r@a@m_64b_16b_width14_5 558 561 VIEW data@r@a@m_64b_16b_width14_5_a 559 GRAPHIC 78,0 26 40560 DESIGN @f@a@d_main 561 VIEW struct.bd 562 GRAPHIC 1399,0 26 70563 DESIGN data_generator 564 VIEW symbol.sb 565 GRAPHIC 14,0 26 81566 DESIGN data_generator 567 VIEW @behavioral 568 GRAPHIC 48,0 27 20569 DESIGN data_generator 570 VIEW @behavioral 571 GRAPHIC 53,0 27 40572 DESIGN data_generator 573 VIEW @behavioral 574 GRAPHIC 58,0 27 50575 DESIGN data_generator 576 VIEW @behavioral 577 GRAPHIC 73,0 27 60578 DESIGN data_generator 579 VIEW @behavioral 580 GRAPHIC 78,0 27 70581 DESIGN data_generator 582 VIEW @behavioral 583 GRAPHIC 402,0 27 80584 DESIGN data_generator 585 VIEW @behavioral 586 GRAPHIC 407,0 2 790587 DESIGN data_generator 588 VIEW @behavioral 589 GRAPHIC 1479,0 28 00590 DESIGN data_generator 591 VIEW @behavioral 592 GRAPHIC 1122,0 28 20593 DESIGN data_generator 594 VIEW @behavioral 595 GRAPHIC 963,0 28 40596 DESIGN data_generator 597 VIEW @behavioral 598 GRAPHIC 1127,0 28 60599 DESIGN data_generator 600 VIEW @behavioral 601 GRAPHIC 1048,0 28 80602 DESIGN data_generator 603 VIEW @behavioral 604 GRAPHIC 958,0 2 890605 DESIGN data_generator 606 VIEW @behavioral 607 GRAPHIC 1053,0 29 00608 DESIGN data_generator 609 VIEW @behavioral 610 GRAPHIC 1201,0 29 10611 DESIGN data_generator 612 VIEW @behavioral 613 GRAPHIC 1196,0 29 20614 DESIGN data_generator 615 VIEW @behavioral 616 GRAPHIC 1206,0 29 30617 DESIGN data_generator 618 VIEW @behavioral 619 GRAPHIC 473,0 29 40620 DESIGN data_generator 621 VIEW @behavioral 622 GRAPHIC 412,0 29 50623 DESIGN data_generator 624 VIEW @behavioral 625 GRAPHIC 1085,0 29 60626 DESIGN data_generator 627 VIEW @behavioral 628 GRAPHIC 1090,0 29 70629 DESIGN data_generator 630 VIEW @behavioral 631 GRAPHIC 1240,0 29 80632 DESIGN data_generator 633 VIEW @behavioral 634 GRAPHIC 526,0 2990635 DESIGN data_generator 636 VIEW @behavioral 637 GRAPHIC 88,0 30 00638 DESIGN data_generator 639 VIEW @behavioral 640 GRAPHIC 285,0 30 10641 DESIGN data_generator 642 VIEW @behavioral 643 GRAPHIC 93,0 30 20644 DESIGN data_generator 645 VIEW @behavioral 646 GRAPHIC 98,0 30 30647 DESIGN data_generator 648 VIEW @behavioral 649 GRAPHIC 1164,0 30 40650 DESIGN data_generator 651 VIEW @behavioral 652 GRAPHIC 1159,0 30 60653 DESIGN data_generator 654 VIEW @behavioral 655 GRAPHIC 898,0 30 70656 DESIGN data_generator 657 VIEW @behavioral 658 GRAPHIC 637,0 30 80659 DESIGN data_generator 660 VIEW @behavioral 661 GRAPHIC 1395,0 3 090662 DESIGN data_generator 663 VIEW @behavioral 664 GRAPHIC 1427,0 31 00665 DESIGN data_generator 666 VIEW @behavioral 667 GRAPHIC 676,0 31 10668 DESIGN data_generator 669 VIEW @behavioral 670 GRAPHIC 1551,0 31 20671 DESIGN data_generator 672 VIEW @behavioral 673 GRAPHIC 1583,0 31 50674 DESIGN data_generator 675 VIEW @behavioral 676 GRAPHIC 681,0 31 60677 DESIGN data_generator 678 VIEW @behavioral 679 GRAPHIC 801,0 31 80680 DESIGN data_generator 681 VIEW @behavioral 682 GRAPHIC 1464,0 32 00683 DESIGN data_generator 684 VIEW @behavioral 685 GRAPHIC 1469,0 32 10686 DESIGN data_generator 687 VIEW @behavioral 688 GRAPHIC 1459,0 32 20689 DESIGN data_generator 690 VIEW @behavioral 691 GRAPHIC 1474,0 32 30692 DESIGN data_generator 693 VIEW @behavioral 694 GRAPHIC 806,0 32 40695 DESIGN data_generator 696 VIEW @behavioral 697 GRAPHIC 811,0 32 50698 DESIGN data_generator 699 VIEW @behavioral 700 GRAPHIC 1519,0 32 60701 DESIGN @f@a@d_main 702 VIEW struct.bd 703 GRAPHIC 4903,0 3 290704 DESIGN @f@a@d_main 705 VIEW struct.bd 706 NO_GRAPHIC 34 7707 DESIGN @f@a@d_main 708 VIEW struct.bd 709 GRAPHIC 11209,0 3 490710 DESIGN @f@a@d_main 711 VIEW struct.bd 712 GRAPHIC 11216,0 35 01713 DESIGN @f@a@d_main 714 VIEW struct.bd 715 NO_GRAPHIC 36 4716 DESIGN @f@a@d_main 717 VIEW struct.bd 718 GRAPHIC 2311,0 36 60719 DESIGN memory_manager 720 VIEW symbol.sb 721 GRAPHIC 14,0 36 71722 DESIGN memory_manager 723 VIEW beha 724 GRAPHIC 138,0 37 20725 DESIGN memory_manager 726 VIEW beha 727 GRAPHIC 194,0 37 30728 DESIGN memory_manager 729 VIEW beha 730 GRAPHIC 349,0 37 40731 DESIGN memory_manager 732 VIEW beha 733 GRAPHIC 949,0 37 50734 DESIGN memory_manager 735 VIEW beha 736 GRAPHIC 569,0 37 70737 DESIGN memory_manager 738 VIEW beha 739 GRAPHIC 224,0 3 790740 DESIGN memory_manager 741 VIEW beha 742 GRAPHIC 254,0 38 00743 DESIGN memory_manager 744 VIEW beha 745 GRAPHIC 804,0 38 10746 DESIGN memory_manager 747 VIEW beha 748 GRAPHIC 433,0 38 20749 DESIGN memory_manager 750 VIEW beha 751 GRAPHIC 622,0 38 30752 DESIGN memory_manager 753 VIEW beha 754 GRAPHIC 289,0 38 40755 DESIGN memory_manager 756 VIEW beha 757 GRAPHIC 309,0 38 50758 DESIGN memory_manager 759 VIEW beha 760 GRAPHIC 284,0 38 60761 DESIGN memory_manager 762 VIEW beha 763 GRAPHIC 294,0 38 70764 DESIGN memory_manager 765 VIEW beha 766 GRAPHIC 304,0 38 80767 DESIGN memory_manager 768 VIEW beha 769 GRAPHIC 299,0 3 890770 DESIGN memory_manager 771 VIEW beha 772 GRAPHIC 379,0 39 00773 DESIGN memory_manager 774 VIEW beha 775 GRAPHIC 915,0 39 10776 DESIGN memory_manager 777 VIEW beha 778 GRAPHIC 51,0 39 20779 DESIGN @f@a@d_main 780 VIEW struct.bd 781 GRAPHIC 5793,0 39 50562 GRAPHIC 78,0 265 0 563 DESIGN @f@a@d_main 564 VIEW struct.bd 565 GRAPHIC 1399,0 268 0 566 DESIGN data_generator 567 VIEW symbol.sb 568 GRAPHIC 14,0 269 1 569 DESIGN data_generator 570 VIEW @behavioral 571 GRAPHIC 48,0 273 0 572 DESIGN data_generator 573 VIEW @behavioral 574 GRAPHIC 53,0 275 0 575 DESIGN data_generator 576 VIEW @behavioral 577 GRAPHIC 58,0 276 0 578 DESIGN data_generator 579 VIEW @behavioral 580 GRAPHIC 73,0 277 0 581 DESIGN data_generator 582 VIEW @behavioral 583 GRAPHIC 78,0 278 0 584 DESIGN data_generator 585 VIEW @behavioral 586 GRAPHIC 402,0 279 0 587 DESIGN data_generator 588 VIEW @behavioral 589 GRAPHIC 407,0 280 0 590 DESIGN data_generator 591 VIEW @behavioral 592 GRAPHIC 1479,0 281 0 593 DESIGN data_generator 594 VIEW @behavioral 595 GRAPHIC 1122,0 283 0 596 DESIGN data_generator 597 VIEW @behavioral 598 GRAPHIC 963,0 285 0 599 DESIGN data_generator 600 VIEW @behavioral 601 GRAPHIC 1127,0 287 0 602 DESIGN data_generator 603 VIEW @behavioral 604 GRAPHIC 1048,0 289 0 605 DESIGN data_generator 606 VIEW @behavioral 607 GRAPHIC 958,0 290 0 608 DESIGN data_generator 609 VIEW @behavioral 610 GRAPHIC 1053,0 291 0 611 DESIGN data_generator 612 VIEW @behavioral 613 GRAPHIC 1201,0 292 0 614 DESIGN data_generator 615 VIEW @behavioral 616 GRAPHIC 1196,0 293 0 617 DESIGN data_generator 618 VIEW @behavioral 619 GRAPHIC 1206,0 294 0 620 DESIGN data_generator 621 VIEW @behavioral 622 GRAPHIC 473,0 295 0 623 DESIGN data_generator 624 VIEW @behavioral 625 GRAPHIC 412,0 296 0 626 DESIGN data_generator 627 VIEW @behavioral 628 GRAPHIC 1085,0 297 0 629 DESIGN data_generator 630 VIEW @behavioral 631 GRAPHIC 1090,0 298 0 632 DESIGN data_generator 633 VIEW @behavioral 634 GRAPHIC 1240,0 299 0 635 DESIGN data_generator 636 VIEW @behavioral 637 GRAPHIC 526,0 300 0 638 DESIGN data_generator 639 VIEW @behavioral 640 GRAPHIC 88,0 301 0 641 DESIGN data_generator 642 VIEW @behavioral 643 GRAPHIC 285,0 302 0 644 DESIGN data_generator 645 VIEW @behavioral 646 GRAPHIC 93,0 303 0 647 DESIGN data_generator 648 VIEW @behavioral 649 GRAPHIC 98,0 304 0 650 DESIGN data_generator 651 VIEW @behavioral 652 GRAPHIC 1164,0 305 0 653 DESIGN data_generator 654 VIEW @behavioral 655 GRAPHIC 1159,0 307 0 656 DESIGN data_generator 657 VIEW @behavioral 658 GRAPHIC 898,0 308 0 659 DESIGN data_generator 660 VIEW @behavioral 661 GRAPHIC 637,0 309 0 662 DESIGN data_generator 663 VIEW @behavioral 664 GRAPHIC 1395,0 310 0 665 DESIGN data_generator 666 VIEW @behavioral 667 GRAPHIC 1427,0 311 0 668 DESIGN data_generator 669 VIEW @behavioral 670 GRAPHIC 676,0 312 0 671 DESIGN data_generator 672 VIEW @behavioral 673 GRAPHIC 1551,0 313 0 674 DESIGN data_generator 675 VIEW @behavioral 676 GRAPHIC 1583,0 316 0 677 DESIGN data_generator 678 VIEW @behavioral 679 GRAPHIC 681,0 317 0 680 DESIGN data_generator 681 VIEW @behavioral 682 GRAPHIC 801,0 319 0 683 DESIGN data_generator 684 VIEW @behavioral 685 GRAPHIC 1464,0 321 0 686 DESIGN data_generator 687 VIEW @behavioral 688 GRAPHIC 1469,0 322 0 689 DESIGN data_generator 690 VIEW @behavioral 691 GRAPHIC 1459,0 323 0 692 DESIGN data_generator 693 VIEW @behavioral 694 GRAPHIC 1474,0 324 0 695 DESIGN data_generator 696 VIEW @behavioral 697 GRAPHIC 806,0 325 0 698 DESIGN data_generator 699 VIEW @behavioral 700 GRAPHIC 811,0 326 0 701 DESIGN data_generator 702 VIEW @behavioral 703 GRAPHIC 1519,0 327 0 704 DESIGN @f@a@d_main 705 VIEW struct.bd 706 GRAPHIC 4903,0 330 0 707 DESIGN @f@a@d_main 708 VIEW struct.bd 709 NO_GRAPHIC 348 710 DESIGN @f@a@d_main 711 VIEW struct.bd 712 GRAPHIC 11209,0 350 0 713 DESIGN @f@a@d_main 714 VIEW struct.bd 715 GRAPHIC 11216,0 351 1 716 DESIGN @f@a@d_main 717 VIEW struct.bd 718 NO_GRAPHIC 365 719 DESIGN @f@a@d_main 720 VIEW struct.bd 721 GRAPHIC 2311,0 367 0 722 DESIGN memory_manager 723 VIEW symbol.sb 724 GRAPHIC 14,0 368 1 725 DESIGN memory_manager 726 VIEW beha 727 GRAPHIC 138,0 373 0 728 DESIGN memory_manager 729 VIEW beha 730 GRAPHIC 194,0 374 0 731 DESIGN memory_manager 732 VIEW beha 733 GRAPHIC 349,0 375 0 734 DESIGN memory_manager 735 VIEW beha 736 GRAPHIC 949,0 376 0 737 DESIGN memory_manager 738 VIEW beha 739 GRAPHIC 569,0 378 0 740 DESIGN memory_manager 741 VIEW beha 742 GRAPHIC 224,0 380 0 743 DESIGN memory_manager 744 VIEW beha 745 GRAPHIC 254,0 381 0 746 DESIGN memory_manager 747 VIEW beha 748 GRAPHIC 804,0 382 0 749 DESIGN memory_manager 750 VIEW beha 751 GRAPHIC 433,0 383 0 752 DESIGN memory_manager 753 VIEW beha 754 GRAPHIC 622,0 384 0 755 DESIGN memory_manager 756 VIEW beha 757 GRAPHIC 289,0 385 0 758 DESIGN memory_manager 759 VIEW beha 760 GRAPHIC 309,0 386 0 761 DESIGN memory_manager 762 VIEW beha 763 GRAPHIC 284,0 387 0 764 DESIGN memory_manager 765 VIEW beha 766 GRAPHIC 294,0 388 0 767 DESIGN memory_manager 768 VIEW beha 769 GRAPHIC 304,0 389 0 770 DESIGN memory_manager 771 VIEW beha 772 GRAPHIC 299,0 390 0 773 DESIGN memory_manager 774 VIEW beha 775 GRAPHIC 379,0 391 0 776 DESIGN memory_manager 777 VIEW beha 778 GRAPHIC 915,0 392 0 779 DESIGN memory_manager 780 VIEW beha 781 GRAPHIC 51,0 393 0 782 DESIGN @f@a@d_main 783 VIEW struct.bd 784 GRAPHIC 5793,0 396 0 782 785 DESIGN spi_interface 783 786 VIEW symbol.sb 784 GRAPHIC 1121,0 39 70787 GRAPHIC 1121,0 398 0 785 788 DESIGN spi_interface 786 789 VIEW symbol.sb 787 GRAPHIC 326,0 39 80790 GRAPHIC 326,0 399 0 788 791 DESIGN spi_interface 789 792 VIEW symbol.sb 790 GRAPHIC 197,0 3990793 GRAPHIC 197,0 400 0 791 794 DESIGN spi_interface 792 795 VIEW symbol.sb 793 GRAPHIC 321,0 40 00796 GRAPHIC 321,0 401 0 794 797 DESIGN spi_interface 795 798 VIEW symbol.sb 796 GRAPHIC 1198,0 40 10799 GRAPHIC 1198,0 402 0 797 800 DESIGN spi_interface 798 801 VIEW symbol.sb 799 GRAPHIC 1017,0 40 20802 GRAPHIC 1017,0 403 0 800 803 DESIGN spi_interface 801 804 VIEW symbol.sb 802 GRAPHIC 1229,0 40 30805 GRAPHIC 1229,0 404 0 803 806 DESIGN spi_interface 804 807 VIEW symbol.sb 805 GRAPHIC 126,0 40 40808 GRAPHIC 126,0 405 0 806 809 DESIGN spi_interface 807 810 VIEW symbol.sb 808 GRAPHIC 819,0 40 50811 GRAPHIC 819,0 406 0 809 812 DESIGN spi_interface 810 813 VIEW symbol.sb 811 GRAPHIC 1022,0 40 60814 GRAPHIC 1022,0 407 0 812 815 DESIGN spi_interface 813 816 VIEW symbol.sb 814 GRAPHIC 824,0 40 70817 GRAPHIC 824,0 408 0 815 818 DESIGN spi_interface 816 819 VIEW symbol.sb 817 GRAPHIC 1283,0 40 80818 DESIGN @f@a@d_main 819 VIEW struct.bd 820 GRAPHIC 1768,0 41 10820 GRAPHIC 1283,0 409 0 821 DESIGN @f@a@d_main 822 VIEW struct.bd 823 GRAPHIC 1768,0 412 0 821 824 DESIGN trigger_counter 822 825 VIEW beha 823 GRAPHIC 48,0 41 30826 GRAPHIC 48,0 414 0 824 827 DESIGN trigger_counter 825 828 VIEW beha 826 GRAPHIC 53,0 41 40829 GRAPHIC 53,0 415 0 827 830 DESIGN trigger_counter 828 831 VIEW beha 829 GRAPHIC 148,0 415 0 830 DESIGN @f@a@d_main 831 VIEW struct.bd 832 GRAPHIC 12625,0 418 0 833 DESIGN @f@a@d_main 834 VIEW struct.bd 835 NO_GRAPHIC 426 836 DESIGN @f@a@d_main 837 VIEW struct.bd 838 GRAPHIC 1606,0 428 0 839 DESIGN w5300_modul 840 VIEW symbol.sb 841 GRAPHIC 14,0 429 1 842 DESIGN w5300_modul 843 VIEW @behavioral 844 GRAPHIC 48,0 433 0 845 DESIGN w5300_modul 846 VIEW @behavioral 847 GRAPHIC 53,0 434 0 848 DESIGN w5300_modul 849 VIEW @behavioral 850 GRAPHIC 58,0 435 0 851 DESIGN w5300_modul 852 VIEW @behavioral 853 GRAPHIC 63,0 436 0 854 DESIGN w5300_modul 855 VIEW @behavioral 856 GRAPHIC 68,0 437 0 857 DESIGN w5300_modul 858 VIEW @behavioral 859 GRAPHIC 73,0 438 0 860 DESIGN w5300_modul 861 VIEW @behavioral 862 GRAPHIC 491,0 439 0 863 DESIGN w5300_modul 864 VIEW @behavioral 865 GRAPHIC 83,0 440 0 866 DESIGN w5300_modul 867 VIEW @behavioral 868 GRAPHIC 88,0 441 0 869 DESIGN w5300_modul 870 VIEW @behavioral 871 GRAPHIC 93,0 442 0 872 DESIGN w5300_modul 873 VIEW @behavioral 874 GRAPHIC 98,0 443 0 875 DESIGN w5300_modul 876 VIEW @behavioral 877 GRAPHIC 103,0 444 0 878 DESIGN w5300_modul 879 VIEW @behavioral 880 GRAPHIC 108,0 445 0 881 DESIGN w5300_modul 882 VIEW @behavioral 883 GRAPHIC 113,0 446 0 884 DESIGN w5300_modul 885 VIEW @behavioral 886 GRAPHIC 885,0 447 0 887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 118,0 448 0 890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 353,0 449 0 893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 348,0 450 0 896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 385,0 451 0 899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 521,0 452 0 902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1187,0 454 0 905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 1192,0 455 0 908 DESIGN w5300_modul 909 VIEW @behavioral 910 GRAPHIC 576,0 456 0 911 DESIGN w5300_modul 912 VIEW @behavioral 913 GRAPHIC 566,0 458 0 914 DESIGN w5300_modul 915 VIEW @behavioral 916 GRAPHIC 551,0 459 0 917 DESIGN w5300_modul 918 VIEW @behavioral 919 GRAPHIC 561,0 460 0 920 DESIGN w5300_modul 921 VIEW @behavioral 922 GRAPHIC 571,0 461 0 923 DESIGN w5300_modul 924 VIEW @behavioral 925 GRAPHIC 640,0 462 0 926 DESIGN w5300_modul 927 VIEW @behavioral 928 GRAPHIC 1052,0 463 0 929 DESIGN w5300_modul 930 VIEW @behavioral 931 GRAPHIC 1057,0 465 0 932 DESIGN w5300_modul 933 VIEW @behavioral 934 GRAPHIC 556,0 467 0 935 DESIGN w5300_modul 936 VIEW @behavioral 937 GRAPHIC 670,0 469 0 938 DESIGN w5300_modul 939 VIEW @behavioral 940 GRAPHIC 723,0 470 0 941 DESIGN w5300_modul 942 VIEW @behavioral 943 GRAPHIC 917,0 471 0 944 DESIGN w5300_modul 945 VIEW @behavioral 946 GRAPHIC 949,0 472 0 947 DESIGN w5300_modul 948 VIEW @behavioral 949 GRAPHIC 954,0 473 0 950 DESIGN w5300_modul 951 VIEW @behavioral 952 GRAPHIC 988,0 474 0 953 DESIGN w5300_modul 954 VIEW @behavioral 955 GRAPHIC 1020,0 475 0 956 DESIGN w5300_modul 957 VIEW @behavioral 958 GRAPHIC 1130,0 476 0 959 DESIGN w5300_modul 960 VIEW @behavioral 961 GRAPHIC 1096,0 477 0 962 DESIGN w5300_modul 963 VIEW @behavioral 964 GRAPHIC 1091,0 478 0 832 GRAPHIC 148,0 416 0 833 DESIGN @f@a@d_main 834 VIEW struct.bd 835 GRAPHIC 12625,0 419 0 836 DESIGN @f@a@d_main 837 VIEW struct.bd 838 NO_GRAPHIC 427 839 DESIGN @f@a@d_main 840 VIEW struct.bd 841 GRAPHIC 1606,0 429 0 842 DESIGN w5300_modul 843 VIEW symbol.sb 844 GRAPHIC 14,0 430 1 845 DESIGN w5300_modul 846 VIEW @behavioral 847 GRAPHIC 48,0 434 0 848 DESIGN w5300_modul 849 VIEW @behavioral 850 GRAPHIC 53,0 435 0 851 DESIGN w5300_modul 852 VIEW @behavioral 853 GRAPHIC 58,0 436 0 854 DESIGN w5300_modul 855 VIEW @behavioral 856 GRAPHIC 63,0 437 0 857 DESIGN w5300_modul 858 VIEW @behavioral 859 GRAPHIC 68,0 438 0 860 DESIGN w5300_modul 861 VIEW @behavioral 862 GRAPHIC 73,0 439 0 863 DESIGN w5300_modul 864 VIEW @behavioral 865 GRAPHIC 491,0 440 0 866 DESIGN w5300_modul 867 VIEW @behavioral 868 GRAPHIC 83,0 441 0 869 DESIGN w5300_modul 870 VIEW @behavioral 871 GRAPHIC 88,0 442 0 872 DESIGN w5300_modul 873 VIEW @behavioral 874 GRAPHIC 93,0 443 0 875 DESIGN w5300_modul 876 VIEW @behavioral 877 GRAPHIC 98,0 444 0 878 DESIGN w5300_modul 879 VIEW @behavioral 880 GRAPHIC 103,0 445 0 881 DESIGN w5300_modul 882 VIEW @behavioral 883 GRAPHIC 108,0 446 0 884 DESIGN w5300_modul 885 VIEW @behavioral 886 GRAPHIC 113,0 447 0 887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 885,0 448 0 890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 118,0 449 0 893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 353,0 450 0 896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 348,0 451 0 899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 385,0 452 0 902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 521,0 453 0 905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 1187,0 455 0 908 DESIGN w5300_modul 909 VIEW @behavioral 910 GRAPHIC 1192,0 456 0 911 DESIGN w5300_modul 912 VIEW @behavioral 913 GRAPHIC 576,0 457 0 914 DESIGN w5300_modul 915 VIEW @behavioral 916 GRAPHIC 566,0 459 0 917 DESIGN w5300_modul 918 VIEW @behavioral 919 GRAPHIC 551,0 460 0 920 DESIGN w5300_modul 921 VIEW @behavioral 922 GRAPHIC 561,0 461 0 923 DESIGN w5300_modul 924 VIEW @behavioral 925 GRAPHIC 571,0 462 0 926 DESIGN w5300_modul 927 VIEW @behavioral 928 GRAPHIC 640,0 463 0 929 DESIGN w5300_modul 930 VIEW @behavioral 931 GRAPHIC 1052,0 464 0 932 DESIGN w5300_modul 933 VIEW @behavioral 934 GRAPHIC 1057,0 466 0 935 DESIGN w5300_modul 936 VIEW @behavioral 937 GRAPHIC 556,0 468 0 938 DESIGN w5300_modul 939 VIEW @behavioral 940 GRAPHIC 1283,0 470 0 941 DESIGN w5300_modul 942 VIEW @behavioral 943 GRAPHIC 1315,0 471 0 944 DESIGN w5300_modul 945 VIEW @behavioral 946 GRAPHIC 1320,0 472 0 947 DESIGN w5300_modul 948 VIEW @behavioral 949 GRAPHIC 670,0 473 0 950 DESIGN w5300_modul 951 VIEW @behavioral 952 GRAPHIC 723,0 474 0 953 DESIGN w5300_modul 954 VIEW @behavioral 955 GRAPHIC 917,0 475 0 956 DESIGN w5300_modul 957 VIEW @behavioral 958 GRAPHIC 949,0 476 0 959 DESIGN w5300_modul 960 VIEW @behavioral 961 GRAPHIC 954,0 477 0 962 DESIGN w5300_modul 963 VIEW @behavioral 964 GRAPHIC 988,0 478 0 965 DESIGN w5300_modul 966 VIEW @behavioral 967 GRAPHIC 1020,0 479 0 968 DESIGN w5300_modul 969 VIEW @behavioral 970 GRAPHIC 1130,0 480 0 971 DESIGN w5300_modul 972 VIEW @behavioral 973 GRAPHIC 1096,0 481 0 974 DESIGN w5300_modul 975 VIEW @behavioral 976 GRAPHIC 1091,0 482 0 965 977 LIBRARY FACT_FAD_lib 966 978 DESIGN @f@a@d_main 967 979 VIEW struct.bd 968 NO_GRAPHIC 481 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 5678,0 484 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 9175,0 485 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 13117,0 486 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 5072,0 487 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 8277,0 488 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 1399,0 489 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 4903,0 490 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 11209,0 491 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 2311,0 492 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 5793,0 493 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 1768,0 494 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 12625,0 495 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 1606,0 496 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 NO_GRAPHIC 499 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 6529,0 501 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 9957,0 504 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 8721,0 507 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 12295,0 510 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 9472,0 513 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 9662,0 516 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 9679,0 519 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 9710,0 522 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 8562,0 525 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 10380,0 536 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 13266,0 539 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 NO_GRAPHIC 542 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 5678,0 544 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 5646,0 546 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 4272,0 547 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 2786,0 548 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5626,0 549 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 5634,0 550 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 9175,0 552 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 4042,0 554 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 10036,0 555 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 9253,0 556 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 9261,0 557 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 6072,0 558 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 3984,0 559 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 3888,0 560 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 9353,0 561 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 9269,0 562 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 9325,0 563 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 9283,0 564 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 9297,0 565 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 9367,0 566 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 9397,0 567 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 9382,0 568 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 13117,0 570 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 13124,0 571 1 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 13143,0 575 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 13159,0 576 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 13165,0 577 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 13210,0 578 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 5072,0 580 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 5582,0 582 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 5090,0 583 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 5130,0 584 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 5184,0 585 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 5122,0 586 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 5106,0 587 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5098,0 588 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 5190,0 589 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 10194,0 590 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 10202,0 591 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 6002,0 592 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 5146,0 593 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 5138,0 594 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 5114,0 595 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 8277,0 597 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5602,0 599 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 334,0 600 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 328,0 601 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 322,0 602 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 4240,0 603 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 364,0 604 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 370,0 605 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 1399,0 607 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 1406,0 608 1 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5602,0 612 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 334,0 613 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 328,0 614 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 322,0 615 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 2299,0 616 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 2576,0 617 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 2582,0 618 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 10467,0 619 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 2588,0 620 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 5184,0 621 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 5745,0 622 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 2594,0 623 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 5190,0 624 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 5404,0 625 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 6018,0 626 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 6002,0 627 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 6008,0 628 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 5138,0 629 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 2600,0 630 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 5480,0 631 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 5474,0 632 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 6064,0 633 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 2642,0 634 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 1411,0 635 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 1682,0 636 0 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 1983,0 637 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 10439,0 638 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 5950,0 639 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 5962,0 640 0 1293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 5626,0 641 0 1296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 2778,0 642 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 9006,0 643 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 5634,0 644 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 8577,0 645 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 12649,0 646 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 12655,0 647 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 4401,0 648 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 4419,0 649 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 10298,0 650 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 10304,0 651 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 10316,0 652 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 10310,0 653 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 4743,0 654 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 4407,0 655 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 11405,0 656 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 4903,0 658 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 4757,0 660 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 4401,0 661 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 4419,0 662 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 4671,0 663 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 4679,0 664 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 4687,0 665 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 4695,0 666 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 4407,0 667 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 4743,0 668 0 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 10298,0 669 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 10310,0 670 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 10304,0 671 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 10316,0 672 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 10322,0 673 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 4948,0 674 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 10010,0 675 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 11209,0 677 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 11216,0 678 1 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 10699,0 684 0 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 10723,0 685 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 10737,0 686 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 10751,0 687 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 12707,0 688 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 10707,0 689 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 10685,0 690 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 10691,0 691 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 2311,0 693 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 2318,0 694 1 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 6082,0 699 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 2588,0 700 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2582,0 701 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 10467,0 702 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 5168,0 703 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2576,0 704 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2594,0 705 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 6018,0 706 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 2600,0 707 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 2642,0 708 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 2488,0 709 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 2482,0 710 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 2494,0 711 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 2476,0 712 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 2506,0 713 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 2500,0 714 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 2470,0 715 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 8416,0 716 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 2299,0 717 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 5793,0 719 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 5805,0 721 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 5745,0 722 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 5146,0 723 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 5404,0 724 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 6008,0 725 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 5829,0 726 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 6160,0 727 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 8732,0 728 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 5480,0 729 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 5837,0 730 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 5474,0 731 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 5821,0 732 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 1768,0 734 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 1983,0 736 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 10439,0 737 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 6276,0 738 0 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 12625,0 740 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 12687,0 742 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 12643,0 743 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 12635,0 744 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 12667,0 745 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 12649,0 746 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 12655,0 747 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 1606,0 749 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 1613,0 750 1 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 3888,0 754 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 376,0 755 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 384,0 756 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 392,0 757 0 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 GRAPHIC 400,0 758 0 1578 DESIGN @f@a@d_main 1579 VIEW struct.bd 1580 GRAPHIC 408,0 759 0 1581 DESIGN @f@a@d_main 1582 VIEW struct.bd 1583 GRAPHIC 5222,0 760 0 1584 DESIGN @f@a@d_main 1585 VIEW struct.bd 1586 GRAPHIC 424,0 761 0 1587 DESIGN @f@a@d_main 1588 VIEW struct.bd 1589 GRAPHIC 432,0 762 0 1590 DESIGN @f@a@d_main 1591 VIEW struct.bd 1592 GRAPHIC 2482,0 763 0 1593 DESIGN @f@a@d_main 1594 VIEW struct.bd 1595 GRAPHIC 2488,0 764 0 1596 DESIGN @f@a@d_main 1597 VIEW struct.bd 1598 GRAPHIC 370,0 765 0 1599 DESIGN @f@a@d_main 1600 VIEW struct.bd 1601 GRAPHIC 364,0 766 0 1602 DESIGN @f@a@d_main 1603 VIEW struct.bd 1604 GRAPHIC 2476,0 767 0 1605 DESIGN @f@a@d_main 1606 VIEW struct.bd 1607 GRAPHIC 8416,0 768 0 1608 DESIGN @f@a@d_main 1609 VIEW struct.bd 1610 GRAPHIC 2470,0 769 0 1611 DESIGN @f@a@d_main 1612 VIEW struct.bd 1613 GRAPHIC 2506,0 770 0 1614 DESIGN @f@a@d_main 1615 VIEW struct.bd 1616 GRAPHIC 2500,0 771 0 1617 DESIGN @f@a@d_main 1618 VIEW struct.bd 1619 GRAPHIC 2494,0 772 0 1620 DESIGN @f@a@d_main 1621 VIEW struct.bd 1622 GRAPHIC 10266,0 773 0 1623 DESIGN @f@a@d_main 1624 VIEW struct.bd 1625 GRAPHIC 13159,0 774 0 1626 DESIGN @f@a@d_main 1627 VIEW struct.bd 1628 GRAPHIC 13165,0 775 0 1629 DESIGN @f@a@d_main 1630 VIEW struct.bd 1631 GRAPHIC 5950,0 776 0 1632 DESIGN @f@a@d_main 1633 VIEW struct.bd 1634 GRAPHIC 5962,0 777 0 1635 DESIGN @f@a@d_main 1636 VIEW struct.bd 1637 GRAPHIC 5090,0 778 0 1638 DESIGN @f@a@d_main 1639 VIEW struct.bd 1640 GRAPHIC 5114,0 779 0 1641 DESIGN @f@a@d_main 1642 VIEW struct.bd 1643 GRAPHIC 5122,0 780 0 1644 DESIGN @f@a@d_main 1645 VIEW struct.bd 1646 GRAPHIC 5130,0 781 0 1647 DESIGN @f@a@d_main 1648 VIEW struct.bd 1649 GRAPHIC 10194,0 782 0 1650 DESIGN @f@a@d_main 1651 VIEW struct.bd 1652 GRAPHIC 10202,0 783 0 1653 DESIGN @f@a@d_main 1654 VIEW struct.bd 1655 GRAPHIC 5106,0 784 0 1656 DESIGN @f@a@d_main 1657 VIEW struct.bd 1658 GRAPHIC 6362,0 785 0 1659 DESIGN @f@a@d_main 1660 VIEW struct.bd 1661 GRAPHIC 6452,0 786 0 1662 DESIGN @f@a@d_main 1663 VIEW struct.bd 1664 GRAPHIC 8752,0 787 0 1665 DESIGN @f@a@d_main 1666 VIEW struct.bd 1667 GRAPHIC 9233,0 788 0 1668 DESIGN @f@a@d_main 1669 VIEW struct.bd 1670 GRAPHIC 9241,0 789 0 1671 DESIGN @f@a@d_main 1672 VIEW struct.bd 1673 GRAPHIC 9943,0 790 0 1674 DESIGN @f@a@d_main 1675 VIEW struct.bd 1676 GRAPHIC 9951,0 791 0 1677 DESIGN @f@a@d_main 1678 VIEW struct.bd 1679 GRAPHIC 11858,0 792 0 1680 DESIGN @f@a@d_main 1681 VIEW struct.bd 1682 GRAPHIC 10637,0 793 0 1683 DESIGN @f@a@d_main 1684 VIEW struct.bd 1685 GRAPHIC 10629,0 794 0 1686 DESIGN @f@a@d_main 1687 VIEW struct.bd 1688 GRAPHIC 6276,0 798 0 1689 DESIGN @f@a@d_main 1690 VIEW struct.bd 1691 GRAPHIC 3888,0 799 0 1692 DESIGN @f@a@d_main 1693 VIEW struct.bd 1694 NO_GRAPHIC 801 980 NO_GRAPHIC 485 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 5678,0 488 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 9175,0 489 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 13117,0 490 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 5072,0 491 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 8277,0 492 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 1399,0 493 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 4903,0 494 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 11209,0 495 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 2311,0 496 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 5793,0 497 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 1768,0 498 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 12625,0 499 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 1606,0 500 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 NO_GRAPHIC 503 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 6529,0 505 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 9957,0 508 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 8721,0 511 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 12295,0 514 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 9472,0 517 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 9662,0 520 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 9679,0 523 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 9710,0 526 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 8562,0 529 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 10380,0 540 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 13266,0 543 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 NO_GRAPHIC 546 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5678,0 548 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 5646,0 550 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 4272,0 551 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 2786,0 552 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 5626,0 553 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 5634,0 554 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 9175,0 556 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 4042,0 558 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 10036,0 559 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 9253,0 560 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 9261,0 561 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 6072,0 562 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 3984,0 563 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 3888,0 564 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 9353,0 565 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 9269,0 566 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 9325,0 567 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 9283,0 568 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 9297,0 569 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 9367,0 570 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 9397,0 571 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 9382,0 572 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 13117,0 574 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 13124,0 575 1 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 13143,0 579 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 13159,0 580 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 13165,0 581 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 13210,0 582 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 5072,0 584 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 5582,0 586 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 5090,0 587 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5130,0 588 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 5184,0 589 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 5122,0 590 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 5106,0 591 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 5098,0 592 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 5190,0 593 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 10194,0 594 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 10202,0 595 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 6002,0 596 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5146,0 597 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 5138,0 598 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 5114,0 599 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 8277,0 601 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 5602,0 603 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 334,0 604 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 328,0 605 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 322,0 606 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 4240,0 607 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 364,0 608 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 370,0 609 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 1399,0 611 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 1406,0 612 1 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 5602,0 616 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 334,0 617 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 328,0 618 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 322,0 619 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 2299,0 620 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 2576,0 621 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 2582,0 622 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 10467,0 623 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 2588,0 624 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 5184,0 625 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 5745,0 626 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 2594,0 627 0 1254 DESIGN @f@a@d_main 1255 VIEW struct.bd 1256 GRAPHIC 5190,0 628 0 1257 DESIGN @f@a@d_main 1258 VIEW struct.bd 1259 GRAPHIC 5404,0 629 0 1260 DESIGN @f@a@d_main 1261 VIEW struct.bd 1262 GRAPHIC 6018,0 630 0 1263 DESIGN @f@a@d_main 1264 VIEW struct.bd 1265 GRAPHIC 6002,0 631 0 1266 DESIGN @f@a@d_main 1267 VIEW struct.bd 1268 GRAPHIC 6008,0 632 0 1269 DESIGN @f@a@d_main 1270 VIEW struct.bd 1271 GRAPHIC 5138,0 633 0 1272 DESIGN @f@a@d_main 1273 VIEW struct.bd 1274 GRAPHIC 2600,0 634 0 1275 DESIGN @f@a@d_main 1276 VIEW struct.bd 1277 GRAPHIC 5480,0 635 0 1278 DESIGN @f@a@d_main 1279 VIEW struct.bd 1280 GRAPHIC 5474,0 636 0 1281 DESIGN @f@a@d_main 1282 VIEW struct.bd 1283 GRAPHIC 6064,0 637 0 1284 DESIGN @f@a@d_main 1285 VIEW struct.bd 1286 GRAPHIC 2642,0 638 0 1287 DESIGN @f@a@d_main 1288 VIEW struct.bd 1289 GRAPHIC 1411,0 639 0 1290 DESIGN @f@a@d_main 1291 VIEW struct.bd 1292 GRAPHIC 1682,0 640 0 1293 DESIGN @f@a@d_main 1294 VIEW struct.bd 1295 GRAPHIC 1983,0 641 0 1296 DESIGN @f@a@d_main 1297 VIEW struct.bd 1298 GRAPHIC 10439,0 642 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 5950,0 643 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 5962,0 644 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 5626,0 645 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 2778,0 646 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 9006,0 647 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 5634,0 648 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 8577,0 649 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 12649,0 650 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 12655,0 651 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 4401,0 652 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 4419,0 653 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 10298,0 654 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 10304,0 655 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 10316,0 656 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 10310,0 657 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 4743,0 658 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 4407,0 659 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 11405,0 660 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 4903,0 662 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 4757,0 664 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 4401,0 665 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 4419,0 666 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 4671,0 667 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 4679,0 668 0 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 4687,0 669 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 4695,0 670 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 4407,0 671 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 4743,0 672 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 10298,0 673 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 10310,0 674 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 10304,0 675 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 10316,0 676 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 10322,0 677 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 4948,0 678 0 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 10010,0 679 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 11209,0 681 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 11216,0 682 1 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 10699,0 688 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 10723,0 689 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 10737,0 690 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 10751,0 691 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 12707,0 692 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 10707,0 693 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 10685,0 694 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 10691,0 695 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2311,0 697 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 2318,0 698 1 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 6082,0 703 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2588,0 704 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2582,0 705 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 10467,0 706 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 5168,0 707 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 2576,0 708 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 2594,0 709 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 6018,0 710 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 2600,0 711 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 2642,0 712 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 2488,0 713 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 2482,0 714 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 2494,0 715 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 2476,0 716 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 2506,0 717 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 2500,0 718 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 2470,0 719 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 8416,0 720 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 2299,0 721 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 5793,0 723 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 5805,0 725 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 5745,0 726 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 5146,0 727 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 5404,0 728 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 6008,0 729 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 5829,0 730 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 6160,0 731 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 8732,0 732 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 5480,0 733 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 5837,0 734 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 5474,0 735 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 5821,0 736 0 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 1768,0 738 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 1983,0 740 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 10439,0 741 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 6276,0 742 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 12625,0 744 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 12687,0 746 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 12643,0 747 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 12635,0 748 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 12667,0 749 0 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 12649,0 750 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 12655,0 751 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 1606,0 753 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 1613,0 754 1 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 GRAPHIC 3888,0 758 0 1578 DESIGN @f@a@d_main 1579 VIEW struct.bd 1580 GRAPHIC 376,0 759 0 1581 DESIGN @f@a@d_main 1582 VIEW struct.bd 1583 GRAPHIC 384,0 760 0 1584 DESIGN @f@a@d_main 1585 VIEW struct.bd 1586 GRAPHIC 392,0 761 0 1587 DESIGN @f@a@d_main 1588 VIEW struct.bd 1589 GRAPHIC 400,0 762 0 1590 DESIGN @f@a@d_main 1591 VIEW struct.bd 1592 GRAPHIC 408,0 763 0 1593 DESIGN @f@a@d_main 1594 VIEW struct.bd 1595 GRAPHIC 5222,0 764 0 1596 DESIGN @f@a@d_main 1597 VIEW struct.bd 1598 GRAPHIC 424,0 765 0 1599 DESIGN @f@a@d_main 1600 VIEW struct.bd 1601 GRAPHIC 432,0 766 0 1602 DESIGN @f@a@d_main 1603 VIEW struct.bd 1604 GRAPHIC 2482,0 767 0 1605 DESIGN @f@a@d_main 1606 VIEW struct.bd 1607 GRAPHIC 2488,0 768 0 1608 DESIGN @f@a@d_main 1609 VIEW struct.bd 1610 GRAPHIC 370,0 769 0 1611 DESIGN @f@a@d_main 1612 VIEW struct.bd 1613 GRAPHIC 364,0 770 0 1614 DESIGN @f@a@d_main 1615 VIEW struct.bd 1616 GRAPHIC 2476,0 771 0 1617 DESIGN @f@a@d_main 1618 VIEW struct.bd 1619 GRAPHIC 8416,0 772 0 1620 DESIGN @f@a@d_main 1621 VIEW struct.bd 1622 GRAPHIC 2470,0 773 0 1623 DESIGN @f@a@d_main 1624 VIEW struct.bd 1625 GRAPHIC 2506,0 774 0 1626 DESIGN @f@a@d_main 1627 VIEW struct.bd 1628 GRAPHIC 2500,0 775 0 1629 DESIGN @f@a@d_main 1630 VIEW struct.bd 1631 GRAPHIC 2494,0 776 0 1632 DESIGN @f@a@d_main 1633 VIEW struct.bd 1634 GRAPHIC 10266,0 777 0 1635 DESIGN @f@a@d_main 1636 VIEW struct.bd 1637 GRAPHIC 13159,0 778 0 1638 DESIGN @f@a@d_main 1639 VIEW struct.bd 1640 GRAPHIC 13165,0 779 0 1641 DESIGN @f@a@d_main 1642 VIEW struct.bd 1643 GRAPHIC 5950,0 780 0 1644 DESIGN @f@a@d_main 1645 VIEW struct.bd 1646 GRAPHIC 5962,0 781 0 1647 DESIGN @f@a@d_main 1648 VIEW struct.bd 1649 GRAPHIC 5090,0 782 0 1650 DESIGN @f@a@d_main 1651 VIEW struct.bd 1652 GRAPHIC 5114,0 783 0 1653 DESIGN @f@a@d_main 1654 VIEW struct.bd 1655 GRAPHIC 5122,0 784 0 1656 DESIGN @f@a@d_main 1657 VIEW struct.bd 1658 GRAPHIC 5130,0 785 0 1659 DESIGN @f@a@d_main 1660 VIEW struct.bd 1661 GRAPHIC 10194,0 786 0 1662 DESIGN @f@a@d_main 1663 VIEW struct.bd 1664 GRAPHIC 10202,0 787 0 1665 DESIGN @f@a@d_main 1666 VIEW struct.bd 1667 GRAPHIC 5106,0 788 0 1668 DESIGN @f@a@d_main 1669 VIEW struct.bd 1670 GRAPHIC 13695,0 789 0 1671 DESIGN @f@a@d_main 1672 VIEW struct.bd 1673 GRAPHIC 13921,0 790 0 1674 DESIGN @f@a@d_main 1675 VIEW struct.bd 1676 GRAPHIC 13929,0 791 0 1677 DESIGN @f@a@d_main 1678 VIEW struct.bd 1679 GRAPHIC 6362,0 792 0 1680 DESIGN @f@a@d_main 1681 VIEW struct.bd 1682 GRAPHIC 6452,0 793 0 1683 DESIGN @f@a@d_main 1684 VIEW struct.bd 1685 GRAPHIC 8752,0 794 0 1686 DESIGN @f@a@d_main 1687 VIEW struct.bd 1688 GRAPHIC 9233,0 795 0 1689 DESIGN @f@a@d_main 1690 VIEW struct.bd 1691 GRAPHIC 9241,0 796 0 1692 DESIGN @f@a@d_main 1693 VIEW struct.bd 1694 GRAPHIC 9943,0 797 0 1695 DESIGN @f@a@d_main 1696 VIEW struct.bd 1697 GRAPHIC 9951,0 798 0 1698 DESIGN @f@a@d_main 1699 VIEW struct.bd 1700 GRAPHIC 11858,0 799 0 1701 DESIGN @f@a@d_main 1702 VIEW struct.bd 1703 GRAPHIC 10637,0 800 0 1704 DESIGN @f@a@d_main 1705 VIEW struct.bd 1706 GRAPHIC 10629,0 801 0 1707 DESIGN @f@a@d_main 1708 VIEW struct.bd 1709 GRAPHIC 6276,0 805 0 1710 DESIGN @f@a@d_main 1711 VIEW struct.bd 1712 GRAPHIC 3888,0 806 0 1713 DESIGN @f@a@d_main 1714 VIEW struct.bd 1715 NO_GRAPHIC 808 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd
r10121 r10123 91 91 number "9" 92 92 ) 93 (EmbeddedInstance 94 name "eb1" 95 number "7" 96 ) 93 97 ] 94 98 libraryRefs [ … … 105 109 (vvPair 106 110 variable "HDLDir" 107 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"111 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 108 112 ) 109 113 (vvPair 110 114 variable "HDSDir" 111 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"115 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 112 116 ) 113 117 (vvPair 114 118 variable "SideDataDesignDir" 115 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"119 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 116 120 ) 117 121 (vvPair 118 122 variable "SideDataUserDir" 119 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"123 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 120 124 ) 121 125 (vvPair 122 126 variable "SourceDir" 123 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"127 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 124 128 ) 125 129 (vvPair … … 137 141 (vvPair 138 142 variable "d" 139 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"143 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board" 140 144 ) 141 145 (vvPair 142 146 variable "d_logical" 143 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"147 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board" 144 148 ) 145 149 (vvPair 146 150 variable "date" 147 value "2 6.01.2011"151 value "27.01.2011" 148 152 ) 149 153 (vvPair 150 154 variable "day" 151 value " Mi"155 value "Do" 152 156 ) 153 157 (vvPair 154 158 variable "day_long" 155 value " Mittwoch"159 value "Donnerstag" 156 160 ) 157 161 (vvPair 158 162 variable "dd" 159 value "2 6"163 value "27" 160 164 ) 161 165 (vvPair … … 233 237 (vvPair 234 238 variable "p" 235 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"239 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 236 240 ) 237 241 (vvPair 238 242 variable "p_logical" 239 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"243 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 240 244 ) 241 245 (vvPair … … 293 297 (vvPair 294 298 variable "time" 295 value "1 1:50:58"299 value "17:58:52" 296 300 ) 297 301 (vvPair … … 684 688 n "wiz_reset" 685 689 t "std_logic" 686 o 4 6690 o 47 687 691 suid 2,0 688 692 i "'1'" … … 723 727 b "(7 DOWNTO 0)" 724 728 posAdd 0 725 o 3 5729 o 36 726 730 suid 7,0 727 731 i "(OTHERS => '0')" … … 760 764 preAdd 0 761 765 posAdd 0 762 o 1 0766 o 11 763 767 suid 18,0 764 768 ) … … 795 799 n "adc_oeb" 796 800 t "std_logic" 797 o 2 7801 o 28 798 802 suid 21,0 799 803 i "'1'" … … 833 837 preAdd 0 834 838 posAdd 0 835 o 8839 o 9 836 840 suid 24,0 837 841 ) … … 868 872 t "std_logic_vector" 869 873 b "(1 downto 0)" 870 o 9874 o 10 871 875 suid 25,0 872 876 ) … … 905 909 t "std_logic_vector" 906 910 b "(9 DOWNTO 0)" 907 o 4 3911 o 44 908 912 suid 26,0 909 913 ) … … 941 945 n "wiz_cs" 942 946 t "std_logic" 943 o 4 4947 o 45 944 948 suid 28,0 945 949 i "'1'" … … 979 983 t "std_logic_vector" 980 984 b "(15 DOWNTO 0)" 981 o 49985 o 50 982 986 suid 27,0 983 987 ) … … 1014 1018 n "wiz_int" 1015 1019 t "std_logic" 1016 o 1 11020 o 12 1017 1021 suid 31,0 1018 1022 ) … … 1050 1054 n "wiz_rd" 1051 1055 t "std_logic" 1052 o 4 51056 o 46 1053 1057 suid 30,0 1054 1058 i "'1'" … … 1087 1091 n "wiz_wr" 1088 1092 t "std_logic" 1089 o 4 71093 o 48 1090 1094 suid 29,0 1091 1095 i "'1'" … … 1123 1127 n "CLK_25_PS" 1124 1128 t "std_logic" 1125 o 1 51129 o 16 1126 1130 suid 35,0 1127 1131 ) … … 1158 1162 n "CLK_50" 1159 1163 t "std_logic" 1160 o 1 61164 o 17 1161 1165 suid 37,0 1162 1166 ) … … 1226 1230 n "adc_data_array" 1227 1231 t "adc_data_array_type" 1228 o 61232 o 7 1229 1233 suid 39,0 1230 1234 ) … … 1261 1265 t "std_logic_vector" 1262 1266 b "(3 DOWNTO 0)" 1263 o 71267 o 8 1264 1268 suid 40,0 1265 1269 ) … … 1297 1301 t "std_logic_vector" 1298 1302 b "(3 downto 0)" 1299 o 3 21303 o 33 1300 1304 suid 48,0 1301 1305 i "(others => '0')" … … 1333 1337 n "drs_dwrite" 1334 1338 t "std_logic" 1335 o 3 31339 o 34 1336 1340 suid 49,0 1337 1341 i "'1'" … … 1368 1372 n "SROUT_in_0" 1369 1373 t "std_logic" 1370 o 21374 o 3 1371 1375 suid 42,0 1372 1376 ) … … 1402 1406 n "SROUT_in_1" 1403 1407 t "std_logic" 1404 o 31408 o 4 1405 1409 suid 43,0 1406 1410 ) … … 1436 1440 n "SROUT_in_2" 1437 1441 t "std_logic" 1438 o 41442 o 5 1439 1443 suid 44,0 1440 1444 ) … … 1470 1474 n "SROUT_in_3" 1471 1475 t "std_logic" 1472 o 51476 o 6 1473 1477 suid 45,0 1474 1478 ) … … 1505 1509 n "RSRLOAD" 1506 1510 t "std_logic" 1507 o 2 31511 o 24 1508 1512 suid 56,0 1509 1513 i "'0'" … … 1541 1545 n "SRCLK" 1542 1546 t "std_logic" 1543 o 2 41547 o 25 1544 1548 suid 57,0 1545 1549 i "'0'" … … 1578 1582 n "dac_cs" 1579 1583 t "std_logic" 1580 o 3 01584 o 31 1581 1585 suid 64,0 1582 1586 ) … … 1614 1618 n "sclk" 1615 1619 t "std_logic" 1616 o 4 01620 o 41 1617 1621 suid 62,0 1618 1622 ) … … 1651 1655 t "std_logic_vector" 1652 1656 b "(3 DOWNTO 0)" 1653 o 4 11657 o 42 1654 1658 suid 65,0 1655 1659 ) … … 1689 1693 preAdd 0 1690 1694 posAdd 0 1691 o 4 81695 o 49 1692 1696 suid 63,0 1693 1697 ) … … 1725 1729 n "mosi" 1726 1730 t "std_logic" 1727 o 3 61731 o 37 1728 1732 suid 66,0 1729 1733 i "'0'" … … 1764 1768 eolc "-- default domino wave off" 1765 1769 posAdd 0 1766 o 3 11770 o 32 1767 1771 suid 67,0 1768 1772 i "'0'" … … 1800 1804 n "adc_clk_en" 1801 1805 t "std_logic" 1802 o 2 61806 o 27 1803 1807 suid 69,0 1804 1808 i "'0'" … … 1839 1843 preAdd 0 1840 1844 posAdd 0 1841 o 1 71845 o 18 1842 1846 suid 76,0 1843 1847 ) … … 1875 1879 n "LOCKED_extraOUT" 1876 1880 t "std_logic" 1877 o 1 81881 o 19 1878 1882 suid 70,0 1879 1883 ) … … 1914 1918 preAdd 0 1915 1919 posAdd 0 1916 o 3 71920 o 38 1917 1921 suid 77,0 1918 1922 i "(OTHERS => '0')" … … 1951 1955 n "PS_DIR_IN" 1952 1956 t "std_logic" 1953 o 2 21957 o 23 1954 1958 suid 80,0 1955 1959 ) … … 1987 1991 n "PSCLK_OUT" 1988 1992 t "std_logic" 1989 o 191993 o 20 1990 1994 suid 74,0 1991 1995 ) … … 2023 2027 n "PSDONE_extraOUT" 2024 2028 t "std_logic" 2025 o 2 02029 o 21 2026 2030 suid 71,0 2027 2031 ) … … 2059 2063 n "PSINCDEC_OUT" 2060 2064 t "std_logic" 2061 o 2 12065 o 22 2062 2066 suid 72,0 2063 2067 ) … … 2097 2101 preAdd 0 2098 2102 posAdd 0 2099 o 3 82103 o 39 2100 2104 suid 79,0 2101 2105 i "'0'" … … 2137 2141 preAdd 0 2138 2142 posAdd 0 2139 o 4 22143 o 43 2140 2144 suid 78,0 2141 2145 i "'0'" … … 2174 2178 n "CLK25_OUT" 2175 2179 t "std_logic" 2176 o 1 22180 o 13 2177 2181 suid 83,0 2178 2182 ) … … 2210 2214 n "CLK25_PSOUT" 2211 2215 t "std_logic" 2212 o 1 32216 o 14 2213 2217 suid 84,0 2214 2218 ) … … 2246 2250 n "CLK50_OUT" 2247 2251 t "std_logic" 2248 o 1 42252 o 15 2249 2253 suid 82,0 2250 2254 ) … … 2282 2286 n "SRIN_out" 2283 2287 t "std_logic" 2284 o 2 52288 o 26 2285 2289 suid 85,0 2286 2290 i "'0'" … … 2319 2323 n "amber" 2320 2324 t "std_logic" 2321 o 292325 o 30 2322 2326 suid 87,0 2323 2327 ) … … 2355 2359 n "green" 2356 2360 t "std_logic" 2357 o 3 42361 o 35 2358 2362 suid 86,0 2359 2363 ) … … 2391 2395 n "red" 2392 2396 t "std_logic" 2393 o 392397 o 40 2394 2398 suid 88,0 2395 2399 ) … … 2427 2431 n "additional_flasher_out" 2428 2432 t "std_logic" 2429 o 2 82433 o 29 2430 2434 suid 90,0 2435 ) 2436 ) 2437 ) 2438 *62 (CptPort 2439 uid 14682,0 2440 ps "OnEdgeStrategy" 2441 shape (Triangle 2442 uid 14683,0 2443 ro 90 2444 va (VaSet 2445 vasetType 1 2446 fg "0,65535,0" 2447 ) 2448 xt "51250,138625,52000,139375" 2449 ) 2450 tg (CPTG 2451 uid 14684,0 2452 ps "CptPortTextPlaceStrategy" 2453 stg "VerticalLayoutStrategy" 2454 f (Text 2455 uid 14685,0 2456 va (VaSet 2457 ) 2458 xt "53000,138500,58500,139500" 2459 st "D_T_in : (1:0)" 2460 blo "53000,139300" 2461 ) 2462 ) 2463 thePort (LogicalPort 2464 decl (Decl 2465 n "D_T_in" 2466 t "std_logic_vector" 2467 b "(1 DOWNTO 0)" 2468 o 2 2469 suid 91,0 2431 2470 ) 2432 2471 ) … … 2449 2488 stg "VerticalLayoutStrategy" 2450 2489 textVec [ 2451 *6 2(Text2490 *63 (Text 2452 2491 uid 172,0 2453 2492 va (VaSet … … 2459 2498 tm "BdLibraryNameMgr" 2460 2499 ) 2461 *6 3(Text2500 *64 (Text 2462 2501 uid 173,0 2463 2502 va (VaSet … … 2469 2508 tm "CptNameMgr" 2470 2509 ) 2471 *6 4(Text2510 *65 (Text 2472 2511 uid 174,0 2473 2512 va (VaSet … … 2521 2560 archFileType "UNKNOWN" 2522 2561 ) 2523 *6 5(PortIoIn2562 *66 (PortIoIn 2524 2563 uid 231,0 2525 2564 shape (CompositeShape … … 2566 2605 ) 2567 2606 ) 2568 *6 6(PortIoIn2607 *67 (PortIoIn 2569 2608 uid 251,0 2570 2609 shape (CompositeShape … … 2611 2650 ) 2612 2651 ) 2613 *6 7(HdlText2652 *68 (HdlText 2614 2653 uid 265,0 2615 2654 optionalChildren [ 2616 *6 8(EmbeddedText2655 *69 (EmbeddedText 2617 2656 uid 271,0 2618 2657 commentText (CommentText … … 2634 2673 va (VaSet 2635 2674 ) 2636 xt "32200,83200, 39700,86200"2675 xt "32200,83200,43700,86200" 2637 2676 st " 2638 2677 -- hard-wired IDs 2639 board_id <= \"0101\";2640 crate_id <= \"01\";2678 board_id <= LINE(5 downto 2); 2679 crate_id <= LINE(1 downto 0); 2641 2680 " 2642 2681 tm "HdlTextMgr" … … 2664 2703 stg "VerticalLayoutStrategy" 2665 2704 textVec [ 2666 * 69(Text2705 *70 (Text 2667 2706 uid 268,0 2668 2707 va (VaSet … … 2674 2713 tm "HdlTextNameMgr" 2675 2714 ) 2676 *7 0(Text2715 *71 (Text 2677 2716 uid 269,0 2678 2717 va (VaSet … … 2700 2739 viewiconposition 0 2701 2740 ) 2702 *7 1(Net2741 *72 (Net 2703 2742 uid 275,0 2704 2743 decl (Decl … … 2716 2755 font "Courier New,8,0" 2717 2756 ) 2718 xt "39000,62400,67500,63200" 2719 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2720 " 2721 ) 2722 ) 2723 *72 (Net 2757 xt "39000,63200,67500,64000" 2758 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2759 ) 2760 ) 2761 *73 (Net 2724 2762 uid 283,0 2725 2763 decl (Decl … … 2735 2773 font "Courier New,8,0" 2736 2774 ) 2737 xt "39000,63200,67500,64000" 2738 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2739 " 2740 ) 2741 ) 2742 *73 (PortIoOut 2775 xt "39000,64000,67500,64800" 2776 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2777 ) 2778 ) 2779 *74 (PortIoOut 2743 2780 uid 472,0 2744 2781 shape (CompositeShape … … 2784 2821 ) 2785 2822 ) 2786 *7 4(PortIoOut2823 *75 (PortIoOut 2787 2824 uid 478,0 2788 2825 shape (CompositeShape … … 2828 2865 ) 2829 2866 ) 2830 *7 5(PortIoOut2867 *76 (PortIoOut 2831 2868 uid 484,0 2832 2869 shape (CompositeShape … … 2872 2909 ) 2873 2910 ) 2874 *7 6(PortIoInOut2911 *77 (PortIoInOut 2875 2912 uid 490,0 2876 2913 shape (CompositeShape … … 2914 2951 ) 2915 2952 ) 2916 *7 7(PortIoIn2953 *78 (PortIoIn 2917 2954 uid 496,0 2918 2955 shape (CompositeShape … … 2958 2995 ) 2959 2996 ) 2960 *7 8(PortIoOut2997 *79 (PortIoOut 2961 2998 uid 502,0 2962 2999 shape (CompositeShape … … 3002 3039 ) 3003 3040 ) 3004 * 79(PortIoOut3041 *80 (PortIoOut 3005 3042 uid 508,0 3006 3043 shape (CompositeShape … … 3046 3083 ) 3047 3084 ) 3048 *8 0(Net3085 *81 (Net 3049 3086 uid 1465,0 3050 3087 decl (Decl … … 3059 3096 font "Courier New,8,0" 3060 3097 ) 3061 xt "39000,61600,63000,62400" 3062 st "SIGNAL adc_data_array : adc_data_array_type 3063 " 3064 ) 3065 ) 3066 *81 (Net 3098 xt "39000,62400,63000,63200" 3099 st "SIGNAL adc_data_array : adc_data_array_type" 3100 ) 3101 ) 3102 *82 (Net 3067 3103 uid 2407,0 3068 3104 decl (Decl … … 3078 3114 font "Courier New,8,0" 3079 3115 ) 3080 xt "39000,37400,67500,38200" 3081 st "RSRLOAD : std_logic := '0' 3082 " 3083 ) 3084 ) 3085 *82 (PortIoOut 3116 xt "39000,38200,67500,39000" 3117 st "RSRLOAD : std_logic := '0'" 3118 ) 3119 ) 3120 *83 (PortIoOut 3086 3121 uid 2415,0 3087 3122 shape (CompositeShape … … 3128 3163 ) 3129 3164 ) 3130 *8 3(Net3165 *84 (Net 3131 3166 uid 2421,0 3132 3167 decl (Decl … … 3142 3177 font "Courier New,8,0" 3143 3178 ) 3144 xt "39000,60000,71000,60800" 3145 st "SIGNAL SRCLK : std_logic := '0' 3146 " 3147 ) 3148 ) 3149 *84 (Net 3179 xt "39000,60800,71000,61600" 3180 st "SIGNAL SRCLK : std_logic := '0'" 3181 ) 3182 ) 3183 *85 (Net 3150 3184 uid 3019,0 3151 3185 decl (Decl … … 3161 3195 font "Courier New,8,0" 3162 3196 ) 3163 xt "39000,66400,67500,67200" 3164 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3165 " 3166 ) 3167 ) 3168 *85 (Net 3197 xt "39000,68000,67500,68800" 3198 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 3199 ) 3200 ) 3201 *86 (Net 3169 3202 uid 3025,0 3170 3203 decl (Decl … … 3179 3212 font "Courier New,8,0" 3180 3213 ) 3181 xt "39000,24600,54000,25400" 3182 st "DAC_CS : std_logic 3183 " 3184 ) 3185 ) 3186 *86 (PortIoOut 3214 xt "39000,25400,54000,26200" 3215 st "DAC_CS : std_logic" 3216 ) 3217 ) 3218 *87 (PortIoOut 3187 3219 uid 3153,0 3188 3220 shape (CompositeShape … … 3229 3261 ) 3230 3262 ) 3231 *8 7(Net3263 *88 (Net 3232 3264 uid 3216,0 3233 3265 decl (Decl … … 3244 3276 font "Courier New,8,0" 3245 3277 ) 3246 xt "39000,17400,54000,18200" 3247 st "X_50M : STD_LOGIC 3248 " 3249 ) 3250 ) 3251 *88 (Net 3278 xt "39000,18200,54000,19000" 3279 st "X_50M : STD_LOGIC" 3280 ) 3281 ) 3282 *89 (Net 3252 3283 uid 3226,0 3253 3284 decl (Decl … … 3262 3293 font "Courier New,8,0" 3263 3294 ) 3264 xt "39000,15800,54000,16600" 3265 st "TRG : STD_LOGIC 3266 " 3267 ) 3268 ) 3269 *89 (HdlText 3295 xt "39000,16600,54000,17400" 3296 st "TRG : STD_LOGIC" 3297 ) 3298 ) 3299 *90 (HdlText 3270 3300 uid 3248,0 3271 3301 optionalChildren [ 3272 *9 0(EmbeddedText3302 *91 (EmbeddedText 3273 3303 uid 3254,0 3274 3304 commentText (CommentText … … 3322 3352 stg "VerticalLayoutStrategy" 3323 3353 textVec [ 3324 *9 1(Text3354 *92 (Text 3325 3355 uid 3251,0 3326 3356 va (VaSet … … 3332 3362 tm "HdlTextNameMgr" 3333 3363 ) 3334 *9 2(Text3364 *93 (Text 3335 3365 uid 3252,0 3336 3366 va (VaSet … … 3358 3388 viewiconposition 0 3359 3389 ) 3360 *9 3(Net3390 *94 (Net 3361 3391 uid 3266,0 3362 3392 decl (Decl … … 3372 3402 font "Courier New,8,0" 3373 3403 ) 3374 xt "39000,20600,64000,21400" 3375 st "A_CLK : std_logic_vector(3 downto 0) 3376 " 3377 ) 3378 ) 3379 *94 (Net 3404 xt "39000,21400,64000,22200" 3405 st "A_CLK : std_logic_vector(3 downto 0)" 3406 ) 3407 ) 3408 *95 (Net 3380 3409 uid 3268,0 3381 3410 decl (Decl … … 3390 3419 font "Courier New,8,0" 3391 3420 ) 3392 xt "39000,52800,57500,53600" 3393 st "SIGNAL CLK_25_PS : std_logic 3394 " 3395 ) 3396 ) 3397 *95 (PortIoOut 3421 xt "39000,53600,57500,54400" 3422 st "SIGNAL CLK_25_PS : std_logic" 3423 ) 3424 ) 3425 *96 (PortIoOut 3398 3426 uid 3284,0 3399 3427 shape (CompositeShape … … 3440 3468 ) 3441 3469 ) 3442 *9 6(Net3470 *97 (Net 3443 3471 uid 3290,0 3444 3472 decl (Decl … … 3455 3483 font "Courier New,8,0" 3456 3484 ) 3457 xt "39000,31800,54000,32600" 3458 st "OE_ADC : STD_LOGIC 3459 " 3460 ) 3461 ) 3462 *97 (PortIoIn 3485 xt "39000,32600,54000,33400" 3486 st "OE_ADC : STD_LOGIC" 3487 ) 3488 ) 3489 *98 (PortIoIn 3463 3490 uid 3292,0 3464 3491 shape (CompositeShape … … 3505 3532 ) 3506 3533 ) 3507 *9 8(Net3534 *99 (Net 3508 3535 uid 3298,0 3509 3536 decl (Decl … … 3520 3547 ) 3521 3548 xt "39000,7000,64000,7800" 3522 st "A_OTR : std_logic_vector(3 DOWNTO 0) 3523 " 3524 ) 3525 ) 3526 *99 (HdlText 3549 st "A_OTR : std_logic_vector(3 DOWNTO 0)" 3550 ) 3551 ) 3552 *100 (HdlText 3527 3553 uid 3300,0 3528 3554 optionalChildren [ 3529 *10 0(EmbeddedText3555 *101 (EmbeddedText 3530 3556 uid 3306,0 3531 3557 commentText (CommentText … … 3579 3605 stg "VerticalLayoutStrategy" 3580 3606 textVec [ 3581 *10 1(Text3607 *102 (Text 3582 3608 uid 3303,0 3583 3609 va (VaSet … … 3589 3615 tm "HdlTextNameMgr" 3590 3616 ) 3591 *10 2(Text3617 *103 (Text 3592 3618 uid 3304,0 3593 3619 va (VaSet … … 3615 3641 viewiconposition 0 3616 3642 ) 3617 *10 3(PortIoIn3643 *104 (PortIoIn 3618 3644 uid 3310,0 3619 3645 shape (CompositeShape … … 3660 3686 ) 3661 3687 ) 3662 *10 4(PortIoIn3688 *105 (PortIoIn 3663 3689 uid 3332,0 3664 3690 shape (CompositeShape … … 3705 3731 ) 3706 3732 ) 3707 *10 5(PortIoIn3733 *106 (PortIoIn 3708 3734 uid 3338,0 3709 3735 shape (CompositeShape … … 3750 3776 ) 3751 3777 ) 3752 *10 6(PortIoIn3778 *107 (PortIoIn 3753 3779 uid 3344,0 3754 3780 shape (CompositeShape … … 3795 3821 ) 3796 3822 ) 3797 *10 7(Net3823 *108 (Net 3798 3824 uid 3374,0 3799 3825 decl (Decl … … 3810 3836 ) 3811 3837 xt "39000,3800,64500,4600" 3812 st "A0_D : std_logic_vector(11 DOWNTO 0) 3813 " 3814 ) 3815 ) 3816 *108 (Net 3838 st "A0_D : std_logic_vector(11 DOWNTO 0)" 3839 ) 3840 ) 3841 *109 (Net 3817 3842 uid 3376,0 3818 3843 decl (Decl … … 3829 3854 ) 3830 3855 xt "39000,4600,64500,5400" 3831 st "A1_D : std_logic_vector(11 DOWNTO 0) 3832 " 3833 ) 3834 ) 3835 *109 (Net 3856 st "A1_D : std_logic_vector(11 DOWNTO 0)" 3857 ) 3858 ) 3859 *110 (Net 3836 3860 uid 3378,0 3837 3861 decl (Decl … … 3848 3872 ) 3849 3873 xt "39000,5400,64500,6200" 3850 st "A2_D : std_logic_vector(11 DOWNTO 0) 3851 " 3852 ) 3853 ) 3854 *110 (Net 3874 st "A2_D : std_logic_vector(11 DOWNTO 0)" 3875 ) 3876 ) 3877 *111 (Net 3855 3878 uid 3380,0 3856 3879 decl (Decl … … 3867 3890 ) 3868 3891 xt "39000,6200,64500,7000" 3869 st "A3_D : std_logic_vector(11 DOWNTO 0) 3870 " 3871 ) 3872 ) 3873 *111 (HdlText 3892 st "A3_D : std_logic_vector(11 DOWNTO 0)" 3893 ) 3894 ) 3895 *112 (HdlText 3874 3896 uid 3394,0 3875 3897 optionalChildren [ 3876 *11 2(EmbeddedText3898 *113 (EmbeddedText 3877 3899 uid 3400,0 3878 3900 commentText (CommentText … … 3926 3948 stg "VerticalLayoutStrategy" 3927 3949 textVec [ 3928 *11 3(Text3950 *114 (Text 3929 3951 uid 3397,0 3930 3952 va (VaSet … … 3936 3958 tm "HdlTextNameMgr" 3937 3959 ) 3938 *11 4(Text3960 *115 (Text 3939 3961 uid 3398,0 3940 3962 va (VaSet … … 3962 3984 viewiconposition 0 3963 3985 ) 3964 *11 5(Net3986 *116 (Net 3965 3987 uid 3460,0 3966 3988 decl (Decl … … 3975 3997 font "Courier New,8,0" 3976 3998 ) 3977 xt "39000,21400,54000,22200" 3978 st "D0_SRCLK : STD_LOGIC 3979 " 3980 ) 3981 ) 3982 *116 (Net 3999 xt "39000,22200,54000,23000" 4000 st "D0_SRCLK : STD_LOGIC" 4001 ) 4002 ) 4003 *117 (Net 3983 4004 uid 3462,0 3984 4005 decl (Decl … … 3993 4014 font "Courier New,8,0" 3994 4015 ) 3995 xt "39000,22200,54000,23000" 3996 st "D1_SRCLK : STD_LOGIC 3997 " 3998 ) 3999 ) 4000 *117 (Net 4016 xt "39000,23000,54000,23800" 4017 st "D1_SRCLK : STD_LOGIC" 4018 ) 4019 ) 4020 *118 (Net 4001 4021 uid 3464,0 4002 4022 decl (Decl … … 4011 4031 font "Courier New,8,0" 4012 4032 ) 4013 xt "39000,23000,54000,23800" 4014 st "D2_SRCLK : STD_LOGIC 4015 " 4016 ) 4017 ) 4018 *118 (Net 4033 xt "39000,23800,54000,24600" 4034 st "D2_SRCLK : STD_LOGIC" 4035 ) 4036 ) 4037 *119 (Net 4019 4038 uid 3466,0 4020 4039 decl (Decl … … 4029 4048 font "Courier New,8,0" 4030 4049 ) 4031 xt "39000,23800,54000,24600" 4032 st "D3_SRCLK : STD_LOGIC 4033 " 4034 ) 4035 ) 4036 *119 (PortIoIn 4050 xt "39000,24600,54000,25400" 4051 st "D3_SRCLK : STD_LOGIC" 4052 ) 4053 ) 4054 *120 (PortIoIn 4037 4055 uid 3476,0 4038 4056 shape (CompositeShape … … 4079 4097 ) 4080 4098 ) 4081 *12 0(PortIoIn4099 *121 (PortIoIn 4082 4100 uid 3482,0 4083 4101 shape (CompositeShape … … 4124 4142 ) 4125 4143 ) 4126 *12 1(PortIoIn4144 *122 (PortIoIn 4127 4145 uid 3488,0 4128 4146 shape (CompositeShape … … 4169 4187 ) 4170 4188 ) 4171 *12 2(PortIoIn4189 *123 (PortIoIn 4172 4190 uid 3494,0 4173 4191 shape (CompositeShape … … 4214 4232 ) 4215 4233 ) 4216 *12 3(Net4234 *124 (Net 4217 4235 uid 3500,0 4218 4236 decl (Decl … … 4228 4246 ) 4229 4247 xt "39000,7800,54000,8600" 4230 st "D0_SROUT : std_logic 4231 " 4232 ) 4233 ) 4234 *124 (Net 4248 st "D0_SROUT : std_logic" 4249 ) 4250 ) 4251 *125 (Net 4235 4252 uid 3502,0 4236 4253 decl (Decl … … 4246 4263 ) 4247 4264 xt "39000,8600,54000,9400" 4248 st "D1_SROUT : std_logic 4249 " 4250 ) 4251 ) 4252 *125 (Net 4265 st "D1_SROUT : std_logic" 4266 ) 4267 ) 4268 *126 (Net 4253 4269 uid 3504,0 4254 4270 decl (Decl … … 4264 4280 ) 4265 4281 xt "39000,9400,54000,10200" 4266 st "D2_SROUT : std_logic 4267 " 4268 ) 4269 ) 4270 *126 (Net 4282 st "D2_SROUT : std_logic" 4283 ) 4284 ) 4285 *127 (Net 4271 4286 uid 3506,0 4272 4287 decl (Decl … … 4282 4297 ) 4283 4298 xt "39000,10200,54000,11000" 4284 st "D3_SROUT : std_logic 4285 " 4286 ) 4287 ) 4288 *127 (PortIoOut 4299 st "D3_SROUT : std_logic" 4300 ) 4301 ) 4302 *128 (PortIoOut 4289 4303 uid 3508,0 4290 4304 shape (CompositeShape … … 4331 4345 ) 4332 4346 ) 4333 *12 8(Net4347 *129 (Net 4334 4348 uid 3514,0 4335 4349 decl (Decl … … 4346 4360 font "Courier New,8,0" 4347 4361 ) 4348 xt "39000,27000,73500,27800" 4349 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 4350 " 4351 ) 4352 ) 4353 *129 (PortIoOut 4362 xt "39000,27800,73500,28600" 4363 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 4364 ) 4365 ) 4366 *130 (PortIoOut 4354 4367 uid 3516,0 4355 4368 shape (CompositeShape … … 4396 4409 ) 4397 4410 ) 4398 *13 0(Net4411 *131 (Net 4399 4412 uid 3522,0 4400 4413 decl (Decl … … 4410 4423 font "Courier New,8,0" 4411 4424 ) 4412 xt "39000,26200,67500,27000" 4413 st "DWRITE : std_logic := '0' 4414 " 4415 ) 4416 ) 4417 *131 (PortIoOut 4425 xt "39000,27000,67500,27800" 4426 st "DWRITE : std_logic := '0'" 4427 ) 4428 ) 4429 *132 (PortIoOut 4418 4430 uid 3536,0 4419 4431 shape (CompositeShape … … 4459 4471 ) 4460 4472 ) 4461 *13 2(HdlText4473 *133 (HdlText 4462 4474 uid 3542,0 4463 4475 optionalChildren [ 4464 *13 3(EmbeddedText4476 *134 (EmbeddedText 4465 4477 uid 3612,0 4466 4478 commentText (CommentText … … 4514 4526 stg "VerticalLayoutStrategy" 4515 4527 textVec [ 4516 *13 4(Text4528 *135 (Text 4517 4529 uid 3545,0 4518 4530 va (VaSet … … 4524 4536 tm "HdlTextNameMgr" 4525 4537 ) 4526 *13 5(Text4538 *136 (Text 4527 4539 uid 3546,0 4528 4540 va (VaSet … … 4550 4562 viewiconposition 0 4551 4563 ) 4552 *13 6(PortIoOut4564 *137 (PortIoOut 4553 4565 uid 3548,0 4554 4566 shape (CompositeShape … … 4594 4606 ) 4595 4607 ) 4596 *13 7(PortIoOut4608 *138 (PortIoOut 4597 4609 uid 3554,0 4598 4610 shape (CompositeShape … … 4638 4650 ) 4639 4651 ) 4640 *13 8(PortIoOut4652 *139 (PortIoOut 4641 4653 uid 3560,0 4642 4654 shape (CompositeShape … … 4682 4694 ) 4683 4695 ) 4684 *1 39(PortIoOut4696 *140 (PortIoOut 4685 4697 uid 3566,0 4686 4698 shape (CompositeShape … … 4726 4738 ) 4727 4739 ) 4728 *14 0(Net4740 *141 (Net 4729 4741 uid 3604,0 4730 4742 decl (Decl … … 4739 4751 font "Courier New,8,0" 4740 4752 ) 4741 xt "39000,39800,54000,40600" 4742 st "T0_CS : std_logic 4743 " 4744 ) 4745 ) 4746 *141 (Net 4753 xt "39000,40600,54000,41400" 4754 st "T0_CS : std_logic" 4755 ) 4756 ) 4757 *142 (Net 4747 4758 uid 3606,0 4748 4759 decl (Decl … … 4757 4768 font "Courier New,8,0" 4758 4769 ) 4759 xt "39000,40600,54000,41400" 4760 st "T1_CS : std_logic 4761 " 4762 ) 4763 ) 4764 *142 (Net 4770 xt "39000,41400,54000,42200" 4771 st "T1_CS : std_logic" 4772 ) 4773 ) 4774 *143 (Net 4765 4775 uid 3608,0 4766 4776 decl (Decl … … 4775 4785 font "Courier New,8,0" 4776 4786 ) 4777 xt "39000,41400,54000,42200" 4778 st "T2_CS : std_logic 4779 " 4780 ) 4781 ) 4782 *143 (Net 4787 xt "39000,42200,54000,43000" 4788 st "T2_CS : std_logic" 4789 ) 4790 ) 4791 *144 (Net 4783 4792 uid 3610,0 4784 4793 decl (Decl … … 4793 4802 font "Courier New,8,0" 4794 4803 ) 4795 xt "39000,42200,54000,43000" 4796 st "T3_CS : std_logic 4797 " 4798 ) 4799 ) 4800 *144 (PortIoOut 4804 xt "39000,43000,54000,43800" 4805 st "T3_CS : std_logic" 4806 ) 4807 ) 4808 *145 (PortIoOut 4801 4809 uid 3624,0 4802 4810 shape (CompositeShape … … 4842 4850 ) 4843 4851 ) 4844 *14 5(Net4852 *146 (Net 4845 4853 uid 3630,0 4846 4854 decl (Decl … … 4855 4863 font "Courier New,8,0" 4856 4864 ) 4857 xt "39000,39000,54000,39800" 4858 st "S_CLK : std_logic 4859 " 4860 ) 4861 ) 4862 *146 (Net 4865 xt "39000,39800,54000,40600" 4866 st "S_CLK : std_logic" 4867 ) 4868 ) 4869 *147 (Net 4863 4870 uid 3632,0 4864 4871 decl (Decl … … 4874 4881 font "Courier New,8,0" 4875 4882 ) 4876 xt "39000,43800,64000,44600" 4877 st "W_A : std_logic_vector(9 DOWNTO 0) 4878 " 4879 ) 4880 ) 4881 *147 (Net 4883 xt "39000,44600,64000,45400" 4884 st "W_A : std_logic_vector(9 DOWNTO 0)" 4885 ) 4886 ) 4887 *148 (Net 4882 4888 uid 3634,0 4883 4889 decl (Decl … … 4893 4899 font "Courier New,8,0" 4894 4900 ) 4895 xt "39000,48600,64500,49400" 4896 st "W_D : std_logic_vector(15 DOWNTO 0) 4897 " 4898 ) 4899 ) 4900 *148 (Net 4901 xt "39000,49400,64500,50200" 4902 st "W_D : std_logic_vector(15 DOWNTO 0)" 4903 ) 4904 ) 4905 *149 (Net 4901 4906 uid 3636,0 4902 4907 decl (Decl … … 4912 4917 font "Courier New,8,0" 4913 4918 ) 4914 xt "39000,46200,67500,47000" 4915 st "W_RES : std_logic := '1' 4916 " 4917 ) 4918 ) 4919 *149 (Net 4919 xt "39000,47000,67500,47800" 4920 st "W_RES : std_logic := '1'" 4921 ) 4922 ) 4923 *150 (Net 4920 4924 uid 3638,0 4921 4925 decl (Decl … … 4931 4935 font "Courier New,8,0" 4932 4936 ) 4933 xt "39000,45400,67500,46200" 4934 st "W_RD : std_logic := '1' 4935 " 4936 ) 4937 ) 4938 *150 (Net 4937 xt "39000,46200,67500,47000" 4938 st "W_RD : std_logic := '1'" 4939 ) 4940 ) 4941 *151 (Net 4939 4942 uid 3640,0 4940 4943 decl (Decl … … 4950 4953 font "Courier New,8,0" 4951 4954 ) 4952 xt "39000,47000,67500,47800" 4953 st "W_WR : std_logic := '1' 4954 " 4955 ) 4956 ) 4957 *151 (Net 4955 xt "39000,47800,67500,48600" 4956 st "W_WR : std_logic := '1'" 4957 ) 4958 ) 4959 *152 (Net 4958 4960 uid 3642,0 4959 4961 decl (Decl … … 4968 4970 font "Courier New,8,0" 4969 4971 ) 4970 xt "39000,16600,54000,17400" 4971 st "W_INT : std_logic 4972 " 4973 ) 4974 ) 4975 *152 (Net 4972 xt "39000,17400,54000,18200" 4973 st "W_INT : std_logic" 4974 ) 4975 ) 4976 *153 (Net 4976 4977 uid 3644,0 4977 4978 decl (Decl … … 4987 4988 font "Courier New,8,0" 4988 4989 ) 4989 xt "39000,44600,67500,45400" 4990 st "W_CS : std_logic := '1' 4991 " 4992 ) 4993 ) 4994 *153 (PortIoInOut 4990 xt "39000,45400,67500,46200" 4991 st "W_CS : std_logic := '1'" 4992 ) 4993 ) 4994 *154 (PortIoInOut 4995 4995 uid 3674,0 4996 4996 shape (CompositeShape … … 5034 5034 ) 5035 5035 ) 5036 *15 4(Net5036 *155 (Net 5037 5037 uid 3680,0 5038 5038 decl (Decl … … 5048 5048 font "Courier New,8,0" 5049 5049 ) 5050 xt "39000,31000,67500,31800" 5051 st "MOSI : std_logic := '0' 5052 " 5053 ) 5054 ) 5055 *155 (PortIoOut 5050 xt "39000,31800,67500,32600" 5051 st "MOSI : std_logic := '0'" 5052 ) 5053 ) 5054 *156 (PortIoOut 5056 5055 uid 3688,0 5057 5056 shape (CompositeShape … … 5097 5096 ) 5098 5097 ) 5099 *15 6(Net5098 *157 (Net 5100 5099 uid 3694,0 5101 5100 decl (Decl … … 5112 5111 font "Courier New,8,0" 5113 5112 ) 5114 xt "39000,47800,54000,48600" 5115 st "MISO : std_logic 5116 " 5117 ) 5118 ) 5119 *157 (HdlText 5113 xt "39000,48600,54000,49400" 5114 st "MISO : std_logic" 5115 ) 5116 ) 5117 *158 (HdlText 5120 5118 uid 3700,0 5121 5119 optionalChildren [ 5122 *15 8(EmbeddedText5120 *159 (EmbeddedText 5123 5121 uid 3706,0 5124 5122 commentText (CommentText … … 5180 5178 stg "VerticalLayoutStrategy" 5181 5179 textVec [ 5182 *1 59(Text5180 *160 (Text 5183 5181 uid 3703,0 5184 5182 va (VaSet … … 5190 5188 tm "HdlTextNameMgr" 5191 5189 ) 5192 *16 0(Text5190 *161 (Text 5193 5191 uid 3704,0 5194 5192 va (VaSet … … 5216 5214 viewiconposition 0 5217 5215 ) 5218 *16 1(PortIoOut5216 *162 (PortIoOut 5219 5217 uid 3710,0 5220 5218 shape (CompositeShape … … 5260 5258 ) 5261 5259 ) 5262 *16 2(PortIoOut5260 *163 (PortIoOut 5263 5261 uid 3716,0 5264 5262 shape (CompositeShape … … 5304 5302 ) 5305 5303 ) 5306 *16 3(PortIoOut5304 *164 (PortIoOut 5307 5305 uid 3722,0 5308 5306 shape (CompositeShape … … 5348 5346 ) 5349 5347 ) 5350 *16 4(PortIoOut5348 *165 (PortIoOut 5351 5349 uid 3728,0 5352 5350 shape (CompositeShape … … 5392 5390 ) 5393 5391 ) 5394 *16 5(PortIoOut5392 *166 (PortIoOut 5395 5393 uid 3734,0 5396 5394 shape (CompositeShape … … 5436 5434 ) 5437 5435 ) 5438 *16 6(PortIoOut5436 *167 (PortIoOut 5439 5437 uid 3740,0 5440 5438 shape (CompositeShape … … 5480 5478 ) 5481 5479 ) 5482 *16 7(PortIoOut5480 *168 (PortIoOut 5483 5481 uid 3752,0 5484 5482 shape (CompositeShape … … 5524 5522 ) 5525 5523 ) 5526 *16 8(Net5524 *169 (Net 5527 5525 uid 3864,0 5528 5526 decl (Decl … … 5537 5535 font "Courier New,8,0" 5538 5536 ) 5539 xt "39000,43000,54000,43800" 5540 st "TRG_V : std_logic 5541 " 5542 ) 5543 ) 5544 *169 (Net 5537 xt "39000,43800,54000,44600" 5538 st "TRG_V : std_logic" 5539 ) 5540 ) 5541 *170 (Net 5545 5542 uid 3866,0 5546 5543 decl (Decl … … 5555 5552 font "Courier New,8,0" 5556 5553 ) 5557 xt "39000,35000,54000,35800" 5558 st "RS485_C_RE : std_logic 5559 " 5560 ) 5561 ) 5562 *170 (Net 5554 xt "39000,35800,54000,36600" 5555 st "RS485_C_RE : std_logic" 5556 ) 5557 ) 5558 *171 (Net 5563 5559 uid 3868,0 5564 5560 decl (Decl … … 5573 5569 font "Courier New,8,0" 5574 5570 ) 5575 xt "39000,33400,54000,34200" 5576 st "RS485_C_DE : std_logic 5577 " 5578 ) 5579 ) 5580 *171 (Net 5571 xt "39000,34200,54000,35000" 5572 st "RS485_C_DE : std_logic" 5573 ) 5574 ) 5575 *172 (Net 5581 5576 uid 3870,0 5582 5577 decl (Decl … … 5591 5586 font "Courier New,8,0" 5592 5587 ) 5593 xt "39000,36600,54000,37400" 5594 st "RS485_E_RE : std_logic 5595 " 5596 ) 5597 ) 5598 *172 (Net 5588 xt "39000,37400,54000,38200" 5589 st "RS485_E_RE : std_logic" 5590 ) 5591 ) 5592 *173 (Net 5599 5593 uid 3872,0 5600 5594 decl (Decl … … 5609 5603 font "Courier New,8,0" 5610 5604 ) 5611 xt "39000,35800,54000,36600" 5612 st "RS485_E_DE : std_logic 5613 " 5614 ) 5615 ) 5616 *173 (Net 5605 xt "39000,36600,54000,37400" 5606 st "RS485_E_DE : std_logic" 5607 ) 5608 ) 5609 *174 (Net 5617 5610 uid 3874,0 5618 5611 decl (Decl … … 5628 5621 font "Courier New,8,0" 5629 5622 ) 5630 xt "39000,25400,67500,26200" 5631 st "DENABLE : std_logic := '0' 5632 " 5633 ) 5634 ) 5635 *174 (Net 5623 xt "39000,26200,67500,27000" 5624 st "DENABLE : std_logic := '0'" 5625 ) 5626 ) 5627 *175 (Net 5636 5628 uid 3878,0 5637 5629 decl (Decl … … 5646 5638 font "Courier New,8,0" 5647 5639 ) 5648 xt "39000,29400,54000,30200" 5649 st "EE_CS : std_logic 5650 " 5651 ) 5652 ) 5653 *175 (PortIoOut 5640 xt "39000,30200,54000,31000" 5641 st "EE_CS : std_logic" 5642 ) 5643 ) 5644 *176 (PortIoOut 5654 5645 uid 3995,0 5655 5646 shape (CompositeShape … … 5696 5687 ) 5697 5688 ) 5698 *17 6(PortIoOut5689 *177 (PortIoOut 5699 5690 uid 4001,0 5700 5691 shape (CompositeShape … … 5741 5732 ) 5742 5733 ) 5743 *17 7(PortIoOut5734 *178 (PortIoOut 5744 5735 uid 4007,0 5745 5736 shape (CompositeShape … … 5786 5777 ) 5787 5778 ) 5788 *17 8(PortIoOut5779 *179 (PortIoOut 5789 5780 uid 4013,0 5790 5781 shape (CompositeShape … … 5831 5822 ) 5832 5823 ) 5833 *1 79(PortIoOut5824 *180 (PortIoOut 5834 5825 uid 4916,0 5835 5826 shape (CompositeShape … … 5844 5835 sl 0 5845 5836 ro 270 5846 xt " 111500,119625,113000,120375"5837 xt "72500,153625,74000,154375" 5847 5838 ) 5848 5839 (Line … … 5850 5841 sl 0 5851 5842 ro 270 5852 xt " 111000,120000,111500,120000"5853 pts [ 5854 " 111000,120000"5855 " 111500,120000"5843 xt "72000,154000,72500,154000" 5844 pts [ 5845 "72000,154000" 5846 "72500,154000" 5856 5847 ] 5857 5848 ) … … 5868 5859 va (VaSet 5869 5860 ) 5870 xt " 114000,119500,115900,120500"5861 xt "75000,153500,76900,154500" 5871 5862 st "D_T" 5872 blo " 114000,120300"5873 tm "WireNameMgr" 5874 ) 5875 ) 5876 ) 5877 *18 0(Net5863 blo "75000,154300" 5864 tm "WireNameMgr" 5865 ) 5866 ) 5867 ) 5868 *181 (Net 5878 5869 uid 5320,0 5879 5870 decl (Decl 5880 5871 n "D_T" 5881 5872 t "std_logic_vector" 5882 b "( 7DOWNTO 0)"5873 b "(5 DOWNTO 0)" 5883 5874 o 31 5884 5875 suid 141,0 … … 5890 5881 font "Courier New,8,0" 5891 5882 ) 5892 xt "39000,27800,73500,28600" 5893 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5894 " 5895 ) 5896 ) 5897 *181 (PortIoIn 5883 xt "39000,28600,73500,29400" 5884 st "D_T : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0')" 5885 ) 5886 ) 5887 *182 (PortIoIn 5898 5888 uid 6781,0 5899 5889 shape (CompositeShape … … 5940 5930 ) 5941 5931 ) 5942 *18 2(Net5932 *183 (Net 5943 5933 uid 6793,0 5944 5934 decl (Decl … … 5955 5945 ) 5956 5946 xt "39000,11000,64000,11800" 5957 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) 5958 " 5959 ) 5960 ) 5961 *183 (PortIoOut 5947 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" 5948 ) 5949 ) 5950 *184 (PortIoOut 5962 5951 uid 6874,0 5963 5952 shape (CompositeShape … … 6003 5992 ) 6004 5993 ) 6005 *18 4(Net5994 *185 (Net 6006 5995 uid 6886,0 6007 5996 decl (Decl … … 6018 6007 font "Courier New,8,0" 6019 6008 ) 6020 xt "39000,28600,73500,29400" 6021 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6022 " 6023 ) 6024 ) 6025 *185 (HdlText 6009 xt "39000,29400,73500,30200" 6010 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6011 ) 6012 ) 6013 *186 (HdlText 6026 6014 uid 7092,0 6027 6015 optionalChildren [ 6028 *18 6(EmbeddedText6016 *187 (EmbeddedText 6029 6017 uid 7098,0 6030 6018 commentText (CommentText … … 6076 6064 stg "VerticalLayoutStrategy" 6077 6065 textVec [ 6078 *18 7(Text6066 *188 (Text 6079 6067 uid 7095,0 6080 6068 va (VaSet … … 6086 6074 tm "HdlTextNameMgr" 6087 6075 ) 6088 *18 8(Text6076 *189 (Text 6089 6077 uid 7096,0 6090 6078 va (VaSet … … 6112 6100 viewiconposition 0 6113 6101 ) 6114 *1 89(PortIoOut6102 *190 (PortIoOut 6115 6103 uid 7138,0 6116 6104 shape (CompositeShape … … 6156 6144 ) 6157 6145 ) 6158 *19 0(Net6146 *191 (Net 6159 6147 uid 7150,0 6160 6148 decl (Decl … … 6171 6159 font "Courier New,8,0" 6172 6160 ) 6173 xt "39000,19000,73500,19800" 6174 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6175 " 6176 ) 6177 ) 6178 *191 (Net 6161 xt "39000,19800,73500,20600" 6162 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6163 ) 6164 ) 6165 *192 (Net 6179 6166 uid 7485,0 6180 6167 decl (Decl … … 6189 6176 font "Courier New,8,0" 6190 6177 ) 6191 xt "39000,64800,57500,65600" 6192 st "SIGNAL dummy : std_logic 6193 " 6194 ) 6195 ) 6196 *192 (MWC 6178 xt "39000,65600,57500,66400" 6179 st "SIGNAL dummy : std_logic" 6180 ) 6181 ) 6182 *193 (MWC 6197 6183 uid 7652,0 6198 6184 optionalChildren [ 6199 *19 3(CptPort6185 *194 (CptPort 6200 6186 uid 7632,0 6201 6187 optionalChildren [ 6202 *19 4(Line6188 *195 (Line 6203 6189 uid 7636,0 6204 6190 layer 5 … … 6259 6245 ) 6260 6246 ) 6261 *19 5(CptPort6247 *196 (CptPort 6262 6248 uid 7637,0 6263 6249 optionalChildren [ 6264 *19 6(Line6250 *197 (Line 6265 6251 uid 7641,0 6266 6252 layer 5 … … 6324 6310 ) 6325 6311 ) 6326 *19 7(CommentGraphic6312 *198 (CommentGraphic 6327 6313 uid 7642,0 6328 6314 shape (PolyLine2D … … 6345 6331 oxt "6000,6000,7000,7000" 6346 6332 ) 6347 *19 8(CommentGraphic6333 *199 (CommentGraphic 6348 6334 uid 7644,0 6349 6335 shape (PolyLine2D … … 6366 6352 oxt "6000,7000,7000,8000" 6367 6353 ) 6368 * 199(CommentGraphic6354 *200 (CommentGraphic 6369 6355 uid 7646,0 6370 6356 shape (PolyLine2D … … 6387 6373 oxt "6988,7329,7988,7329" 6388 6374 ) 6389 *20 0(CommentGraphic6375 *201 (CommentGraphic 6390 6376 uid 7648,0 6391 6377 shape (PolyLine2D … … 6406 6392 oxt "8000,7000,9000,7000" 6407 6393 ) 6408 *20 1(CommentGraphic6394 *202 (CommentGraphic 6409 6395 uid 7650,0 6410 6396 shape (PolyLine2D … … 6447 6433 stg "VerticalLayoutStrategy" 6448 6434 textVec [ 6449 *20 2(Text6435 *203 (Text 6450 6436 uid 7655,0 6451 6437 va (VaSet … … 6457 6443 blo "90350,83900" 6458 6444 ) 6459 *20 3(Text6445 *204 (Text 6460 6446 uid 7656,0 6461 6447 va (VaSet … … 6466 6452 blo "90350,84900" 6467 6453 ) 6468 *20 4(Text6454 *205 (Text 6469 6455 uid 7657,0 6470 6456 va (VaSet … … 6511 6497 ) 6512 6498 ) 6513 *20 5(Net6499 *206 (Net 6514 6500 uid 8851,0 6515 6501 decl (Decl … … 6526 6512 font "Courier New,8,0" 6527 6513 ) 6528 xt "39000,64000,77000,64800" 6529 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6530 " 6531 ) 6532 ) 6533 *206 (Net 6514 xt "39000,64800,77000,65600" 6515 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6516 ) 6517 ) 6518 *207 (Net 6534 6519 uid 9500,0 6535 6520 decl (Decl … … 6544 6529 font "Courier New,8,0" 6545 6530 ) 6546 xt "39000,54400,57500,55200" 6547 st "SIGNAL CLK_50 : std_logic 6548 " 6549 ) 6550 ) 6551 *207 (MWC 6531 xt "39000,55200,57500,56000" 6532 st "SIGNAL CLK_50 : std_logic" 6533 ) 6534 ) 6535 *208 (MWC 6552 6536 uid 10023,0 6553 6537 optionalChildren [ 6554 *20 8(CptPort6538 *209 (CptPort 6555 6539 uid 9995,0 6556 6540 optionalChildren [ 6557 *2 09(Line6541 *210 (Line 6558 6542 uid 9999,0 6559 6543 layer 5 … … 6568 6552 ] 6569 6553 ) 6570 *21 0(Property6554 *211 (Property 6571 6555 uid 10000,0 6572 6556 pclass "_MW_GEOM_" … … 6612 6596 ) 6613 6597 ) 6614 *21 1(CptPort6598 *212 (CptPort 6615 6599 uid 10001,0 6616 6600 optionalChildren [ 6617 *21 2(Line6601 *213 (Line 6618 6602 uid 10005,0 6619 6603 layer 5 … … 6667 6651 ) 6668 6652 ) 6669 *21 3(CptPort6653 *214 (CptPort 6670 6654 uid 10006,0 6671 6655 optionalChildren [ 6672 *21 4(Line6656 *215 (Line 6673 6657 uid 10010,0 6674 6658 layer 5 … … 6721 6705 ) 6722 6706 ) 6723 *21 5(CommentGraphic6707 *216 (CommentGraphic 6724 6708 uid 10011,0 6725 6709 optionalChildren [ 6726 *21 6(Property6710 *217 (Property 6727 6711 uid 10013,0 6728 6712 pclass "_MW_GEOM_" … … 6748 6732 oxt "11000,6000,11000,6000" 6749 6733 ) 6750 *21 7(CommentGraphic6734 *218 (CommentGraphic 6751 6735 uid 10014,0 6752 6736 optionalChildren [ 6753 *21 8(Property6737 *219 (Property 6754 6738 uid 10016,0 6755 6739 pclass "_MW_GEOM_" … … 6775 6759 oxt "11000,10000,11000,10000" 6776 6760 ) 6777 *2 19(Grouping6761 *220 (Grouping 6778 6762 uid 10017,0 6779 6763 optionalChildren [ 6780 *22 0(CommentGraphic6764 *221 (CommentGraphic 6781 6765 uid 10019,0 6782 6766 shape (PolyLine2D … … 6799 6783 oxt "9000,6000,11000,10000" 6800 6784 ) 6801 *22 1(CommentGraphic6785 *222 (CommentGraphic 6802 6786 uid 10021,0 6803 6787 shape (Arc2D … … 6852 6836 stg "VerticalLayoutStrategy" 6853 6837 textVec [ 6854 *22 2(Text6838 *223 (Text 6855 6839 uid 10026,0 6856 6840 va (VaSet … … 6862 6846 blo "44500,73300" 6863 6847 ) 6864 *22 3(Text6848 *224 (Text 6865 6849 uid 10027,0 6866 6850 va (VaSet … … 6871 6855 blo "44500,74300" 6872 6856 ) 6873 *22 4(Text6857 *225 (Text 6874 6858 uid 10028,0 6875 6859 va (VaSet … … 6916 6900 ) 6917 6901 ) 6918 *22 5(Net6902 *226 (Net 6919 6903 uid 10032,0 6920 6904 decl (Decl … … 6929 6913 font "Courier New,8,0" 6930 6914 ) 6931 xt "39000,53600,57500,54400" 6932 st "SIGNAL CLK_25_PS1 : std_logic 6933 " 6934 ) 6935 ) 6936 *226 (Net 6915 xt "39000,54400,57500,55200" 6916 st "SIGNAL CLK_25_PS1 : std_logic" 6917 ) 6918 ) 6919 *227 (Net 6937 6920 uid 10050,0 6938 6921 decl (Decl … … 6948 6931 font "Courier New,8,0" 6949 6932 ) 6950 xt "39000,60800,71000,61600" 6951 st "SIGNAL adc_clk_en : std_logic := '0' 6952 " 6953 ) 6954 ) 6955 *227 (PortIoOut 6933 xt "39000,61600,71000,62400" 6934 st "SIGNAL adc_clk_en : std_logic := '0'" 6935 ) 6936 ) 6937 *228 (PortIoOut 6956 6938 uid 10296,0 6957 6939 shape (CompositeShape … … 6997 6979 ) 6998 6980 ) 6999 *22 8(Net6981 *229 (Net 7000 6982 uid 10308,0 7001 6983 decl (Decl … … 7012 6994 font "Courier New,8,0" 7013 6995 ) 7014 xt "39000,18200,73500,19000" 7015 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0') 7016 " 7017 ) 7018 ) 7019 *229 (HdlText 6996 xt "39000,19000,73500,19800" 6997 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0')" 6998 ) 6999 ) 7000 *230 (HdlText 7020 7001 uid 10310,0 7021 7002 optionalChildren [ 7022 *23 0(EmbeddedText7003 *231 (EmbeddedText 7023 7004 uid 10316,0 7024 7005 commentText (CommentText … … 7062 7043 A1_T(7) <= drs_channel_id(3); 7063 7044 7064 A0_T(5 downto 0) <= POSITION_ID;7045 A0_T(5 downto 0) <= (others => '0'); 7065 7046 A0_T(6) <= REFCLK; 7066 7047 A0_T(7) <= RS485_E_DI; … … 7094 7075 stg "VerticalLayoutStrategy" 7095 7076 textVec [ 7096 *23 1(Text7077 *232 (Text 7097 7078 uid 10313,0 7098 7079 va (VaSet … … 7104 7085 tm "HdlTextNameMgr" 7105 7086 ) 7106 *23 2(Text7087 *233 (Text 7107 7088 uid 10314,0 7108 7089 va (VaSet … … 7130 7111 viewiconposition 0 7131 7112 ) 7132 *23 3(Net7113 *234 (Net 7133 7114 uid 10496,0 7134 7115 decl (Decl … … 7143 7124 font "Courier New,8,0" 7144 7125 ) 7145 xt "39000,52000,57500,52800" 7146 st "SIGNAL CLK50_OUT : std_logic 7147 " 7148 ) 7149 ) 7150 *234 (Net 7126 xt "39000,52800,57500,53600" 7127 st "SIGNAL CLK50_OUT : std_logic" 7128 ) 7129 ) 7130 *235 (Net 7151 7131 uid 10504,0 7152 7132 decl (Decl … … 7161 7141 font "Courier New,8,0" 7162 7142 ) 7163 xt "39000,50400,57500,51200" 7164 st "SIGNAL CLK25_OUT : std_logic 7165 " 7166 ) 7167 ) 7168 *235 (Net 7143 xt "39000,51200,57500,52000" 7144 st "SIGNAL CLK25_OUT : std_logic" 7145 ) 7146 ) 7147 *236 (Net 7169 7148 uid 10512,0 7170 7149 decl (Decl … … 7179 7158 font "Courier New,8,0" 7180 7159 ) 7181 xt "39000,51200,57500,52000" 7182 st "SIGNAL CLK25_PSOUT : std_logic 7183 " 7184 ) 7185 ) 7186 *236 (Net 7160 xt "39000,52000,57500,52800" 7161 st "SIGNAL CLK25_PSOUT : std_logic" 7162 ) 7163 ) 7164 *237 (Net 7187 7165 uid 10520,0 7188 7166 decl (Decl … … 7197 7175 font "Courier New,8,0" 7198 7176 ) 7199 xt "39000,59200,57500,60000" 7200 st "SIGNAL PS_DIR_IN : std_logic 7201 " 7202 ) 7203 ) 7204 *237 (Net 7177 xt "39000,60000,57500,60800" 7178 st "SIGNAL PS_DIR_IN : std_logic" 7179 ) 7180 ) 7181 *238 (Net 7205 7182 uid 10544,0 7206 7183 decl (Decl … … 7215 7192 font "Courier New,8,0" 7216 7193 ) 7217 xt "39000,58400,57500,59200" 7218 st "SIGNAL PSINCDEC_OUT : std_logic 7219 " 7220 ) 7221 ) 7222 *238 (Net 7194 xt "39000,59200,57500,60000" 7195 st "SIGNAL PSINCDEC_OUT : std_logic" 7196 ) 7197 ) 7198 *239 (Net 7223 7199 uid 10552,0 7224 7200 decl (Decl … … 7235 7211 font "Courier New,8,0" 7236 7212 ) 7237 xt "39000,55200,57500,56000" 7238 st "SIGNAL DCM_locked : std_logic 7239 " 7240 ) 7241 ) 7242 *239 (Net 7213 xt "39000,56000,57500,56800" 7214 st "SIGNAL DCM_locked : std_logic" 7215 ) 7216 ) 7217 *240 (Net 7243 7218 uid 10560,0 7244 7219 decl (Decl … … 7256 7231 font "Courier New,8,0" 7257 7232 ) 7258 xt "39000,65600,71000,66400" 7259 st "SIGNAL ready : std_logic := '0' 7260 " 7261 ) 7262 ) 7263 *240 (Net 7233 xt "39000,67200,71000,68000" 7234 st "SIGNAL ready : std_logic := '0'" 7235 ) 7236 ) 7237 *241 (Net 7264 7238 uid 10568,0 7265 7239 decl (Decl … … 7278 7252 font "Courier New,8,0" 7279 7253 ) 7280 xt "39000,6 7200,71000,68800"7254 xt "39000,68800,71000,70400" 7281 7255 st "-- status: 7282 SIGNAL shifting : std_logic := '0' 7283 " 7284 ) 7285 ) 7286 *241 (Net 7256 SIGNAL shifting : std_logic := '0'" 7257 ) 7258 ) 7259 *242 (Net 7287 7260 uid 10576,0 7288 7261 decl (Decl … … 7297 7270 font "Courier New,8,0" 7298 7271 ) 7299 xt "39000,57600,57500,58400" 7300 st "SIGNAL PSDONE_extraOUT : std_logic 7301 " 7302 ) 7303 ) 7304 *242 (Net 7272 xt "39000,58400,57500,59200" 7273 st "SIGNAL PSDONE_extraOUT : std_logic" 7274 ) 7275 ) 7276 *243 (Net 7305 7277 uid 10584,0 7306 7278 decl (Decl … … 7315 7287 font "Courier New,8,0" 7316 7288 ) 7317 xt "39000,56800,57500,57600" 7318 st "SIGNAL PSCLK_OUT : std_logic 7319 " 7320 ) 7321 ) 7322 *243 (Net 7289 xt "39000,57600,57500,58400" 7290 st "SIGNAL PSCLK_OUT : std_logic" 7291 ) 7292 ) 7293 *244 (Net 7323 7294 uid 10592,0 7324 7295 decl (Decl … … 7333 7304 font "Courier New,8,0" 7334 7305 ) 7335 xt "39000,56000,57500,56800" 7336 st "SIGNAL LOCKED_extraOUT : std_logic 7337 " 7338 ) 7339 ) 7340 *244 (PortIoIn 7306 xt "39000,56800,57500,57600" 7307 st "SIGNAL LOCKED_extraOUT : std_logic" 7308 ) 7309 ) 7310 *245 (PortIoIn 7341 7311 uid 11090,0 7342 7312 shape (CompositeShape … … 7383 7353 ) 7384 7354 ) 7385 *24 5(Net7355 *246 (Net 7386 7356 uid 11102,0 7387 7357 decl (Decl … … 7396 7366 font "Courier New,8,0" 7397 7367 ) 7398 xt "39000,13400,54000,14200" 7399 st "RS485_C_DI : std_logic 7400 " 7401 ) 7402 ) 7403 *246 (PortIoOut 7368 xt "39000,14200,54000,15000" 7369 st "RS485_C_DI : std_logic" 7370 ) 7371 ) 7372 *247 (PortIoOut 7404 7373 uid 11104,0 7405 7374 shape (CompositeShape … … 7445 7414 ) 7446 7415 ) 7447 *24 7(Net7416 *248 (Net 7448 7417 uid 11116,0 7449 7418 decl (Decl … … 7458 7427 font "Courier New,8,0" 7459 7428 ) 7460 xt "39000,34200,54000,35000" 7461 st "RS485_C_DO : std_logic 7462 " 7463 ) 7464 ) 7465 *248 (PortIoIn 7429 xt "39000,35000,54000,35800" 7430 st "RS485_C_DO : std_logic" 7431 ) 7432 ) 7433 *249 (PortIoIn 7466 7434 uid 11508,0 7467 7435 shape (CompositeShape … … 7508 7476 ) 7509 7477 ) 7510 *2 49(Net7478 *250 (Net 7511 7479 uid 11520,0 7512 7480 decl (Decl … … 7521 7489 font "Courier New,8,0" 7522 7490 ) 7523 xt "39000,14200,54000,15000" 7524 st "RS485_E_DI : std_logic 7525 " 7526 ) 7527 ) 7528 *250 (Net 7491 xt "39000,15000,54000,15800" 7492 st "RS485_E_DI : std_logic" 7493 ) 7494 ) 7495 *251 (Net 7529 7496 uid 11534,0 7530 7497 decl (Decl … … 7539 7506 font "Courier New,8,0" 7540 7507 ) 7541 xt "39000,15000,54000,15800" 7542 st "RS485_E_DO : std_logic 7543 " 7544 ) 7545 ) 7546 *251 (PortIoIn 7508 xt "39000,15800,54000,16600" 7509 st "RS485_E_DO : std_logic" 7510 ) 7511 ) 7512 *252 (PortIoIn 7547 7513 uid 11922,0 7548 7514 shape (CompositeShape … … 7589 7555 ) 7590 7556 ) 7591 *25 2(PortIoOut7557 *253 (PortIoOut 7592 7558 uid 12326,0 7593 7559 shape (CompositeShape … … 7633 7599 ) 7634 7600 ) 7635 *25 3(Net7601 *254 (Net 7636 7602 uid 12334,0 7637 7603 decl (Decl … … 7647 7613 font "Courier New,8,0" 7648 7614 ) 7649 xt "39000,38200,67500,39000" 7650 st "SRIN : std_logic := '0' 7651 " 7652 ) 7653 ) 7654 *254 (PortIoOut 7615 xt "39000,39000,67500,39800" 7616 st "SRIN : std_logic := '0'" 7617 ) 7618 ) 7619 *255 (PortIoOut 7655 7620 uid 12539,0 7656 7621 shape (CompositeShape … … 7696 7661 ) 7697 7662 ) 7698 *25 5(PortIoOut7663 *256 (PortIoOut 7699 7664 uid 12553,0 7700 7665 shape (CompositeShape … … 7740 7705 ) 7741 7706 ) 7742 *25 6(PortIoOut7707 *257 (PortIoOut 7743 7708 uid 12567,0 7744 7709 shape (CompositeShape … … 7784 7749 ) 7785 7750 ) 7786 *25 7(Net7751 *258 (Net 7787 7752 uid 12762,0 7788 7753 decl (Decl … … 7797 7762 font "Courier New,8,0" 7798 7763 ) 7799 xt "39000,19800,54000,20600" 7800 st "AMBER_LED : std_logic 7801 " 7802 ) 7803 ) 7804 *258 (Net 7764 xt "39000,20600,54000,21400" 7765 st "AMBER_LED : std_logic" 7766 ) 7767 ) 7768 *259 (Net 7805 7769 uid 12764,0 7806 7770 decl (Decl … … 7815 7779 font "Courier New,8,0" 7816 7780 ) 7817 xt "39000,30200,54000,31000" 7818 st "GREEN_LED : std_logic 7819 " 7820 ) 7821 ) 7822 *259 (Net 7781 xt "39000,31000,54000,31800" 7782 st "GREEN_LED : std_logic" 7783 ) 7784 ) 7785 *260 (Net 7823 7786 uid 12766,0 7824 7787 decl (Decl … … 7833 7796 font "Courier New,8,0" 7834 7797 ) 7835 xt "39000,32600,54000,33400" 7836 st "RED_LED : std_logic 7837 " 7838 ) 7839 ) 7840 *260 (PortIoIn 7798 xt "39000,33400,54000,34200" 7799 st "RED_LED : std_logic" 7800 ) 7801 ) 7802 *261 (PortIoIn 7841 7803 uid 13516,0 7842 7804 shape (CompositeShape … … 7851 7813 sl 0 7852 7814 ro 270 7853 xt "1 10000,147625,111500,148375"7815 xt "10000,80625,11500,81375" 7854 7816 ) 7855 7817 (Line … … 7857 7819 sl 0 7858 7820 ro 270 7859 xt "11 1500,148000,112000,148000"7860 pts [ 7861 "11 1500,148000"7862 "1 12000,148000"7821 xt "11500,81000,12000,81000" 7822 pts [ 7823 "11500,81000" 7824 "12000,81000" 7863 7825 ] 7864 7826 ) … … 7875 7837 va (VaSet 7876 7838 ) 7877 xt " 103300,147500,109000,148500"7878 st " POSITION_ID"7839 xt "6900,80500,9000,81500" 7840 st "LINE" 7879 7841 ju 2 7880 blo " 109000,148300"7881 tm "WireNameMgr" 7882 ) 7883 ) 7884 ) 7885 *26 1(Net7842 blo "9000,81300" 7843 tm "WireNameMgr" 7844 ) 7845 ) 7846 ) 7847 *262 (Net 7886 7848 uid 13528,0 7887 7849 decl (Decl 7888 n " POSITION_ID"7850 n "LINE" 7889 7851 t "std_logic_vector" 7890 7852 b "( 5 DOWNTO 0 )" … … 7897 7859 font "Courier New,8,0" 7898 7860 ) 7899 xt "39000,11800,65000,12600" 7900 st "POSITION_ID : std_logic_vector( 5 DOWNTO 0 ) 7901 " 7902 ) 7903 ) 7904 *262 (PortIoIn 7861 xt "39000,12600,65000,13400" 7862 st "LINE : std_logic_vector( 5 DOWNTO 0 )" 7863 ) 7864 ) 7865 *263 (PortIoIn 7905 7866 uid 13628,0 7906 7867 shape (CompositeShape … … 7947 7908 ) 7948 7909 ) 7949 *26 3(Net7910 *264 (Net 7950 7911 uid 13640,0 7951 7912 decl (Decl … … 7960 7921 font "Courier New,8,0" 7961 7922 ) 7962 xt "39000,12600,54000,13400" 7963 st "REFCLK : std_logic 7923 xt "39000,13400,54000,14200" 7924 st "REFCLK : std_logic" 7925 ) 7926 ) 7927 *265 (PortIoIn 7928 uid 14322,0 7929 shape (CompositeShape 7930 uid 14323,0 7931 va (VaSet 7932 vasetType 1 7933 fg "0,0,32768" 7934 ) 7935 optionalChildren [ 7936 (Pentagon 7937 uid 14324,0 7938 sl 0 7939 ro 270 7940 xt "37000,138625,38500,139375" 7941 ) 7942 (Line 7943 uid 14325,0 7944 sl 0 7945 ro 270 7946 xt "38500,139000,39000,139000" 7947 pts [ 7948 "38500,139000" 7949 "39000,139000" 7950 ] 7951 ) 7952 ] 7953 ) 7954 stc 0 7955 sf 1 7956 tg (WTG 7957 uid 14326,0 7958 ps "PortIoTextPlaceStrategy" 7959 stg "STSignalDisplayStrategy" 7960 f (Text 7961 uid 14327,0 7962 va (VaSet 7963 ) 7964 xt "33100,138500,36000,139500" 7965 st "D_T_in" 7966 ju 2 7967 blo "36000,139300" 7968 tm "WireNameMgr" 7969 ) 7970 ) 7971 ) 7972 *266 (Net 7973 uid 14334,0 7974 decl (Decl 7975 n "D_T_in" 7976 t "std_logic_vector" 7977 b "(1 DOWNTO 0)" 7978 o 80 7979 suid 213,0 7980 ) 7981 declText (MLText 7982 uid 14335,0 7983 va (VaSet 7984 font "Courier New,8,0" 7985 ) 7986 xt "39000,11800,64000,12600" 7987 st "D_T_in : std_logic_vector(1 DOWNTO 0)" 7988 ) 7989 ) 7990 *267 (HdlText 7991 uid 14346,0 7992 optionalChildren [ 7993 *268 (EmbeddedText 7994 uid 14352,0 7995 commentText (CommentText 7996 uid 14353,0 7997 ps "CenterOffsetStrategy" 7998 shape (Rectangle 7999 uid 14354,0 8000 va (VaSet 8001 vasetType 1 8002 fg "65535,65535,65535" 8003 lineColor "0,0,32768" 8004 lineWidth 2 8005 ) 8006 xt "63000,156000,76000,169000" 8007 ) 8008 oxt "0,0,18000,5000" 8009 text (MLText 8010 uid 14355,0 8011 va (VaSet 8012 ) 8013 xt "63200,156200,76000,158200" 8014 st " 8015 D_T(5 downto 0) <= (others => '0'); 7964 8016 " 7965 ) 7966 ) 7967 *264 (Wire 8017 tm "HdlTextMgr" 8018 wrapOption 3 8019 visibleHeight 13000 8020 visibleWidth 13000 8021 ) 8022 ) 8023 ) 8024 ] 8025 shape (Rectangle 8026 uid 14347,0 8027 va (VaSet 8028 vasetType 1 8029 fg "65535,65535,37120" 8030 lineColor "0,0,32768" 8031 lineWidth 2 8032 ) 8033 xt "66000,153000,70000,156000" 8034 ) 8035 oxt "0,0,8000,10000" 8036 ttg (MlTextGroup 8037 uid 14348,0 8038 ps "CenterOffsetStrategy" 8039 stg "VerticalLayoutStrategy" 8040 textVec [ 8041 *269 (Text 8042 uid 14349,0 8043 va (VaSet 8044 font "Arial,8,1" 8045 ) 8046 xt "68150,153000,69850,154000" 8047 st "eb1" 8048 blo "68150,153800" 8049 tm "HdlTextNameMgr" 8050 ) 8051 *270 (Text 8052 uid 14350,0 8053 va (VaSet 8054 font "Arial,8,1" 8055 ) 8056 xt "68150,154000,68950,155000" 8057 st "7" 8058 blo "68150,154800" 8059 tm "HdlTextNumberMgr" 8060 ) 8061 ] 8062 ) 8063 viewicon (ZoomableIcon 8064 uid 14351,0 8065 sl 0 8066 va (VaSet 8067 vasetType 1 8068 fg "49152,49152,49152" 8069 ) 8070 xt "66250,154250,67750,155750" 8071 iconName "TextFile.png" 8072 iconMaskName "TextFile.msk" 8073 ftype 21 8074 ) 8075 viewiconposition 0 8076 ) 8077 *271 (Net 8078 uid 15173,0 8079 decl (Decl 8080 n "led" 8081 t "std_logic_vector" 8082 b "(7 DOWNTO 0)" 8083 posAdd 0 8084 o 81 8085 suid 215,0 8086 i "(OTHERS => '0')" 8087 ) 8088 declText (MLText 8089 uid 15174,0 8090 va (VaSet 8091 font "Courier New,8,0" 8092 ) 8093 xt "39000,66400,77000,67200" 8094 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8095 ) 8096 ) 8097 *272 (Wire 7968 8098 uid 245,0 7969 8099 shape (OrthoPolyLine … … 7979 8109 ) 7980 8110 start &27 7981 end &6 68111 end &67 7982 8112 ss 0 7983 8113 sat 32 … … 8002 8132 ) 8003 8133 ) 8004 on &8 78005 ) 8006 *2 65(Wire8134 on &88 8135 ) 8136 *273 (Wire 8007 8137 uid 277,0 8008 8138 shape (OrthoPolyLine … … 8019 8149 ) 8020 8150 start &17 8021 end &6 78151 end &68 8022 8152 sat 32 8023 8153 eat 2 … … 8040 8170 ) 8041 8171 ) 8042 on &7 18043 ) 8044 *2 66(Wire8172 on &72 8173 ) 8174 *274 (Wire 8045 8175 uid 285,0 8046 8176 shape (OrthoPolyLine … … 8057 8187 ) 8058 8188 start &18 8059 end &6 78189 end &68 8060 8190 sat 32 8061 8191 eat 2 … … 8078 8208 ) 8079 8209 ) 8080 on &7 28081 ) 8082 *2 67(Wire8210 on &73 8211 ) 8212 *275 (Wire 8083 8213 uid 362,0 8084 8214 shape (OrthoPolyLine … … 8093 8223 ] 8094 8224 ) 8095 start &9 58225 start &96 8096 8226 end &16 8097 8227 sat 32 … … 8116 8246 ) 8117 8247 ) 8118 on &9 68119 ) 8120 *2 68(Wire8248 on &97 8249 ) 8250 *276 (Wire 8121 8251 uid 418,0 8122 8252 shape (OrthoPolyLine … … 8132 8262 ) 8133 8263 start &13 8134 end &7 38264 end &74 8135 8265 sat 32 8136 8266 eat 32 … … 8154 8284 ) 8155 8285 ) 8156 on &14 88157 ) 8158 *2 69(Wire8286 on &149 8287 ) 8288 *277 (Wire 8159 8289 uid 426,0 8160 8290 shape (OrthoPolyLine … … 8171 8301 ) 8172 8302 start &19 8173 end &7 48303 end &75 8174 8304 sat 32 8175 8305 eat 32 … … 8194 8324 ) 8195 8325 ) 8196 on &14 68197 ) 8198 *27 0(Wire8326 on &147 8327 ) 8328 *278 (Wire 8199 8329 uid 434,0 8200 8330 shape (OrthoPolyLine … … 8210 8340 ) 8211 8341 start &20 8212 end &7 58342 end &76 8213 8343 sat 32 8214 8344 eat 32 … … 8232 8362 ) 8233 8363 ) 8234 on &15 28235 ) 8236 *27 1(Wire8364 on &153 8365 ) 8366 *279 (Wire 8237 8367 uid 442,0 8238 8368 shape (OrthoPolyLine … … 8249 8379 ) 8250 8380 start &21 8251 end &7 68381 end &77 8252 8382 sat 32 8253 8383 eat 32 … … 8272 8402 ) 8273 8403 ) 8274 on &14 78275 ) 8276 *2 72(Wire8404 on &148 8405 ) 8406 *280 (Wire 8277 8407 uid 450,0 8278 8408 shape (OrthoPolyLine … … 8287 8417 ] 8288 8418 ) 8289 start &7 78419 start &78 8290 8420 end &22 8291 8421 sat 32 … … 8310 8440 ) 8311 8441 ) 8312 on &15 18313 ) 8314 *2 73(Wire8442 on &152 8443 ) 8444 *281 (Wire 8315 8445 uid 458,0 8316 8446 shape (OrthoPolyLine … … 8326 8456 ) 8327 8457 start &23 8328 end &788329 sat 328330 eat 328331 stc 08332 st 08333 sf 18334 si 08335 tg (WTG8336 uid 462,08337 ps "ConnStartEndStrategy"8338 stg "STSignalDisplayStrategy"8339 f (Text8340 uid 463,08341 va (VaSet8342 isHidden 18343 )8344 xt "82000,71000,84700,72000"8345 st "W_RD"8346 blo "82000,71800"8347 tm "WireNameMgr"8348 )8349 )8350 on &1498351 )8352 *274 (Wire8353 uid 466,08354 shape (OrthoPolyLine8355 uid 467,08356 va (VaSet8357 vasetType 38358 )8359 xt "80750,73000,111000,73000"8360 pts [8361 "80750,73000"8362 "111000,73000"8363 ]8364 )8365 start &248366 8458 end &79 8367 8459 sat 32 … … 8372 8464 si 0 8373 8465 tg (WTG 8466 uid 462,0 8467 ps "ConnStartEndStrategy" 8468 stg "STSignalDisplayStrategy" 8469 f (Text 8470 uid 463,0 8471 va (VaSet 8472 isHidden 1 8473 ) 8474 xt "82000,71000,84700,72000" 8475 st "W_RD" 8476 blo "82000,71800" 8477 tm "WireNameMgr" 8478 ) 8479 ) 8480 on &150 8481 ) 8482 *282 (Wire 8483 uid 466,0 8484 shape (OrthoPolyLine 8485 uid 467,0 8486 va (VaSet 8487 vasetType 3 8488 ) 8489 xt "80750,73000,111000,73000" 8490 pts [ 8491 "80750,73000" 8492 "111000,73000" 8493 ] 8494 ) 8495 start &24 8496 end &80 8497 sat 32 8498 eat 32 8499 stc 0 8500 st 0 8501 sf 1 8502 si 0 8503 tg (WTG 8374 8504 uid 470,0 8375 8505 ps "ConnStartEndStrategy" … … 8386 8516 ) 8387 8517 ) 8388 on &15 08389 ) 8390 *2 75(Wire8518 on &151 8519 ) 8520 *283 (Wire 8391 8521 uid 1467,0 8392 8522 shape (OrthoPolyLine … … 8401 8531 ] 8402 8532 ) 8403 start & 998533 start &100 8404 8534 end &28 8405 8535 sat 2 … … 8422 8552 ) 8423 8553 ) 8424 on &8 08425 ) 8426 *2 76(Wire8554 on &81 8555 ) 8556 *284 (Wire 8427 8557 uid 1730,0 8428 8558 shape (OrthoPolyLine … … 8438 8568 ] 8439 8569 ) 8440 start &9 78570 start &98 8441 8571 end &29 8442 8572 sat 32 … … 8462 8592 ) 8463 8593 ) 8464 on &9 88465 ) 8466 *2 77(Wire8594 on &99 8595 ) 8596 *285 (Wire 8467 8597 uid 1833,0 8468 8598 shape (OrthoPolyLine … … 8478 8608 ] 8479 8609 ) 8480 start &18 58481 end &12 78610 start &186 8611 end &128 8482 8612 sat 2 8483 8613 eat 32 … … 8502 8632 ) 8503 8633 ) 8504 on &12 88505 ) 8506 *2 78(Wire8634 on &129 8635 ) 8636 *286 (Wire 8507 8637 uid 1841,0 8508 8638 shape (OrthoPolyLine … … 8518 8648 ) 8519 8649 start &31 8520 end &1 298650 end &130 8521 8651 sat 32 8522 8652 eat 32 … … 8540 8670 ) 8541 8671 ) 8542 on &13 08543 ) 8544 *2 79(Wire8672 on &131 8673 ) 8674 *287 (Wire 8545 8675 uid 1865,0 8546 8676 shape (OrthoPolyLine … … 8555 8685 ] 8556 8686 ) 8557 start &1 198687 start &120 8558 8688 end &32 8559 8689 sat 32 … … 8578 8708 ) 8579 8709 ) 8580 on &12 38581 ) 8582 *28 0(Wire8710 on &124 8711 ) 8712 *288 (Wire 8583 8713 uid 1873,0 8584 8714 shape (OrthoPolyLine … … 8593 8723 ] 8594 8724 ) 8595 start &12 08725 start &121 8596 8726 end &33 8597 8727 sat 32 … … 8616 8746 ) 8617 8747 ) 8618 on &12 48619 ) 8620 *28 1(Wire8748 on &125 8749 ) 8750 *289 (Wire 8621 8751 uid 1881,0 8622 8752 shape (OrthoPolyLine … … 8631 8761 ] 8632 8762 ) 8633 start &12 18763 start &122 8634 8764 end &34 8635 8765 sat 32 … … 8654 8784 ) 8655 8785 ) 8656 on &12 58657 ) 8658 *2 82(Wire8786 on &126 8787 ) 8788 *290 (Wire 8659 8789 uid 1889,0 8660 8790 shape (OrthoPolyLine … … 8669 8799 ] 8670 8800 ) 8671 start &12 28801 start &123 8672 8802 end &35 8673 8803 sat 32 … … 8692 8822 ) 8693 8823 ) 8694 on &12 68695 ) 8696 *2 83(Wire8824 on &127 8825 ) 8826 *291 (Wire 8697 8827 uid 2409,0 8698 8828 shape (OrthoPolyLine … … 8708 8838 ) 8709 8839 start &36 8710 end &8 28840 end &83 8711 8841 sat 32 8712 8842 eat 32 … … 8730 8860 ) 8731 8861 ) 8732 on &8 18733 ) 8734 *2 84(Wire8862 on &82 8863 ) 8864 *292 (Wire 8735 8865 uid 2423,0 8736 8866 shape (OrthoPolyLine … … 8746 8876 ) 8747 8877 start &37 8748 end &11 18878 end &112 8749 8879 sat 32 8750 8880 eat 1 … … 8768 8898 ) 8769 8899 ) 8770 on &8 38771 ) 8772 *2 85(Wire8900 on &84 8901 ) 8902 *293 (Wire 8773 8903 uid 3009,0 8774 8904 shape (OrthoPolyLine … … 8784 8914 ) 8785 8915 start &39 8786 end &14 48916 end &145 8787 8917 sat 32 8788 8918 eat 32 … … 8806 8936 ) 8807 8937 ) 8808 on &14 58809 ) 8810 *2 86(Wire8938 on &146 8939 ) 8940 *294 (Wire 8811 8941 uid 3015,0 8812 8942 shape (OrthoPolyLine … … 8822 8952 ) 8823 8953 start &41 8824 end &15 38954 end &154 8825 8955 sat 32 8826 8956 eat 32 … … 8844 8974 ) 8845 8975 ) 8846 on &15 68847 ) 8848 *2 87(Wire8976 on &157 8977 ) 8978 *295 (Wire 8849 8979 uid 3021,0 8850 8980 shape (OrthoPolyLine … … 8861 8991 ) 8862 8992 start &40 8863 end &13 28993 end &133 8864 8994 sat 32 8865 8995 eat 1 … … 8882 9012 ) 8883 9013 ) 8884 on &8 48885 ) 8886 *2 88(Wire9014 on &85 9015 ) 9016 *296 (Wire 8887 9017 uid 3027,0 8888 9018 shape (OrthoPolyLine … … 8897 9027 ] 8898 9028 ) 8899 start &19 58900 end &13 19029 start &196 9030 end &132 8901 9031 ss 0 8902 9032 sat 32 … … 8921 9051 ) 8922 9052 ) 8923 on &8 58924 ) 8925 *2 89(Wire9053 on &86 9054 ) 9055 *297 (Wire 8926 9056 uid 3218,0 8927 9057 shape (OrthoPolyLine … … 8936 9066 ] 8937 9067 ) 8938 start &6 59068 start &66 8939 9069 end &15 8940 9070 sat 32 … … 8959 9089 ) 8960 9090 ) 8961 on &8 88962 ) 8963 *29 0(Wire9091 on &89 9092 ) 9093 *298 (Wire 8964 9094 uid 3260,0 8965 9095 shape (OrthoPolyLine … … 8975 9105 ] 8976 9106 ) 8977 start &8 68978 end & 899107 start &87 9108 end &90 8979 9109 sat 32 8980 9110 eat 2 … … 8999 9129 ) 9000 9130 ) 9001 on &9 39002 ) 9003 *29 1(Wire9131 on &94 9132 ) 9133 *299 (Wire 9004 9134 uid 3270,0 9005 9135 shape (OrthoPolyLine … … 9016 9146 ] 9017 9147 ) 9018 start &20 89019 end & 899148 start &209 9149 end &90 9020 9150 sat 32 9021 9151 eat 1 … … 9037 9167 ) 9038 9168 ) 9039 on &9 49040 ) 9041 * 292(Wire9169 on &95 9170 ) 9171 *300 (Wire 9042 9172 uid 3318,0 9043 9173 shape (OrthoPolyLine … … 9053 9183 ] 9054 9184 ) 9055 start &10 39056 end & 999185 start &104 9186 end &100 9057 9187 sat 32 9058 9188 eat 1 … … 9077 9207 ) 9078 9208 ) 9079 on &10 79080 ) 9081 * 293(Wire9209 on &108 9210 ) 9211 *301 (Wire 9082 9212 uid 3352,0 9083 9213 shape (OrthoPolyLine … … 9093 9223 ] 9094 9224 ) 9095 start &10 49096 end & 999225 start &105 9226 end &100 9097 9227 sat 32 9098 9228 eat 1 … … 9117 9247 ) 9118 9248 ) 9119 on &10 89120 ) 9121 * 294(Wire9249 on &109 9250 ) 9251 *302 (Wire 9122 9252 uid 3360,0 9123 9253 shape (OrthoPolyLine … … 9133 9263 ] 9134 9264 ) 9135 start &10 59136 end & 999265 start &106 9266 end &100 9137 9267 sat 32 9138 9268 eat 1 … … 9157 9287 ) 9158 9288 ) 9159 on &1 099160 ) 9161 * 295(Wire9289 on &110 9290 ) 9291 *303 (Wire 9162 9292 uid 3368,0 9163 9293 shape (OrthoPolyLine … … 9173 9303 ] 9174 9304 ) 9175 start &10 69176 end & 999305 start &107 9306 end &100 9177 9307 sat 32 9178 9308 eat 1 … … 9197 9327 ) 9198 9328 ) 9199 on &11 09200 ) 9201 * 296(Wire9329 on &111 9330 ) 9331 *304 (Wire 9202 9332 uid 3430,0 9203 9333 shape (OrthoPolyLine … … 9212 9342 ] 9213 9343 ) 9214 start &17 59215 end &11 19344 start &176 9345 end &112 9216 9346 sat 32 9217 9347 eat 2 … … 9235 9365 ) 9236 9366 ) 9237 on &11 59238 ) 9239 * 297(Wire9367 on &116 9368 ) 9369 *305 (Wire 9240 9370 uid 3438,0 9241 9371 shape (OrthoPolyLine … … 9250 9380 ] 9251 9381 ) 9252 start &17 69253 end &11 19382 start &177 9383 end &112 9254 9384 sat 32 9255 9385 eat 2 … … 9273 9403 ) 9274 9404 ) 9275 on &11 69276 ) 9277 * 298(Wire9405 on &117 9406 ) 9407 *306 (Wire 9278 9408 uid 3446,0 9279 9409 shape (OrthoPolyLine … … 9288 9418 ] 9289 9419 ) 9290 start &17 79291 end &11 19420 start &178 9421 end &112 9292 9422 sat 32 9293 9423 eat 2 … … 9311 9441 ) 9312 9442 ) 9313 on &11 79314 ) 9315 * 299(Wire9443 on &118 9444 ) 9445 *307 (Wire 9316 9446 uid 3454,0 9317 9447 shape (OrthoPolyLine … … 9326 9456 ] 9327 9457 ) 9328 start &17 89329 end &11 19458 start &179 9459 end &112 9330 9460 sat 32 9331 9461 eat 2 … … 9349 9479 ) 9350 9480 ) 9351 on &11 89352 ) 9353 *30 0(Wire9481 on &119 9482 ) 9483 *308 (Wire 9354 9484 uid 3574,0 9355 9485 shape (OrthoPolyLine … … 9364 9494 ] 9365 9495 ) 9366 start &13 69367 end &13 29496 start &137 9497 end &133 9368 9498 sat 32 9369 9499 eat 2 … … 9387 9517 ) 9388 9518 ) 9389 on &14 09390 ) 9391 *30 1(Wire9519 on &141 9520 ) 9521 *309 (Wire 9392 9522 uid 3582,0 9393 9523 shape (OrthoPolyLine … … 9402 9532 ] 9403 9533 ) 9404 start &13 79405 end &13 29534 start &138 9535 end &133 9406 9536 sat 32 9407 9537 eat 2 … … 9425 9555 ) 9426 9556 ) 9427 on &14 19428 ) 9429 *3 02(Wire9557 on &142 9558 ) 9559 *310 (Wire 9430 9560 uid 3590,0 9431 9561 shape (OrthoPolyLine … … 9440 9570 ] 9441 9571 ) 9442 start &13 89443 end &13 29572 start &139 9573 end &133 9444 9574 sat 32 9445 9575 eat 2 … … 9463 9593 ) 9464 9594 ) 9465 on &14 29466 ) 9467 *3 03(Wire9595 on &143 9596 ) 9597 *311 (Wire 9468 9598 uid 3598,0 9469 9599 shape (OrthoPolyLine … … 9478 9608 ] 9479 9609 ) 9480 start &1 399481 end &13 29610 start &140 9611 end &133 9482 9612 sat 32 9483 9613 eat 2 … … 9501 9631 ) 9502 9632 ) 9503 on &14 39504 ) 9505 *3 04(Wire9633 on &144 9634 ) 9635 *312 (Wire 9506 9636 uid 3682,0 9507 9637 shape (OrthoPolyLine … … 9517 9647 ) 9518 9648 start &42 9519 end &15 59649 end &156 9520 9650 sat 32 9521 9651 eat 32 … … 9539 9669 ) 9540 9670 ) 9541 on &15 49542 ) 9543 *3 05(Wire9671 on &155 9672 ) 9673 *313 (Wire 9544 9674 uid 3778,0 9545 9675 shape (OrthoPolyLine … … 9554 9684 ] 9555 9685 ) 9556 start &16 19686 start &162 9557 9687 end &61 9558 9688 es 0 … … 9578 9708 ) 9579 9709 ) 9580 on &16 89581 ) 9582 *3 06(Wire9710 on &169 9711 ) 9712 *314 (Wire 9583 9713 uid 3786,0 9584 9714 shape (OrthoPolyLine … … 9593 9723 ] 9594 9724 ) 9595 start &16 29596 end &15 79725 start &163 9726 end &158 9597 9727 sat 32 9598 9728 eat 2 … … 9616 9746 ) 9617 9747 ) 9618 on &1 699619 ) 9620 *3 07(Wire9748 on &170 9749 ) 9750 *315 (Wire 9621 9751 uid 3794,0 9622 9752 shape (OrthoPolyLine … … 9631 9761 ] 9632 9762 ) 9633 start &16 39634 end &15 79763 start &164 9764 end &158 9635 9765 sat 32 9636 9766 eat 2 … … 9654 9784 ) 9655 9785 ) 9656 on &17 09657 ) 9658 *3 08(Wire9786 on &171 9787 ) 9788 *316 (Wire 9659 9789 uid 3802,0 9660 9790 shape (OrthoPolyLine … … 9667 9797 "139000,150000" 9668 9798 "136000,150000" 9669 ]9670 )9671 start &1649672 sat 329673 eat 169674 stc 09675 st 09676 sf 19677 si 09678 tg (WTG9679 uid 3806,09680 ps "ConnStartEndStrategy"9681 stg "STSignalDisplayStrategy"9682 f (Text9683 uid 3807,09684 va (VaSet9685 isHidden 19686 )9687 xt "136000,149000,141500,150000"9688 st "RS485_E_RE"9689 blo "136000,149800"9690 tm "WireNameMgr"9691 )9692 )9693 on &1719694 )9695 *309 (Wire9696 uid 3810,09697 shape (OrthoPolyLine9698 uid 3811,09699 va (VaSet9700 vasetType 39701 )9702 xt "134000,149000,137000,149000"9703 pts [9704 "137000,149000"9705 "134000,149000"9706 9799 ] 9707 9800 ) … … 9714 9807 si 0 9715 9808 tg (WTG 9809 uid 3806,0 9810 ps "ConnStartEndStrategy" 9811 stg "STSignalDisplayStrategy" 9812 f (Text 9813 uid 3807,0 9814 va (VaSet 9815 isHidden 1 9816 ) 9817 xt "136000,149000,141500,150000" 9818 st "RS485_E_RE" 9819 blo "136000,149800" 9820 tm "WireNameMgr" 9821 ) 9822 ) 9823 on &172 9824 ) 9825 *317 (Wire 9826 uid 3810,0 9827 shape (OrthoPolyLine 9828 uid 3811,0 9829 va (VaSet 9830 vasetType 3 9831 ) 9832 xt "134000,149000,137000,149000" 9833 pts [ 9834 "137000,149000" 9835 "134000,149000" 9836 ] 9837 ) 9838 start &166 9839 sat 32 9840 eat 16 9841 stc 0 9842 st 0 9843 sf 1 9844 si 0 9845 tg (WTG 9716 9846 uid 3814,0 9717 9847 ps "ConnStartEndStrategy" … … 9728 9858 ) 9729 9859 ) 9730 on &17 29731 ) 9732 *31 0(Wire9860 on &173 9861 ) 9862 *318 (Wire 9733 9863 uid 3834,0 9734 9864 shape (OrthoPolyLine … … 9743 9873 ] 9744 9874 ) 9745 start &16 79746 end &15 79875 start &168 9876 end &158 9747 9877 sat 32 9748 9878 eat 2 … … 9766 9896 ) 9767 9897 ) 9768 on &17 49769 ) 9770 *31 1(Wire9898 on &175 9899 ) 9900 *319 (Wire 9771 9901 uid 4942,0 9772 9902 shape (OrthoPolyLine … … 9776 9906 lineWidth 2 9777 9907 ) 9778 xt " 80750,120000,111000,120000"9779 pts [ 9780 " 80750,120000"9781 " 111000,120000"9782 ] 9783 ) 9784 start & 149785 end &1 799786 sat 329908 xt "70000,154000,72000,154000" 9909 pts [ 9910 "70000,154000" 9911 "72000,154000" 9912 ] 9913 ) 9914 start &267 9915 end &180 9916 sat 2 9787 9917 eat 32 9788 9918 sty 1 … … 9800 9930 isHidden 1 9801 9931 ) 9802 xt " 82750,117000,84650,118000"9932 xt "71750,151000,73650,152000" 9803 9933 st "D_T" 9804 blo " 82750,117800"9805 tm "WireNameMgr" 9806 ) 9807 ) 9808 on &18 09809 ) 9810 *3 12(Wire9934 blo "71750,151800" 9935 tm "WireNameMgr" 9936 ) 9937 ) 9938 on &181 9939 ) 9940 *320 (Wire 9811 9941 uid 6431,0 9812 9942 shape (OrthoPolyLine … … 9822 9952 ) 9823 9953 start &43 9824 end &16 69954 end &167 9825 9955 sat 32 9826 9956 eat 32 … … 9844 9974 ) 9845 9975 ) 9846 on &17 39847 ) 9848 *3 13(Wire9976 on &174 9977 ) 9978 *321 (Wire 9849 9979 uid 7144,0 9850 9980 shape (OrthoPolyLine … … 9860 9990 ] 9861 9991 ) 9862 start &2 299863 end &1 899992 start &230 9993 end &190 9864 9994 sat 2 9865 9995 eat 32 … … 9883 10013 ) 9884 10014 ) 9885 on &19 09886 ) 9887 *3 14(Wire10015 on &191 10016 ) 10017 *322 (Wire 9888 10018 uid 7477,0 9889 10019 shape (OrthoPolyLine … … 9899 10029 ) 9900 10030 start &38 9901 end &19 310031 end &194 9902 10032 es 0 9903 10033 sat 32 … … 9920 10050 ) 9921 10051 ) 9922 on &19 19923 ) 9924 *3 15(Wire10052 on &192 10053 ) 10054 *323 (Wire 9925 10055 uid 8853,0 9926 10056 shape (OrthoPolyLine … … 9939 10069 ) 9940 10070 start &30 9941 end &18 510071 end &186 9942 10072 sat 32 9943 10073 eat 1 … … 9960 10090 ) 9961 10091 ) 9962 on &20 59963 ) 9964 *3 16(Wire10092 on &206 10093 ) 10094 *324 (Wire 9965 10095 uid 9502,0 9966 10096 shape (OrthoPolyLine … … 9995 10125 ) 9996 10126 ) 9997 on &20 69998 ) 9999 *3 17(Wire10127 on &207 10128 ) 10129 *325 (Wire 10000 10130 uid 10034,0 10001 10131 shape (OrthoPolyLine … … 10012 10142 ) 10013 10143 start &25 10014 end &21 310144 end &214 10015 10145 sat 32 10016 10146 eat 32 … … 10033 10163 ) 10034 10164 ) 10035 on &22 510036 ) 10037 *3 18(Wire10165 on &226 10166 ) 10167 *326 (Wire 10038 10168 uid 10052,0 10039 10169 shape (OrthoPolyLine … … 10049 10179 ) 10050 10180 start &44 10051 end &21 110181 end &212 10052 10182 sat 32 10053 10183 eat 32 … … 10070 10200 ) 10071 10201 ) 10072 on &22 610073 ) 10074 *3 19(Wire10202 on &227 10203 ) 10204 *327 (Wire 10075 10205 uid 10302,0 10076 10206 shape (OrthoPolyLine … … 10086 10216 ] 10087 10217 ) 10088 start &2 2910089 end &22 710218 start &230 10219 end &228 10090 10220 sat 2 10091 10221 eat 32 … … 10109 10239 ) 10110 10240 ) 10111 on &22 810112 ) 10113 *32 0(Wire10241 on &229 10242 ) 10243 *328 (Wire 10114 10244 uid 10498,0 10115 10245 shape (OrthoPolyLine … … 10144 10274 ) 10145 10275 ) 10146 on &23 310147 ) 10148 *32 1(Wire10276 on &234 10277 ) 10278 *329 (Wire 10149 10279 uid 10506,0 10150 10280 shape (OrthoPolyLine … … 10179 10309 ) 10180 10310 ) 10181 on &23 410182 ) 10183 *3 22(Wire10311 on &235 10312 ) 10313 *330 (Wire 10184 10314 uid 10514,0 10185 10315 shape (OrthoPolyLine … … 10214 10344 ) 10215 10345 ) 10216 on &23 510217 ) 10218 *3 23(Wire10346 on &236 10347 ) 10348 *331 (Wire 10219 10349 uid 10522,0 10220 10350 shape (OrthoPolyLine … … 10249 10379 ) 10250 10380 ) 10251 on &23 610252 ) 10253 *3 24(Wire10381 on &237 10382 ) 10383 *332 (Wire 10254 10384 uid 10546,0 10255 10385 shape (OrthoPolyLine … … 10284 10414 ) 10285 10415 ) 10286 on &23 710287 ) 10288 *3 25(Wire10416 on &238 10417 ) 10418 *333 (Wire 10289 10419 uid 10554,0 10290 10420 shape (OrthoPolyLine … … 10319 10449 ) 10320 10450 ) 10321 on &23 810322 ) 10323 *3 26(Wire10451 on &239 10452 ) 10453 *334 (Wire 10324 10454 uid 10562,0 10325 10455 shape (OrthoPolyLine … … 10354 10484 ) 10355 10485 ) 10356 on &2 3910357 ) 10358 *3 27(Wire10486 on &240 10487 ) 10488 *335 (Wire 10359 10489 uid 10570,0 10360 10490 shape (OrthoPolyLine … … 10389 10519 ) 10390 10520 ) 10391 on &24 010392 ) 10393 *3 28(Wire10521 on &241 10522 ) 10523 *336 (Wire 10394 10524 uid 10578,0 10395 10525 shape (OrthoPolyLine … … 10424 10554 ) 10425 10555 ) 10426 on &24 110427 ) 10428 *3 29(Wire10556 on &242 10557 ) 10558 *337 (Wire 10429 10559 uid 10586,0 10430 10560 shape (OrthoPolyLine … … 10459 10589 ) 10460 10590 ) 10461 on &24 210462 ) 10463 *33 0(Wire10591 on &243 10592 ) 10593 *338 (Wire 10464 10594 uid 10594,0 10465 10595 shape (OrthoPolyLine … … 10494 10624 ) 10495 10625 ) 10496 on &24 310497 ) 10498 *33 1(Wire10626 on &244 10627 ) 10628 *339 (Wire 10499 10629 uid 11096,0 10500 10630 shape (OrthoPolyLine … … 10509 10639 ] 10510 10640 ) 10511 start &24 410512 end &15 710641 start &245 10642 end &158 10513 10643 sat 32 10514 10644 eat 1 … … 10531 10661 ) 10532 10662 ) 10533 on &24 510534 ) 10535 *3 32(Wire10663 on &246 10664 ) 10665 *340 (Wire 10536 10666 uid 11110,0 10537 10667 shape (OrthoPolyLine … … 10546 10676 ] 10547 10677 ) 10548 start &15 710549 end &24 610678 start &158 10679 end &247 10550 10680 sat 2 10551 10681 eat 32 … … 10568 10698 ) 10569 10699 ) 10570 on &24 710571 ) 10572 *3 33(Wire10700 on &248 10701 ) 10702 *341 (Wire 10573 10703 uid 11514,0 10574 10704 shape (OrthoPolyLine … … 10583 10713 ] 10584 10714 ) 10585 start &24 810715 start &249 10586 10716 sat 32 10587 10717 eat 16 … … 10604 10734 ) 10605 10735 ) 10606 on &2 4910607 ) 10608 *3 34(Wire10736 on &250 10737 ) 10738 *342 (Wire 10609 10739 uid 11528,0 10610 10740 shape (OrthoPolyLine … … 10619 10749 ] 10620 10750 ) 10621 end &25 110751 end &252 10622 10752 sat 16 10623 10753 eat 32 … … 10640 10770 ) 10641 10771 ) 10642 on &25 010643 ) 10644 *3 35(Wire10772 on &251 10773 ) 10774 *343 (Wire 10645 10775 uid 12320,0 10646 10776 shape (OrthoPolyLine … … 10656 10786 ) 10657 10787 start &57 10658 end &25 210788 end &253 10659 10789 sat 32 10660 10790 eat 32 … … 10678 10808 ) 10679 10809 ) 10680 on &25 310681 ) 10682 *3 36(Wire10810 on &254 10811 ) 10812 *344 (Wire 10683 10813 uid 12545,0 10684 10814 shape (OrthoPolyLine … … 10694 10824 ) 10695 10825 start &58 10696 end &25 410826 end &255 10697 10827 ss 0 10698 10828 sat 32 … … 10716 10846 ) 10717 10847 ) 10718 on &25 710719 ) 10720 *3 37(Wire10848 on &258 10849 ) 10850 *345 (Wire 10721 10851 uid 12559,0 10722 10852 shape (OrthoPolyLine … … 10732 10862 ) 10733 10863 start &60 10734 end &25510735 sat 3210736 eat 3210737 st 010738 sf 110739 si 010740 tg (WTG10741 uid 12563,010742 ps "ConnStartEndStrategy"10743 stg "STSignalDisplayStrategy"10744 f (Text10745 uid 12564,010746 va (VaSet10747 isHidden 110748 )10749 xt "83000,142000,88100,143000"10750 st "GREEN_LED"10751 blo "83000,142800"10752 tm "WireNameMgr"10753 )10754 )10755 on &25810756 )10757 *338 (Wire10758 uid 12573,010759 shape (OrthoPolyLine10760 uid 12574,010761 va (VaSet10762 vasetType 310763 )10764 xt "80750,142000,87000,143000"10765 pts [10766 "80750,142000"10767 "87000,143000"10768 ]10769 )10770 start &5910771 10864 end &256 10772 10865 sat 32 … … 10776 10869 si 0 10777 10870 tg (WTG 10871 uid 12563,0 10872 ps "ConnStartEndStrategy" 10873 stg "STSignalDisplayStrategy" 10874 f (Text 10875 uid 12564,0 10876 va (VaSet 10877 isHidden 1 10878 ) 10879 xt "83000,142000,88100,143000" 10880 st "GREEN_LED" 10881 blo "83000,142800" 10882 tm "WireNameMgr" 10883 ) 10884 ) 10885 on &259 10886 ) 10887 *346 (Wire 10888 uid 12573,0 10889 shape (OrthoPolyLine 10890 uid 12574,0 10891 va (VaSet 10892 vasetType 3 10893 ) 10894 xt "80750,142000,87000,143000" 10895 pts [ 10896 "80750,142000" 10897 "87000,143000" 10898 ] 10899 ) 10900 start &59 10901 end &257 10902 sat 32 10903 eat 32 10904 st 0 10905 sf 1 10906 si 0 10907 tg (WTG 10778 10908 uid 12577,0 10779 10909 ps "ConnStartEndStrategy" … … 10790 10920 ) 10791 10921 ) 10792 on &2 5910793 ) 10794 *3 39(Wire10922 on &260 10923 ) 10924 *347 (Wire 10795 10925 uid 13522,0 10796 10926 shape (OrthoPolyLine … … 10800 10930 lineWidth 2 10801 10931 ) 10802 xt "1 12000,148000,120000,148000"10803 pts [ 10804 "1 12000,148000"10805 " 120000,148000"10806 ] 10807 ) 10808 start &26 010809 end & 22910932 xt "12000,81000,24000,81000" 10933 pts [ 10934 "12000,81000" 10935 "24000,81000" 10936 ] 10937 ) 10938 start &261 10939 end &68 10810 10940 sat 32 10811 10941 eat 1 … … 10821 10951 uid 13527,0 10822 10952 va (VaSet 10823 isHidden 1 10824 ) 10825 xt "114000,147000,121900,148000" 10826 st "POSITION_ID : (5:0)" 10827 blo "114000,147800" 10828 tm "WireNameMgr" 10829 ) 10830 ) 10831 on &261 10832 ) 10833 *340 (Wire 10953 ) 10954 xt "14000,80000,18700,81000" 10955 st "LINE : (5:0)" 10956 blo "14000,80800" 10957 tm "WireNameMgr" 10958 ) 10959 ) 10960 on &262 10961 ) 10962 *348 (Wire 10834 10963 uid 13538,0 10835 10964 shape (OrthoPolyLine … … 10844 10973 ] 10845 10974 ) 10846 end &2 2910975 end &230 10847 10976 sat 16 10848 10977 eat 1 … … 10864 10993 ) 10865 10994 ) 10866 on &24 310867 ) 10868 *34 1(Wire10995 on &244 10996 ) 10997 *349 (Wire 10869 10998 uid 13546,0 10870 10999 shape (OrthoPolyLine … … 10879 11008 ] 10880 11009 ) 10881 end &2 2911010 end &230 10882 11011 sat 16 10883 11012 eat 1 … … 10899 11028 ) 10900 11029 ) 10901 on &24 210902 ) 10903 *3 42(Wire11030 on &243 11031 ) 11032 *350 (Wire 10904 11033 uid 13554,0 10905 11034 shape (OrthoPolyLine … … 10914 11043 ] 10915 11044 ) 10916 end &2 2911045 end &230 10917 11046 sat 16 10918 11047 eat 1 … … 10934 11063 ) 10935 11064 ) 10936 on &24 110937 ) 10938 *3 43(Wire11065 on &242 11066 ) 11067 *351 (Wire 10939 11068 uid 13570,0 10940 11069 shape (OrthoPolyLine … … 10949 11078 ] 10950 11079 ) 10951 end &2 2911080 end &230 10952 11081 sat 16 10953 11082 eat 1 … … 10969 11098 ) 10970 11099 ) 10971 on &25 310972 ) 10973 *3 44(Wire11100 on &254 11101 ) 11102 *352 (Wire 10974 11103 uid 13578,0 10975 11104 shape (OrthoPolyLine … … 10985 11114 ] 10986 11115 ) 10987 end &2 2911116 end &230 10988 11117 sat 16 10989 11118 eat 1 … … 11006 11135 ) 11007 11136 ) 11008 on &20 511009 ) 11010 *3 45(Wire11137 on &206 11138 ) 11139 *353 (Wire 11011 11140 uid 13610,0 11012 11141 shape (OrthoPolyLine … … 11021 11150 ] 11022 11151 ) 11023 start &18 111024 end &2 2911152 start &182 11153 end &230 11025 11154 sat 32 11026 11155 eat 1 … … 11043 11172 ) 11044 11173 ) 11045 on &18 211046 ) 11047 *3 46(Wire11174 on &183 11175 ) 11176 *354 (Wire 11048 11177 uid 13618,0 11049 11178 shape (OrthoPolyLine … … 11059 11188 ] 11060 11189 ) 11061 start &2 2911062 end &18 311190 start &230 11191 end &184 11063 11192 sat 2 11064 11193 eat 32 … … 11082 11211 ) 11083 11212 ) 11084 on &18 411085 ) 11086 *3 47(Wire11213 on &185 11214 ) 11215 *355 (Wire 11087 11216 uid 13634,0 11088 11217 shape (OrthoPolyLine … … 11097 11226 ] 11098 11227 ) 11099 start &26 211100 end &2 2911228 start &263 11229 end &230 11101 11230 sat 32 11102 11231 eat 1 … … 11119 11248 ) 11120 11249 ) 11121 on &26 311122 ) 11123 *3 48(Wire11250 on &264 11251 ) 11252 *356 (Wire 11124 11253 uid 13650,0 11125 11254 shape (OrthoPolyLine … … 11134 11263 ] 11135 11264 ) 11136 end &2 2911265 end &230 11137 11266 sat 16 11138 11267 eat 1 … … 11154 11283 ) 11155 11284 ) 11156 on &2 4911157 ) 11158 *3 49(Wire11285 on &250 11286 ) 11287 *357 (Wire 11159 11288 uid 13658,0 11160 11289 shape (OrthoPolyLine … … 11169 11298 ] 11170 11299 ) 11171 start &2 2911300 start &230 11172 11301 sat 2 11173 11302 eat 16 … … 11189 11318 ) 11190 11319 ) 11191 on &17 211192 ) 11193 *35 0(Wire11320 on &173 11321 ) 11322 *358 (Wire 11194 11323 uid 13666,0 11195 11324 shape (OrthoPolyLine … … 11204 11333 ] 11205 11334 ) 11206 start &2 2911335 start &230 11207 11336 sat 2 11208 11337 eat 16 … … 11224 11353 ) 11225 11354 ) 11226 on &171 11355 on &172 11356 ) 11357 *359 (Wire 11358 uid 14328,0 11359 shape (OrthoPolyLine 11360 uid 14329,0 11361 va (VaSet 11362 vasetType 3 11363 lineWidth 2 11364 ) 11365 xt "39000,139000,51250,139000" 11366 pts [ 11367 "39000,139000" 11368 "51250,139000" 11369 ] 11370 ) 11371 start &265 11372 end &62 11373 sat 32 11374 eat 32 11375 sty 1 11376 st 0 11377 sf 1 11378 si 0 11379 tg (WTG 11380 uid 14332,0 11381 ps "ConnStartEndStrategy" 11382 stg "STSignalDisplayStrategy" 11383 f (Text 11384 uid 14333,0 11385 va (VaSet 11386 isHidden 1 11387 ) 11388 xt "41000,138000,46500,139000" 11389 st "D_T_in : (1:0)" 11390 blo "41000,138800" 11391 tm "WireNameMgr" 11392 ) 11393 ) 11394 on &266 11395 ) 11396 *360 (Wire 11397 uid 15175,0 11398 shape (OrthoPolyLine 11399 uid 15176,0 11400 va (VaSet 11401 vasetType 3 11402 lineWidth 2 11403 ) 11404 xt "80750,120000,87000,120000" 11405 pts [ 11406 "80750,120000" 11407 "87000,120000" 11408 ] 11409 ) 11410 start &14 11411 sat 32 11412 eat 16 11413 sty 1 11414 st 0 11415 sf 1 11416 si 0 11417 tg (WTG 11418 uid 15179,0 11419 ps "ConnStartEndStrategy" 11420 stg "STSignalDisplayStrategy" 11421 f (Text 11422 uid 15180,0 11423 va (VaSet 11424 ) 11425 xt "82000,119000,86000,120000" 11426 st "led : (7:0)" 11427 blo "82000,119800" 11428 tm "WireNameMgr" 11429 ) 11430 ) 11431 on &271 11227 11432 ) 11228 11433 ] … … 11238 11443 color "26368,26368,26368" 11239 11444 ) 11240 packageList *3 51 (PackageList11445 packageList *361 (PackageList 11241 11446 uid 41,0 11242 11447 stg "VerticalLayoutStrategy" 11243 11448 textVec [ 11244 *3 52 (Text11449 *362 (Text 11245 11450 uid 42,0 11246 11451 va (VaSet … … 11251 11456 blo "0,800" 11252 11457 ) 11253 *3 53 (MLText11458 *363 (MLText 11254 11459 uid 43,0 11255 11460 va (VaSet … … 11272 11477 stg "VerticalLayoutStrategy" 11273 11478 textVec [ 11274 *3 54 (Text11479 *364 (Text 11275 11480 uid 45,0 11276 11481 va (VaSet … … 11282 11487 blo "20000,800" 11283 11488 ) 11284 *3 55 (Text11489 *365 (Text 11285 11490 uid 46,0 11286 11491 va (VaSet … … 11292 11497 blo "20000,1800" 11293 11498 ) 11294 *3 56 (MLText11499 *366 (MLText 11295 11500 uid 47,0 11296 11501 va (VaSet … … 11302 11507 tm "BdCompilerDirectivesTextMgr" 11303 11508 ) 11304 *3 57 (Text11509 *367 (Text 11305 11510 uid 48,0 11306 11511 va (VaSet … … 11312 11517 blo "20000,4800" 11313 11518 ) 11314 *3 58 (MLText11519 *368 (MLText 11315 11520 uid 49,0 11316 11521 va (VaSet … … 11320 11525 tm "BdCompilerDirectivesTextMgr" 11321 11526 ) 11322 *3 59 (Text11527 *369 (Text 11323 11528 uid 50,0 11324 11529 va (VaSet … … 11330 11535 blo "20000,5800" 11331 11536 ) 11332 *3 60 (MLText11537 *370 (MLText 11333 11538 uid 51,0 11334 11539 va (VaSet … … 11342 11547 ) 11343 11548 windowSize "0,0,1281,1024" 11344 viewArea " 70599,117336,126603,163521"11549 viewArea "47500,114900,130258,183150" 11345 11550 cachedDiagramExtent "0,0,699000,450107" 11346 11551 pageSetupInfo (PageSetupInfo … … 11355 11560 hasePageBreakOrigin 1 11356 11561 pageBreakOrigin "0,0" 11357 lastUid 1 4001,011562 lastUid 15337,0 11358 11563 defaultCommentText (CommentText 11359 11564 shape (Rectangle … … 11417 11622 stg "VerticalLayoutStrategy" 11418 11623 textVec [ 11419 *3 61 (Text11624 *371 (Text 11420 11625 va (VaSet 11421 11626 font "Arial,8,1" … … 11426 11631 tm "BdLibraryNameMgr" 11427 11632 ) 11428 *3 62 (Text11633 *372 (Text 11429 11634 va (VaSet 11430 11635 font "Arial,8,1" … … 11435 11640 tm "BlkNameMgr" 11436 11641 ) 11437 *3 63 (Text11642 *373 (Text 11438 11643 va (VaSet 11439 11644 font "Arial,8,1" … … 11486 11691 stg "VerticalLayoutStrategy" 11487 11692 textVec [ 11488 *3 64 (Text11693 *374 (Text 11489 11694 va (VaSet 11490 11695 font "Arial,8,1" … … 11494 11699 blo "550,4300" 11495 11700 ) 11496 *3 65 (Text11701 *375 (Text 11497 11702 va (VaSet 11498 11703 font "Arial,8,1" … … 11502 11707 blo "550,5300" 11503 11708 ) 11504 *3 66 (Text11709 *376 (Text 11505 11710 va (VaSet 11506 11711 font "Arial,8,1" … … 11551 11756 stg "VerticalLayoutStrategy" 11552 11757 textVec [ 11553 *3 67 (Text11758 *377 (Text 11554 11759 va (VaSet 11555 11760 font "Arial,8,1" … … 11560 11765 tm "BdLibraryNameMgr" 11561 11766 ) 11562 *3 68 (Text11767 *378 (Text 11563 11768 va (VaSet 11564 11769 font "Arial,8,1" … … 11569 11774 tm "CptNameMgr" 11570 11775 ) 11571 *3 69 (Text11776 *379 (Text 11572 11777 va (VaSet 11573 11778 font "Arial,8,1" … … 11623 11828 stg "VerticalLayoutStrategy" 11624 11829 textVec [ 11625 *3 70 (Text11830 *380 (Text 11626 11831 va (VaSet 11627 11832 font "Arial,8,1" … … 11631 11836 blo "500,4300" 11632 11837 ) 11633 *3 71 (Text11838 *381 (Text 11634 11839 va (VaSet 11635 11840 font "Arial,8,1" … … 11639 11844 blo "500,5300" 11640 11845 ) 11641 *3 72 (Text11846 *382 (Text 11642 11847 va (VaSet 11643 11848 font "Arial,8,1" … … 11684 11889 stg "VerticalLayoutStrategy" 11685 11890 textVec [ 11686 *3 73 (Text11891 *383 (Text 11687 11892 va (VaSet 11688 11893 font "Arial,8,1" … … 11692 11897 blo "50,4300" 11693 11898 ) 11694 *3 74 (Text11899 *384 (Text 11695 11900 va (VaSet 11696 11901 font "Arial,8,1" … … 11700 11905 blo "50,5300" 11701 11906 ) 11702 *3 75 (Text11907 *385 (Text 11703 11908 va (VaSet 11704 11909 font "Arial,8,1" … … 11741 11946 stg "VerticalLayoutStrategy" 11742 11947 textVec [ 11743 *3 76 (Text11948 *386 (Text 11744 11949 va (VaSet 11745 11950 font "Arial,8,1" … … 11750 11955 tm "HdlTextNameMgr" 11751 11956 ) 11752 *3 77 (Text11957 *387 (Text 11753 11958 va (VaSet 11754 11959 font "Arial,8,1" … … 12153 12358 stg "VerticalLayoutStrategy" 12154 12359 textVec [ 12155 *3 78 (Text12360 *388 (Text 12156 12361 va (VaSet 12157 12362 font "Arial,8,1" … … 12161 12366 blo "14100,20800" 12162 12367 ) 12163 *3 79 (MLText12368 *389 (MLText 12164 12369 va (VaSet 12165 12370 ) … … 12213 12418 stg "VerticalLayoutStrategy" 12214 12419 textVec [ 12215 *3 80 (Text12420 *390 (Text 12216 12421 va (VaSet 12217 12422 font "Arial,8,1" … … 12221 12426 blo "14100,20800" 12222 12427 ) 12223 *3 81 (MLText12428 *391 (MLText 12224 12429 va (VaSet 12225 12430 ) … … 12339 12544 font "Arial,8,1" 12340 12545 ) 12341 xt "37000, 49400,44100,50400"12546 xt "37000,50200,44100,51200" 12342 12547 st "Diagram Signals:" 12343 blo "37000,5 0200"12548 blo "37000,51000" 12344 12549 ) 12345 12550 postUserLabel (Text … … 12365 12570 commonDM (CommonDM 12366 12571 ldm (LogicalDM 12367 suid 21 2,012572 suid 215,0 12368 12573 usingSuid 1 12369 emptyRow *3 82 (LEmptyRow12574 emptyRow *392 (LEmptyRow 12370 12575 ) 12371 12576 uid 54,0 12372 12577 optionalChildren [ 12373 *3 83 (RefLabelRowHdr12374 ) 12375 *3 84 (TitleRowHdr12376 ) 12377 *3 85 (FilterRowHdr12378 ) 12379 *3 86 (RefLabelColHdr12578 *393 (RefLabelRowHdr 12579 ) 12580 *394 (TitleRowHdr 12581 ) 12582 *395 (FilterRowHdr 12583 ) 12584 *396 (RefLabelColHdr 12380 12585 tm "RefLabelColHdrMgr" 12381 12586 ) 12382 *3 87 (RowExpandColHdr12587 *397 (RowExpandColHdr 12383 12588 tm "RowExpandColHdrMgr" 12384 12589 ) 12385 *3 88 (GroupColHdr12590 *398 (GroupColHdr 12386 12591 tm "GroupColHdrMgr" 12387 12592 ) 12388 *3 89 (NameColHdr12593 *399 (NameColHdr 12389 12594 tm "BlockDiagramNameColHdrMgr" 12390 12595 ) 12391 * 390 (ModeColHdr12596 *400 (ModeColHdr 12392 12597 tm "BlockDiagramModeColHdrMgr" 12393 12598 ) 12394 * 391 (TypeColHdr12599 *401 (TypeColHdr 12395 12600 tm "BlockDiagramTypeColHdrMgr" 12396 12601 ) 12397 * 392 (BoundsColHdr12602 *402 (BoundsColHdr 12398 12603 tm "BlockDiagramBoundsColHdrMgr" 12399 12604 ) 12400 * 393 (InitColHdr12605 *403 (InitColHdr 12401 12606 tm "BlockDiagramInitColHdrMgr" 12402 12607 ) 12403 * 394 (EolColHdr12608 *404 (EolColHdr 12404 12609 tm "BlockDiagramEolColHdrMgr" 12405 12610 ) 12406 * 395 (LeafLogPort12611 *405 (LeafLogPort 12407 12612 port (LogicalPort 12408 12613 m 4 … … 12419 12624 uid 327,0 12420 12625 ) 12421 * 396 (LeafLogPort12626 *406 (LeafLogPort 12422 12627 port (LogicalPort 12423 12628 m 4 … … 12432 12637 uid 329,0 12433 12638 ) 12434 * 397 (LeafLogPort12639 *407 (LeafLogPort 12435 12640 port (LogicalPort 12436 12641 m 4 … … 12444 12649 uid 1491,0 12445 12650 ) 12446 * 398 (LeafLogPort12651 *408 (LeafLogPort 12447 12652 port (LogicalPort 12448 12653 m 1 … … 12457 12662 uid 2435,0 12458 12663 ) 12459 * 399 (LeafLogPort12664 *409 (LeafLogPort 12460 12665 port (LogicalPort 12461 12666 m 4 … … 12470 12675 uid 2437,0 12471 12676 ) 12472 *4 00 (LeafLogPort12677 *410 (LeafLogPort 12473 12678 port (LogicalPort 12474 12679 m 4 … … 12483 12688 uid 3037,0 12484 12689 ) 12485 *4 01 (LeafLogPort12690 *411 (LeafLogPort 12486 12691 port (LogicalPort 12487 12692 m 1 … … 12495 12700 uid 3039,0 12496 12701 ) 12497 *4 02 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3663,0 13665 13898 ) 13666 *5 15(MRCItem13667 litem &4 3113899 *527 (MRCItem 13900 litem &441 13668 13901 pos 30 13669 13902 dimension 20 13670 13903 uid 3665,0 13671 13904 ) 13672 *5 16(MRCItem13673 litem &4 3213905 *528 (MRCItem 13906 litem &442 13674 13907 pos 31 13675 13908 dimension 20 13676 13909 uid 3667,0 13677 13910 ) 13678 *5 17(MRCItem13679 litem &4 3313911 *529 (MRCItem 13912 litem &443 13680 13913 pos 32 13681 13914 dimension 20 13682 13915 uid 3669,0 13683 13916 ) 13684 *5 18(MRCItem13685 litem &4 3413917 *530 (MRCItem 13918 litem &444 13686 13919 pos 33 13687 13920 dimension 20 13688 13921 uid 3697,0 13689 13922 ) 13690 *5 19(MRCItem13691 litem &4 3513923 *531 (MRCItem 13924 litem &445 13692 13925 pos 34 13693 13926 dimension 20 13694 13927 uid 3699,0 13695 13928 ) 13696 *5 20(MRCItem13697 litem &4 3613929 *532 (MRCItem 13930 litem &446 13698 13931 pos 35 13699 13932 dimension 20 13700 13933 uid 3887,0 13701 13934 ) 13702 *5 21(MRCItem13703 litem &4 3713935 *533 (MRCItem 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dimension 20 13898 14131 uid 12769,0 13899 14132 ) 13900 *5 54(MRCItem13901 litem &4 7014133 *566 (MRCItem 14134 litem &480 13902 14135 pos 75 13903 14136 dimension 20 13904 14137 uid 12771,0 13905 14138 ) 13906 *5 55(MRCItem13907 litem &4 7114139 *567 (MRCItem 14140 litem &481 13908 14141 pos 76 13909 14142 dimension 20 13910 14143 uid 12773,0 13911 14144 ) 13912 *5 56(MRCItem13913 litem &4 7214145 *568 (MRCItem 14146 litem &482 13914 14147 pos 77 13915 14148 dimension 20 13916 14149 uid 13515,0 13917 14150 ) 13918 *5 57(MRCItem13919 litem &4 7314151 *569 (MRCItem 14152 litem &483 13920 14153 pos 78 13921 14154 dimension 20 13922 14155 uid 13627,0 14156 ) 14157 *570 (MRCItem 14158 litem &484 14159 pos 79 14160 dimension 20 14161 uid 14321,0 14162 ) 14163 *571 (MRCItem 14164 litem &485 14165 pos 80 14166 dimension 20 14167 uid 15182,0 13923 14168 ) 13924 14169 ] … … 13933 14178 uid 73,0 13934 14179 optionalChildren [ 13935 *5 58(MRCItem13936 litem &3 8614180 *572 (MRCItem 14181 litem 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65(MRCItem13978 litem & 39414222 *579 (MRCItem 14223 litem &404 13979 14224 pos 7 13980 14225 dimension 80 … … 13996 14241 genericsCommonDM (CommonDM 13997 14242 ldm (LogicalDM 13998 emptyRow *5 66(LEmptyRow14243 emptyRow *580 (LEmptyRow 13999 14244 ) 14000 14245 uid 83,0 14001 14246 optionalChildren [ 14002 *5 67(RefLabelRowHdr14003 ) 14004 *5 68(TitleRowHdr14005 ) 14006 *5 69(FilterRowHdr14007 ) 14008 *5 70(RefLabelColHdr14247 *581 (RefLabelRowHdr 14248 ) 14249 *582 (TitleRowHdr 14250 ) 14251 *583 (FilterRowHdr 14252 ) 14253 *584 (RefLabelColHdr 14009 14254 tm "RefLabelColHdrMgr" 14010 14255 ) 14011 *5 71(RowExpandColHdr14256 *585 (RowExpandColHdr 14012 14257 tm "RowExpandColHdrMgr" 14013 14258 ) 14014 *5 72(GroupColHdr14259 *586 (GroupColHdr 14015 14260 tm "GroupColHdrMgr" 14016 14261 ) 14017 *5 73(NameColHdr14262 *587 (NameColHdr 14018 14263 tm "GenericNameColHdrMgr" 14019 14264 ) 14020 *5 74(TypeColHdr14265 *588 (TypeColHdr 14021 14266 tm "GenericTypeColHdrMgr" 14022 14267 ) 14023 *5 75(InitColHdr14268 *589 (InitColHdr 14024 14269 tm "GenericValueColHdrMgr" 14025 14270 ) 14026 *5 76(PragmaColHdr14271 *590 (PragmaColHdr 14027 14272 tm "GenericPragmaColHdrMgr" 14028 14273 ) 14029 *5 77(EolColHdr14274 *591 (EolColHdr 14030 14275 tm "GenericEolColHdrMgr" 14031 14276 ) … … 14037 14282 uid 95,0 14038 14283 optionalChildren [ 14039 *5 78(Sheet14284 *592 (Sheet 14040 14285 sheetRow (SheetRow 14041 14286 headerVa (MVa … … 14054 14299 font "Tahoma,10,0" 14055 14300 ) 14056 emptyMRCItem *5 79(MRCItem14057 litem &5 6614301 emptyMRCItem *593 (MRCItem 14302 litem &580 14058 14303 pos 0 14059 14304 dimension 20 … … 14061 14306 uid 97,0 14062 14307 optionalChildren [ 14063 *5 80(MRCItem14064 litem &5 6714308 *594 (MRCItem 14309 litem &581 14065 14310 pos 0 14066 14311 dimension 20 14067 14312 uid 98,0 14068 14313 ) 14069 *5 81(MRCItem14070 litem &5 6814314 *595 (MRCItem 14315 litem &582 14071 14316 pos 1 14072 14317 dimension 23 14073 14318 uid 99,0 14074 14319 ) 14075 *5 82(MRCItem14076 litem &5 6914320 *596 (MRCItem 14321 litem &583 14077 14322 pos 2 14078 14323 hidden 1 … … 14091 14336 uid 101,0 14092 14337 optionalChildren [ 14093 *5 83(MRCItem14094 litem &5 7014338 *597 (MRCItem 14339 litem &584 14095 14340 pos 0 14096 14341 dimension 20 14097 14342 uid 102,0 14098 14343 ) 14099 *5 84(MRCItem14100 litem &5 7214344 *598 (MRCItem 14345 litem &586 14101 14346 pos 1 14102 14347 dimension 50 14103 14348 uid 103,0 14104 14349 ) 14105 *5 85(MRCItem14106 litem &5 7314350 *599 (MRCItem 14351 litem &587 14107 14352 pos 2 14108 14353 dimension 100 14109 14354 uid 104,0 14110 14355 ) 14111 * 586(MRCItem14112 litem &5 7414356 *600 (MRCItem 14357 litem &588 14113 14358 pos 3 14114 14359 dimension 100 14115 14360 uid 105,0 14116 14361 ) 14117 * 587(MRCItem14118 litem &5 7514362 *601 (MRCItem 14363 litem &589 14119 14364 pos 4 14120 14365 dimension 50 14121 14366 uid 106,0 14122 14367 ) 14123 * 588(MRCItem14124 litem &5 7614368 *602 (MRCItem 14369 litem &590 14125 14370 pos 5 14126 14371 dimension 50 14127 14372 uid 107,0 14128 14373 ) 14129 * 589(MRCItem14130 litem &5 7714374 *603 (MRCItem 14375 litem &591 14131 14376 pos 6 14132 14377 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak
r10121 r10123 91 91 number "9" 92 92 ) 93 (EmbeddedInstance 94 name "eb1" 95 number "7" 96 ) 93 97 ] 94 98 libraryRefs [ … … 105 109 (vvPair 106 110 variable "HDLDir" 107 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"111 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 108 112 ) 109 113 (vvPair 110 114 variable "HDSDir" 111 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"115 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 112 116 ) 113 117 (vvPair 114 118 variable "SideDataDesignDir" 115 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"119 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 116 120 ) 117 121 (vvPair 118 122 variable "SideDataUserDir" 119 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"123 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 120 124 ) 121 125 (vvPair 122 126 variable "SourceDir" 123 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"127 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 124 128 ) 125 129 (vvPair … … 137 141 (vvPair 138 142 variable "d" 139 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"143 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board" 140 144 ) 141 145 (vvPair 142 146 variable "d_logical" 143 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"147 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board" 144 148 ) 145 149 (vvPair 146 150 variable "date" 147 value "2 6.01.2011"151 value "27.01.2011" 148 152 ) 149 153 (vvPair 150 154 variable "day" 151 value " Mi"155 value "Do" 152 156 ) 153 157 (vvPair 154 158 variable "day_long" 155 value " Mittwoch"159 value "Donnerstag" 156 160 ) 157 161 (vvPair 158 162 variable "dd" 159 value "2 6"163 value "27" 160 164 ) 161 165 (vvPair … … 233 237 (vvPair 234 238 variable "p" 235 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"239 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 236 240 ) 237 241 (vvPair 238 242 variable "p_logical" 239 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"243 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 240 244 ) 241 245 (vvPair … … 293 297 (vvPair 294 298 variable "time" 295 value "1 1:33:02"299 value "16:56:58" 296 300 ) 297 301 (vvPair … … 345 349 bg "0,0,32768" 346 350 ) 347 xt "99200,4000,108 800,5000"351 xt "99200,4000,108700,5000" 348 352 st " 349 353 by %user on %dd %month %year … … 684 688 n "wiz_reset" 685 689 t "std_logic" 686 o 4 8690 o 47 687 691 suid 2,0 688 692 i "'1'" … … 723 727 b "(7 DOWNTO 0)" 724 728 posAdd 0 725 o 3 7729 o 36 726 730 suid 7,0 727 731 i "(OTHERS => '0')" … … 760 764 preAdd 0 761 765 posAdd 0 762 o 1 0766 o 11 763 767 suid 18,0 764 768 ) … … 795 799 n "adc_oeb" 796 800 t "std_logic" 797 o 2 9801 o 28 798 802 suid 21,0 799 803 i "'1'" … … 833 837 preAdd 0 834 838 posAdd 0 835 o 8839 o 9 836 840 suid 24,0 837 841 ) … … 868 872 t "std_logic_vector" 869 873 b "(1 downto 0)" 870 o 9874 o 10 871 875 suid 25,0 872 876 ) … … 905 909 t "std_logic_vector" 906 910 b "(9 DOWNTO 0)" 907 o 4 5911 o 44 908 912 suid 26,0 909 913 ) … … 941 945 n "wiz_cs" 942 946 t "std_logic" 943 o 4 6947 o 45 944 948 suid 28,0 945 949 i "'1'" … … 979 983 t "std_logic_vector" 980 984 b "(15 DOWNTO 0)" 981 o 5 1985 o 50 982 986 suid 27,0 983 987 ) … … 1014 1018 n "wiz_int" 1015 1019 t "std_logic" 1016 o 1 11020 o 12 1017 1021 suid 31,0 1018 1022 ) … … 1050 1054 n "wiz_rd" 1051 1055 t "std_logic" 1052 o 4 71056 o 46 1053 1057 suid 30,0 1054 1058 i "'1'" … … 1087 1091 n "wiz_wr" 1088 1092 t "std_logic" 1089 o 4 91093 o 48 1090 1094 suid 29,0 1091 1095 i "'1'" … … 1123 1127 n "CLK_25_PS" 1124 1128 t "std_logic" 1125 o 1 51129 o 16 1126 1130 suid 35,0 1127 1131 ) … … 1158 1162 n "CLK_50" 1159 1163 t "std_logic" 1160 o 1 61164 o 17 1161 1165 suid 37,0 1162 1166 ) … … 1226 1230 n "adc_data_array" 1227 1231 t "adc_data_array_type" 1228 o 61232 o 7 1229 1233 suid 39,0 1230 1234 ) … … 1261 1265 t "std_logic_vector" 1262 1266 b "(3 DOWNTO 0)" 1263 o 71267 o 8 1264 1268 suid 40,0 1265 1269 ) … … 1297 1301 t "std_logic_vector" 1298 1302 b "(3 downto 0)" 1299 o 3 41303 o 33 1300 1304 suid 48,0 1301 1305 i "(others => '0')" … … 1333 1337 n "drs_dwrite" 1334 1338 t "std_logic" 1335 o 3 51339 o 34 1336 1340 suid 49,0 1337 1341 i "'1'" … … 1368 1372 n "SROUT_in_0" 1369 1373 t "std_logic" 1370 o 21374 o 3 1371 1375 suid 42,0 1372 1376 ) … … 1402 1406 n "SROUT_in_1" 1403 1407 t "std_logic" 1404 o 31408 o 4 1405 1409 suid 43,0 1406 1410 ) … … 1436 1440 n "SROUT_in_2" 1437 1441 t "std_logic" 1438 o 41442 o 5 1439 1443 suid 44,0 1440 1444 ) … … 1470 1474 n "SROUT_in_3" 1471 1475 t "std_logic" 1472 o 51476 o 6 1473 1477 suid 45,0 1474 1478 ) … … 1505 1509 n "RSRLOAD" 1506 1510 t "std_logic" 1507 o 2 51511 o 24 1508 1512 suid 56,0 1509 1513 i "'0'" … … 1541 1545 n "SRCLK" 1542 1546 t "std_logic" 1543 o 2 61547 o 25 1544 1548 suid 57,0 1545 1549 i "'0'" … … 1578 1582 n "dac_cs" 1579 1583 t "std_logic" 1580 o 3 21584 o 31 1581 1585 suid 64,0 1582 1586 ) … … 1614 1618 n "sclk" 1615 1619 t "std_logic" 1616 o 4 21620 o 41 1617 1621 suid 62,0 1618 1622 ) … … 1651 1655 t "std_logic_vector" 1652 1656 b "(3 DOWNTO 0)" 1653 o 4 31657 o 42 1654 1658 suid 65,0 1655 1659 ) … … 1689 1693 preAdd 0 1690 1694 posAdd 0 1691 o 501695 o 49 1692 1696 suid 63,0 1693 1697 ) … … 1725 1729 n "mosi" 1726 1730 t "std_logic" 1727 o 3 81731 o 37 1728 1732 suid 66,0 1729 1733 i "'0'" … … 1764 1768 eolc "-- default domino wave off" 1765 1769 posAdd 0 1766 o 3 31770 o 32 1767 1771 suid 67,0 1768 1772 i "'0'" … … 1800 1804 n "adc_clk_en" 1801 1805 t "std_logic" 1802 o 2 81806 o 27 1803 1807 suid 69,0 1804 1808 i "'0'" … … 1839 1843 preAdd 0 1840 1844 posAdd 0 1841 o 1 71845 o 18 1842 1846 suid 76,0 1843 1847 ) … … 1875 1879 n "LOCKED_extraOUT" 1876 1880 t "std_logic" 1877 o 1 81881 o 19 1878 1882 suid 70,0 1879 1883 ) … … 1914 1918 preAdd 0 1915 1919 posAdd 0 1916 o 3 91920 o 38 1917 1921 suid 77,0 1918 1922 i "(OTHERS => '0')" … … 1957 1961 ) 1958 1962 *49 (CptPort 1959 uid 10266,01960 ps "OnEdgeStrategy"1961 shape (Triangle1962 uid 10267,01963 ro 901964 va (VaSet1965 vasetType 11966 fg "0,65535,0"1967 )1968 xt "80000,126625,80750,127375"1969 )1970 tg (CPTG1971 uid 10268,01972 ps "CptPortTextPlaceStrategy"1973 stg "RightVerticalLayoutStrategy"1974 f (Text1975 uid 10269,01976 va (VaSet1977 )1978 xt "74800,126500,79000,127500"1979 st "PS_DO_IN"1980 ju 21981 blo "79000,127300"1982 )1983 )1984 thePort (LogicalPort1985 m 11986 decl (Decl1987 n "PS_DO_IN"1988 t "std_logic"1989 o 241990 suid 81,01991 )1992 )1993 )1994 *50 (CptPort1995 1963 uid 10270,0 1996 1964 ps "OnEdgeStrategy" … … 2023 1991 n "PSCLK_OUT" 2024 1992 t "std_logic" 2025 o 191993 o 20 2026 1994 suid 74,0 2027 1995 ) 2028 1996 ) 2029 1997 ) 2030 *5 1(CptPort1998 *50 (CptPort 2031 1999 uid 10274,0 2032 2000 ps "OnEdgeStrategy" … … 2059 2027 n "PSDONE_extraOUT" 2060 2028 t "std_logic" 2061 o 2 02029 o 21 2062 2030 suid 71,0 2063 2031 ) 2064 2032 ) 2065 2033 ) 2066 *52 (CptPort 2067 uid 10278,0 2068 ps "OnEdgeStrategy" 2069 shape (Triangle 2070 uid 10279,0 2071 ro 90 2072 va (VaSet 2073 vasetType 1 2074 fg "0,65535,0" 2075 ) 2076 xt "80000,128625,80750,129375" 2077 ) 2078 tg (CPTG 2079 uid 10280,0 2080 ps "CptPortTextPlaceStrategy" 2081 stg "RightVerticalLayoutStrategy" 2082 f (Text 2083 uid 10281,0 2084 va (VaSet 2085 ) 2086 xt "74400,128500,79000,129500" 2087 st "PSEN_OUT" 2088 ju 2 2089 blo "79000,129300" 2090 ) 2091 ) 2092 thePort (LogicalPort 2093 m 1 2094 decl (Decl 2095 n "PSEN_OUT" 2096 t "std_logic" 2097 o 21 2098 suid 73,0 2099 ) 2100 ) 2101 ) 2102 *53 (CptPort 2034 *51 (CptPort 2103 2035 uid 10282,0 2104 2036 ps "OnEdgeStrategy" … … 2136 2068 ) 2137 2069 ) 2138 *5 4(CptPort2070 *52 (CptPort 2139 2071 uid 10286,0 2140 2072 ps "OnEdgeStrategy" … … 2169 2101 preAdd 0 2170 2102 posAdd 0 2171 o 402103 o 39 2172 2104 suid 79,0 2173 2105 i "'0'" … … 2175 2107 ) 2176 2108 ) 2177 *5 5(CptPort2109 *53 (CptPort 2178 2110 uid 10290,0 2179 2111 ps "OnEdgeStrategy" … … 2209 2141 preAdd 0 2210 2142 posAdd 0 2211 o 4 42143 o 43 2212 2144 suid 78,0 2213 2145 i "'0'" … … 2215 2147 ) 2216 2148 ) 2217 *5 6(CptPort2149 *54 (CptPort 2218 2150 uid 10320,0 2219 2151 ps "OnEdgeStrategy" … … 2246 2178 n "CLK25_OUT" 2247 2179 t "std_logic" 2248 o 1 22180 o 13 2249 2181 suid 83,0 2250 2182 ) 2251 2183 ) 2252 2184 ) 2253 *5 7(CptPort2185 *55 (CptPort 2254 2186 uid 10324,0 2255 2187 ps "OnEdgeStrategy" … … 2282 2214 n "CLK25_PSOUT" 2283 2215 t "std_logic" 2284 o 1 32216 o 14 2285 2217 suid 84,0 2286 2218 ) 2287 2219 ) 2288 2220 ) 2289 *5 8(CptPort2221 *56 (CptPort 2290 2222 uid 10328,0 2291 2223 ps "OnEdgeStrategy" … … 2318 2250 n "CLK50_OUT" 2319 2251 t "std_logic" 2320 o 1 42252 o 15 2321 2253 suid 82,0 2322 2254 ) 2323 2255 ) 2324 2256 ) 2325 *5 9(CptPort2257 *57 (CptPort 2326 2258 uid 12314,0 2327 2259 ps "OnEdgeStrategy" … … 2354 2286 n "SRIN_out" 2355 2287 t "std_logic" 2356 o 2 72288 o 26 2357 2289 suid 85,0 2358 2290 i "'0'" … … 2360 2292 ) 2361 2293 ) 2362 * 60(CptPort2294 *58 (CptPort 2363 2295 uid 12521,0 2364 2296 ps "OnEdgeStrategy" … … 2391 2323 n "amber" 2392 2324 t "std_logic" 2393 o 3 12325 o 30 2394 2326 suid 87,0 2395 2327 ) 2396 2328 ) 2397 2329 ) 2398 * 61(CptPort2330 *59 (CptPort 2399 2331 uid 12525,0 2400 2332 ps "OnEdgeStrategy" … … 2427 2359 n "green" 2428 2360 t "std_logic" 2429 o 3 62361 o 35 2430 2362 suid 86,0 2431 2363 ) 2432 2364 ) 2433 2365 ) 2434 *6 2(CptPort2366 *60 (CptPort 2435 2367 uid 12529,0 2436 2368 ps "OnEdgeStrategy" … … 2463 2395 n "red" 2464 2396 t "std_logic" 2465 o 4 12397 o 40 2466 2398 suid 88,0 2467 2399 ) 2468 2400 ) 2469 2401 ) 2470 *6 3(CptPort2402 *61 (CptPort 2471 2403 uid 13843,0 2472 2404 ps "OnEdgeStrategy" … … 2499 2431 n "additional_flasher_out" 2500 2432 t "std_logic" 2501 o 302433 o 29 2502 2434 suid 90,0 2435 ) 2436 ) 2437 ) 2438 *62 (CptPort 2439 uid 14682,0 2440 ps "OnEdgeStrategy" 2441 shape (Triangle 2442 uid 14683,0 2443 ro 90 2444 va (VaSet 2445 vasetType 1 2446 fg "0,65535,0" 2447 ) 2448 xt "51250,138625,52000,139375" 2449 ) 2450 tg (CPTG 2451 uid 14684,0 2452 ps "CptPortTextPlaceStrategy" 2453 stg "VerticalLayoutStrategy" 2454 f (Text 2455 uid 14685,0 2456 va (VaSet 2457 ) 2458 xt "53000,138500,58500,139500" 2459 st "D_T_in : (1:0)" 2460 blo "53000,139300" 2461 ) 2462 ) 2463 thePort (LogicalPort 2464 decl (Decl 2465 n "D_T_in" 2466 t "std_logic_vector" 2467 b "(1 DOWNTO 0)" 2468 o 2 2469 suid 91,0 2503 2470 ) 2504 2471 ) … … 2521 2488 stg "VerticalLayoutStrategy" 2522 2489 textVec [ 2490 *63 (Text 2491 uid 172,0 2492 va (VaSet 2493 font "Arial,8,1" 2494 ) 2495 xt "55200,141000,61400,142000" 2496 st "FACT_FAD_lib" 2497 blo "55200,141800" 2498 tm "BdLibraryNameMgr" 2499 ) 2523 2500 *64 (Text 2524 uid 17 2,02501 uid 173,0 2525 2502 va (VaSet 2526 2503 font "Arial,8,1" 2527 2504 ) 2528 xt "5 2200,123000,58400,124000"2529 st "FA CT_FAD_lib"2530 blo "5 2200,123800"2531 tm " BdLibraryNameMgr"2505 xt "55200,142000,59400,143000" 2506 st "FAD_main" 2507 blo "55200,142800" 2508 tm "CptNameMgr" 2532 2509 ) 2533 2510 *65 (Text 2534 uid 17 3,02511 uid 174,0 2535 2512 va (VaSet 2536 2513 font "Arial,8,1" 2537 2514 ) 2538 xt "52200,124000,56400,125000" 2539 st "FAD_main" 2540 blo "52200,124800" 2541 tm "CptNameMgr" 2542 ) 2543 *66 (Text 2544 uid 174,0 2545 va (VaSet 2546 font "Arial,8,1" 2547 ) 2548 xt "52200,125000,58000,126000" 2515 xt "55200,143000,61000,144000" 2549 2516 st "I_board_main" 2550 blo "5 2200,125800"2517 blo "55200,143800" 2551 2518 tm "InstanceNameMgr" 2552 2519 ) … … 2593 2560 archFileType "UNKNOWN" 2594 2561 ) 2595 *6 7(PortIoIn2562 *66 (PortIoIn 2596 2563 uid 231,0 2597 2564 shape (CompositeShape … … 2638 2605 ) 2639 2606 ) 2640 *6 8(PortIoIn2607 *67 (PortIoIn 2641 2608 uid 251,0 2642 2609 shape (CompositeShape … … 2683 2650 ) 2684 2651 ) 2685 *6 9(HdlText2652 *68 (HdlText 2686 2653 uid 265,0 2687 2654 optionalChildren [ 2688 * 70(EmbeddedText2655 *69 (EmbeddedText 2689 2656 uid 271,0 2690 2657 commentText (CommentText … … 2706 2673 va (VaSet 2707 2674 ) 2708 xt "32200,83200, 39700,86200"2675 xt "32200,83200,43700,86200" 2709 2676 st " 2710 2677 -- hard-wired IDs 2711 board_id <= \"0101\";2712 crate_id <= \"01\";2678 board_id <= LINE(5 downto 2); 2679 crate_id <= LINE(1 downto 0); 2713 2680 " 2714 2681 tm "HdlTextMgr" … … 2736 2703 stg "VerticalLayoutStrategy" 2737 2704 textVec [ 2738 *7 1(Text2705 *70 (Text 2739 2706 uid 268,0 2740 2707 va (VaSet … … 2746 2713 tm "HdlTextNameMgr" 2747 2714 ) 2748 *7 2(Text2715 *71 (Text 2749 2716 uid 269,0 2750 2717 va (VaSet … … 2772 2739 viewiconposition 0 2773 2740 ) 2774 *7 3(Net2741 *72 (Net 2775 2742 uid 275,0 2776 2743 decl (Decl … … 2788 2755 font "Courier New,8,0" 2789 2756 ) 2790 xt "39000,6 4000,67500,64800"2757 xt "39000,63200,67500,64000" 2791 2758 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2792 2759 " 2793 2760 ) 2794 2761 ) 2795 *7 4(Net2762 *73 (Net 2796 2763 uid 283,0 2797 2764 decl (Decl … … 2807 2774 font "Courier New,8,0" 2808 2775 ) 2809 xt "39000,64 800,67500,65600"2776 xt "39000,64000,67500,64800" 2810 2777 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2811 2778 " 2812 2779 ) 2813 2780 ) 2814 *7 5(PortIoOut2781 *74 (PortIoOut 2815 2782 uid 472,0 2816 2783 shape (CompositeShape … … 2856 2823 ) 2857 2824 ) 2858 *7 6(PortIoOut2825 *75 (PortIoOut 2859 2826 uid 478,0 2860 2827 shape (CompositeShape … … 2900 2867 ) 2901 2868 ) 2902 *7 7(PortIoOut2869 *76 (PortIoOut 2903 2870 uid 484,0 2904 2871 shape (CompositeShape … … 2944 2911 ) 2945 2912 ) 2946 *7 8(PortIoInOut2913 *77 (PortIoInOut 2947 2914 uid 490,0 2948 2915 shape (CompositeShape … … 2986 2953 ) 2987 2954 ) 2988 *7 9(PortIoIn2955 *78 (PortIoIn 2989 2956 uid 496,0 2990 2957 shape (CompositeShape … … 3030 2997 ) 3031 2998 ) 3032 * 80(PortIoOut2999 *79 (PortIoOut 3033 3000 uid 502,0 3034 3001 shape (CompositeShape … … 3074 3041 ) 3075 3042 ) 3076 *8 1(PortIoOut3043 *80 (PortIoOut 3077 3044 uid 508,0 3078 3045 shape (CompositeShape … … 3118 3085 ) 3119 3086 ) 3120 *8 2(Net3087 *81 (Net 3121 3088 uid 1465,0 3122 3089 decl (Decl … … 3131 3098 font "Courier New,8,0" 3132 3099 ) 3133 xt "39000,6 3200,63000,64000"3100 xt "39000,62400,63000,63200" 3134 3101 st "SIGNAL adc_data_array : adc_data_array_type 3135 3102 " 3136 3103 ) 3137 3104 ) 3138 *8 3(Net3105 *82 (Net 3139 3106 uid 2407,0 3140 3107 decl (Decl … … 3150 3117 font "Courier New,8,0" 3151 3118 ) 3152 xt "39000,3 7400,67500,38200"3119 xt "39000,38200,67500,39000" 3153 3120 st "RSRLOAD : std_logic := '0' 3154 3121 " 3155 3122 ) 3156 3123 ) 3157 *8 4(PortIoOut3124 *83 (PortIoOut 3158 3125 uid 2415,0 3159 3126 shape (CompositeShape … … 3200 3167 ) 3201 3168 ) 3202 *8 5(Net3169 *84 (Net 3203 3170 uid 2421,0 3204 3171 decl (Decl … … 3214 3181 font "Courier New,8,0" 3215 3182 ) 3216 xt "39000,6 1600,71000,62400"3183 xt "39000,60800,71000,61600" 3217 3184 st "SIGNAL SRCLK : std_logic := '0' 3218 3185 " 3219 3186 ) 3220 3187 ) 3221 *8 6(Net3188 *85 (Net 3222 3189 uid 3019,0 3223 3190 decl (Decl … … 3238 3205 ) 3239 3206 ) 3240 *8 7(Net3207 *86 (Net 3241 3208 uid 3025,0 3242 3209 decl (Decl … … 3251 3218 font "Courier New,8,0" 3252 3219 ) 3253 xt "39000,2 4600,54000,25400"3220 xt "39000,25400,54000,26200" 3254 3221 st "DAC_CS : std_logic 3255 3222 " 3256 3223 ) 3257 3224 ) 3258 *8 8(PortIoOut3225 *87 (PortIoOut 3259 3226 uid 3153,0 3260 3227 shape (CompositeShape … … 3301 3268 ) 3302 3269 ) 3303 *8 9(Net3270 *88 (Net 3304 3271 uid 3216,0 3305 3272 decl (Decl … … 3316 3283 font "Courier New,8,0" 3317 3284 ) 3318 xt "39000,1 7400,54000,18200"3285 xt "39000,18200,54000,19000" 3319 3286 st "X_50M : STD_LOGIC 3320 3287 " 3321 3288 ) 3322 3289 ) 3323 * 90(Net3290 *89 (Net 3324 3291 uid 3226,0 3325 3292 decl (Decl … … 3334 3301 font "Courier New,8,0" 3335 3302 ) 3336 xt "39000,1 5800,54000,16600"3303 xt "39000,16600,54000,17400" 3337 3304 st "TRG : STD_LOGIC 3338 3305 " 3339 3306 ) 3340 3307 ) 3341 *9 1(HdlText3308 *90 (HdlText 3342 3309 uid 3248,0 3343 3310 optionalChildren [ 3344 *9 2(EmbeddedText3311 *91 (EmbeddedText 3345 3312 uid 3254,0 3346 3313 commentText (CommentText … … 3394 3361 stg "VerticalLayoutStrategy" 3395 3362 textVec [ 3396 *9 3(Text3363 *92 (Text 3397 3364 uid 3251,0 3398 3365 va (VaSet … … 3404 3371 tm "HdlTextNameMgr" 3405 3372 ) 3406 *9 4(Text3373 *93 (Text 3407 3374 uid 3252,0 3408 3375 va (VaSet … … 3430 3397 viewiconposition 0 3431 3398 ) 3432 *9 5(Net3399 *94 (Net 3433 3400 uid 3266,0 3434 3401 decl (Decl … … 3444 3411 font "Courier New,8,0" 3445 3412 ) 3446 xt "39000,2 0600,64000,21400"3413 xt "39000,21400,64000,22200" 3447 3414 st "A_CLK : std_logic_vector(3 downto 0) 3448 3415 " 3449 3416 ) 3450 3417 ) 3451 *9 6(Net3418 *95 (Net 3452 3419 uid 3268,0 3453 3420 decl (Decl … … 3462 3429 font "Courier New,8,0" 3463 3430 ) 3464 xt "39000,5 2800,57500,53600"3431 xt "39000,53600,57500,54400" 3465 3432 st "SIGNAL CLK_25_PS : std_logic 3466 3433 " 3467 3434 ) 3468 3435 ) 3469 *9 7(PortIoOut3436 *96 (PortIoOut 3470 3437 uid 3284,0 3471 3438 shape (CompositeShape … … 3512 3479 ) 3513 3480 ) 3514 *9 8(Net3481 *97 (Net 3515 3482 uid 3290,0 3516 3483 decl (Decl … … 3527 3494 font "Courier New,8,0" 3528 3495 ) 3529 xt "39000,3 1800,54000,32600"3496 xt "39000,32600,54000,33400" 3530 3497 st "OE_ADC : STD_LOGIC 3531 3498 " 3532 3499 ) 3533 3500 ) 3534 *9 9(PortIoIn3501 *98 (PortIoIn 3535 3502 uid 3292,0 3536 3503 shape (CompositeShape … … 3577 3544 ) 3578 3545 ) 3579 * 100(Net3546 *99 (Net 3580 3547 uid 3298,0 3581 3548 decl (Decl … … 3596 3563 ) 3597 3564 ) 3598 *10 1(HdlText3565 *100 (HdlText 3599 3566 uid 3300,0 3600 3567 optionalChildren [ 3601 *10 2(EmbeddedText3568 *101 (EmbeddedText 3602 3569 uid 3306,0 3603 3570 commentText (CommentText … … 3651 3618 stg "VerticalLayoutStrategy" 3652 3619 textVec [ 3653 *10 3(Text3620 *102 (Text 3654 3621 uid 3303,0 3655 3622 va (VaSet … … 3661 3628 tm "HdlTextNameMgr" 3662 3629 ) 3663 *10 4(Text3630 *103 (Text 3664 3631 uid 3304,0 3665 3632 va (VaSet … … 3687 3654 viewiconposition 0 3688 3655 ) 3689 *10 5(PortIoIn3656 *104 (PortIoIn 3690 3657 uid 3310,0 3691 3658 shape (CompositeShape … … 3732 3699 ) 3733 3700 ) 3734 *10 6(PortIoIn3701 *105 (PortIoIn 3735 3702 uid 3332,0 3736 3703 shape (CompositeShape … … 3777 3744 ) 3778 3745 ) 3779 *10 7(PortIoIn3746 *106 (PortIoIn 3780 3747 uid 3338,0 3781 3748 shape (CompositeShape … … 3822 3789 ) 3823 3790 ) 3824 *10 8(PortIoIn3791 *107 (PortIoIn 3825 3792 uid 3344,0 3826 3793 shape (CompositeShape … … 3867 3834 ) 3868 3835 ) 3869 *10 9(Net3836 *108 (Net 3870 3837 uid 3374,0 3871 3838 decl (Decl … … 3886 3853 ) 3887 3854 ) 3888 *1 10(Net3855 *109 (Net 3889 3856 uid 3376,0 3890 3857 decl (Decl … … 3905 3872 ) 3906 3873 ) 3907 *11 1(Net3874 *110 (Net 3908 3875 uid 3378,0 3909 3876 decl (Decl … … 3924 3891 ) 3925 3892 ) 3926 *11 2(Net3893 *111 (Net 3927 3894 uid 3380,0 3928 3895 decl (Decl … … 3943 3910 ) 3944 3911 ) 3945 *11 3(HdlText3912 *112 (HdlText 3946 3913 uid 3394,0 3947 3914 optionalChildren [ 3948 *11 4(EmbeddedText3915 *113 (EmbeddedText 3949 3916 uid 3400,0 3950 3917 commentText (CommentText … … 3998 3965 stg "VerticalLayoutStrategy" 3999 3966 textVec [ 4000 *11 5(Text3967 *114 (Text 4001 3968 uid 3397,0 4002 3969 va (VaSet … … 4008 3975 tm "HdlTextNameMgr" 4009 3976 ) 4010 *11 6(Text3977 *115 (Text 4011 3978 uid 3398,0 4012 3979 va (VaSet … … 4034 4001 viewiconposition 0 4035 4002 ) 4036 *11 7(Net4003 *116 (Net 4037 4004 uid 3460,0 4038 4005 decl (Decl … … 4047 4014 font "Courier New,8,0" 4048 4015 ) 4049 xt "39000,2 1400,54000,22200"4016 xt "39000,22200,54000,23000" 4050 4017 st "D0_SRCLK : STD_LOGIC 4051 4018 " 4052 4019 ) 4053 4020 ) 4054 *11 8(Net4021 *117 (Net 4055 4022 uid 3462,0 4056 4023 decl (Decl … … 4065 4032 font "Courier New,8,0" 4066 4033 ) 4067 xt "39000,2 2200,54000,23000"4034 xt "39000,23000,54000,23800" 4068 4035 st "D1_SRCLK : STD_LOGIC 4069 4036 " 4070 4037 ) 4071 4038 ) 4072 *11 9(Net4039 *118 (Net 4073 4040 uid 3464,0 4074 4041 decl (Decl … … 4083 4050 font "Courier New,8,0" 4084 4051 ) 4085 xt "39000,23 000,54000,23800"4052 xt "39000,23800,54000,24600" 4086 4053 st "D2_SRCLK : STD_LOGIC 4087 4054 " 4088 4055 ) 4089 4056 ) 4090 *1 20(Net4057 *119 (Net 4091 4058 uid 3466,0 4092 4059 decl (Decl … … 4101 4068 font "Courier New,8,0" 4102 4069 ) 4103 xt "39000,2 3800,54000,24600"4070 xt "39000,24600,54000,25400" 4104 4071 st "D3_SRCLK : STD_LOGIC 4105 4072 " 4106 4073 ) 4107 4074 ) 4108 *12 1(PortIoIn4075 *120 (PortIoIn 4109 4076 uid 3476,0 4110 4077 shape (CompositeShape … … 4151 4118 ) 4152 4119 ) 4153 *12 2(PortIoIn4120 *121 (PortIoIn 4154 4121 uid 3482,0 4155 4122 shape (CompositeShape … … 4196 4163 ) 4197 4164 ) 4198 *12 3(PortIoIn4165 *122 (PortIoIn 4199 4166 uid 3488,0 4200 4167 shape (CompositeShape … … 4241 4208 ) 4242 4209 ) 4243 *12 4(PortIoIn4210 *123 (PortIoIn 4244 4211 uid 3494,0 4245 4212 shape (CompositeShape … … 4286 4253 ) 4287 4254 ) 4288 *12 5(Net4255 *124 (Net 4289 4256 uid 3500,0 4290 4257 decl (Decl … … 4304 4271 ) 4305 4272 ) 4306 *12 6(Net4273 *125 (Net 4307 4274 uid 3502,0 4308 4275 decl (Decl … … 4322 4289 ) 4323 4290 ) 4324 *12 7(Net4291 *126 (Net 4325 4292 uid 3504,0 4326 4293 decl (Decl … … 4340 4307 ) 4341 4308 ) 4342 *12 8(Net4309 *127 (Net 4343 4310 uid 3506,0 4344 4311 decl (Decl … … 4358 4325 ) 4359 4326 ) 4360 *12 9(PortIoOut4327 *128 (PortIoOut 4361 4328 uid 3508,0 4362 4329 shape (CompositeShape … … 4403 4370 ) 4404 4371 ) 4405 *1 30(Net4372 *129 (Net 4406 4373 uid 3514,0 4407 4374 decl (Decl … … 4418 4385 font "Courier New,8,0" 4419 4386 ) 4420 xt "39000,27 000,73500,27800"4387 xt "39000,27800,73500,28600" 4421 4388 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 4422 4389 " 4423 4390 ) 4424 4391 ) 4425 *13 1(PortIoOut4392 *130 (PortIoOut 4426 4393 uid 3516,0 4427 4394 shape (CompositeShape … … 4468 4435 ) 4469 4436 ) 4470 *13 2(Net4437 *131 (Net 4471 4438 uid 3522,0 4472 4439 decl (Decl … … 4482 4449 font "Courier New,8,0" 4483 4450 ) 4484 xt "39000,2 6200,67500,27000"4451 xt "39000,27000,67500,27800" 4485 4452 st "DWRITE : std_logic := '0' 4486 4453 " 4487 4454 ) 4488 4455 ) 4489 *13 3(PortIoOut4456 *132 (PortIoOut 4490 4457 uid 3536,0 4491 4458 shape (CompositeShape … … 4531 4498 ) 4532 4499 ) 4533 *13 4(HdlText4500 *133 (HdlText 4534 4501 uid 3542,0 4535 4502 optionalChildren [ 4536 *13 5(EmbeddedText4503 *134 (EmbeddedText 4537 4504 uid 3612,0 4538 4505 commentText (CommentText … … 4586 4553 stg "VerticalLayoutStrategy" 4587 4554 textVec [ 4588 *13 6(Text4555 *135 (Text 4589 4556 uid 3545,0 4590 4557 va (VaSet … … 4596 4563 tm "HdlTextNameMgr" 4597 4564 ) 4598 *13 7(Text4565 *136 (Text 4599 4566 uid 3546,0 4600 4567 va (VaSet … … 4622 4589 viewiconposition 0 4623 4590 ) 4624 *13 8(PortIoOut4591 *137 (PortIoOut 4625 4592 uid 3548,0 4626 4593 shape (CompositeShape … … 4666 4633 ) 4667 4634 ) 4668 *13 9(PortIoOut4635 *138 (PortIoOut 4669 4636 uid 3554,0 4670 4637 shape (CompositeShape … … 4710 4677 ) 4711 4678 ) 4712 *1 40(PortIoOut4679 *139 (PortIoOut 4713 4680 uid 3560,0 4714 4681 shape (CompositeShape … … 4754 4721 ) 4755 4722 ) 4756 *14 1(PortIoOut4723 *140 (PortIoOut 4757 4724 uid 3566,0 4758 4725 shape (CompositeShape … … 4798 4765 ) 4799 4766 ) 4800 *14 2(Net4767 *141 (Net 4801 4768 uid 3604,0 4802 4769 decl (Decl … … 4811 4778 font "Courier New,8,0" 4812 4779 ) 4813 xt "39000, 39800,54000,40600"4780 xt "39000,40600,54000,41400" 4814 4781 st "T0_CS : std_logic 4815 4782 " 4816 4783 ) 4817 4784 ) 4818 *14 3(Net4785 *142 (Net 4819 4786 uid 3606,0 4820 4787 decl (Decl … … 4829 4796 font "Courier New,8,0" 4830 4797 ) 4831 xt "39000,4 0600,54000,41400"4798 xt "39000,41400,54000,42200" 4832 4799 st "T1_CS : std_logic 4833 4800 " 4834 4801 ) 4835 4802 ) 4836 *14 4(Net4803 *143 (Net 4837 4804 uid 3608,0 4838 4805 decl (Decl … … 4847 4814 font "Courier New,8,0" 4848 4815 ) 4849 xt "39000,4 1400,54000,42200"4816 xt "39000,42200,54000,43000" 4850 4817 st "T2_CS : std_logic 4851 4818 " 4852 4819 ) 4853 4820 ) 4854 *14 5(Net4821 *144 (Net 4855 4822 uid 3610,0 4856 4823 decl (Decl … … 4865 4832 font "Courier New,8,0" 4866 4833 ) 4867 xt "39000,4 2200,54000,43000"4834 xt "39000,43000,54000,43800" 4868 4835 st "T3_CS : std_logic 4869 4836 " 4870 4837 ) 4871 4838 ) 4872 *14 6(PortIoOut4839 *145 (PortIoOut 4873 4840 uid 3624,0 4874 4841 shape (CompositeShape … … 4914 4881 ) 4915 4882 ) 4916 *14 7(Net4883 *146 (Net 4917 4884 uid 3630,0 4918 4885 decl (Decl … … 4927 4894 font "Courier New,8,0" 4928 4895 ) 4929 xt "39000,39 000,54000,39800"4896 xt "39000,39800,54000,40600" 4930 4897 st "S_CLK : std_logic 4931 4898 " 4932 4899 ) 4933 4900 ) 4934 *14 8(Net4901 *147 (Net 4935 4902 uid 3632,0 4936 4903 decl (Decl … … 4946 4913 font "Courier New,8,0" 4947 4914 ) 4948 xt "39000,4 3800,64000,44600"4915 xt "39000,44600,64000,45400" 4949 4916 st "W_A : std_logic_vector(9 DOWNTO 0) 4950 4917 " 4951 4918 ) 4952 4919 ) 4953 *14 9(Net4920 *148 (Net 4954 4921 uid 3634,0 4955 4922 decl (Decl … … 4965 4932 font "Courier New,8,0" 4966 4933 ) 4967 xt "39000,4 8600,64500,49400"4934 xt "39000,49400,64500,50200" 4968 4935 st "W_D : std_logic_vector(15 DOWNTO 0) 4969 4936 " 4970 4937 ) 4971 4938 ) 4972 *1 50(Net4939 *149 (Net 4973 4940 uid 3636,0 4974 4941 decl (Decl … … 4984 4951 font "Courier New,8,0" 4985 4952 ) 4986 xt "39000,4 6200,67500,47000"4953 xt "39000,47000,67500,47800" 4987 4954 st "W_RES : std_logic := '1' 4988 4955 " 4989 4956 ) 4990 4957 ) 4991 *15 1(Net4958 *150 (Net 4992 4959 uid 3638,0 4993 4960 decl (Decl … … 5003 4970 font "Courier New,8,0" 5004 4971 ) 5005 xt "39000,4 5400,67500,46200"4972 xt "39000,46200,67500,47000" 5006 4973 st "W_RD : std_logic := '1' 5007 4974 " 5008 4975 ) 5009 4976 ) 5010 *15 2(Net4977 *151 (Net 5011 4978 uid 3640,0 5012 4979 decl (Decl … … 5022 4989 font "Courier New,8,0" 5023 4990 ) 5024 xt "39000,47 000,67500,47800"4991 xt "39000,47800,67500,48600" 5025 4992 st "W_WR : std_logic := '1' 5026 4993 " 5027 4994 ) 5028 4995 ) 5029 *15 3(Net4996 *152 (Net 5030 4997 uid 3642,0 5031 4998 decl (Decl … … 5040 5007 font "Courier New,8,0" 5041 5008 ) 5042 xt "39000,1 6600,54000,17400"5009 xt "39000,17400,54000,18200" 5043 5010 st "W_INT : std_logic 5044 5011 " 5045 5012 ) 5046 5013 ) 5047 *15 4(Net5014 *153 (Net 5048 5015 uid 3644,0 5049 5016 decl (Decl … … 5059 5026 font "Courier New,8,0" 5060 5027 ) 5061 xt "39000,4 4600,67500,45400"5028 xt "39000,45400,67500,46200" 5062 5029 st "W_CS : std_logic := '1' 5063 5030 " 5064 5031 ) 5065 5032 ) 5066 *15 5(PortIoInOut5033 *154 (PortIoInOut 5067 5034 uid 3674,0 5068 5035 shape (CompositeShape … … 5106 5073 ) 5107 5074 ) 5108 *15 6(Net5075 *155 (Net 5109 5076 uid 3680,0 5110 5077 decl (Decl … … 5120 5087 font "Courier New,8,0" 5121 5088 ) 5122 xt "39000,31 000,67500,31800"5089 xt "39000,31800,67500,32600" 5123 5090 st "MOSI : std_logic := '0' 5124 5091 " 5125 5092 ) 5126 5093 ) 5127 *15 7(PortIoOut5094 *156 (PortIoOut 5128 5095 uid 3688,0 5129 5096 shape (CompositeShape … … 5169 5136 ) 5170 5137 ) 5171 *15 8(Net5138 *157 (Net 5172 5139 uid 3694,0 5173 5140 decl (Decl … … 5184 5151 font "Courier New,8,0" 5185 5152 ) 5186 xt "39000,4 7800,54000,48600"5153 xt "39000,48600,54000,49400" 5187 5154 st "MISO : std_logic 5188 5155 " 5189 5156 ) 5190 5157 ) 5191 *15 9(HdlText5158 *158 (HdlText 5192 5159 uid 3700,0 5193 5160 optionalChildren [ 5194 *1 60(EmbeddedText5161 *159 (EmbeddedText 5195 5162 uid 3706,0 5196 5163 commentText (CommentText … … 5252 5219 stg "VerticalLayoutStrategy" 5253 5220 textVec [ 5254 *16 1(Text5221 *160 (Text 5255 5222 uid 3703,0 5256 5223 va (VaSet … … 5262 5229 tm "HdlTextNameMgr" 5263 5230 ) 5264 *16 2(Text5231 *161 (Text 5265 5232 uid 3704,0 5266 5233 va (VaSet … … 5288 5255 viewiconposition 0 5289 5256 ) 5290 *16 3(PortIoOut5257 *162 (PortIoOut 5291 5258 uid 3710,0 5292 5259 shape (CompositeShape … … 5332 5299 ) 5333 5300 ) 5334 *16 4(PortIoOut5301 *163 (PortIoOut 5335 5302 uid 3716,0 5336 5303 shape (CompositeShape … … 5376 5343 ) 5377 5344 ) 5378 *16 5(PortIoOut5345 *164 (PortIoOut 5379 5346 uid 3722,0 5380 5347 shape (CompositeShape … … 5420 5387 ) 5421 5388 ) 5422 *16 6(PortIoOut5389 *165 (PortIoOut 5423 5390 uid 3728,0 5424 5391 shape (CompositeShape … … 5464 5431 ) 5465 5432 ) 5466 *16 7(PortIoOut5433 *166 (PortIoOut 5467 5434 uid 3734,0 5468 5435 shape (CompositeShape … … 5508 5475 ) 5509 5476 ) 5510 *16 8(PortIoOut5477 *167 (PortIoOut 5511 5478 uid 3740,0 5512 5479 shape (CompositeShape … … 5552 5519 ) 5553 5520 ) 5554 *16 9(PortIoOut5521 *168 (PortIoOut 5555 5522 uid 3752,0 5556 5523 shape (CompositeShape … … 5596 5563 ) 5597 5564 ) 5598 *1 70(Net5565 *169 (Net 5599 5566 uid 3864,0 5600 5567 decl (Decl … … 5609 5576 font "Courier New,8,0" 5610 5577 ) 5611 xt "39000,43 000,54000,43800"5578 xt "39000,43800,54000,44600" 5612 5579 st "TRG_V : std_logic 5613 5580 " 5614 5581 ) 5615 5582 ) 5616 *17 1(Net5583 *170 (Net 5617 5584 uid 3866,0 5618 5585 decl (Decl … … 5627 5594 font "Courier New,8,0" 5628 5595 ) 5629 xt "39000,35 000,54000,35800"5596 xt "39000,35800,54000,36600" 5630 5597 st "RS485_C_RE : std_logic 5631 5598 " 5632 5599 ) 5633 5600 ) 5634 *17 2(Net5601 *171 (Net 5635 5602 uid 3868,0 5636 5603 decl (Decl … … 5645 5612 font "Courier New,8,0" 5646 5613 ) 5647 xt "39000,3 3400,54000,34200"5614 xt "39000,34200,54000,35000" 5648 5615 st "RS485_C_DE : std_logic 5649 5616 " 5650 5617 ) 5651 5618 ) 5652 *17 3(Net5619 *172 (Net 5653 5620 uid 3870,0 5654 5621 decl (Decl … … 5663 5630 font "Courier New,8,0" 5664 5631 ) 5665 xt "39000,3 6600,54000,37400"5632 xt "39000,37400,54000,38200" 5666 5633 st "RS485_E_RE : std_logic 5667 5634 " 5668 5635 ) 5669 5636 ) 5670 *17 4(Net5637 *173 (Net 5671 5638 uid 3872,0 5672 5639 decl (Decl … … 5681 5648 font "Courier New,8,0" 5682 5649 ) 5683 xt "39000,3 5800,54000,36600"5650 xt "39000,36600,54000,37400" 5684 5651 st "RS485_E_DE : std_logic 5685 5652 " 5686 5653 ) 5687 5654 ) 5688 *17 5(Net5655 *174 (Net 5689 5656 uid 3874,0 5690 5657 decl (Decl … … 5700 5667 font "Courier New,8,0" 5701 5668 ) 5702 xt "39000,2 5400,67500,26200"5669 xt "39000,26200,67500,27000" 5703 5670 st "DENABLE : std_logic := '0' 5704 5671 " 5705 5672 ) 5706 5673 ) 5707 *17 6(Net5674 *175 (Net 5708 5675 uid 3878,0 5709 5676 decl (Decl … … 5718 5685 font "Courier New,8,0" 5719 5686 ) 5720 xt "39000, 29400,54000,30200"5687 xt "39000,30200,54000,31000" 5721 5688 st "EE_CS : std_logic 5722 5689 " 5723 5690 ) 5724 5691 ) 5725 *17 7(PortIoOut5692 *176 (PortIoOut 5726 5693 uid 3995,0 5727 5694 shape (CompositeShape … … 5768 5735 ) 5769 5736 ) 5770 *17 8(PortIoOut5737 *177 (PortIoOut 5771 5738 uid 4001,0 5772 5739 shape (CompositeShape … … 5813 5780 ) 5814 5781 ) 5815 *17 9(PortIoOut5782 *178 (PortIoOut 5816 5783 uid 4007,0 5817 5784 shape (CompositeShape … … 5858 5825 ) 5859 5826 ) 5860 *1 80(PortIoOut5827 *179 (PortIoOut 5861 5828 uid 4013,0 5862 5829 shape (CompositeShape … … 5903 5870 ) 5904 5871 ) 5905 *18 1(PortIoOut5872 *180 (PortIoOut 5906 5873 uid 4916,0 5907 5874 shape (CompositeShape … … 5916 5883 sl 0 5917 5884 ro 270 5918 xt " 111500,119625,113000,120375"5885 xt "72500,153625,74000,154375" 5919 5886 ) 5920 5887 (Line … … 5922 5889 sl 0 5923 5890 ro 270 5924 xt " 111000,120000,111500,120000"5925 pts [ 5926 " 111000,120000"5927 " 111500,120000"5891 xt "72000,154000,72500,154000" 5892 pts [ 5893 "72000,154000" 5894 "72500,154000" 5928 5895 ] 5929 5896 ) … … 5940 5907 va (VaSet 5941 5908 ) 5942 xt " 114000,119500,115900,120500"5909 xt "75000,153500,76900,154500" 5943 5910 st "D_T" 5944 blo " 114000,120300"5945 tm "WireNameMgr" 5946 ) 5947 ) 5948 ) 5949 *18 2(Net5911 blo "75000,154300" 5912 tm "WireNameMgr" 5913 ) 5914 ) 5915 ) 5916 *181 (Net 5950 5917 uid 5320,0 5951 5918 decl (Decl 5952 5919 n "D_T" 5953 5920 t "std_logic_vector" 5954 b "( 7DOWNTO 0)"5921 b "(5 DOWNTO 0)" 5955 5922 o 31 5956 5923 suid 141,0 … … 5962 5929 font "Courier New,8,0" 5963 5930 ) 5964 xt "39000,2 7800,73500,28600"5965 st "D_T : std_logic_vector( 7DOWNTO 0) := (OTHERS => '0')5931 xt "39000,28600,73500,29400" 5932 st "D_T : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0') 5966 5933 " 5967 5934 ) 5968 5935 ) 5969 *18 3(PortIoIn5936 *182 (PortIoIn 5970 5937 uid 6781,0 5971 5938 shape (CompositeShape … … 6012 5979 ) 6013 5980 ) 6014 *18 4(Net5981 *183 (Net 6015 5982 uid 6793,0 6016 5983 decl (Decl … … 6031 5998 ) 6032 5999 ) 6033 *18 5(PortIoOut6000 *184 (PortIoOut 6034 6001 uid 6874,0 6035 6002 shape (CompositeShape … … 6075 6042 ) 6076 6043 ) 6077 *18 6(Net6044 *185 (Net 6078 6045 uid 6886,0 6079 6046 decl (Decl … … 6090 6057 font "Courier New,8,0" 6091 6058 ) 6092 xt "39000,2 8600,73500,29400"6059 xt "39000,29400,73500,30200" 6093 6060 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6094 6061 " 6095 6062 ) 6096 6063 ) 6097 *18 7(HdlText6064 *186 (HdlText 6098 6065 uid 7092,0 6099 6066 optionalChildren [ 6100 *18 8(EmbeddedText6067 *187 (EmbeddedText 6101 6068 uid 7098,0 6102 6069 commentText (CommentText … … 6148 6115 stg "VerticalLayoutStrategy" 6149 6116 textVec [ 6150 *18 9(Text6117 *188 (Text 6151 6118 uid 7095,0 6152 6119 va (VaSet … … 6158 6125 tm "HdlTextNameMgr" 6159 6126 ) 6160 *1 90(Text6127 *189 (Text 6161 6128 uid 7096,0 6162 6129 va (VaSet … … 6184 6151 viewiconposition 0 6185 6152 ) 6186 *19 1(PortIoOut6153 *190 (PortIoOut 6187 6154 uid 7138,0 6188 6155 shape (CompositeShape … … 6228 6195 ) 6229 6196 ) 6230 *19 2(Net6197 *191 (Net 6231 6198 uid 7150,0 6232 6199 decl (Decl … … 6243 6210 font "Courier New,8,0" 6244 6211 ) 6245 xt "39000,19 000,73500,19800"6212 xt "39000,19800,73500,20600" 6246 6213 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6247 6214 " 6248 6215 ) 6249 6216 ) 6250 *19 3(Net6217 *192 (Net 6251 6218 uid 7485,0 6252 6219 decl (Decl … … 6261 6228 font "Courier New,8,0" 6262 6229 ) 6263 xt "39000,6 6400,57500,67200"6230 xt "39000,65600,57500,66400" 6264 6231 st "SIGNAL dummy : std_logic 6265 6232 " 6266 6233 ) 6267 6234 ) 6268 *19 4(MWC6235 *193 (MWC 6269 6236 uid 7652,0 6270 6237 optionalChildren [ 6271 *19 5(CptPort6238 *194 (CptPort 6272 6239 uid 7632,0 6273 6240 optionalChildren [ 6274 *19 6(Line6241 *195 (Line 6275 6242 uid 7636,0 6276 6243 layer 5 … … 6331 6298 ) 6332 6299 ) 6333 *19 7(CptPort6300 *196 (CptPort 6334 6301 uid 7637,0 6335 6302 optionalChildren [ 6336 *19 8(Line6303 *197 (Line 6337 6304 uid 7641,0 6338 6305 layer 5 … … 6396 6363 ) 6397 6364 ) 6398 *19 9(CommentGraphic6365 *198 (CommentGraphic 6399 6366 uid 7642,0 6400 6367 shape (PolyLine2D … … 6417 6384 oxt "6000,6000,7000,7000" 6418 6385 ) 6419 * 200(CommentGraphic6386 *199 (CommentGraphic 6420 6387 uid 7644,0 6421 6388 shape (PolyLine2D … … 6438 6405 oxt "6000,7000,7000,8000" 6439 6406 ) 6440 *20 1(CommentGraphic6407 *200 (CommentGraphic 6441 6408 uid 7646,0 6442 6409 shape (PolyLine2D … … 6459 6426 oxt "6988,7329,7988,7329" 6460 6427 ) 6461 *20 2(CommentGraphic6428 *201 (CommentGraphic 6462 6429 uid 7648,0 6463 6430 shape (PolyLine2D … … 6478 6445 oxt "8000,7000,9000,7000" 6479 6446 ) 6480 *20 3(CommentGraphic6447 *202 (CommentGraphic 6481 6448 uid 7650,0 6482 6449 shape (PolyLine2D … … 6519 6486 stg "VerticalLayoutStrategy" 6520 6487 textVec [ 6521 *20 4(Text6488 *203 (Text 6522 6489 uid 7655,0 6523 6490 va (VaSet … … 6529 6496 blo "90350,83900" 6530 6497 ) 6531 *20 5(Text6498 *204 (Text 6532 6499 uid 7656,0 6533 6500 va (VaSet … … 6538 6505 blo "90350,84900" 6539 6506 ) 6540 *20 6(Text6507 *205 (Text 6541 6508 uid 7657,0 6542 6509 va (VaSet … … 6583 6550 ) 6584 6551 ) 6585 *20 7(Net6552 *206 (Net 6586 6553 uid 8851,0 6587 6554 decl (Decl … … 6598 6565 font "Courier New,8,0" 6599 6566 ) 6600 xt "39000,6 5600,77000,66400"6567 xt "39000,64800,77000,65600" 6601 6568 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6602 6569 " 6603 6570 ) 6604 6571 ) 6605 *20 8(Net6572 *207 (Net 6606 6573 uid 9500,0 6607 6574 decl (Decl … … 6616 6583 font "Courier New,8,0" 6617 6584 ) 6618 xt "39000,5 4400,57500,55200"6585 xt "39000,55200,57500,56000" 6619 6586 st "SIGNAL CLK_50 : std_logic 6620 6587 " 6621 6588 ) 6622 6589 ) 6623 *20 9(MWC6590 *208 (MWC 6624 6591 uid 10023,0 6625 6592 optionalChildren [ 6626 *2 10(CptPort6593 *209 (CptPort 6627 6594 uid 9995,0 6628 6595 optionalChildren [ 6629 *21 1(Line6596 *210 (Line 6630 6597 uid 9999,0 6631 6598 layer 5 … … 6640 6607 ] 6641 6608 ) 6642 *21 2(Property6609 *211 (Property 6643 6610 uid 10000,0 6644 6611 pclass "_MW_GEOM_" … … 6684 6651 ) 6685 6652 ) 6686 *21 3(CptPort6653 *212 (CptPort 6687 6654 uid 10001,0 6688 6655 optionalChildren [ 6689 *21 4(Line6656 *213 (Line 6690 6657 uid 10005,0 6691 6658 layer 5 … … 6739 6706 ) 6740 6707 ) 6741 *21 5(CptPort6708 *214 (CptPort 6742 6709 uid 10006,0 6743 6710 optionalChildren [ 6744 *21 6(Line6711 *215 (Line 6745 6712 uid 10010,0 6746 6713 layer 5 … … 6793 6760 ) 6794 6761 ) 6795 *21 7(CommentGraphic6762 *216 (CommentGraphic 6796 6763 uid 10011,0 6797 6764 optionalChildren [ 6798 *21 8(Property6765 *217 (Property 6799 6766 uid 10013,0 6800 6767 pclass "_MW_GEOM_" … … 6820 6787 oxt "11000,6000,11000,6000" 6821 6788 ) 6822 *21 9(CommentGraphic6789 *218 (CommentGraphic 6823 6790 uid 10014,0 6824 6791 optionalChildren [ 6825 *2 20(Property6792 *219 (Property 6826 6793 uid 10016,0 6827 6794 pclass "_MW_GEOM_" … … 6847 6814 oxt "11000,10000,11000,10000" 6848 6815 ) 6849 *22 1(Grouping6816 *220 (Grouping 6850 6817 uid 10017,0 6851 6818 optionalChildren [ 6852 *22 2(CommentGraphic6819 *221 (CommentGraphic 6853 6820 uid 10019,0 6854 6821 shape (PolyLine2D … … 6871 6838 oxt "9000,6000,11000,10000" 6872 6839 ) 6873 *22 3(CommentGraphic6840 *222 (CommentGraphic 6874 6841 uid 10021,0 6875 6842 shape (Arc2D … … 6924 6891 stg "VerticalLayoutStrategy" 6925 6892 textVec [ 6926 *22 4(Text6893 *223 (Text 6927 6894 uid 10026,0 6928 6895 va (VaSet … … 6934 6901 blo "44500,73300" 6935 6902 ) 6936 *22 5(Text6903 *224 (Text 6937 6904 uid 10027,0 6938 6905 va (VaSet … … 6943 6910 blo "44500,74300" 6944 6911 ) 6945 *22 6(Text6912 *225 (Text 6946 6913 uid 10028,0 6947 6914 va (VaSet … … 6988 6955 ) 6989 6956 ) 6990 *22 7(Net6957 *226 (Net 6991 6958 uid 10032,0 6992 6959 decl (Decl … … 7001 6968 font "Courier New,8,0" 7002 6969 ) 7003 xt "39000,5 3600,57500,54400"6970 xt "39000,54400,57500,55200" 7004 6971 st "SIGNAL CLK_25_PS1 : std_logic 7005 6972 " 7006 6973 ) 7007 6974 ) 7008 *22 8(Net6975 *227 (Net 7009 6976 uid 10050,0 7010 6977 decl (Decl … … 7020 6987 font "Courier New,8,0" 7021 6988 ) 7022 xt "39000,6 2400,71000,63200"6989 xt "39000,61600,71000,62400" 7023 6990 st "SIGNAL adc_clk_en : std_logic := '0' 7024 6991 " 7025 6992 ) 7026 6993 ) 7027 *22 9(PortIoOut6994 *228 (PortIoOut 7028 6995 uid 10296,0 7029 6996 shape (CompositeShape … … 7069 7036 ) 7070 7037 ) 7071 *2 30(Net7038 *229 (Net 7072 7039 uid 10308,0 7073 7040 decl (Decl … … 7084 7051 font "Courier New,8,0" 7085 7052 ) 7086 xt "39000,1 8200,73500,19000"7053 xt "39000,19000,73500,19800" 7087 7054 st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0') 7088 7055 " 7089 7056 ) 7090 7057 ) 7091 *23 1(HdlText7058 *230 (HdlText 7092 7059 uid 10310,0 7093 7060 optionalChildren [ 7094 *23 2(EmbeddedText7061 *231 (EmbeddedText 7095 7062 uid 10316,0 7096 7063 commentText (CommentText … … 7134 7101 A1_T(7) <= drs_channel_id(3); 7135 7102 7136 A0_T(5 downto 0) <= POSITION_ID;7103 A0_T(5 downto 0) <= (others => '0'); 7137 7104 A0_T(6) <= REFCLK; 7138 7105 A0_T(7) <= RS485_E_DI; … … 7166 7133 stg "VerticalLayoutStrategy" 7167 7134 textVec [ 7168 *23 3(Text7135 *232 (Text 7169 7136 uid 10313,0 7170 7137 va (VaSet … … 7176 7143 tm "HdlTextNameMgr" 7177 7144 ) 7178 *23 4(Text7145 *233 (Text 7179 7146 uid 10314,0 7180 7147 va (VaSet … … 7202 7169 viewiconposition 0 7203 7170 ) 7204 *23 5(Net7171 *234 (Net 7205 7172 uid 10496,0 7206 7173 decl (Decl … … 7215 7182 font "Courier New,8,0" 7216 7183 ) 7217 xt "39000,52 000,57500,52800"7184 xt "39000,52800,57500,53600" 7218 7185 st "SIGNAL CLK50_OUT : std_logic 7219 7186 " 7220 7187 ) 7221 7188 ) 7222 *23 6(Net7189 *235 (Net 7223 7190 uid 10504,0 7224 7191 decl (Decl … … 7233 7200 font "Courier New,8,0" 7234 7201 ) 7235 xt "39000,5 0400,57500,51200"7202 xt "39000,51200,57500,52000" 7236 7203 st "SIGNAL CLK25_OUT : std_logic 7237 7204 " 7238 7205 ) 7239 7206 ) 7240 *23 7(Net7207 *236 (Net 7241 7208 uid 10512,0 7242 7209 decl (Decl … … 7251 7218 font "Courier New,8,0" 7252 7219 ) 7253 xt "39000,5 1200,57500,52000"7220 xt "39000,52000,57500,52800" 7254 7221 st "SIGNAL CLK25_PSOUT : std_logic 7255 7222 " 7256 7223 ) 7257 7224 ) 7258 *23 8(Net7225 *237 (Net 7259 7226 uid 10520,0 7260 7227 decl (Decl … … 7274 7241 ) 7275 7242 ) 7276 *239 (Net 7277 uid 10528,0 7278 decl (Decl 7279 n "PS_DO_IN" 7280 t "std_logic" 7281 o 71 7282 suid 188,0 7283 ) 7284 declText (MLText 7285 uid 10529,0 7286 va (VaSet 7287 font "Courier New,8,0" 7288 ) 7289 xt "39000,60800,57500,61600" 7290 st "SIGNAL PS_DO_IN : std_logic 7291 " 7292 ) 7293 ) 7294 *240 (Net 7295 uid 10536,0 7296 decl (Decl 7297 n "PSEN_OUT" 7298 t "std_logic" 7299 o 68 7300 suid 189,0 7301 ) 7302 declText (MLText 7303 uid 10537,0 7304 va (VaSet 7305 font "Courier New,8,0" 7306 ) 7307 xt "39000,58400,57500,59200" 7308 st "SIGNAL PSEN_OUT : std_logic 7309 " 7310 ) 7311 ) 7312 *241 (Net 7243 *238 (Net 7313 7244 uid 10544,0 7314 7245 decl (Decl … … 7328 7259 ) 7329 7260 ) 7330 *2 42(Net7261 *239 (Net 7331 7262 uid 10552,0 7332 7263 decl (Decl … … 7343 7274 font "Courier New,8,0" 7344 7275 ) 7345 xt "39000,5 5200,57500,56000"7276 xt "39000,56000,57500,56800" 7346 7277 st "SIGNAL DCM_locked : std_logic 7347 7278 " 7348 7279 ) 7349 7280 ) 7350 *24 3(Net7281 *240 (Net 7351 7282 uid 10560,0 7352 7283 decl (Decl … … 7369 7300 ) 7370 7301 ) 7371 *24 4(Net7302 *241 (Net 7372 7303 uid 10568,0 7373 7304 decl (Decl … … 7392 7323 ) 7393 7324 ) 7394 *24 5(Net7325 *242 (Net 7395 7326 uid 10576,0 7396 7327 decl (Decl … … 7405 7336 font "Courier New,8,0" 7406 7337 ) 7407 xt "39000,5 7600,57500,58400"7338 xt "39000,58400,57500,59200" 7408 7339 st "SIGNAL PSDONE_extraOUT : std_logic 7409 7340 " 7410 7341 ) 7411 7342 ) 7412 *24 6(Net7343 *243 (Net 7413 7344 uid 10584,0 7414 7345 decl (Decl … … 7423 7354 font "Courier New,8,0" 7424 7355 ) 7425 xt "39000,5 6800,57500,57600"7356 xt "39000,57600,57500,58400" 7426 7357 st "SIGNAL PSCLK_OUT : std_logic 7427 7358 " 7428 7359 ) 7429 7360 ) 7430 *24 7(Net7361 *244 (Net 7431 7362 uid 10592,0 7432 7363 decl (Decl … … 7441 7372 font "Courier New,8,0" 7442 7373 ) 7443 xt "39000,56 000,57500,56800"7374 xt "39000,56800,57500,57600" 7444 7375 st "SIGNAL LOCKED_extraOUT : std_logic 7445 7376 " 7446 7377 ) 7447 7378 ) 7448 *24 8(PortIoIn7379 *245 (PortIoIn 7449 7380 uid 11090,0 7450 7381 shape (CompositeShape … … 7491 7422 ) 7492 7423 ) 7493 *24 9(Net7424 *246 (Net 7494 7425 uid 11102,0 7495 7426 decl (Decl … … 7504 7435 font "Courier New,8,0" 7505 7436 ) 7506 xt "39000,1 3400,54000,14200"7437 xt "39000,14200,54000,15000" 7507 7438 st "RS485_C_DI : std_logic 7508 7439 " 7509 7440 ) 7510 7441 ) 7511 *2 50(PortIoOut7442 *247 (PortIoOut 7512 7443 uid 11104,0 7513 7444 shape (CompositeShape … … 7553 7484 ) 7554 7485 ) 7555 *2 51(Net7486 *248 (Net 7556 7487 uid 11116,0 7557 7488 decl (Decl … … 7566 7497 font "Courier New,8,0" 7567 7498 ) 7568 xt "39000,3 4200,54000,35000"7499 xt "39000,35000,54000,35800" 7569 7500 st "RS485_C_DO : std_logic 7570 7501 " 7571 7502 ) 7572 7503 ) 7573 *2 52(PortIoIn7504 *249 (PortIoIn 7574 7505 uid 11508,0 7575 7506 shape (CompositeShape … … 7616 7547 ) 7617 7548 ) 7618 *25 3(Net7549 *250 (Net 7619 7550 uid 11520,0 7620 7551 decl (Decl … … 7629 7560 font "Courier New,8,0" 7630 7561 ) 7631 xt "39000,1 4200,54000,15000"7562 xt "39000,15000,54000,15800" 7632 7563 st "RS485_E_DI : std_logic 7633 7564 " 7634 7565 ) 7635 7566 ) 7636 *25 4(Net7567 *251 (Net 7637 7568 uid 11534,0 7638 7569 decl (Decl … … 7647 7578 font "Courier New,8,0" 7648 7579 ) 7649 xt "39000,15 000,54000,15800"7580 xt "39000,15800,54000,16600" 7650 7581 st "RS485_E_DO : std_logic 7651 7582 " 7652 7583 ) 7653 7584 ) 7654 *25 5(PortIoIn7585 *252 (PortIoIn 7655 7586 uid 11922,0 7656 7587 shape (CompositeShape … … 7697 7628 ) 7698 7629 ) 7699 *25 6(PortIoOut7630 *253 (PortIoOut 7700 7631 uid 12326,0 7701 7632 shape (CompositeShape … … 7741 7672 ) 7742 7673 ) 7743 *25 7(Net7674 *254 (Net 7744 7675 uid 12334,0 7745 7676 decl (Decl … … 7755 7686 font "Courier New,8,0" 7756 7687 ) 7757 xt "39000,3 8200,67500,39000"7688 xt "39000,39000,67500,39800" 7758 7689 st "SRIN : std_logic := '0' 7759 7690 " 7760 7691 ) 7761 7692 ) 7762 *25 8(PortIoOut7693 *255 (PortIoOut 7763 7694 uid 12539,0 7764 7695 shape (CompositeShape … … 7804 7735 ) 7805 7736 ) 7806 *25 9(PortIoOut7737 *256 (PortIoOut 7807 7738 uid 12553,0 7808 7739 shape (CompositeShape … … 7848 7779 ) 7849 7780 ) 7850 *2 60(PortIoOut7781 *257 (PortIoOut 7851 7782 uid 12567,0 7852 7783 shape (CompositeShape … … 7892 7823 ) 7893 7824 ) 7894 *2 61(Net7825 *258 (Net 7895 7826 uid 12762,0 7896 7827 decl (Decl … … 7905 7836 font "Courier New,8,0" 7906 7837 ) 7907 xt "39000, 19800,54000,20600"7838 xt "39000,20600,54000,21400" 7908 7839 st "AMBER_LED : std_logic 7909 7840 " 7910 7841 ) 7911 7842 ) 7912 *2 62(Net7843 *259 (Net 7913 7844 uid 12764,0 7914 7845 decl (Decl … … 7923 7854 font "Courier New,8,0" 7924 7855 ) 7925 xt "39000,3 0200,54000,31000"7856 xt "39000,31000,54000,31800" 7926 7857 st "GREEN_LED : std_logic 7927 7858 " 7928 7859 ) 7929 7860 ) 7930 *26 3(Net7861 *260 (Net 7931 7862 uid 12766,0 7932 7863 decl (Decl … … 7941 7872 font "Courier New,8,0" 7942 7873 ) 7943 xt "39000,3 2600,54000,33400"7874 xt "39000,33400,54000,34200" 7944 7875 st "RED_LED : std_logic 7945 7876 " 7946 7877 ) 7947 7878 ) 7948 *26 4(PortIoIn7879 *261 (PortIoIn 7949 7880 uid 13516,0 7950 7881 shape (CompositeShape … … 7959 7890 sl 0 7960 7891 ro 270 7961 xt "1 10000,147625,111500,148375"7892 xt "10000,80625,11500,81375" 7962 7893 ) 7963 7894 (Line … … 7965 7896 sl 0 7966 7897 ro 270 7967 xt "11 1500,148000,112000,148000"7968 pts [ 7969 "11 1500,148000"7970 "1 12000,148000"7898 xt "11500,81000,12000,81000" 7899 pts [ 7900 "11500,81000" 7901 "12000,81000" 7971 7902 ] 7972 7903 ) … … 7983 7914 va (VaSet 7984 7915 ) 7985 xt " 103300,147500,109000,148500"7986 st " POSITION_ID"7916 xt "6900,80500,9000,81500" 7917 st "LINE" 7987 7918 ju 2 7988 blo " 109000,148300"7989 tm "WireNameMgr" 7990 ) 7991 ) 7992 ) 7993 *26 5(Net7919 blo "9000,81300" 7920 tm "WireNameMgr" 7921 ) 7922 ) 7923 ) 7924 *262 (Net 7994 7925 uid 13528,0 7995 7926 decl (Decl 7996 n " POSITION_ID"7927 n "LINE" 7997 7928 t "std_logic_vector" 7998 7929 b "( 5 DOWNTO 0 )" … … 8005 7936 font "Courier New,8,0" 8006 7937 ) 8007 xt "39000,1 1800,65000,12600"8008 st " POSITION_ID: std_logic_vector( 5 DOWNTO 0 )7938 xt "39000,12600,65000,13400" 7939 st "LINE : std_logic_vector( 5 DOWNTO 0 ) 8009 7940 " 8010 7941 ) 8011 7942 ) 8012 *26 6(PortIoIn7943 *263 (PortIoIn 8013 7944 uid 13628,0 8014 7945 shape (CompositeShape … … 8055 7986 ) 8056 7987 ) 8057 *26 7(Net7988 *264 (Net 8058 7989 uid 13640,0 8059 7990 decl (Decl … … 8068 7999 font "Courier New,8,0" 8069 8000 ) 8070 xt "39000,1 2600,54000,13400"8001 xt "39000,13400,54000,14200" 8071 8002 st "REFCLK : std_logic 8072 8003 " 8073 8004 ) 8074 8005 ) 8075 *268 (Wire 8006 *265 (PortIoIn 8007 uid 14322,0 8008 shape (CompositeShape 8009 uid 14323,0 8010 va (VaSet 8011 vasetType 1 8012 fg "0,0,32768" 8013 ) 8014 optionalChildren [ 8015 (Pentagon 8016 uid 14324,0 8017 sl 0 8018 ro 270 8019 xt "37000,138625,38500,139375" 8020 ) 8021 (Line 8022 uid 14325,0 8023 sl 0 8024 ro 270 8025 xt "38500,139000,39000,139000" 8026 pts [ 8027 "38500,139000" 8028 "39000,139000" 8029 ] 8030 ) 8031 ] 8032 ) 8033 stc 0 8034 sf 1 8035 tg (WTG 8036 uid 14326,0 8037 ps "PortIoTextPlaceStrategy" 8038 stg "STSignalDisplayStrategy" 8039 f (Text 8040 uid 14327,0 8041 va (VaSet 8042 ) 8043 xt "33100,138500,36000,139500" 8044 st "D_T_in" 8045 ju 2 8046 blo "36000,139300" 8047 tm "WireNameMgr" 8048 ) 8049 ) 8050 ) 8051 *266 (Net 8052 uid 14334,0 8053 decl (Decl 8054 n "D_T_in" 8055 t "std_logic_vector" 8056 b "(1 DOWNTO 0)" 8057 o 80 8058 suid 213,0 8059 ) 8060 declText (MLText 8061 uid 14335,0 8062 va (VaSet 8063 font "Courier New,8,0" 8064 ) 8065 xt "39000,11800,64000,12600" 8066 st "D_T_in : std_logic_vector(1 DOWNTO 0) 8067 " 8068 ) 8069 ) 8070 *267 (HdlText 8071 uid 14346,0 8072 optionalChildren [ 8073 *268 (EmbeddedText 8074 uid 14352,0 8075 commentText (CommentText 8076 uid 14353,0 8077 ps "CenterOffsetStrategy" 8078 shape (Rectangle 8079 uid 14354,0 8080 va (VaSet 8081 vasetType 1 8082 fg "65535,65535,65535" 8083 lineColor "0,0,32768" 8084 lineWidth 2 8085 ) 8086 xt "63000,156000,76000,169000" 8087 ) 8088 oxt "0,0,18000,5000" 8089 text (MLText 8090 uid 14355,0 8091 va (VaSet 8092 ) 8093 xt "63200,156200,76000,158200" 8094 st " 8095 D_T(5 downto 0) <= led (5 downto 0); 8096 " 8097 tm "HdlTextMgr" 8098 wrapOption 3 8099 visibleHeight 13000 8100 visibleWidth 13000 8101 ) 8102 ) 8103 ) 8104 ] 8105 shape (Rectangle 8106 uid 14347,0 8107 va (VaSet 8108 vasetType 1 8109 fg "65535,65535,37120" 8110 lineColor "0,0,32768" 8111 lineWidth 2 8112 ) 8113 xt "66000,153000,70000,156000" 8114 ) 8115 oxt "0,0,8000,10000" 8116 ttg (MlTextGroup 8117 uid 14348,0 8118 ps "CenterOffsetStrategy" 8119 stg "VerticalLayoutStrategy" 8120 textVec [ 8121 *269 (Text 8122 uid 14349,0 8123 va (VaSet 8124 font "Arial,8,1" 8125 ) 8126 xt "68150,153000,69850,154000" 8127 st "eb1" 8128 blo "68150,153800" 8129 tm "HdlTextNameMgr" 8130 ) 8131 *270 (Text 8132 uid 14350,0 8133 va (VaSet 8134 font "Arial,8,1" 8135 ) 8136 xt "68150,154000,68950,155000" 8137 st "7" 8138 blo "68150,154800" 8139 tm "HdlTextNumberMgr" 8140 ) 8141 ] 8142 ) 8143 viewicon (ZoomableIcon 8144 uid 14351,0 8145 sl 0 8146 va (VaSet 8147 vasetType 1 8148 fg "49152,49152,49152" 8149 ) 8150 xt "66250,154250,67750,155750" 8151 iconName "TextFile.png" 8152 iconMaskName "TextFile.msk" 8153 ftype 21 8154 ) 8155 viewiconposition 0 8156 ) 8157 *271 (Net 8158 uid 15173,0 8159 decl (Decl 8160 n "led" 8161 t "std_logic_vector" 8162 b "(7 DOWNTO 0)" 8163 posAdd 0 8164 o 81 8165 suid 215,0 8166 i "(OTHERS => '0')" 8167 ) 8168 declText (MLText 8169 uid 15174,0 8170 va (VaSet 8171 font "Courier New,8,0" 8172 ) 8173 xt "39000,66400,77000,67200" 8174 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 8175 " 8176 ) 8177 ) 8178 *272 (Wire 8076 8179 uid 245,0 8077 8180 shape (OrthoPolyLine … … 8087 8190 ) 8088 8191 start &27 8089 end &6 88192 end &67 8090 8193 ss 0 8091 8194 sat 32 … … 8110 8213 ) 8111 8214 ) 8112 on &8 98113 ) 8114 *2 69(Wire8215 on &88 8216 ) 8217 *273 (Wire 8115 8218 uid 277,0 8116 8219 shape (OrthoPolyLine … … 8127 8230 ) 8128 8231 start &17 8129 end &6 98232 end &68 8130 8233 sat 32 8131 8234 eat 2 … … 8148 8251 ) 8149 8252 ) 8150 on &7 38151 ) 8152 *27 0(Wire8253 on &72 8254 ) 8255 *274 (Wire 8153 8256 uid 285,0 8154 8257 shape (OrthoPolyLine … … 8165 8268 ) 8166 8269 start &18 8167 end &6 98270 end &68 8168 8271 sat 32 8169 8272 eat 2 … … 8186 8289 ) 8187 8290 ) 8188 on &7 48189 ) 8190 *27 1(Wire8291 on &73 8292 ) 8293 *275 (Wire 8191 8294 uid 362,0 8192 8295 shape (OrthoPolyLine … … 8201 8304 ] 8202 8305 ) 8203 start &9 78306 start &96 8204 8307 end &16 8205 8308 sat 32 … … 8224 8327 ) 8225 8328 ) 8226 on &9 88227 ) 8228 *27 2(Wire8329 on &97 8330 ) 8331 *276 (Wire 8229 8332 uid 418,0 8230 8333 shape (OrthoPolyLine … … 8240 8343 ) 8241 8344 start &13 8242 end &7 58345 end &74 8243 8346 sat 32 8244 8347 eat 32 … … 8262 8365 ) 8263 8366 ) 8264 on &1 508265 ) 8266 *27 3(Wire8367 on &149 8368 ) 8369 *277 (Wire 8267 8370 uid 426,0 8268 8371 shape (OrthoPolyLine … … 8279 8382 ) 8280 8383 start &19 8281 end &7 68384 end &75 8282 8385 sat 32 8283 8386 eat 32 … … 8302 8405 ) 8303 8406 ) 8304 on &14 88305 ) 8306 *27 4(Wire8407 on &147 8408 ) 8409 *278 (Wire 8307 8410 uid 434,0 8308 8411 shape (OrthoPolyLine … … 8318 8421 ) 8319 8422 start &20 8320 end &7 78423 end &76 8321 8424 sat 32 8322 8425 eat 32 … … 8340 8443 ) 8341 8444 ) 8342 on &15 48343 ) 8344 *27 5(Wire8445 on &153 8446 ) 8447 *279 (Wire 8345 8448 uid 442,0 8346 8449 shape (OrthoPolyLine … … 8357 8460 ) 8358 8461 start &21 8359 end &7 88462 end &77 8360 8463 sat 32 8361 8464 eat 32 … … 8380 8483 ) 8381 8484 ) 8382 on &14 98383 ) 8384 *2 76(Wire8485 on &148 8486 ) 8487 *280 (Wire 8385 8488 uid 450,0 8386 8489 shape (OrthoPolyLine … … 8395 8498 ] 8396 8499 ) 8397 start &7 98500 start &78 8398 8501 end &22 8399 8502 sat 32 … … 8418 8521 ) 8419 8522 ) 8420 on &15 38421 ) 8422 *2 77(Wire8523 on &152 8524 ) 8525 *281 (Wire 8423 8526 uid 458,0 8424 8527 shape (OrthoPolyLine … … 8434 8537 ) 8435 8538 start &23 8539 end &79 8540 sat 32 8541 eat 32 8542 stc 0 8543 st 0 8544 sf 1 8545 si 0 8546 tg (WTG 8547 uid 462,0 8548 ps "ConnStartEndStrategy" 8549 stg "STSignalDisplayStrategy" 8550 f (Text 8551 uid 463,0 8552 va (VaSet 8553 isHidden 1 8554 ) 8555 xt "82000,71000,84700,72000" 8556 st "W_RD" 8557 blo "82000,71800" 8558 tm "WireNameMgr" 8559 ) 8560 ) 8561 on &150 8562 ) 8563 *282 (Wire 8564 uid 466,0 8565 shape (OrthoPolyLine 8566 uid 467,0 8567 va (VaSet 8568 vasetType 3 8569 ) 8570 xt "80750,73000,111000,73000" 8571 pts [ 8572 "80750,73000" 8573 "111000,73000" 8574 ] 8575 ) 8576 start &24 8436 8577 end &80 8437 8578 sat 32 … … 8442 8583 si 0 8443 8584 tg (WTG 8444 uid 462,08445 ps "ConnStartEndStrategy"8446 stg "STSignalDisplayStrategy"8447 f (Text8448 uid 463,08449 va (VaSet8450 isHidden 18451 )8452 xt "82000,71000,84700,72000"8453 st "W_RD"8454 blo "82000,71800"8455 tm "WireNameMgr"8456 )8457 )8458 on &1518459 )8460 *278 (Wire8461 uid 466,08462 shape (OrthoPolyLine8463 uid 467,08464 va (VaSet8465 vasetType 38466 )8467 xt "80750,73000,111000,73000"8468 pts [8469 "80750,73000"8470 "111000,73000"8471 ]8472 )8473 start &248474 end &818475 sat 328476 eat 328477 stc 08478 st 08479 sf 18480 si 08481 tg (WTG8482 8585 uid 470,0 8483 8586 ps "ConnStartEndStrategy" … … 8494 8597 ) 8495 8598 ) 8496 on &15 28497 ) 8498 *2 79(Wire8599 on &151 8600 ) 8601 *283 (Wire 8499 8602 uid 1467,0 8500 8603 shape (OrthoPolyLine … … 8509 8612 ] 8510 8613 ) 8511 start &10 18614 start &100 8512 8615 end &28 8513 8616 sat 2 … … 8530 8633 ) 8531 8634 ) 8532 on &8 28533 ) 8534 *28 0(Wire8635 on &81 8636 ) 8637 *284 (Wire 8535 8638 uid 1730,0 8536 8639 shape (OrthoPolyLine … … 8546 8649 ] 8547 8650 ) 8548 start &9 98651 start &98 8549 8652 end &29 8550 8653 sat 32 … … 8570 8673 ) 8571 8674 ) 8572 on & 1008573 ) 8574 *28 1(Wire8675 on &99 8676 ) 8677 *285 (Wire 8575 8678 uid 1833,0 8576 8679 shape (OrthoPolyLine … … 8586 8689 ] 8587 8690 ) 8588 start &18 78589 end &12 98691 start &186 8692 end &128 8590 8693 sat 2 8591 8694 eat 32 … … 8610 8713 ) 8611 8714 ) 8612 on &1 308613 ) 8614 *28 2(Wire8715 on &129 8716 ) 8717 *286 (Wire 8615 8718 uid 1841,0 8616 8719 shape (OrthoPolyLine … … 8626 8729 ) 8627 8730 start &31 8628 end &13 18731 end &130 8629 8732 sat 32 8630 8733 eat 32 … … 8648 8751 ) 8649 8752 ) 8650 on &13 28651 ) 8652 *28 3(Wire8753 on &131 8754 ) 8755 *287 (Wire 8653 8756 uid 1865,0 8654 8757 shape (OrthoPolyLine … … 8663 8766 ] 8664 8767 ) 8665 start &12 18768 start &120 8666 8769 end &32 8667 8770 sat 32 … … 8686 8789 ) 8687 8790 ) 8688 on &12 58689 ) 8690 *28 4(Wire8791 on &124 8792 ) 8793 *288 (Wire 8691 8794 uid 1873,0 8692 8795 shape (OrthoPolyLine … … 8701 8804 ] 8702 8805 ) 8703 start &12 28806 start &121 8704 8807 end &33 8705 8808 sat 32 … … 8724 8827 ) 8725 8828 ) 8726 on &12 68727 ) 8728 *28 5(Wire8829 on &125 8830 ) 8831 *289 (Wire 8729 8832 uid 1881,0 8730 8833 shape (OrthoPolyLine … … 8739 8842 ] 8740 8843 ) 8741 start &12 38844 start &122 8742 8845 end &34 8743 8846 sat 32 … … 8762 8865 ) 8763 8866 ) 8764 on &12 78765 ) 8766 *2 86(Wire8867 on &126 8868 ) 8869 *290 (Wire 8767 8870 uid 1889,0 8768 8871 shape (OrthoPolyLine … … 8777 8880 ] 8778 8881 ) 8779 start &12 48882 start &123 8780 8883 end &35 8781 8884 sat 32 … … 8800 8903 ) 8801 8904 ) 8802 on &12 88803 ) 8804 *2 87(Wire8905 on &127 8906 ) 8907 *291 (Wire 8805 8908 uid 2409,0 8806 8909 shape (OrthoPolyLine … … 8816 8919 ) 8817 8920 start &36 8818 end &8 48921 end &83 8819 8922 sat 32 8820 8923 eat 32 … … 8838 8941 ) 8839 8942 ) 8840 on &8 38841 ) 8842 *2 88(Wire8943 on &82 8944 ) 8945 *292 (Wire 8843 8946 uid 2423,0 8844 8947 shape (OrthoPolyLine … … 8854 8957 ) 8855 8958 start &37 8856 end &11 38959 end &112 8857 8960 sat 32 8858 8961 eat 1 … … 8876 8979 ) 8877 8980 ) 8878 on &8 58879 ) 8880 *2 89(Wire8981 on &84 8982 ) 8983 *293 (Wire 8881 8984 uid 3009,0 8882 8985 shape (OrthoPolyLine … … 8892 8995 ) 8893 8996 start &39 8894 end &14 68997 end &145 8895 8998 sat 32 8896 8999 eat 32 … … 8914 9017 ) 8915 9018 ) 8916 on &14 78917 ) 8918 *29 0(Wire9019 on &146 9020 ) 9021 *294 (Wire 8919 9022 uid 3015,0 8920 9023 shape (OrthoPolyLine … … 8930 9033 ) 8931 9034 start &41 8932 end &15 59035 end &154 8933 9036 sat 32 8934 9037 eat 32 … … 8952 9055 ) 8953 9056 ) 8954 on &15 88955 ) 8956 *29 1(Wire9057 on &157 9058 ) 9059 *295 (Wire 8957 9060 uid 3021,0 8958 9061 shape (OrthoPolyLine … … 8969 9072 ) 8970 9073 start &40 8971 end &13 49074 end &133 8972 9075 sat 32 8973 9076 eat 1 … … 8990 9093 ) 8991 9094 ) 8992 on &8 68993 ) 8994 *29 2(Wire9095 on &85 9096 ) 9097 *296 (Wire 8995 9098 uid 3027,0 8996 9099 shape (OrthoPolyLine … … 9005 9108 ] 9006 9109 ) 9007 start &19 79008 end &13 39110 start &196 9111 end &132 9009 9112 ss 0 9010 9113 sat 32 … … 9029 9132 ) 9030 9133 ) 9031 on &8 79032 ) 9033 *29 3(Wire9134 on &86 9135 ) 9136 *297 (Wire 9034 9137 uid 3218,0 9035 9138 shape (OrthoPolyLine … … 9044 9147 ] 9045 9148 ) 9046 start &6 79149 start &66 9047 9150 end &15 9048 9151 sat 32 … … 9067 9170 ) 9068 9171 ) 9069 on & 909070 ) 9071 *29 4(Wire9172 on &89 9173 ) 9174 *298 (Wire 9072 9175 uid 3260,0 9073 9176 shape (OrthoPolyLine … … 9083 9186 ] 9084 9187 ) 9085 start &8 89086 end &9 19188 start &87 9189 end &90 9087 9190 sat 32 9088 9191 eat 2 … … 9107 9210 ) 9108 9211 ) 9109 on &9 59110 ) 9111 *29 5(Wire9212 on &94 9213 ) 9214 *299 (Wire 9112 9215 uid 3270,0 9113 9216 shape (OrthoPolyLine … … 9124 9227 ] 9125 9228 ) 9126 start &2 109127 end &9 19229 start &209 9230 end &90 9128 9231 sat 32 9129 9232 eat 1 … … 9145 9248 ) 9146 9249 ) 9147 on &9 69148 ) 9149 * 296(Wire9250 on &95 9251 ) 9252 *300 (Wire 9150 9253 uid 3318,0 9151 9254 shape (OrthoPolyLine … … 9161 9264 ] 9162 9265 ) 9163 start &10 59164 end &10 19266 start &104 9267 end &100 9165 9268 sat 32 9166 9269 eat 1 … … 9185 9288 ) 9186 9289 ) 9187 on &10 99188 ) 9189 * 297(Wire9290 on &108 9291 ) 9292 *301 (Wire 9190 9293 uid 3352,0 9191 9294 shape (OrthoPolyLine … … 9201 9304 ] 9202 9305 ) 9203 start &10 69204 end &10 19306 start &105 9307 end &100 9205 9308 sat 32 9206 9309 eat 1 … … 9225 9328 ) 9226 9329 ) 9227 on &1 109228 ) 9229 * 298(Wire9330 on &109 9331 ) 9332 *302 (Wire 9230 9333 uid 3360,0 9231 9334 shape (OrthoPolyLine … … 9241 9344 ] 9242 9345 ) 9243 start &10 79244 end &10 19346 start &106 9347 end &100 9245 9348 sat 32 9246 9349 eat 1 … … 9265 9368 ) 9266 9369 ) 9267 on &11 19268 ) 9269 * 299(Wire9370 on &110 9371 ) 9372 *303 (Wire 9270 9373 uid 3368,0 9271 9374 shape (OrthoPolyLine … … 9281 9384 ] 9282 9385 ) 9283 start &10 89284 end &10 19386 start &107 9387 end &100 9285 9388 sat 32 9286 9389 eat 1 … … 9305 9408 ) 9306 9409 ) 9307 on &11 29308 ) 9309 *30 0(Wire9410 on &111 9411 ) 9412 *304 (Wire 9310 9413 uid 3430,0 9311 9414 shape (OrthoPolyLine … … 9320 9423 ] 9321 9424 ) 9322 start &17 79323 end &11 39425 start &176 9426 end &112 9324 9427 sat 32 9325 9428 eat 2 … … 9343 9446 ) 9344 9447 ) 9345 on &11 79346 ) 9347 *30 1(Wire9448 on &116 9449 ) 9450 *305 (Wire 9348 9451 uid 3438,0 9349 9452 shape (OrthoPolyLine … … 9358 9461 ] 9359 9462 ) 9360 start &17 89361 end &11 39463 start &177 9464 end &112 9362 9465 sat 32 9363 9466 eat 2 … … 9381 9484 ) 9382 9485 ) 9383 on &11 89384 ) 9385 *30 2(Wire9486 on &117 9487 ) 9488 *306 (Wire 9386 9489 uid 3446,0 9387 9490 shape (OrthoPolyLine … … 9396 9499 ] 9397 9500 ) 9398 start &17 99399 end &11 39501 start &178 9502 end &112 9400 9503 sat 32 9401 9504 eat 2 … … 9419 9522 ) 9420 9523 ) 9421 on &11 99422 ) 9423 *30 3(Wire9524 on &118 9525 ) 9526 *307 (Wire 9424 9527 uid 3454,0 9425 9528 shape (OrthoPolyLine … … 9434 9537 ] 9435 9538 ) 9436 start &1 809437 end &11 39539 start &179 9540 end &112 9438 9541 sat 32 9439 9542 eat 2 … … 9457 9560 ) 9458 9561 ) 9459 on &1 209460 ) 9461 *30 4(Wire9562 on &119 9563 ) 9564 *308 (Wire 9462 9565 uid 3574,0 9463 9566 shape (OrthoPolyLine … … 9472 9575 ] 9473 9576 ) 9474 start &13 89475 end &13 49577 start &137 9578 end &133 9476 9579 sat 32 9477 9580 eat 2 … … 9495 9598 ) 9496 9599 ) 9497 on &14 29498 ) 9499 *30 5(Wire9600 on &141 9601 ) 9602 *309 (Wire 9500 9603 uid 3582,0 9501 9604 shape (OrthoPolyLine … … 9510 9613 ] 9511 9614 ) 9512 start &13 99513 end &13 49615 start &138 9616 end &133 9514 9617 sat 32 9515 9618 eat 2 … … 9533 9636 ) 9534 9637 ) 9535 on &14 39536 ) 9537 *3 06(Wire9638 on &142 9639 ) 9640 *310 (Wire 9538 9641 uid 3590,0 9539 9642 shape (OrthoPolyLine … … 9548 9651 ] 9549 9652 ) 9550 start &1 409551 end &13 49653 start &139 9654 end &133 9552 9655 sat 32 9553 9656 eat 2 … … 9571 9674 ) 9572 9675 ) 9573 on &14 49574 ) 9575 *3 07(Wire9676 on &143 9677 ) 9678 *311 (Wire 9576 9679 uid 3598,0 9577 9680 shape (OrthoPolyLine … … 9586 9689 ] 9587 9690 ) 9588 start &14 19589 end &13 49691 start &140 9692 end &133 9590 9693 sat 32 9591 9694 eat 2 … … 9609 9712 ) 9610 9713 ) 9611 on &14 59612 ) 9613 *3 08(Wire9714 on &144 9715 ) 9716 *312 (Wire 9614 9717 uid 3682,0 9615 9718 shape (OrthoPolyLine … … 9625 9728 ) 9626 9729 start &42 9627 end &15 79730 end &156 9628 9731 sat 32 9629 9732 eat 32 … … 9647 9750 ) 9648 9751 ) 9649 on &15 69650 ) 9651 *3 09(Wire9752 on &155 9753 ) 9754 *313 (Wire 9652 9755 uid 3778,0 9653 9756 shape (OrthoPolyLine … … 9662 9765 ] 9663 9766 ) 9664 start &16 39665 end &6 39767 start &162 9768 end &61 9666 9769 es 0 9667 9770 sat 32 … … 9686 9789 ) 9687 9790 ) 9688 on &1 709689 ) 9690 *31 0(Wire9791 on &169 9792 ) 9793 *314 (Wire 9691 9794 uid 3786,0 9692 9795 shape (OrthoPolyLine … … 9701 9804 ] 9702 9805 ) 9703 start &16 49704 end &15 99806 start &163 9807 end &158 9705 9808 sat 32 9706 9809 eat 2 … … 9724 9827 ) 9725 9828 ) 9726 on &17 19727 ) 9728 *31 1(Wire9829 on &170 9830 ) 9831 *315 (Wire 9729 9832 uid 3794,0 9730 9833 shape (OrthoPolyLine … … 9739 9842 ] 9740 9843 ) 9741 start &16 59742 end &15 99844 start &164 9845 end &158 9743 9846 sat 32 9744 9847 eat 2 … … 9762 9865 ) 9763 9866 ) 9764 on &17 29765 ) 9766 *31 2(Wire9867 on &171 9868 ) 9869 *316 (Wire 9767 9870 uid 3802,0 9768 9871 shape (OrthoPolyLine … … 9775 9878 "139000,150000" 9776 9879 "136000,150000" 9880 ] 9881 ) 9882 start &165 9883 sat 32 9884 eat 16 9885 stc 0 9886 st 0 9887 sf 1 9888 si 0 9889 tg (WTG 9890 uid 3806,0 9891 ps "ConnStartEndStrategy" 9892 stg "STSignalDisplayStrategy" 9893 f (Text 9894 uid 3807,0 9895 va (VaSet 9896 isHidden 1 9897 ) 9898 xt "136000,149000,141500,150000" 9899 st "RS485_E_RE" 9900 blo "136000,149800" 9901 tm "WireNameMgr" 9902 ) 9903 ) 9904 on &172 9905 ) 9906 *317 (Wire 9907 uid 3810,0 9908 shape (OrthoPolyLine 9909 uid 3811,0 9910 va (VaSet 9911 vasetType 3 9912 ) 9913 xt "134000,149000,137000,149000" 9914 pts [ 9915 "137000,149000" 9916 "134000,149000" 9777 9917 ] 9778 9918 ) … … 9785 9925 si 0 9786 9926 tg (WTG 9787 uid 3806,09788 ps "ConnStartEndStrategy"9789 stg "STSignalDisplayStrategy"9790 f (Text9791 uid 3807,09792 va (VaSet9793 isHidden 19794 )9795 xt "136000,149000,141500,150000"9796 st "RS485_E_RE"9797 blo "136000,149800"9798 tm "WireNameMgr"9799 )9800 )9801 on &1739802 )9803 *313 (Wire9804 uid 3810,09805 shape (OrthoPolyLine9806 uid 3811,09807 va (VaSet9808 vasetType 39809 )9810 xt "134000,149000,137000,149000"9811 pts [9812 "137000,149000"9813 "134000,149000"9814 ]9815 )9816 start &1679817 sat 329818 eat 169819 stc 09820 st 09821 sf 19822 si 09823 tg (WTG9824 9927 uid 3814,0 9825 9928 ps "ConnStartEndStrategy" … … 9836 9939 ) 9837 9940 ) 9838 on &17 49839 ) 9840 *31 4(Wire9941 on &173 9942 ) 9943 *318 (Wire 9841 9944 uid 3834,0 9842 9945 shape (OrthoPolyLine … … 9851 9954 ] 9852 9955 ) 9853 start &16 99854 end &15 99956 start &168 9957 end &158 9855 9958 sat 32 9856 9959 eat 2 … … 9874 9977 ) 9875 9978 ) 9876 on &17 69877 ) 9878 *31 5(Wire9979 on &175 9980 ) 9981 *319 (Wire 9879 9982 uid 4942,0 9880 9983 shape (OrthoPolyLine … … 9884 9987 lineWidth 2 9885 9988 ) 9886 xt " 80750,120000,111000,120000"9887 pts [ 9888 " 80750,120000"9889 " 111000,120000"9890 ] 9891 ) 9892 start & 149893 end &18 19894 sat 329989 xt "70000,154000,72000,154000" 9990 pts [ 9991 "70000,154000" 9992 "72000,154000" 9993 ] 9994 ) 9995 start &267 9996 end &180 9997 sat 2 9895 9998 eat 32 9896 9999 sty 1 … … 9908 10011 isHidden 1 9909 10012 ) 9910 xt " 82750,117000,84650,118000"10013 xt "71750,151000,73650,152000" 9911 10014 st "D_T" 9912 blo " 82750,117800"9913 tm "WireNameMgr" 9914 ) 9915 ) 9916 on &18 29917 ) 9918 *3 16(Wire10015 blo "71750,151800" 10016 tm "WireNameMgr" 10017 ) 10018 ) 10019 on &181 10020 ) 10021 *320 (Wire 9919 10022 uid 6431,0 9920 10023 shape (OrthoPolyLine … … 9930 10033 ) 9931 10034 start &43 9932 end &16 810035 end &167 9933 10036 sat 32 9934 10037 eat 32 … … 9952 10055 ) 9953 10056 ) 9954 on &17 59955 ) 9956 *3 17(Wire10057 on &174 10058 ) 10059 *321 (Wire 9957 10060 uid 7144,0 9958 10061 shape (OrthoPolyLine … … 9968 10071 ] 9969 10072 ) 9970 start &23 19971 end &19 110073 start &230 10074 end &190 9972 10075 sat 2 9973 10076 eat 32 … … 9991 10094 ) 9992 10095 ) 9993 on &19 29994 ) 9995 *3 18(Wire10096 on &191 10097 ) 10098 *322 (Wire 9996 10099 uid 7477,0 9997 10100 shape (OrthoPolyLine … … 10007 10110 ) 10008 10111 start &38 10009 end &19 510112 end &194 10010 10113 es 0 10011 10114 sat 32 … … 10028 10131 ) 10029 10132 ) 10030 on &19 310031 ) 10032 *3 19(Wire10133 on &192 10134 ) 10135 *323 (Wire 10033 10136 uid 8853,0 10034 10137 shape (OrthoPolyLine … … 10047 10150 ) 10048 10151 start &30 10049 end &18 710152 end &186 10050 10153 sat 32 10051 10154 eat 1 … … 10068 10171 ) 10069 10172 ) 10070 on &20 710071 ) 10072 *32 0(Wire10173 on &206 10174 ) 10175 *324 (Wire 10073 10176 uid 9502,0 10074 10177 shape (OrthoPolyLine … … 10103 10206 ) 10104 10207 ) 10105 on &20 810106 ) 10107 *32 1(Wire10208 on &207 10209 ) 10210 *325 (Wire 10108 10211 uid 10034,0 10109 10212 shape (OrthoPolyLine … … 10120 10223 ) 10121 10224 start &25 10122 end &21 510225 end &214 10123 10226 sat 32 10124 10227 eat 32 … … 10141 10244 ) 10142 10245 ) 10143 on &22 710144 ) 10145 *32 2(Wire10246 on &226 10247 ) 10248 *326 (Wire 10146 10249 uid 10052,0 10147 10250 shape (OrthoPolyLine … … 10157 10260 ) 10158 10261 start &44 10159 end &21 310262 end &212 10160 10263 sat 32 10161 10264 eat 32 … … 10178 10281 ) 10179 10282 ) 10180 on &22 810181 ) 10182 *32 3(Wire10283 on &227 10284 ) 10285 *327 (Wire 10183 10286 uid 10302,0 10184 10287 shape (OrthoPolyLine … … 10194 10297 ] 10195 10298 ) 10196 start &23 110197 end &22 910299 start &230 10300 end &228 10198 10301 sat 2 10199 10302 eat 32 … … 10217 10320 ) 10218 10321 ) 10219 on &2 3010220 ) 10221 *32 4(Wire10322 on &229 10323 ) 10324 *328 (Wire 10222 10325 uid 10498,0 10223 10326 shape (OrthoPolyLine … … 10230 10333 "80750,123000" 10231 10334 "88000,123000" 10232 ]10233 )10234 start &5810235 sat 3210236 eat 1610237 st 010238 sf 110239 si 010240 tg (WTG10241 uid 10502,010242 ps "ConnStartEndStrategy"10243 stg "STSignalDisplayStrategy"10244 f (Text10245 uid 10503,010246 va (VaSet10247 )10248 xt "82000,122000,86800,123000"10249 st "CLK50_OUT"10250 blo "82000,122800"10251 tm "WireNameMgr"10252 )10253 )10254 on &23510255 )10256 *325 (Wire10257 uid 10506,010258 shape (OrthoPolyLine10259 uid 10507,010260 va (VaSet10261 vasetType 310262 )10263 xt "80750,124000,88000,124000"10264 pts [10265 "80750,124000"10266 "88000,124000"10267 10335 ] 10268 10336 ) … … 10274 10342 si 0 10275 10343 tg (WTG 10344 uid 10502,0 10345 ps "ConnStartEndStrategy" 10346 stg "STSignalDisplayStrategy" 10347 f (Text 10348 uid 10503,0 10349 va (VaSet 10350 ) 10351 xt "82000,122000,86800,123000" 10352 st "CLK50_OUT" 10353 blo "82000,122800" 10354 tm "WireNameMgr" 10355 ) 10356 ) 10357 on &234 10358 ) 10359 *329 (Wire 10360 uid 10506,0 10361 shape (OrthoPolyLine 10362 uid 10507,0 10363 va (VaSet 10364 vasetType 3 10365 ) 10366 xt "80750,124000,88000,124000" 10367 pts [ 10368 "80750,124000" 10369 "88000,124000" 10370 ] 10371 ) 10372 start &54 10373 sat 32 10374 eat 16 10375 st 0 10376 sf 1 10377 si 0 10378 tg (WTG 10276 10379 uid 10510,0 10277 10380 ps "ConnStartEndStrategy" … … 10287 10390 ) 10288 10391 ) 10289 on &23 610290 ) 10291 *3 26(Wire10392 on &235 10393 ) 10394 *330 (Wire 10292 10395 uid 10514,0 10293 10396 shape (OrthoPolyLine … … 10302 10405 ] 10303 10406 ) 10304 start &5 710407 start &55 10305 10408 sat 32 10306 10409 eat 16 … … 10322 10425 ) 10323 10426 ) 10324 on &23 710325 ) 10326 *3 27(Wire10427 on &236 10428 ) 10429 *331 (Wire 10327 10430 uid 10522,0 10328 10431 shape (OrthoPolyLine … … 10357 10460 ) 10358 10461 ) 10462 on &237 10463 ) 10464 *332 (Wire 10465 uid 10546,0 10466 shape (OrthoPolyLine 10467 uid 10547,0 10468 va (VaSet 10469 vasetType 3 10470 ) 10471 xt "80750,128000,90000,128000" 10472 pts [ 10473 "80750,128000" 10474 "90000,128000" 10475 ] 10476 ) 10477 start &51 10478 sat 32 10479 eat 16 10480 st 0 10481 sf 1 10482 si 0 10483 tg (WTG 10484 uid 10550,0 10485 ps "ConnStartEndStrategy" 10486 stg "STSignalDisplayStrategy" 10487 f (Text 10488 uid 10551,0 10489 va (VaSet 10490 ) 10491 xt "82000,127000,89000,128000" 10492 st "PSINCDEC_OUT" 10493 blo "82000,127800" 10494 tm "WireNameMgr" 10495 ) 10496 ) 10359 10497 on &238 10360 10498 ) 10361 *3 28(Wire10362 uid 105 30,010499 *333 (Wire 10500 uid 10554,0 10363 10501 shape (OrthoPolyLine 10364 uid 105 31,010502 uid 10555,0 10365 10503 va (VaSet 10366 10504 vasetType 3 10367 10505 ) 10368 xt "80750,127000,87000,127000" 10369 pts [ 10370 "80750,127000" 10371 "87000,127000" 10506 xt "80750,130000,88000,130000" 10507 pts [ 10508 "80750,130000" 10509 "88000,130000" 10510 ] 10511 ) 10512 start &45 10513 sat 32 10514 eat 16 10515 st 0 10516 sf 1 10517 si 0 10518 tg (WTG 10519 uid 10558,0 10520 ps "ConnStartEndStrategy" 10521 stg "STSignalDisplayStrategy" 10522 f (Text 10523 uid 10559,0 10524 va (VaSet 10525 ) 10526 xt "82000,129000,87200,130000" 10527 st "DCM_locked" 10528 blo "82000,129800" 10529 tm "WireNameMgr" 10530 ) 10531 ) 10532 on &239 10533 ) 10534 *334 (Wire 10535 uid 10562,0 10536 shape (OrthoPolyLine 10537 uid 10563,0 10538 va (VaSet 10539 vasetType 3 10540 ) 10541 xt "80750,132000,85000,132000" 10542 pts [ 10543 "80750,132000" 10544 "85000,132000" 10545 ] 10546 ) 10547 start &52 10548 sat 32 10549 eat 16 10550 st 0 10551 sf 1 10552 si 0 10553 tg (WTG 10554 uid 10566,0 10555 ps "ConnStartEndStrategy" 10556 stg "STSignalDisplayStrategy" 10557 f (Text 10558 uid 10567,0 10559 va (VaSet 10560 ) 10561 xt "82000,131000,84200,132000" 10562 st "ready" 10563 blo "82000,131800" 10564 tm "WireNameMgr" 10565 ) 10566 ) 10567 on &240 10568 ) 10569 *335 (Wire 10570 uid 10570,0 10571 shape (OrthoPolyLine 10572 uid 10571,0 10573 va (VaSet 10574 vasetType 3 10575 ) 10576 xt "80750,133000,86000,133000" 10577 pts [ 10578 "80750,133000" 10579 "86000,133000" 10580 ] 10581 ) 10582 start &53 10583 sat 32 10584 eat 16 10585 st 0 10586 sf 1 10587 si 0 10588 tg (WTG 10589 uid 10574,0 10590 ps "ConnStartEndStrategy" 10591 stg "STSignalDisplayStrategy" 10592 f (Text 10593 uid 10575,0 10594 va (VaSet 10595 ) 10596 xt "82000,132000,84900,133000" 10597 st "shifting" 10598 blo "82000,132800" 10599 tm "WireNameMgr" 10600 ) 10601 ) 10602 on &241 10603 ) 10604 *336 (Wire 10605 uid 10578,0 10606 shape (OrthoPolyLine 10607 uid 10579,0 10608 va (VaSet 10609 vasetType 3 10610 ) 10611 xt "80750,134000,91000,134000" 10612 pts [ 10613 "80750,134000" 10614 "91000,134000" 10615 ] 10616 ) 10617 start &50 10618 sat 32 10619 eat 16 10620 st 0 10621 sf 1 10622 si 0 10623 tg (WTG 10624 uid 10582,0 10625 ps "ConnStartEndStrategy" 10626 stg "STSignalDisplayStrategy" 10627 f (Text 10628 uid 10583,0 10629 va (VaSet 10630 ) 10631 xt "82000,133000,89800,134000" 10632 st "PSDONE_extraOUT" 10633 blo "82000,133800" 10634 tm "WireNameMgr" 10635 ) 10636 ) 10637 on &242 10638 ) 10639 *337 (Wire 10640 uid 10586,0 10641 shape (OrthoPolyLine 10642 uid 10587,0 10643 va (VaSet 10644 vasetType 3 10645 ) 10646 xt "80750,135000,88000,135000" 10647 pts [ 10648 "80750,135000" 10649 "88000,135000" 10372 10650 ] 10373 10651 ) … … 10379 10657 si 0 10380 10658 tg (WTG 10381 uid 10534,010382 ps "ConnStartEndStrategy"10383 stg "STSignalDisplayStrategy"10384 f (Text10385 uid 10535,010386 va (VaSet10387 )10388 xt "82000,126000,86200,127000"10389 st "PS_DO_IN"10390 blo "82000,126800"10391 tm "WireNameMgr"10392 )10393 )10394 on &23910395 )10396 *329 (Wire10397 uid 10538,010398 shape (OrthoPolyLine10399 uid 10539,010400 va (VaSet10401 vasetType 310402 )10403 xt "80750,129000,88000,129000"10404 pts [10405 "80750,129000"10406 "88000,129000"10407 ]10408 )10409 start &5210410 sat 3210411 eat 1610412 st 010413 sf 110414 si 010415 tg (WTG10416 uid 10542,010417 ps "ConnStartEndStrategy"10418 stg "STSignalDisplayStrategy"10419 f (Text10420 uid 10543,010421 va (VaSet10422 )10423 xt "82000,128000,86600,129000"10424 st "PSEN_OUT"10425 blo "82000,128800"10426 tm "WireNameMgr"10427 )10428 )10429 on &24010430 )10431 *330 (Wire10432 uid 10546,010433 shape (OrthoPolyLine10434 uid 10547,010435 va (VaSet10436 vasetType 310437 )10438 xt "80750,128000,90000,128000"10439 pts [10440 "80750,128000"10441 "90000,128000"10442 ]10443 )10444 start &5310445 sat 3210446 eat 1610447 st 010448 sf 110449 si 010450 tg (WTG10451 uid 10550,010452 ps "ConnStartEndStrategy"10453 stg "STSignalDisplayStrategy"10454 f (Text10455 uid 10551,010456 va (VaSet10457 )10458 xt "82000,127000,89000,128000"10459 st "PSINCDEC_OUT"10460 blo "82000,127800"10461 tm "WireNameMgr"10462 )10463 )10464 on &24110465 )10466 *331 (Wire10467 uid 10554,010468 shape (OrthoPolyLine10469 uid 10555,010470 va (VaSet10471 vasetType 310472 )10473 xt "80750,130000,88000,130000"10474 pts [10475 "80750,130000"10476 "88000,130000"10477 ]10478 )10479 start &4510480 sat 3210481 eat 1610482 st 010483 sf 110484 si 010485 tg (WTG10486 uid 10558,010487 ps "ConnStartEndStrategy"10488 stg "STSignalDisplayStrategy"10489 f (Text10490 uid 10559,010491 va (VaSet10492 )10493 xt "82000,129000,87200,130000"10494 st "DCM_locked"10495 blo "82000,129800"10496 tm "WireNameMgr"10497 )10498 )10499 on &24210500 )10501 *332 (Wire10502 uid 10562,010503 shape (OrthoPolyLine10504 uid 10563,010505 va (VaSet10506 vasetType 310507 )10508 xt "80750,132000,85000,132000"10509 pts [10510 "80750,132000"10511 "85000,132000"10512 ]10513 )10514 start &5410515 sat 3210516 eat 1610517 st 010518 sf 110519 si 010520 tg (WTG10521 uid 10566,010522 ps "ConnStartEndStrategy"10523 stg "STSignalDisplayStrategy"10524 f (Text10525 uid 10567,010526 va (VaSet10527 )10528 xt "82000,131000,84200,132000"10529 st "ready"10530 blo "82000,131800"10531 tm "WireNameMgr"10532 )10533 )10534 on &24310535 )10536 *333 (Wire10537 uid 10570,010538 shape (OrthoPolyLine10539 uid 10571,010540 va (VaSet10541 vasetType 310542 )10543 xt "80750,133000,86000,133000"10544 pts [10545 "80750,133000"10546 "86000,133000"10547 ]10548 )10549 start &5510550 sat 3210551 eat 1610552 st 010553 sf 110554 si 010555 tg (WTG10556 uid 10574,010557 ps "ConnStartEndStrategy"10558 stg "STSignalDisplayStrategy"10559 f (Text10560 uid 10575,010561 va (VaSet10562 )10563 xt "82000,132000,84900,133000"10564 st "shifting"10565 blo "82000,132800"10566 tm "WireNameMgr"10567 )10568 )10569 on &24410570 )10571 *334 (Wire10572 uid 10578,010573 shape (OrthoPolyLine10574 uid 10579,010575 va (VaSet10576 vasetType 310577 )10578 xt "80750,134000,91000,134000"10579 pts [10580 "80750,134000"10581 "91000,134000"10582 ]10583 )10584 start &5110585 sat 3210586 eat 1610587 st 010588 sf 110589 si 010590 tg (WTG10591 uid 10582,010592 ps "ConnStartEndStrategy"10593 stg "STSignalDisplayStrategy"10594 f (Text10595 uid 10583,010596 va (VaSet10597 )10598 xt "82000,133000,89800,134000"10599 st "PSDONE_extraOUT"10600 blo "82000,133800"10601 tm "WireNameMgr"10602 )10603 )10604 on &24510605 )10606 *335 (Wire10607 uid 10586,010608 shape (OrthoPolyLine10609 uid 10587,010610 va (VaSet10611 vasetType 310612 )10613 xt "80750,135000,88000,135000"10614 pts [10615 "80750,135000"10616 "88000,135000"10617 ]10618 )10619 start &5010620 sat 3210621 eat 1610622 st 010623 sf 110624 si 010625 tg (WTG10626 10659 uid 10590,0 10627 10660 ps "ConnStartEndStrategy" … … 10637 10670 ) 10638 10671 ) 10639 on &24 610640 ) 10641 *33 6(Wire10672 on &243 10673 ) 10674 *338 (Wire 10642 10675 uid 10594,0 10643 10676 shape (OrthoPolyLine … … 10672 10705 ) 10673 10706 ) 10674 on &24 710675 ) 10676 *33 7(Wire10707 on &244 10708 ) 10709 *339 (Wire 10677 10710 uid 11096,0 10678 10711 shape (OrthoPolyLine … … 10687 10720 ] 10688 10721 ) 10689 start &24 810690 end &15 910722 start &245 10723 end &158 10691 10724 sat 32 10692 10725 eat 1 … … 10709 10742 ) 10710 10743 ) 10711 on &24 910712 ) 10713 *3 38(Wire10744 on &246 10745 ) 10746 *340 (Wire 10714 10747 uid 11110,0 10715 10748 shape (OrthoPolyLine … … 10724 10757 ] 10725 10758 ) 10726 start &15 910727 end &2 5010759 start &158 10760 end &247 10728 10761 sat 2 10729 10762 eat 32 … … 10746 10779 ) 10747 10780 ) 10748 on &2 5110749 ) 10750 *3 39(Wire10781 on &248 10782 ) 10783 *341 (Wire 10751 10784 uid 11514,0 10752 10785 shape (OrthoPolyLine … … 10761 10794 ] 10762 10795 ) 10763 start &2 5210796 start &249 10764 10797 sat 32 10765 10798 eat 16 … … 10782 10815 ) 10783 10816 ) 10784 on &25 310785 ) 10786 *34 0(Wire10817 on &250 10818 ) 10819 *342 (Wire 10787 10820 uid 11528,0 10788 10821 shape (OrthoPolyLine … … 10797 10830 ] 10798 10831 ) 10799 end &25 510832 end &252 10800 10833 sat 16 10801 10834 eat 32 … … 10818 10851 ) 10819 10852 ) 10820 on &25 410821 ) 10822 *34 1(Wire10853 on &251 10854 ) 10855 *343 (Wire 10823 10856 uid 12320,0 10824 10857 shape (OrthoPolyLine … … 10833 10866 ] 10834 10867 ) 10835 start &5 910836 end &25 610868 start &57 10869 end &253 10837 10870 sat 32 10838 10871 eat 32 … … 10856 10889 ) 10857 10890 ) 10858 on &25 710859 ) 10860 *34 2(Wire10891 on &254 10892 ) 10893 *344 (Wire 10861 10894 uid 12545,0 10862 10895 shape (OrthoPolyLine … … 10871 10904 ] 10872 10905 ) 10873 start & 6010874 end &25 810906 start &58 10907 end &255 10875 10908 ss 0 10876 10909 sat 32 … … 10894 10927 ) 10895 10928 ) 10896 on &2 6110897 ) 10898 *34 3(Wire10929 on &258 10930 ) 10931 *345 (Wire 10899 10932 uid 12559,0 10900 10933 shape (OrthoPolyLine … … 10909 10942 ] 10910 10943 ) 10911 start &6 210912 end &25 910944 start &60 10945 end &256 10913 10946 sat 32 10914 10947 eat 32 … … 10931 10964 ) 10932 10965 ) 10933 on &2 6210934 ) 10935 *34 4(Wire10966 on &259 10967 ) 10968 *346 (Wire 10936 10969 uid 12573,0 10937 10970 shape (OrthoPolyLine … … 10946 10979 ] 10947 10980 ) 10948 start & 6110949 end &2 6010981 start &59 10982 end &257 10950 10983 sat 32 10951 10984 eat 32 … … 10968 11001 ) 10969 11002 ) 10970 on &26 310971 ) 10972 *34 5(Wire11003 on &260 11004 ) 11005 *347 (Wire 10973 11006 uid 13522,0 10974 11007 shape (OrthoPolyLine … … 10978 11011 lineWidth 2 10979 11012 ) 10980 xt "1 12000,148000,120000,148000"10981 pts [ 10982 "1 12000,148000"10983 " 120000,148000"10984 ] 10985 ) 10986 start &26 410987 end & 23111013 xt "12000,81000,24000,81000" 11014 pts [ 11015 "12000,81000" 11016 "24000,81000" 11017 ] 11018 ) 11019 start &261 11020 end &68 10988 11021 sat 32 10989 11022 eat 1 … … 10999 11032 uid 13527,0 11000 11033 va (VaSet 11001 isHidden 1 11002 ) 11003 xt "114000,147000,121900,148000" 11004 st "POSITION_ID : (5:0)" 11005 blo "114000,147800" 11006 tm "WireNameMgr" 11007 ) 11008 ) 11009 on &265 11010 ) 11011 *346 (Wire 11034 ) 11035 xt "14000,80000,18700,81000" 11036 st "LINE : (5:0)" 11037 blo "14000,80800" 11038 tm "WireNameMgr" 11039 ) 11040 ) 11041 on &262 11042 ) 11043 *348 (Wire 11012 11044 uid 13538,0 11013 11045 shape (OrthoPolyLine … … 11022 11054 ] 11023 11055 ) 11024 end &23 111056 end &230 11025 11057 sat 16 11026 11058 eat 1 … … 11042 11074 ) 11043 11075 ) 11044 on &24 711045 ) 11046 *34 7(Wire11076 on &244 11077 ) 11078 *349 (Wire 11047 11079 uid 13546,0 11048 11080 shape (OrthoPolyLine … … 11057 11089 ] 11058 11090 ) 11059 end &23 111091 end &230 11060 11092 sat 16 11061 11093 eat 1 … … 11077 11109 ) 11078 11110 ) 11079 on &24 611080 ) 11081 *3 48(Wire11111 on &243 11112 ) 11113 *350 (Wire 11082 11114 uid 13554,0 11083 11115 shape (OrthoPolyLine … … 11092 11124 ] 11093 11125 ) 11094 end &23 111126 end &230 11095 11127 sat 16 11096 11128 eat 1 … … 11112 11144 ) 11113 11145 ) 11114 on &24 511115 ) 11116 *3 49(Wire11146 on &242 11147 ) 11148 *351 (Wire 11117 11149 uid 13570,0 11118 11150 shape (OrthoPolyLine … … 11127 11159 ] 11128 11160 ) 11129 end &23 111161 end &230 11130 11162 sat 16 11131 11163 eat 1 … … 11147 11179 ) 11148 11180 ) 11149 on &25 711150 ) 11151 *35 0(Wire11181 on &254 11182 ) 11183 *352 (Wire 11152 11184 uid 13578,0 11153 11185 shape (OrthoPolyLine … … 11163 11195 ] 11164 11196 ) 11165 end &23 111197 end &230 11166 11198 sat 16 11167 11199 eat 1 … … 11184 11216 ) 11185 11217 ) 11186 on &20 711187 ) 11188 *35 1(Wire11218 on &206 11219 ) 11220 *353 (Wire 11189 11221 uid 13610,0 11190 11222 shape (OrthoPolyLine … … 11199 11231 ] 11200 11232 ) 11201 start &18 311202 end &23 111233 start &182 11234 end &230 11203 11235 sat 32 11204 11236 eat 1 … … 11221 11253 ) 11222 11254 ) 11223 on &18 411224 ) 11225 *35 2(Wire11255 on &183 11256 ) 11257 *354 (Wire 11226 11258 uid 13618,0 11227 11259 shape (OrthoPolyLine … … 11237 11269 ] 11238 11270 ) 11239 start &23 111240 end &18 511271 start &230 11272 end &184 11241 11273 sat 2 11242 11274 eat 32 … … 11260 11292 ) 11261 11293 ) 11262 on &18 611263 ) 11264 *35 3(Wire11294 on &185 11295 ) 11296 *355 (Wire 11265 11297 uid 13634,0 11266 11298 shape (OrthoPolyLine … … 11275 11307 ] 11276 11308 ) 11277 start &26 611278 end &23 111309 start &263 11310 end &230 11279 11311 sat 32 11280 11312 eat 1 … … 11297 11329 ) 11298 11330 ) 11299 on &26 711300 ) 11301 *35 4(Wire11331 on &264 11332 ) 11333 *356 (Wire 11302 11334 uid 13650,0 11303 11335 shape (OrthoPolyLine … … 11312 11344 ] 11313 11345 ) 11314 end &23 111346 end &230 11315 11347 sat 16 11316 11348 eat 1 … … 11332 11364 ) 11333 11365 ) 11334 on &25 311335 ) 11336 *35 5(Wire11366 on &250 11367 ) 11368 *357 (Wire 11337 11369 uid 13658,0 11338 11370 shape (OrthoPolyLine … … 11347 11379 ] 11348 11380 ) 11349 start &23 111381 start &230 11350 11382 sat 2 11351 11383 eat 16 … … 11367 11399 ) 11368 11400 ) 11369 on &17 411370 ) 11371 *35 6(Wire11401 on &173 11402 ) 11403 *358 (Wire 11372 11404 uid 13666,0 11373 11405 shape (OrthoPolyLine … … 11382 11414 ] 11383 11415 ) 11384 start &23 111416 start &230 11385 11417 sat 2 11386 11418 eat 16 … … 11402 11434 ) 11403 11435 ) 11404 on &173 11436 on &172 11437 ) 11438 *359 (Wire 11439 uid 14328,0 11440 shape (OrthoPolyLine 11441 uid 14329,0 11442 va (VaSet 11443 vasetType 3 11444 lineWidth 2 11445 ) 11446 xt "39000,139000,51250,139000" 11447 pts [ 11448 "39000,139000" 11449 "51250,139000" 11450 ] 11451 ) 11452 start &265 11453 end &62 11454 sat 32 11455 eat 32 11456 sty 1 11457 st 0 11458 sf 1 11459 si 0 11460 tg (WTG 11461 uid 14332,0 11462 ps "ConnStartEndStrategy" 11463 stg "STSignalDisplayStrategy" 11464 f (Text 11465 uid 14333,0 11466 va (VaSet 11467 isHidden 1 11468 ) 11469 xt "41000,138000,46500,139000" 11470 st "D_T_in : (1:0)" 11471 blo "41000,138800" 11472 tm "WireNameMgr" 11473 ) 11474 ) 11475 on &266 11476 ) 11477 *360 (Wire 11478 uid 15175,0 11479 shape (OrthoPolyLine 11480 uid 15176,0 11481 va (VaSet 11482 vasetType 3 11483 lineWidth 2 11484 ) 11485 xt "80750,120000,87000,120000" 11486 pts [ 11487 "80750,120000" 11488 "87000,120000" 11489 ] 11490 ) 11491 start &14 11492 sat 32 11493 eat 16 11494 sty 1 11495 st 0 11496 sf 1 11497 si 0 11498 tg (WTG 11499 uid 15179,0 11500 ps "ConnStartEndStrategy" 11501 stg "STSignalDisplayStrategy" 11502 f (Text 11503 uid 15180,0 11504 va (VaSet 11505 ) 11506 xt "82000,119000,86000,120000" 11507 st "led : (7:0)" 11508 blo "82000,119800" 11509 tm "WireNameMgr" 11510 ) 11511 ) 11512 on &271 11405 11513 ) 11406 11514 ] … … 11416 11524 color "26368,26368,26368" 11417 11525 ) 11418 packageList *3 57(PackageList11526 packageList *361 (PackageList 11419 11527 uid 41,0 11420 11528 stg "VerticalLayoutStrategy" 11421 11529 textVec [ 11422 *3 58(Text11530 *362 (Text 11423 11531 uid 42,0 11424 11532 va (VaSet … … 11429 11537 blo "0,800" 11430 11538 ) 11431 *3 59(MLText11539 *363 (MLText 11432 11540 uid 43,0 11433 11541 va (VaSet … … 11450 11558 stg "VerticalLayoutStrategy" 11451 11559 textVec [ 11452 *36 0(Text11560 *364 (Text 11453 11561 uid 45,0 11454 11562 va (VaSet … … 11460 11568 blo "20000,800" 11461 11569 ) 11462 *36 1(Text11570 *365 (Text 11463 11571 uid 46,0 11464 11572 va (VaSet … … 11470 11578 blo "20000,1800" 11471 11579 ) 11472 *36 2(MLText11580 *366 (MLText 11473 11581 uid 47,0 11474 11582 va (VaSet … … 11480 11588 tm "BdCompilerDirectivesTextMgr" 11481 11589 ) 11482 *36 3(Text11590 *367 (Text 11483 11591 uid 48,0 11484 11592 va (VaSet … … 11490 11598 blo "20000,4800" 11491 11599 ) 11492 *36 4(MLText11600 *368 (MLText 11493 11601 uid 49,0 11494 11602 va (VaSet … … 11498 11606 tm "BdCompilerDirectivesTextMgr" 11499 11607 ) 11500 *36 5(Text11608 *369 (Text 11501 11609 uid 50,0 11502 11610 va (VaSet … … 11508 11616 blo "20000,5800" 11509 11617 ) 11510 *3 66(MLText11618 *370 (MLText 11511 11619 uid 51,0 11512 11620 va (VaSet … … 11520 11628 ) 11521 11629 windowSize "0,0,1281,1024" 11522 viewArea "4 4182,100210,114187,157942"11630 viewArea "47500,114900,130258,183150" 11523 11631 cachedDiagramExtent "0,0,699000,450107" 11524 11632 pageSetupInfo (PageSetupInfo … … 11533 11641 hasePageBreakOrigin 1 11534 11642 pageBreakOrigin "0,0" 11535 lastUid 1 4001,011643 lastUid 15182,0 11536 11644 defaultCommentText (CommentText 11537 11645 shape (Rectangle … … 11595 11703 stg "VerticalLayoutStrategy" 11596 11704 textVec [ 11597 *3 67(Text11705 *371 (Text 11598 11706 va (VaSet 11599 11707 font "Arial,8,1" … … 11604 11712 tm "BdLibraryNameMgr" 11605 11713 ) 11606 *3 68(Text11714 *372 (Text 11607 11715 va (VaSet 11608 11716 font "Arial,8,1" … … 11613 11721 tm "BlkNameMgr" 11614 11722 ) 11615 *3 69(Text11723 *373 (Text 11616 11724 va (VaSet 11617 11725 font "Arial,8,1" … … 11664 11772 stg "VerticalLayoutStrategy" 11665 11773 textVec [ 11666 *37 0(Text11774 *374 (Text 11667 11775 va (VaSet 11668 11776 font "Arial,8,1" … … 11672 11780 blo "550,4300" 11673 11781 ) 11674 *37 1(Text11782 *375 (Text 11675 11783 va (VaSet 11676 11784 font "Arial,8,1" … … 11680 11788 blo "550,5300" 11681 11789 ) 11682 *37 2(Text11790 *376 (Text 11683 11791 va (VaSet 11684 11792 font "Arial,8,1" … … 11729 11837 stg "VerticalLayoutStrategy" 11730 11838 textVec [ 11731 *37 3(Text11839 *377 (Text 11732 11840 va (VaSet 11733 11841 font "Arial,8,1" … … 11738 11846 tm "BdLibraryNameMgr" 11739 11847 ) 11740 *37 4(Text11848 *378 (Text 11741 11849 va (VaSet 11742 11850 font "Arial,8,1" … … 11747 11855 tm "CptNameMgr" 11748 11856 ) 11749 *37 5(Text11857 *379 (Text 11750 11858 va (VaSet 11751 11859 font "Arial,8,1" … … 11801 11909 stg "VerticalLayoutStrategy" 11802 11910 textVec [ 11803 *3 76(Text11911 *380 (Text 11804 11912 va (VaSet 11805 11913 font "Arial,8,1" … … 11809 11917 blo "500,4300" 11810 11918 ) 11811 *3 77(Text11919 *381 (Text 11812 11920 va (VaSet 11813 11921 font "Arial,8,1" … … 11817 11925 blo "500,5300" 11818 11926 ) 11819 *3 78(Text11927 *382 (Text 11820 11928 va (VaSet 11821 11929 font "Arial,8,1" … … 11862 11970 stg "VerticalLayoutStrategy" 11863 11971 textVec [ 11864 *3 79(Text11972 *383 (Text 11865 11973 va (VaSet 11866 11974 font "Arial,8,1" … … 11870 11978 blo "50,4300" 11871 11979 ) 11872 *38 0(Text11980 *384 (Text 11873 11981 va (VaSet 11874 11982 font "Arial,8,1" … … 11878 11986 blo "50,5300" 11879 11987 ) 11880 *38 1(Text11988 *385 (Text 11881 11989 va (VaSet 11882 11990 font "Arial,8,1" … … 11919 12027 stg "VerticalLayoutStrategy" 11920 12028 textVec [ 11921 *38 2(Text12029 *386 (Text 11922 12030 va (VaSet 11923 12031 font "Arial,8,1" … … 11928 12036 tm "HdlTextNameMgr" 11929 12037 ) 11930 *38 3(Text12038 *387 (Text 11931 12039 va (VaSet 11932 12040 font "Arial,8,1" … … 12331 12439 stg "VerticalLayoutStrategy" 12332 12440 textVec [ 12333 *38 4(Text12441 *388 (Text 12334 12442 va (VaSet 12335 12443 font "Arial,8,1" … … 12339 12447 blo "14100,20800" 12340 12448 ) 12341 *38 5(MLText12449 *389 (MLText 12342 12450 va (VaSet 12343 12451 ) … … 12391 12499 stg "VerticalLayoutStrategy" 12392 12500 textVec [ 12393 *3 86(Text12501 *390 (Text 12394 12502 va (VaSet 12395 12503 font "Arial,8,1" … … 12399 12507 blo "14100,20800" 12400 12508 ) 12401 *3 87(MLText12509 *391 (MLText 12402 12510 va (VaSet 12403 12511 ) … … 12517 12625 font "Arial,8,1" 12518 12626 ) 12519 xt "37000, 49400,44100,50400"12627 xt "37000,50200,44100,51200" 12520 12628 st "Diagram Signals:" 12521 blo "37000,5 0200"12629 blo "37000,51000" 12522 12630 ) 12523 12631 postUserLabel (Text … … 12543 12651 commonDM (CommonDM 12544 12652 ldm (LogicalDM 12545 suid 21 2,012653 suid 215,0 12546 12654 usingSuid 1 12547 emptyRow *3 88(LEmptyRow12655 emptyRow *392 (LEmptyRow 12548 12656 ) 12549 12657 uid 54,0 12550 12658 optionalChildren [ 12551 *3 89(RefLabelRowHdr12552 ) 12553 *39 0(TitleRowHdr12554 ) 12555 *39 1(FilterRowHdr12556 ) 12557 *39 2(RefLabelColHdr12659 *393 (RefLabelRowHdr 12660 ) 12661 *394 (TitleRowHdr 12662 ) 12663 *395 (FilterRowHdr 12664 ) 12665 *396 (RefLabelColHdr 12558 12666 tm "RefLabelColHdrMgr" 12559 12667 ) 12560 *39 3(RowExpandColHdr12668 *397 (RowExpandColHdr 12561 12669 tm "RowExpandColHdrMgr" 12562 12670 ) 12563 *39 4(GroupColHdr12671 *398 (GroupColHdr 12564 12672 tm "GroupColHdrMgr" 12565 12673 ) 12566 *39 5(NameColHdr12674 *399 (NameColHdr 12567 12675 tm "BlockDiagramNameColHdrMgr" 12568 12676 ) 12569 * 396(ModeColHdr12677 *400 (ModeColHdr 12570 12678 tm "BlockDiagramModeColHdrMgr" 12571 12679 ) 12572 * 397(TypeColHdr12680 *401 (TypeColHdr 12573 12681 tm "BlockDiagramTypeColHdrMgr" 12574 12682 ) 12575 * 398(BoundsColHdr12683 *402 (BoundsColHdr 12576 12684 tm "BlockDiagramBoundsColHdrMgr" 12577 12685 ) 12578 * 399(InitColHdr12686 *403 (InitColHdr 12579 12687 tm "BlockDiagramInitColHdrMgr" 12580 12688 ) 12581 *40 0(EolColHdr12689 *404 (EolColHdr 12582 12690 tm "BlockDiagramEolColHdrMgr" 12583 12691 ) 12584 *40 1(LeafLogPort12692 *405 (LeafLogPort 12585 12693 port (LogicalPort 12586 12694 m 4 … … 12597 12705 uid 327,0 12598 12706 ) 12599 *40 2(LeafLogPort12707 *406 (LeafLogPort 12600 12708 port (LogicalPort 12601 12709 m 4 … … 12610 12718 uid 329,0 12611 12719 ) 12612 *40 3(LeafLogPort12720 *407 (LeafLogPort 12613 12721 port (LogicalPort 12614 12722 m 4 … … 12622 12730 uid 1491,0 12623 12731 ) 12624 *40 4(LeafLogPort12732 *408 (LeafLogPort 12625 12733 port (LogicalPort 12626 12734 m 1 … … 12635 12743 uid 2435,0 12636 12744 ) 12637 *40 5(LeafLogPort12745 *409 (LeafLogPort 12638 12746 port (LogicalPort 12639 12747 m 4 … … 12648 12756 uid 2437,0 12649 12757 ) 12650 *4 06(LeafLogPort12758 *410 (LeafLogPort 12651 12759 port (LogicalPort 12652 12760 m 4 … … 12661 12769 uid 3037,0 12662 12770 ) 12663 *4 07(LeafLogPort12771 *411 (LeafLogPort 12664 12772 port (LogicalPort 12665 12773 m 1 … … 12673 12781 uid 3039,0 12674 12782 ) 12675 *4 08(LeafLogPort12783 *412 (LeafLogPort 12676 12784 port (LogicalPort 12677 12785 decl (Decl … … 12686 12794 uid 3276,0 12687 12795 ) 12688 *4 09(LeafLogPort12796 *413 (LeafLogPort 12689 12797 port (LogicalPort 12690 12798 decl (Decl … … 12697 12805 uid 3278,0 12698 12806 ) 12699 *41 0(LeafLogPort12807 *414 (LeafLogPort 12700 12808 port (LogicalPort 12701 12809 m 1 … … 12710 12818 uid 3280,0 12711 12819 ) 12712 *41 1(LeafLogPort12820 *415 (LeafLogPort 12713 12821 port (LogicalPort 12714 12822 m 4 … … 12722 12830 uid 3282,0 12723 12831 ) 12724 *41 2(LeafLogPort12832 *416 (LeafLogPort 12725 12833 port (LogicalPort 12726 12834 m 1 … … 12736 12844 uid 3382,0 12737 12845 ) 12738 *41 3(LeafLogPort12846 *417 (LeafLogPort 12739 12847 port (LogicalPort 12740 12848 decl (Decl … … 12748 12856 uid 3384,0 12749 12857 ) 12750 *41 4(LeafLogPort12858 *418 (LeafLogPort 12751 12859 port (LogicalPort 12752 12860 decl (Decl … … 12760 12868 uid 3386,0 12761 12869 ) 12762 *41 5(LeafLogPort12870 *419 (LeafLogPort 12763 12871 port (LogicalPort 12764 12872 decl (Decl … … 12772 12880 uid 3388,0 12773 12881 ) 12774 *4 16(LeafLogPort12882 *420 (LeafLogPort 12775 12883 port (LogicalPort 12776 12884 decl (Decl … … 12784 12892 uid 3390,0 12785 12893 ) 12786 *4 17(LeafLogPort12894 *421 (LeafLogPort 12787 12895 port (LogicalPort 12788 12896 decl (Decl … … 12796 12904 uid 3392,0 12797 12905 ) 12798 *4 18(LeafLogPort12906 *422 (LeafLogPort 12799 12907 port (LogicalPort 12800 12908 m 1 … … 12808 12916 uid 3468,0 12809 12917 ) 12810 *4 19(LeafLogPort12918 *423 (LeafLogPort 12811 12919 port (LogicalPort 12812 12920 m 1 … … 12820 12928 uid 3470,0 12821 12929 ) 12822 *42 0(LeafLogPort12930 *424 (LeafLogPort 12823 12931 port (LogicalPort 12824 12932 m 1 … … 12832 12940 uid 3472,0 12833 12941 ) 12834 *42 1(LeafLogPort12942 *425 (LeafLogPort 12835 12943 port (LogicalPort 12836 12944 m 1 … … 12844 12952 uid 3474,0 12845 12953 ) 12846 *42 2(LeafLogPort12954 *426 (LeafLogPort 12847 12955 port (LogicalPort 12848 12956 decl (Decl … … 12855 12963 uid 3524,0 12856 12964 ) 12857 *42 3(LeafLogPort12965 *427 (LeafLogPort 12858 12966 port (LogicalPort 12859 12967 decl (Decl … … 12866 12974 uid 3526,0 12867 12975 ) 12868 *42 4(LeafLogPort12976 *428 (LeafLogPort 12869 12977 port (LogicalPort 12870 12978 decl (Decl … … 12877 12985 uid 3528,0 12878 12986 ) 12879 *42 5(LeafLogPort12987 *429 (LeafLogPort 12880 12988 port (LogicalPort 12881 12989 decl (Decl … … 12888 12996 uid 3530,0 12889 12997 ) 12890 *4 26(LeafLogPort12998 *430 (LeafLogPort 12891 12999 port (LogicalPort 12892 13000 m 1 … … 12902 13010 uid 3532,0 12903 13011 ) 12904 *4 27(LeafLogPort13012 *431 (LeafLogPort 12905 13013 port (LogicalPort 12906 13014 m 1 … … 12915 13023 uid 3534,0 12916 13024 ) 12917 *428 (LeafLogPort12918 port (LogicalPort12919 m 112920 decl (Decl12921 n "T0_CS"12922 t "std_logic"12923 o 4612924 suid 101,012925 )12926 )12927 uid 3646,012928 )12929 *429 (LeafLogPort12930 port (LogicalPort12931 m 112932 decl (Decl12933 n "T1_CS"12934 t "std_logic"12935 o 4712936 suid 102,012937 )12938 )12939 uid 3648,012940 )12941 *430 (LeafLogPort12942 port (LogicalPort12943 m 112944 decl (Decl12945 n "T2_CS"12946 t "std_logic"12947 o 4812948 suid 103,012949 )12950 )12951 uid 3650,012952 )12953 *431 (LeafLogPort12954 port (LogicalPort12955 m 112956 decl (Decl12957 n "T3_CS"12958 t "std_logic"12959 o 4912960 suid 104,012961 )12962 )12963 uid 3652,012964 )12965 13025 *432 (LeafLogPort 12966 13026 port (LogicalPort 12967 13027 m 1 12968 13028 decl (Decl 13029 n "T0_CS" 13030 t "std_logic" 13031 o 46 13032 suid 101,0 13033 ) 13034 ) 13035 uid 3646,0 13036 ) 13037 *433 (LeafLogPort 13038 port (LogicalPort 13039 m 1 13040 decl (Decl 13041 n "T1_CS" 13042 t "std_logic" 13043 o 47 13044 suid 102,0 13045 ) 13046 ) 13047 uid 3648,0 13048 ) 13049 *434 (LeafLogPort 13050 port (LogicalPort 13051 m 1 13052 decl (Decl 13053 n "T2_CS" 13054 t "std_logic" 13055 o 48 13056 suid 103,0 13057 ) 13058 ) 13059 uid 3650,0 13060 ) 13061 *435 (LeafLogPort 13062 port (LogicalPort 13063 m 1 13064 decl (Decl 13065 n "T3_CS" 13066 t "std_logic" 13067 o 49 13068 suid 104,0 13069 ) 13070 ) 13071 uid 3652,0 13072 ) 13073 *436 (LeafLogPort 13074 port (LogicalPort 13075 m 1 13076 decl (Decl 12969 13077 n "S_CLK" 12970 13078 t "std_logic" … … 12975 13083 uid 3654,0 12976 13084 ) 12977 *43 3(LeafLogPort13085 *437 (LeafLogPort 12978 13086 port (LogicalPort 12979 13087 m 1 … … 12988 13096 uid 3656,0 12989 13097 ) 12990 *43 4(LeafLogPort13098 *438 (LeafLogPort 12991 13099 port (LogicalPort 12992 13100 m 2 … … 13001 13109 uid 3658,0 13002 13110 ) 13003 *43 5(LeafLogPort13111 *439 (LeafLogPort 13004 13112 port (LogicalPort 13005 13113 m 1 … … 13014 13122 uid 3660,0 13015 13123 ) 13016 *4 36(LeafLogPort13124 *440 (LeafLogPort 13017 13125 port (LogicalPort 13018 13126 m 1 … … 13027 13135 uid 3662,0 13028 13136 ) 13029 *4 37(LeafLogPort13137 *441 (LeafLogPort 13030 13138 port (LogicalPort 13031 13139 m 1 … … 13040 13148 uid 3664,0 13041 13149 ) 13042 *4 38(LeafLogPort13150 *442 (LeafLogPort 13043 13151 port (LogicalPort 13044 13152 decl (Decl … … 13051 13159 uid 3666,0 13052 13160 ) 13053 *4 39(LeafLogPort13161 *443 (LeafLogPort 13054 13162 port (LogicalPort 13055 13163 m 1 … … 13064 13172 uid 3668,0 13065 13173 ) 13066 *44 0(LeafLogPort13174 *444 (LeafLogPort 13067 13175 port (LogicalPort 13068 13176 m 1 … … 13077 13185 uid 3696,0 13078 13186 ) 13079 *44 1(LeafLogPort13187 *445 (LeafLogPort 13080 13188 port (LogicalPort 13081 13189 m 2 … … 13091 13199 uid 3698,0 13092 13200 ) 13093 *442 (LeafLogPort13094 port (LogicalPort13095 m 113096 decl (Decl13097 n "TRG_V"13098 t "std_logic"13099 o 5013100 suid 126,013101 )13102 )13103 uid 3886,013104 )13105 *443 (LeafLogPort13106 port (LogicalPort13107 m 113108 decl (Decl13109 n "RS485_C_RE"13110 t "std_logic"13111 o 4013112 suid 127,013113 )13114 )13115 uid 3888,013116 )13117 *444 (LeafLogPort13118 port (LogicalPort13119 m 113120 decl (Decl13121 n "RS485_C_DE"13122 t "std_logic"13123 o 3813124 suid 128,013125 )13126 )13127 uid 3890,013128 )13129 *445 (LeafLogPort13130 port (LogicalPort13131 m 113132 decl (Decl13133 n "RS485_E_RE"13134 t "std_logic"13135 o 4213136 suid 129,013137 )13138 )13139 uid 3892,013140 )13141 13201 *446 (LeafLogPort 13142 13202 port (LogicalPort 13143 13203 m 1 13144 13204 decl (Decl 13145 n " RS485_E_DE"13146 t "std_logic" 13147 o 4113148 suid 1 30,013149 ) 13150 ) 13151 uid 38 94,013205 n "TRG_V" 13206 t "std_logic" 13207 o 50 13208 suid 126,0 13209 ) 13210 ) 13211 uid 3886,0 13152 13212 ) 13153 13213 *447 (LeafLogPort … … 13155 13215 m 1 13156 13216 decl (Decl 13217 n "RS485_C_RE" 13218 t "std_logic" 13219 o 40 13220 suid 127,0 13221 ) 13222 ) 13223 uid 3888,0 13224 ) 13225 *448 (LeafLogPort 13226 port (LogicalPort 13227 m 1 13228 decl (Decl 13229 n "RS485_C_DE" 13230 t "std_logic" 13231 o 38 13232 suid 128,0 13233 ) 13234 ) 13235 uid 3890,0 13236 ) 13237 *449 (LeafLogPort 13238 port (LogicalPort 13239 m 1 13240 decl (Decl 13241 n "RS485_E_RE" 13242 t "std_logic" 13243 o 42 13244 suid 129,0 13245 ) 13246 ) 13247 uid 3892,0 13248 ) 13249 *450 (LeafLogPort 13250 port (LogicalPort 13251 m 1 13252 decl (Decl 13253 n "RS485_E_DE" 13254 t "std_logic" 13255 o 41 13256 suid 130,0 13257 ) 13258 ) 13259 uid 3894,0 13260 ) 13261 *451 (LeafLogPort 13262 port (LogicalPort 13263 m 1 13264 decl (Decl 13157 13265 n "DENABLE" 13158 13266 t "std_logic" … … 13164 13272 uid 3896,0 13165 13273 ) 13166 *4 48(LeafLogPort13274 *452 (LeafLogPort 13167 13275 port (LogicalPort 13168 13276 m 1 … … 13176 13284 uid 3900,0 13177 13285 ) 13178 *4 49(LeafLogPort13286 *453 (LeafLogPort 13179 13287 port (LogicalPort 13180 13288 m 1 … … 13182 13290 n "D_T" 13183 13291 t "std_logic_vector" 13184 b "( 7DOWNTO 0)"13292 b "(5 DOWNTO 0)" 13185 13293 o 31 13186 13294 suid 141,0 … … 13190 13298 uid 5322,0 13191 13299 ) 13192 *45 0(LeafLogPort13300 *454 (LeafLogPort 13193 13301 port (LogicalPort 13194 13302 decl (Decl … … 13203 13311 scheme 0 13204 13312 ) 13205 *45 1(LeafLogPort13313 *455 (LeafLogPort 13206 13314 port (LogicalPort 13207 13315 m 1 … … 13218 13326 scheme 0 13219 13327 ) 13220 *45 2(LeafLogPort13328 *456 (LeafLogPort 13221 13329 port (LogicalPort 13222 13330 m 1 … … 13233 13341 scheme 0 13234 13342 ) 13235 *45 3(LeafLogPort13343 *457 (LeafLogPort 13236 13344 port (LogicalPort 13237 13345 m 4 … … 13246 13354 scheme 0 13247 13355 ) 13248 *45 4(LeafLogPort13356 *458 (LeafLogPort 13249 13357 port (LogicalPort 13250 13358 m 4 … … 13260 13368 uid 8875,0 13261 13369 ) 13262 *45 5(LeafLogPort13370 *459 (LeafLogPort 13263 13371 port (LogicalPort 13264 13372 m 4 … … 13272 13380 uid 9516,0 13273 13381 ) 13274 *4 56(LeafLogPort13382 *460 (LeafLogPort 13275 13383 port (LogicalPort 13276 13384 m 4 … … 13284 13392 uid 10056,0 13285 13393 ) 13286 *4 57(LeafLogPort13394 *461 (LeafLogPort 13287 13395 port (LogicalPort 13288 13396 m 4 … … 13297 13405 uid 10058,0 13298 13406 ) 13299 *4 58(LeafLogPort13407 *462 (LeafLogPort 13300 13408 port (LogicalPort 13301 13409 m 1 … … 13312 13420 scheme 0 13313 13421 ) 13314 *459 (LeafLogPort13315 port (LogicalPort13316 m 413317 decl (Decl13318 n "CLK50_OUT"13319 t "std_logic"13320 o 6013321 suid 184,013322 )13323 )13324 uid 10704,013325 )13326 *460 (LeafLogPort13327 port (LogicalPort13328 m 413329 decl (Decl13330 n "CLK25_OUT"13331 t "std_logic"13332 o 5813333 suid 185,013334 )13335 )13336 uid 10706,013337 )13338 *461 (LeafLogPort13339 port (LogicalPort13340 m 413341 decl (Decl13342 n "CLK25_PSOUT"13343 t "std_logic"13344 o 5913345 suid 186,013346 )13347 )13348 uid 10708,013349 )13350 *462 (LeafLogPort13351 port (LogicalPort13352 m 413353 decl (Decl13354 n "PS_DIR_IN"13355 t "std_logic"13356 o 7013357 suid 187,013358 )13359 )13360 uid 10710,013361 )13362 13422 *463 (LeafLogPort 13363 13423 port (LogicalPort 13364 13424 m 4 13365 13425 decl (Decl 13366 n " PS_DO_IN"13367 t "std_logic" 13368 o 7113369 suid 18 8,013370 ) 13371 ) 13372 uid 107 12,013426 n "CLK50_OUT" 13427 t "std_logic" 13428 o 60 13429 suid 184,0 13430 ) 13431 ) 13432 uid 10704,0 13373 13433 ) 13374 13434 *464 (LeafLogPort … … 13376 13436 m 4 13377 13437 decl (Decl 13378 n " PSEN_OUT"13379 t "std_logic" 13380 o 6813381 suid 18 9,013382 ) 13383 ) 13384 uid 107 14,013438 n "CLK25_OUT" 13439 t "std_logic" 13440 o 58 13441 suid 185,0 13442 ) 13443 ) 13444 uid 10706,0 13385 13445 ) 13386 13446 *465 (LeafLogPort … … 13388 13448 m 4 13389 13449 decl (Decl 13450 n "CLK25_PSOUT" 13451 t "std_logic" 13452 o 59 13453 suid 186,0 13454 ) 13455 ) 13456 uid 10708,0 13457 ) 13458 *466 (LeafLogPort 13459 port (LogicalPort 13460 m 4 13461 decl (Decl 13462 n "PS_DIR_IN" 13463 t "std_logic" 13464 o 70 13465 suid 187,0 13466 ) 13467 ) 13468 uid 10710,0 13469 ) 13470 *467 (LeafLogPort 13471 port (LogicalPort 13472 m 4 13473 decl (Decl 13390 13474 n "PSINCDEC_OUT" 13391 13475 t "std_logic" … … 13396 13480 uid 10716,0 13397 13481 ) 13398 *46 6(LeafLogPort13482 *468 (LeafLogPort 13399 13483 port (LogicalPort 13400 13484 m 4 … … 13410 13494 uid 10718,0 13411 13495 ) 13412 *46 7(LeafLogPort13496 *469 (LeafLogPort 13413 13497 port (LogicalPort 13414 13498 m 4 … … 13425 13509 uid 10720,0 13426 13510 ) 13427 *4 68(LeafLogPort13511 *470 (LeafLogPort 13428 13512 port (LogicalPort 13429 13513 m 4 … … 13441 13525 uid 10722,0 13442 13526 ) 13443 *469 (LeafLogPort13444 port (LogicalPort13445 m 413446 decl (Decl13447 n "PSDONE_extraOUT"13448 t "std_logic"13449 o 6713450 suid 194,013451 )13452 )13453 uid 10724,013454 )13455 *470 (LeafLogPort13456 port (LogicalPort13457 m 413458 decl (Decl13459 n "PSCLK_OUT"13460 t "std_logic"13461 o 6613462 suid 195,013463 )13464 )13465 uid 10726,013466 )13467 13527 *471 (LeafLogPort 13468 13528 port (LogicalPort 13469 13529 m 4 13470 13530 decl (Decl 13531 n "PSDONE_extraOUT" 13532 t "std_logic" 13533 o 67 13534 suid 194,0 13535 ) 13536 ) 13537 uid 10724,0 13538 ) 13539 *472 (LeafLogPort 13540 port (LogicalPort 13541 m 4 13542 decl (Decl 13543 n "PSCLK_OUT" 13544 t "std_logic" 13545 o 66 13546 suid 195,0 13547 ) 13548 ) 13549 uid 10726,0 13550 ) 13551 *473 (LeafLogPort 13552 port (LogicalPort 13553 m 4 13554 decl (Decl 13471 13555 n "LOCKED_extraOUT" 13472 13556 t "std_logic" … … 13477 13561 uid 10728,0 13478 13562 ) 13479 *47 2(LeafLogPort13563 *474 (LeafLogPort 13480 13564 port (LogicalPort 13481 13565 decl (Decl … … 13489 13573 scheme 0 13490 13574 ) 13491 *47 3(LeafLogPort13575 *475 (LeafLogPort 13492 13576 port (LogicalPort 13493 13577 m 1 … … 13502 13586 scheme 0 13503 13587 ) 13504 *47 4(LeafLogPort13588 *476 (LeafLogPort 13505 13589 port (LogicalPort 13506 13590 decl (Decl … … 13514 13598 scheme 0 13515 13599 ) 13516 *47 5(LeafLogPort13600 *477 (LeafLogPort 13517 13601 port (LogicalPort 13518 13602 decl (Decl … … 13526 13610 scheme 0 13527 13611 ) 13528 *47 6(LeafLogPort13612 *478 (LeafLogPort 13529 13613 port (LogicalPort 13530 13614 m 1 … … 13539 13623 uid 12336,0 13540 13624 ) 13541 *477 (LeafLogPort13542 port (LogicalPort13543 m 113544 decl (Decl13545 n "AMBER_LED"13546 t "std_logic"13547 o 2113548 suid 207,013549 )13550 )13551 uid 12768,013552 )13553 *478 (LeafLogPort13554 port (LogicalPort13555 m 113556 decl (Decl13557 n "GREEN_LED"13558 t "std_logic"13559 o 3413560 suid 208,013561 )13562 )13563 uid 12770,013564 )13565 13625 *479 (LeafLogPort 13566 13626 port (LogicalPort 13567 13627 m 1 13568 13628 decl (Decl 13629 n "AMBER_LED" 13630 t "std_logic" 13631 o 21 13632 suid 207,0 13633 ) 13634 ) 13635 uid 12768,0 13636 ) 13637 *480 (LeafLogPort 13638 port (LogicalPort 13639 m 1 13640 decl (Decl 13641 n "GREEN_LED" 13642 t "std_logic" 13643 o 34 13644 suid 208,0 13645 ) 13646 ) 13647 uid 12770,0 13648 ) 13649 *481 (LeafLogPort 13650 port (LogicalPort 13651 m 1 13652 decl (Decl 13569 13653 n "RED_LED" 13570 13654 t "std_logic" … … 13575 13659 uid 12772,0 13576 13660 ) 13577 *48 0(LeafLogPort13661 *482 (LeafLogPort 13578 13662 port (LogicalPort 13579 13663 decl (Decl 13580 n " POSITION_ID"13664 n "LINE" 13581 13665 t "std_logic_vector" 13582 13666 b "( 5 DOWNTO 0 )" … … 13588 13672 scheme 0 13589 13673 ) 13590 *48 1(LeafLogPort13674 *483 (LeafLogPort 13591 13675 port (LogicalPort 13592 13676 decl (Decl … … 13599 13683 uid 13626,0 13600 13684 scheme 0 13685 ) 13686 *484 (LeafLogPort 13687 port (LogicalPort 13688 decl (Decl 13689 n "D_T_in" 13690 t "std_logic_vector" 13691 b "(1 DOWNTO 0)" 13692 o 80 13693 suid 213,0 13694 ) 13695 ) 13696 uid 14320,0 13697 scheme 0 13698 ) 13699 *485 (LeafLogPort 13700 port (LogicalPort 13701 m 4 13702 decl (Decl 13703 n "led" 13704 t "std_logic_vector" 13705 b "(7 DOWNTO 0)" 13706 posAdd 0 13707 o 81 13708 suid 215,0 13709 i "(OTHERS => '0')" 13710 ) 13711 ) 13712 uid 15181,0 13601 13713 ) 13602 13714 ] … … 13607 13719 uid 67,0 13608 13720 optionalChildren [ 13609 *48 2(Sheet13721 *486 (Sheet 13610 13722 sheetRow (SheetRow 13611 13723 headerVa (MVa … … 13624 13736 font "Tahoma,10,0" 13625 13737 ) 13626 emptyMRCItem *48 3(MRCItem13627 litem &3 8813738 emptyMRCItem *487 (MRCItem 13739 litem &392 13628 13740 pos 81 13629 13741 dimension 20 … … 13631 13743 uid 69,0 13632 13744 optionalChildren [ 13633 *48 4(MRCItem13634 litem &3 8913745 *488 (MRCItem 13746 litem &393 13635 13747 pos 0 13636 13748 dimension 20 13637 13749 uid 70,0 13638 13750 ) 13639 *48 5(MRCItem13640 litem &39 013751 *489 (MRCItem 13752 litem &394 13641 13753 pos 1 13642 13754 dimension 23 13643 13755 uid 71,0 13644 13756 ) 13645 *4 86(MRCItem13646 litem &39 113757 *490 (MRCItem 13758 litem &395 13647 13759 pos 2 13648 13760 hidden 1 … … 13650 13762 uid 72,0 13651 13763 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13690 13802 pos 1 13691 13803 dimension 20 13692 13804 uid 3040,0 13693 13805 ) 13694 *49 4(MRCItem13695 litem &4 0813806 *498 (MRCItem 13807 litem &412 13696 13808 pos 2 13697 13809 dimension 20 13698 13810 uid 3277,0 13699 13811 ) 13700 *49 5(MRCItem13701 litem &4 0913812 *499 (MRCItem 13813 litem &413 13702 13814 pos 3 13703 13815 dimension 20 13704 13816 uid 3279,0 13705 13817 ) 13706 * 496(MRCItem13707 litem &41 013818 *500 (MRCItem 13819 litem &414 13708 13820 pos 4 13709 13821 dimension 20 13710 13822 uid 3281,0 13711 13823 ) 13712 * 497(MRCItem13713 litem &41 113824 *501 (MRCItem 13825 litem &415 13714 13826 pos 57 13715 13827 dimension 20 13716 13828 uid 3283,0 13717 13829 ) 13718 * 498(MRCItem13719 litem &41 213830 *502 (MRCItem 13831 litem &416 13720 13832 pos 5 13721 13833 dimension 20 13722 13834 uid 3383,0 13723 13835 ) 13724 * 499(MRCItem13725 litem &41 313836 *503 (MRCItem 13837 litem &417 13726 13838 pos 6 13727 13839 dimension 20 13728 13840 uid 3385,0 13729 13841 ) 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14151 dimension 20 14040 uid 107 17,014041 ) 14042 *55 2(MRCItem14043 litem &4 6614152 uid 10721,0 14153 ) 14154 *556 (MRCItem 14155 litem &470 14044 14156 pos 70 14045 14157 dimension 20 14046 uid 107 19,014047 ) 14048 *55 3(MRCItem14049 litem &4 6714158 uid 10723,0 14159 ) 14160 *557 (MRCItem 14161 litem &471 14050 14162 pos 71 14051 14163 dimension 20 14052 uid 1072 1,014053 ) 14054 *55 4(MRCItem14055 litem &4 6814164 uid 10725,0 14165 ) 14166 *558 (MRCItem 14167 litem &472 14056 14168 pos 72 14057 14169 dimension 20 14058 uid 1072 3,014059 ) 14060 *55 5(MRCItem14061 litem &4 6914170 uid 10727,0 14171 ) 14172 *559 (MRCItem 14173 litem &473 14062 14174 pos 73 14063 14175 dimension 20 14064 uid 10725,014065 )14066 *556 (MRCItem14067 litem &47014068 pos 7414069 dimension 2014070 uid 10727,014071 )14072 *557 (MRCItem14073 litem &47114074 pos 7514075 dimension 2014076 14176 uid 10729,0 14077 14177 ) 14078 *5 58(MRCItem14079 litem &47 214178 *560 (MRCItem 14179 litem &474 14080 14180 pos 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uid 127 69,014113 ) 14114 *56 4(MRCItem14115 litem &4 7814224 uid 12773,0 14225 ) 14226 *568 (MRCItem 14227 litem &482 14116 14228 pos 77 14117 14229 dimension 20 14118 uid 1 2771,014119 ) 14120 *56 5(MRCItem14121 litem &4 7914230 uid 13515,0 14231 ) 14232 *569 (MRCItem 14233 litem &483 14122 14234 pos 78 14123 14235 dimension 20 14124 uid 1 2773,014125 ) 14126 *5 66(MRCItem14127 litem &48 014236 uid 13627,0 14237 ) 14238 *570 (MRCItem 14239 litem &484 14128 14240 pos 79 14129 14241 dimension 20 14130 uid 1 3515,014131 ) 14132 *5 67(MRCItem14133 litem &48 114242 uid 14321,0 14243 ) 14244 *571 (MRCItem 14245 litem &485 14134 14246 pos 80 14135 14247 dimension 20 14136 uid 1 3627,014248 uid 15182,0 14137 14249 ) 14138 14250 ] … … 14147 14259 uid 73,0 14148 14260 optionalChildren [ 14149 *5 68(MRCItem14150 litem &39 214261 *572 (MRCItem 14262 litem &396 14151 14263 pos 0 14152 14264 dimension 20 14153 14265 uid 74,0 14154 14266 ) 14155 *5 69(MRCItem14156 litem &39 414267 *573 (MRCItem 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genericsCommonDM (CommonDM 14211 14323 ldm (LogicalDM 14212 emptyRow *5 76(LEmptyRow14324 emptyRow *580 (LEmptyRow 14213 14325 ) 14214 14326 uid 83,0 14215 14327 optionalChildren [ 14216 *5 77(RefLabelRowHdr14217 ) 14218 *5 78(TitleRowHdr14219 ) 14220 *5 79(FilterRowHdr14221 ) 14222 *58 0(RefLabelColHdr14328 *581 (RefLabelRowHdr 14329 ) 14330 *582 (TitleRowHdr 14331 ) 14332 *583 (FilterRowHdr 14333 ) 14334 *584 (RefLabelColHdr 14223 14335 tm "RefLabelColHdrMgr" 14224 14336 ) 14225 *58 1(RowExpandColHdr14337 *585 (RowExpandColHdr 14226 14338 tm "RowExpandColHdrMgr" 14227 14339 ) 14228 *58 2(GroupColHdr14340 *586 (GroupColHdr 14229 14341 tm "GroupColHdrMgr" 14230 14342 ) 14231 *58 3(NameColHdr14343 *587 (NameColHdr 14232 14344 tm "GenericNameColHdrMgr" 14233 14345 ) 14234 *58 4(TypeColHdr14346 *588 (TypeColHdr 14235 14347 tm "GenericTypeColHdrMgr" 14236 14348 ) 14237 *58 5(InitColHdr14349 *589 (InitColHdr 14238 14350 tm "GenericValueColHdrMgr" 14239 14351 ) 14240 *5 86(PragmaColHdr14352 *590 (PragmaColHdr 14241 14353 tm "GenericPragmaColHdrMgr" 14242 14354 ) 14243 *5 87(EolColHdr14355 *591 (EolColHdr 14244 14356 tm "GenericEolColHdrMgr" 14245 14357 ) … … 14251 14363 uid 95,0 14252 14364 optionalChildren [ 14253 *5 88(Sheet14365 *592 (Sheet 14254 14366 sheetRow (SheetRow 14255 14367 headerVa (MVa … … 14268 14380 font "Tahoma,10,0" 14269 14381 ) 14270 emptyMRCItem *5 89(MRCItem14271 litem &5 7614382 emptyMRCItem *593 (MRCItem 14383 litem &580 14272 14384 pos 0 14273 14385 dimension 20 … … 14275 14387 uid 97,0 14276 14388 optionalChildren [ 14277 *59 0(MRCItem14278 litem &5 7714389 *594 (MRCItem 14390 litem &581 14279 14391 pos 0 14280 14392 dimension 20 14281 14393 uid 98,0 14282 14394 ) 14283 *59 1(MRCItem14284 litem &5 7814395 *595 (MRCItem 14396 litem &582 14285 14397 pos 1 14286 14398 dimension 23 14287 14399 uid 99,0 14288 14400 ) 14289 *59 2(MRCItem14290 litem &5 7914401 *596 (MRCItem 14402 litem &583 14291 14403 pos 2 14292 14404 hidden 1 … … 14305 14417 uid 101,0 14306 14418 optionalChildren [ 14307 *59 3(MRCItem14308 litem &58 014419 *597 (MRCItem 14420 litem &584 14309 14421 pos 0 14310 14422 dimension 20 14311 14423 uid 102,0 14312 14424 ) 14313 *59 4(MRCItem14314 litem &58 214425 *598 (MRCItem 14426 litem &586 14315 14427 pos 1 14316 14428 dimension 50 14317 14429 uid 103,0 14318 14430 ) 14319 *59 5(MRCItem14320 litem &58 314431 *599 (MRCItem 14432 litem &587 14321 14433 pos 2 14322 14434 dimension 100 14323 14435 uid 104,0 14324 14436 ) 14325 * 596(MRCItem14326 litem &58 414437 *600 (MRCItem 14438 litem &588 14327 14439 pos 3 14328 14440 dimension 100 14329 14441 uid 105,0 14330 14442 ) 14331 * 597(MRCItem14332 litem &58 514443 *601 (MRCItem 14444 litem &589 14333 14445 pos 4 14334 14446 dimension 50 14335 14447 uid 106,0 14336 14448 ) 14337 * 598(MRCItem14338 litem &5 8614449 *602 (MRCItem 14450 litem &590 14339 14451 pos 5 14340 14452 dimension 50 14341 14453 uid 107,0 14342 14454 ) 14343 * 599(MRCItem14344 litem &5 8714455 *603 (MRCItem 14456 litem &591 14345 14457 pos 6 14346 14458 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb
r10121 r10123 17 17 ) 18 18 version "24.1" 19 appVersion "2009. 1 (Build 12)"19 appVersion "2009.2 (Build 10)" 20 20 model (Symbol 21 21 commonDM (CommonDM 22 22 ldm (LogicalDM 23 suid 8 1,023 suid 83,0 24 24 usingSuid 1 25 25 emptyRow *1 (LEmptyRow … … 66 66 n "RSRLOAD" 67 67 t "std_logic" 68 o 4 368 o 44 69 69 suid 11,0 70 70 i "'0'" … … 80 80 preAdd 0 81 81 posAdd 0 82 o 1 882 o 19 83 83 suid 15,0 84 84 ) … … 91 91 n "TRG" 92 92 t "STD_LOGIC" 93 o 1 693 o 17 94 94 suid 16,0 95 95 ) … … 104 104 t "std_logic_vector" 105 105 b "(3 downto 0)" 106 o 2 2106 o 23 107 107 suid 17,0 108 108 ) … … 118 118 preAdd 0 119 119 posAdd 0 120 o 3 6120 o 37 121 121 suid 18,0 122 122 ) … … 190 190 n "D0_SRCLK" 191 191 t "STD_LOGIC" 192 o 2 3192 o 24 193 193 suid 24,0 194 194 ) … … 202 202 n "D1_SRCLK" 203 203 t "STD_LOGIC" 204 o 2 4204 o 25 205 205 suid 25,0 206 206 ) … … 214 214 n "D2_SRCLK" 215 215 t "STD_LOGIC" 216 o 2 5216 o 26 217 217 suid 26,0 218 218 ) … … 226 226 n "D3_SRCLK" 227 227 t "STD_LOGIC" 228 o 2 6228 o 27 229 229 suid 27,0 230 230 ) … … 283 283 t "std_logic_vector" 284 284 b "(3 DOWNTO 0)" 285 o 3 0285 o 31 286 286 suid 32,0 287 287 i "(others => '0')" … … 296 296 n "DWRITE" 297 297 t "std_logic" 298 o 29298 o 30 299 299 suid 33,0 300 300 i "'0'" … … 309 309 n "DAC_CS" 310 310 t "std_logic" 311 o 2 7311 o 28 312 312 suid 34,0 313 313 ) … … 321 321 n "T0_CS" 322 322 t "std_logic" 323 o 47 324 suid 35,0 325 ) 326 ) 327 uid 1340,0 328 ) 329 *36 (LogPort 330 port (LogicalPort 331 m 1 332 decl (Decl 333 n "T1_CS" 334 t "std_logic" 335 o 48 336 suid 36,0 337 ) 338 ) 339 uid 1342,0 340 ) 341 *37 (LogPort 342 port (LogicalPort 343 m 1 344 decl (Decl 345 n "T2_CS" 346 t "std_logic" 347 o 49 348 suid 37,0 349 ) 350 ) 351 uid 1344,0 352 ) 353 *38 (LogPort 354 port (LogicalPort 355 m 1 356 decl (Decl 357 n "T3_CS" 358 t "std_logic" 359 o 50 360 suid 38,0 361 ) 362 ) 363 uid 1346,0 364 ) 365 *39 (LogPort 366 port (LogicalPort 367 m 1 368 decl (Decl 369 n "S_CLK" 370 t "std_logic" 323 371 o 46 324 suid 35,0325 )326 )327 uid 1340,0328 )329 *36 (LogPort330 port (LogicalPort331 m 1332 decl (Decl333 n "T1_CS"334 t "std_logic"335 o 47336 suid 36,0337 )338 )339 uid 1342,0340 )341 *37 (LogPort342 port (LogicalPort343 m 1344 decl (Decl345 n "T2_CS"346 t "std_logic"347 o 48348 suid 37,0349 )350 )351 uid 1344,0352 )353 *38 (LogPort354 port (LogicalPort355 m 1356 decl (Decl357 n "T3_CS"358 t "std_logic"359 o 49360 suid 38,0361 )362 )363 uid 1346,0364 )365 *39 (LogPort366 port (LogicalPort367 m 1368 decl (Decl369 n "S_CLK"370 t "std_logic"371 o 45372 372 suid 39,0 373 373 ) … … 382 382 t "std_logic_vector" 383 383 b "(9 DOWNTO 0)" 384 o 5 1384 o 52 385 385 suid 40,0 386 386 ) … … 395 395 t "std_logic_vector" 396 396 b "(15 DOWNTO 0)" 397 o 5 7397 o 58 398 398 suid 41,0 399 399 ) … … 407 407 n "W_RES" 408 408 t "std_logic" 409 o 5 4409 o 55 410 410 suid 42,0 411 411 i "'1'" … … 420 420 n "W_RD" 421 421 t "std_logic" 422 o 5 3422 o 54 423 423 suid 43,0 424 424 i "'1'" … … 433 433 n "W_WR" 434 434 t "std_logic" 435 o 5 5435 o 56 436 436 suid 44,0 437 437 i "'1'" … … 445 445 n "W_INT" 446 446 t "std_logic" 447 o 1 7447 o 18 448 448 suid 45,0 449 449 ) … … 457 457 n "W_CS" 458 458 t "std_logic" 459 o 5 2459 o 53 460 460 suid 46,0 461 461 i "'1'" … … 470 470 n "MOSI" 471 471 t "std_logic" 472 o 3 5472 o 36 473 473 suid 47,0 474 474 i "'0'" … … 485 485 preAdd 0 486 486 posAdd 0 487 o 5 6487 o 57 488 488 suid 48,0 489 489 ) … … 497 497 n "TRG_V" 498 498 t "std_logic" 499 o 5 0499 o 51 500 500 suid 49,0 501 501 ) … … 509 509 n "RS485_C_RE" 510 510 t "std_logic" 511 o 4 0511 o 41 512 512 suid 50,0 513 513 ) … … 521 521 n "RS485_C_DE" 522 522 t "std_logic" 523 o 3 8523 o 39 524 524 suid 51,0 525 525 ) … … 533 533 n "RS485_E_RE" 534 534 t "std_logic" 535 o 43 536 suid 52,0 537 ) 538 ) 539 uid 1661,0 540 ) 541 *53 (LogPort 542 port (LogicalPort 543 m 1 544 decl (Decl 545 n "RS485_E_DE" 546 t "std_logic" 535 547 o 42 536 suid 52,0537 )538 )539 uid 1661,0540 )541 *53 (LogPort542 port (LogicalPort543 m 1544 decl (Decl545 n "RS485_E_DE"546 t "std_logic"547 o 41548 548 suid 53,0 549 549 ) … … 557 557 n "DENABLE" 558 558 t "std_logic" 559 o 2 8559 o 29 560 560 suid 54,0 561 561 i "'0'" … … 570 570 n "SRIN" 571 571 t "std_logic" 572 o 4 4572 o 45 573 573 suid 55,0 574 574 i "'0'" … … 583 583 n "EE_CS" 584 584 t "std_logic" 585 o 3 3585 o 34 586 586 suid 56,0 587 587 ) … … 595 595 n "D_T" 596 596 t "std_logic_vector" 597 b "( 7DOWNTO 0)"598 o 3 1597 b "(5 DOWNTO 0)" 598 o 32 599 599 suid 61,0 600 600 i "(OTHERS => '0')" … … 622 622 t "std_logic_vector" 623 623 b "(3 DOWNTO 0)" 624 o 3 2624 o 33 625 625 suid 65,0 626 626 i "(others => '0')" … … 636 636 t "std_logic_vector" 637 637 b "(7 DOWNTO 0)" 638 o 2 0638 o 21 639 639 suid 66,0 640 640 i "(OTHERS => '0')" … … 650 650 t "std_logic_vector" 651 651 b "(7 DOWNTO 0)" 652 o 19652 o 20 653 653 suid 68,0 654 654 i "(others => '0')" … … 662 662 n "RS485_C_DI" 663 663 t "std_logic" 664 o 14 665 suid 69,0 666 ) 667 ) 668 uid 3578,0 669 ) 670 *63 (LogPort 671 port (LogicalPort 672 m 1 673 decl (Decl 674 n "RS485_C_DO" 675 t "std_logic" 676 o 40 677 suid 70,0 678 ) 679 ) 680 uid 3580,0 681 ) 682 *64 (LogPort 683 port (LogicalPort 684 decl (Decl 685 n "RS485_E_DI" 686 t "std_logic" 687 o 15 688 suid 71,0 689 ) 690 ) 691 uid 3684,0 692 ) 693 *65 (LogPort 694 port (LogicalPort 695 decl (Decl 696 n "RS485_E_DO" 697 t "std_logic" 698 o 16 699 suid 72,0 700 ) 701 ) 702 uid 3686,0 703 ) 704 *66 (LogPort 705 port (LogicalPort 706 m 1 707 decl (Decl 708 n "AMBER_LED" 709 t "std_logic" 710 o 22 711 suid 77,0 712 ) 713 ) 714 uid 4028,0 715 ) 716 *67 (LogPort 717 port (LogicalPort 718 m 1 719 decl (Decl 720 n "GREEN_LED" 721 t "std_logic" 722 o 35 723 suid 78,0 724 ) 725 ) 726 uid 4030,0 727 ) 728 *68 (LogPort 729 port (LogicalPort 730 m 1 731 decl (Decl 732 n "RED_LED" 733 t "std_logic" 734 o 38 735 suid 79,0 736 ) 737 ) 738 uid 4032,0 739 ) 740 *69 (LogPort 741 port (LogicalPort 742 decl (Decl 743 n "REFCLK" 744 t "std_logic" 664 745 o 13 665 suid 69,0 666 ) 667 ) 668 uid 3578,0 669 ) 670 *63 (LogPort 671 port (LogicalPort 672 m 1 673 decl (Decl 674 n "RS485_C_DO" 675 t "std_logic" 676 o 39 677 suid 70,0 678 ) 679 ) 680 uid 3580,0 681 ) 682 *64 (LogPort 683 port (LogicalPort 684 decl (Decl 685 n "RS485_E_DI" 686 t "std_logic" 687 o 14 688 suid 71,0 689 ) 690 ) 691 uid 3684,0 692 ) 693 *65 (LogPort 694 port (LogicalPort 695 decl (Decl 696 n "RS485_E_DO" 697 t "std_logic" 698 o 15 699 suid 72,0 700 ) 701 ) 702 uid 3686,0 703 ) 704 *66 (LogPort 705 port (LogicalPort 706 m 1 707 decl (Decl 708 n "AMBER_LED" 709 t "std_logic" 710 o 21 711 suid 77,0 712 ) 713 ) 714 uid 4028,0 715 ) 716 *67 (LogPort 717 port (LogicalPort 718 m 1 719 decl (Decl 720 n "GREEN_LED" 721 t "std_logic" 722 o 34 723 suid 78,0 724 ) 725 ) 726 uid 4030,0 727 ) 728 *68 (LogPort 729 port (LogicalPort 730 m 1 731 decl (Decl 732 n "RED_LED" 733 t "std_logic" 734 o 37 735 suid 79,0 736 ) 737 ) 738 uid 4032,0 739 ) 740 *69 (LogPort 741 port (LogicalPort 742 decl (Decl 743 n "POSITION_ID" 746 suid 81,0 747 ) 748 ) 749 uid 4263,0 750 ) 751 *70 (LogPort 752 port (LogicalPort 753 decl (Decl 754 n "LINE" 744 755 t "std_logic_vector" 745 756 b "( 5 DOWNTO 0 )" 757 o 12 758 suid 82,0 759 ) 760 ) 761 uid 4293,0 762 ) 763 *71 (LogPort 764 port (LogicalPort 765 decl (Decl 766 n "D_T_in" 767 t "std_logic_vector" 768 b "(1 DOWNTO 0)" 746 769 o 11 747 suid 80,0 748 ) 749 ) 750 uid 4164,0 751 ) 752 *70 (LogPort 753 port (LogicalPort 754 decl (Decl 755 n "REFCLK" 756 t "std_logic" 757 o 12 758 suid 81,0 759 ) 760 ) 761 uid 4263,0 770 suid 83,0 771 ) 772 ) 773 uid 4323,0 762 774 ) 763 775 ] … … 768 780 uid 66,0 769 781 optionalChildren [ 770 *7 1(Sheet782 *72 (Sheet 771 783 sheetRow (SheetRow 772 784 headerVa (MVa … … 785 797 font "Tahoma,10,0" 786 798 ) 787 emptyMRCItem *7 2(MRCItem799 emptyMRCItem *73 (MRCItem 788 800 litem &1 789 801 pos 3 … … 792 804 uid 68,0 793 805 optionalChildren [ 794 *7 3(MRCItem806 *74 (MRCItem 795 807 litem &2 796 808 pos 0 … … 798 810 uid 69,0 799 811 ) 800 *7 4(MRCItem812 *75 (MRCItem 801 813 litem &3 802 814 pos 1 … … 804 816 uid 70,0 805 817 ) 806 *7 5(MRCItem818 *76 (MRCItem 807 819 litem &4 808 820 pos 2 … … 811 823 uid 71,0 812 824 ) 813 *7 6(MRCItem825 *77 (MRCItem 814 826 litem &14 815 827 pos 0 … … 817 829 uid 689,0 818 830 ) 819 *7 7(MRCItem831 *78 (MRCItem 820 832 litem &15 821 833 pos 2 … … 823 835 uid 1110,0 824 836 ) 825 *7 8(MRCItem837 *79 (MRCItem 826 838 litem &16 827 839 pos 3 … … 829 841 uid 1112,0 830 842 ) 831 * 79(MRCItem843 *80 (MRCItem 832 844 litem &17 833 845 pos 4 … … 835 847 uid 1114,0 836 848 ) 837 *8 0(MRCItem849 *81 (MRCItem 838 850 litem &18 839 851 pos 5 … … 841 853 uid 1154,0 842 854 ) 843 *8 1(MRCItem855 *82 (MRCItem 844 856 litem &19 845 857 pos 6 … … 847 859 uid 1156,0 848 860 ) 849 *8 2(MRCItem861 *83 (MRCItem 850 862 litem &20 851 863 pos 7 … … 853 865 uid 1158,0 854 866 ) 855 *8 3(MRCItem867 *84 (MRCItem 856 868 litem &21 857 869 pos 8 … … 859 871 uid 1160,0 860 872 ) 861 *8 4(MRCItem873 *85 (MRCItem 862 874 litem &22 863 875 pos 9 … … 865 877 uid 1162,0 866 878 ) 867 *8 5(MRCItem879 *86 (MRCItem 868 880 litem &23 869 881 pos 10 … … 871 883 uid 1164,0 872 884 ) 873 *8 6(MRCItem885 *87 (MRCItem 874 886 litem &24 875 887 pos 11 … … 877 889 uid 1219,0 878 890 ) 879 *8 7(MRCItem891 *88 (MRCItem 880 892 litem &25 881 893 pos 12 … … 883 895 uid 1221,0 884 896 ) 885 *8 8(MRCItem897 *89 (MRCItem 886 898 litem &26 887 899 pos 13 … … 889 901 uid 1223,0 890 902 ) 891 * 89(MRCItem903 *90 (MRCItem 892 904 litem &27 893 905 pos 14 … … 895 907 uid 1225,0 896 908 ) 897 *9 0(MRCItem909 *91 (MRCItem 898 910 litem &28 899 911 pos 15 … … 901 913 uid 1270,0 902 914 ) 903 *9 1(MRCItem915 *92 (MRCItem 904 916 litem &29 905 917 pos 16 … … 907 919 uid 1272,0 908 920 ) 909 *9 2(MRCItem921 *93 (MRCItem 910 922 litem &30 911 923 pos 17 … … 913 925 uid 1274,0 914 926 ) 915 *9 3(MRCItem927 *94 (MRCItem 916 928 litem &31 917 929 pos 18 … … 919 931 uid 1276,0 920 932 ) 921 *9 4(MRCItem933 *95 (MRCItem 922 934 litem &32 923 935 pos 19 … … 925 937 uid 1278,0 926 938 ) 927 *9 5(MRCItem939 *96 (MRCItem 928 940 litem &33 929 941 pos 20 … … 931 943 uid 1280,0 932 944 ) 933 *9 6(MRCItem945 *97 (MRCItem 934 946 litem &34 935 947 pos 1 … … 937 949 uid 1337,0 938 950 ) 939 *9 7(MRCItem951 *98 (MRCItem 940 952 litem &35 941 953 pos 21 … … 943 955 uid 1339,0 944 956 ) 945 *9 8(MRCItem957 *99 (MRCItem 946 958 litem &36 947 959 pos 22 … … 949 961 uid 1341,0 950 962 ) 951 * 99(MRCItem963 *100 (MRCItem 952 964 litem &37 953 965 pos 23 … … 955 967 uid 1343,0 956 968 ) 957 *10 0(MRCItem969 *101 (MRCItem 958 970 litem &38 959 971 pos 24 … … 961 973 uid 1345,0 962 974 ) 963 *10 1(MRCItem975 *102 (MRCItem 964 976 litem &39 965 977 pos 25 … … 967 979 uid 1347,0 968 980 ) 969 *10 2(MRCItem981 *103 (MRCItem 970 982 litem &40 971 983 pos 26 … … 973 985 uid 1349,0 974 986 ) 975 *10 3(MRCItem987 *104 (MRCItem 976 988 litem &41 977 989 pos 27 … … 979 991 uid 1351,0 980 992 ) 981 *10 4(MRCItem993 *105 (MRCItem 982 994 litem &42 983 995 pos 28 … … 985 997 uid 1353,0 986 998 ) 987 *10 5(MRCItem999 *106 (MRCItem 988 1000 litem &43 989 1001 pos 29 … … 991 1003 uid 1355,0 992 1004 ) 993 *10 6(MRCItem1005 *107 (MRCItem 994 1006 litem &44 995 1007 pos 30 … … 997 1009 uid 1357,0 998 1010 ) 999 *10 7(MRCItem1011 *108 (MRCItem 1000 1012 litem &45 1001 1013 pos 31 … … 1003 1015 uid 1359,0 1004 1016 ) 1005 *10 8(MRCItem1017 *109 (MRCItem 1006 1018 litem &46 1007 1019 pos 32 … … 1009 1021 uid 1361,0 1010 1022 ) 1011 *1 09(MRCItem1023 *110 (MRCItem 1012 1024 litem &47 1013 1025 pos 33 … … 1015 1027 uid 1616,0 1016 1028 ) 1017 *11 0(MRCItem1029 *111 (MRCItem 1018 1030 litem &48 1019 1031 pos 34 … … 1021 1033 uid 1618,0 1022 1034 ) 1023 *11 1(MRCItem1035 *112 (MRCItem 1024 1036 litem &49 1025 1037 pos 35 … … 1027 1039 uid 1654,0 1028 1040 ) 1029 *11 2(MRCItem1041 *113 (MRCItem 1030 1042 litem &50 1031 1043 pos 36 … … 1033 1045 uid 1656,0 1034 1046 ) 1035 *11 3(MRCItem1047 *114 (MRCItem 1036 1048 litem &51 1037 1049 pos 37 … … 1039 1051 uid 1658,0 1040 1052 ) 1041 *11 4(MRCItem1053 *115 (MRCItem 1042 1054 litem &52 1043 1055 pos 38 … … 1045 1057 uid 1660,0 1046 1058 ) 1047 *11 5(MRCItem1059 *116 (MRCItem 1048 1060 litem &53 1049 1061 pos 39 … … 1051 1063 uid 1662,0 1052 1064 ) 1053 *11 6(MRCItem1065 *117 (MRCItem 1054 1066 litem &54 1055 1067 pos 40 … … 1057 1069 uid 1664,0 1058 1070 ) 1059 *11 7(MRCItem1071 *118 (MRCItem 1060 1072 litem &55 1061 1073 pos 51 … … 1063 1075 uid 1666,0 1064 1076 ) 1065 *11 8(MRCItem1077 *119 (MRCItem 1066 1078 litem &56 1067 1079 pos 41 … … 1069 1081 uid 1668,0 1070 1082 ) 1071 *1 19(MRCItem1083 *120 (MRCItem 1072 1084 litem &57 1073 1085 pos 42 … … 1075 1087 uid 2066,0 1076 1088 ) 1077 *12 0(MRCItem1089 *121 (MRCItem 1078 1090 litem &58 1079 1091 pos 43 … … 1081 1093 uid 2917,0 1082 1094 ) 1083 *12 1(MRCItem1095 *122 (MRCItem 1084 1096 litem &59 1085 1097 pos 44 … … 1087 1099 uid 2947,0 1088 1100 ) 1089 *12 2(MRCItem1101 *123 (MRCItem 1090 1102 litem &60 1091 1103 pos 45 … … 1093 1105 uid 3024,0 1094 1106 ) 1095 *12 3(MRCItem1107 *124 (MRCItem 1096 1108 litem &61 1097 1109 pos 46 … … 1099 1111 uid 3454,0 1100 1112 ) 1101 *12 4(MRCItem1113 *125 (MRCItem 1102 1114 litem &62 1103 1115 pos 47 … … 1105 1117 uid 3577,0 1106 1118 ) 1107 *12 5(MRCItem1119 *126 (MRCItem 1108 1120 litem &63 1109 1121 pos 48 … … 1111 1123 uid 3579,0 1112 1124 ) 1113 *12 6(MRCItem1125 *127 (MRCItem 1114 1126 litem &64 1115 1127 pos 49 … … 1117 1129 uid 3683,0 1118 1130 ) 1119 *12 7(MRCItem1131 *128 (MRCItem 1120 1132 litem &65 1121 1133 pos 50 … … 1123 1135 uid 3685,0 1124 1136 ) 1125 *12 8(MRCItem1137 *129 (MRCItem 1126 1138 litem &66 1127 1139 pos 52 … … 1129 1141 uid 4027,0 1130 1142 ) 1131 *1 29(MRCItem1143 *130 (MRCItem 1132 1144 litem &67 1133 1145 pos 53 … … 1135 1147 uid 4029,0 1136 1148 ) 1137 *13 0(MRCItem1149 *131 (MRCItem 1138 1150 litem &68 1139 1151 pos 54 … … 1141 1153 uid 4031,0 1142 1154 ) 1143 *13 1(MRCItem1155 *132 (MRCItem 1144 1156 litem &69 1157 pos 56 1158 dimension 20 1159 uid 4262,0 1160 ) 1161 *133 (MRCItem 1162 litem &70 1145 1163 pos 55 1146 1164 dimension 20 1147 uid 4 163,01148 ) 1149 *13 2(MRCItem1150 litem &7 01151 pos 5 61152 dimension 20 1153 uid 4 262,01165 uid 4292,0 1166 ) 1167 *134 (MRCItem 1168 litem &71 1169 pos 57 1170 dimension 20 1171 uid 4322,0 1154 1172 ) 1155 1173 ] … … 1164 1182 uid 72,0 1165 1183 optionalChildren [ 1166 *13 3(MRCItem1184 *135 (MRCItem 1167 1185 litem &5 1168 1186 pos 0 … … 1170 1188 uid 73,0 1171 1189 ) 1172 *13 4(MRCItem1190 *136 (MRCItem 1173 1191 litem &7 1174 1192 pos 1 … … 1176 1194 uid 74,0 1177 1195 ) 1178 *13 5(MRCItem1196 *137 (MRCItem 1179 1197 litem &8 1180 1198 pos 2 … … 1182 1200 uid 75,0 1183 1201 ) 1184 *13 6(MRCItem1202 *138 (MRCItem 1185 1203 litem &9 1186 1204 pos 3 … … 1188 1206 uid 76,0 1189 1207 ) 1190 *13 7(MRCItem1208 *139 (MRCItem 1191 1209 litem &10 1192 1210 pos 4 … … 1194 1212 uid 77,0 1195 1213 ) 1196 *1 38(MRCItem1214 *140 (MRCItem 1197 1215 litem &11 1198 1216 pos 5 … … 1200 1218 uid 78,0 1201 1219 ) 1202 *1 39(MRCItem1220 *141 (MRCItem 1203 1221 litem &12 1204 1222 pos 6 … … 1206 1224 uid 79,0 1207 1225 ) 1208 *14 0(MRCItem1226 *142 (MRCItem 1209 1227 litem &13 1210 1228 pos 7 … … 1227 1245 genericsCommonDM (CommonDM 1228 1246 ldm (LogicalDM 1229 emptyRow *14 1(LEmptyRow1247 emptyRow *143 (LEmptyRow 1230 1248 ) 1231 1249 uid 82,0 1232 1250 optionalChildren [ 1233 *14 2(RefLabelRowHdr1234 ) 1235 *14 3(TitleRowHdr1236 ) 1237 *14 4(FilterRowHdr1238 ) 1239 *14 5(RefLabelColHdr1251 *144 (RefLabelRowHdr 1252 ) 1253 *145 (TitleRowHdr 1254 ) 1255 *146 (FilterRowHdr 1256 ) 1257 *147 (RefLabelColHdr 1240 1258 tm "RefLabelColHdrMgr" 1241 1259 ) 1242 *14 6(RowExpandColHdr1260 *148 (RowExpandColHdr 1243 1261 tm "RowExpandColHdrMgr" 1244 1262 ) 1245 *14 7(GroupColHdr1263 *149 (GroupColHdr 1246 1264 tm "GroupColHdrMgr" 1247 1265 ) 1248 *1 48(NameColHdr1266 *150 (NameColHdr 1249 1267 tm "GenericNameColHdrMgr" 1250 1268 ) 1251 *1 49(TypeColHdr1269 *151 (TypeColHdr 1252 1270 tm "GenericTypeColHdrMgr" 1253 1271 ) 1254 *15 0(InitColHdr1272 *152 (InitColHdr 1255 1273 tm "GenericValueColHdrMgr" 1256 1274 ) 1257 *15 1(PragmaColHdr1275 *153 (PragmaColHdr 1258 1276 tm "GenericPragmaColHdrMgr" 1259 1277 ) 1260 *15 2(EolColHdr1278 *154 (EolColHdr 1261 1279 tm "GenericEolColHdrMgr" 1262 1280 ) … … 1268 1286 uid 94,0 1269 1287 optionalChildren [ 1270 *15 3(Sheet1288 *155 (Sheet 1271 1289 sheetRow (SheetRow 1272 1290 headerVa (MVa … … 1285 1303 font "Tahoma,10,0" 1286 1304 ) 1287 emptyMRCItem *15 4(MRCItem1288 litem &14 11305 emptyMRCItem *156 (MRCItem 1306 litem &143 1289 1307 pos 3 1290 1308 dimension 20 … … 1292 1310 uid 96,0 1293 1311 optionalChildren [ 1294 *15 5(MRCItem1295 litem &14 21312 *157 (MRCItem 1313 litem &144 1296 1314 pos 0 1297 1315 dimension 20 1298 1316 uid 97,0 1299 1317 ) 1300 *15 6(MRCItem1301 litem &14 31318 *158 (MRCItem 1319 litem &145 1302 1320 pos 1 1303 1321 dimension 23 1304 1322 uid 98,0 1305 1323 ) 1306 *15 7(MRCItem1307 litem &14 41324 *159 (MRCItem 1325 litem &146 1308 1326 pos 2 1309 1327 hidden 1 … … 1322 1340 uid 100,0 1323 1341 optionalChildren [ 1324 *1 58(MRCItem1325 litem &14 51342 *160 (MRCItem 1343 litem &147 1326 1344 pos 0 1327 1345 dimension 20 1328 1346 uid 101,0 1329 1347 ) 1330 *1 59(MRCItem1331 litem &14 71348 *161 (MRCItem 1349 litem &149 1332 1350 pos 1 1333 1351 dimension 50 1334 1352 uid 102,0 1335 1353 ) 1336 *16 0(MRCItem1337 litem &1 481354 *162 (MRCItem 1355 litem &150 1338 1356 pos 2 1339 1357 dimension 100 1340 1358 uid 103,0 1341 1359 ) 1342 *16 1(MRCItem1343 litem &1 491360 *163 (MRCItem 1361 litem &151 1344 1362 pos 3 1345 1363 dimension 100 1346 1364 uid 104,0 1347 1365 ) 1348 *16 2(MRCItem1349 litem &15 01366 *164 (MRCItem 1367 litem &152 1350 1368 pos 4 1351 1369 dimension 50 1352 1370 uid 105,0 1353 1371 ) 1354 *16 3(MRCItem1355 litem &15 11372 *165 (MRCItem 1373 litem &153 1356 1374 pos 5 1357 1375 dimension 50 1358 1376 uid 106,0 1359 1377 ) 1360 *16 4(MRCItem1361 litem &15 21378 *166 (MRCItem 1379 litem &154 1362 1380 pos 6 1363 1381 dimension 80 … … 1382 1400 (vvPair 1383 1401 variable "HDLDir" 1384 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"1402 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 1385 1403 ) 1386 1404 (vvPair 1387 1405 variable "HDSDir" 1388 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"1406 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 1389 1407 ) 1390 1408 (vvPair 1391 1409 variable "SideDataDesignDir" 1392 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"1410 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info" 1393 1411 ) 1394 1412 (vvPair 1395 1413 variable "SideDataUserDir" 1396 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"1414 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user" 1397 1415 ) 1398 1416 (vvPair 1399 1417 variable "SourceDir" 1400 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"1418 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 1401 1419 ) 1402 1420 (vvPair … … 1414 1432 (vvPair 1415 1433 variable "d" 1416 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board"1434 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board" 1417 1435 ) 1418 1436 (vvPair 1419 1437 variable "d_logical" 1420 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board"1438 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board" 1421 1439 ) 1422 1440 (vvPair 1423 1441 variable "date" 1424 value " 14.01.2011"1442 value "27.01.2011" 1425 1443 ) 1426 1444 (vvPair 1427 1445 variable "day" 1428 value " Fr"1446 value "Do" 1429 1447 ) 1430 1448 (vvPair 1431 1449 variable "day_long" 1432 value " Freitag"1450 value "Donnerstag" 1433 1451 ) 1434 1452 (vvPair 1435 1453 variable "dd" 1436 value " 14"1454 value "27" 1437 1455 ) 1438 1456 (vvPair … … 1462 1480 (vvPair 1463 1481 variable "host" 1464 value " IHP110"1482 value "E5B-LABOR6" 1465 1483 ) 1466 1484 (vvPair … … 1510 1528 (vvPair 1511 1529 variable "p" 1512 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"1530 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb" 1513 1531 ) 1514 1532 (vvPair 1515 1533 variable "p_logical" 1516 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"1534 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb" 1517 1535 ) 1518 1536 (vvPair … … 1538 1556 (vvPair 1539 1557 variable "task_ModelSimPath" 1540 value " D:\\modeltech_6.5e\\win32"1558 value "<TBD>" 1541 1559 ) 1542 1560 (vvPair … … 1570 1588 (vvPair 1571 1589 variable "time" 1572 value " 09:57:26"1590 value "17:58:52" 1573 1591 ) 1574 1592 (vvPair … … 1578 1596 (vvPair 1579 1597 variable "user" 1580 value "d aqct3"1598 value "dneise" 1581 1599 ) 1582 1600 (vvPair 1583 1601 variable "version" 1584 value "2009. 1 (Build 12)"1602 value "2009.2 (Build 10)" 1585 1603 ) 1586 1604 (vvPair … … 1601 1619 uid 51,0 1602 1620 optionalChildren [ 1603 *16 5(SymbolBody1621 *167 (SymbolBody 1604 1622 uid 8,0 1605 1623 optionalChildren [ 1606 *16 6(CptPort1624 *168 (CptPort 1607 1625 uid 693,0 1608 1626 ps "OnEdgeStrategy" … … 1646 1664 font "Courier New,8,0" 1647 1665 ) 1648 xt "44000,35600,75500,36400" 1649 st "RSRLOAD : OUT std_logic := '0' ; 1650 " 1666 xt "44000,36400,75000,37200" 1667 st "RSRLOAD : OUT std_logic := '0' ;" 1651 1668 ) 1652 1669 thePort (LogicalPort … … 1655 1672 n "RSRLOAD" 1656 1673 t "std_logic" 1657 o 4 31674 o 44 1658 1675 suid 11,0 1659 1676 i "'0'" … … 1661 1678 ) 1662 1679 ) 1663 *16 7(CptPort1680 *169 (CptPort 1664 1681 uid 1116,0 1665 1682 ps "OnEdgeStrategy" … … 1692 1709 font "Courier New,8,0" 1693 1710 ) 1694 xt "44000,15600,62000,16400" 1695 st "X_50M : IN STD_LOGIC ; 1696 " 1711 xt "44000,16400,61500,17200" 1712 st "X_50M : IN STD_LOGIC ;" 1697 1713 ) 1698 1714 thePort (LogicalPort … … 1702 1718 preAdd 0 1703 1719 posAdd 0 1704 o 1 81720 o 19 1705 1721 suid 15,0 1706 1722 ) 1707 1723 ) 1708 1724 ) 1709 *1 68(CptPort1725 *170 (CptPort 1710 1726 uid 1121,0 1711 1727 ps "OnEdgeStrategy" … … 1738 1754 font "Courier New,8,0" 1739 1755 ) 1740 xt "44000,14000,62000,14800" 1741 st "TRG : IN STD_LOGIC ; 1742 " 1756 xt "44000,14800,61500,15600" 1757 st "TRG : IN STD_LOGIC ;" 1743 1758 ) 1744 1759 thePort (LogicalPort … … 1746 1761 n "TRG" 1747 1762 t "STD_LOGIC" 1748 o 1 61763 o 17 1749 1764 suid 16,0 1750 1765 ) 1751 1766 ) 1752 1767 ) 1753 *1 69(CptPort1768 *171 (CptPort 1754 1769 uid 1126,0 1755 1770 ps "OnEdgeStrategy" … … 1783 1798 font "Courier New,8,0" 1784 1799 ) 1785 xt "44000,18800,72000,19600" 1786 st "A_CLK : OUT std_logic_vector (3 downto 0) ; 1787 " 1800 xt "44000,19600,71500,20400" 1801 st "A_CLK : OUT std_logic_vector (3 downto 0) ;" 1788 1802 ) 1789 1803 thePort (LogicalPort … … 1793 1807 t "std_logic_vector" 1794 1808 b "(3 downto 0)" 1795 o 2 21809 o 23 1796 1810 suid 17,0 1797 1811 ) 1798 1812 ) 1799 1813 ) 1800 *17 0(CptPort1814 *172 (CptPort 1801 1815 uid 1166,0 1802 1816 ps "OnEdgeStrategy" … … 1830 1844 font "Courier New,8,0" 1831 1845 ) 1832 xt "44000,30000,62000,30800" 1833 st "OE_ADC : OUT STD_LOGIC ; 1834 " 1846 xt "44000,30800,61500,31600" 1847 st "OE_ADC : OUT STD_LOGIC ;" 1835 1848 ) 1836 1849 thePort (LogicalPort … … 1841 1854 preAdd 0 1842 1855 posAdd 0 1843 o 3 61856 o 37 1844 1857 suid 18,0 1845 1858 ) 1846 1859 ) 1847 1860 ) 1848 *17 1(CptPort1861 *173 (CptPort 1849 1862 uid 1171,0 1850 1863 ps "OnEdgeStrategy" … … 1877 1890 font "Courier New,8,0" 1878 1891 ) 1879 xt "44000,5200,72000,6000" 1880 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ; 1881 " 1892 xt "44000,5200,71500,6000" 1893 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ;" 1882 1894 ) 1883 1895 thePort (LogicalPort … … 1891 1903 ) 1892 1904 ) 1893 *17 2(CptPort1905 *174 (CptPort 1894 1906 uid 1176,0 1895 1907 ps "OnEdgeStrategy" … … 1922 1934 font "Courier New,8,0" 1923 1935 ) 1924 xt "44000,2000,72500,2800" 1925 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ; 1926 " 1936 xt "44000,2000,72000,2800" 1937 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ;" 1927 1938 ) 1928 1939 thePort (LogicalPort … … 1936 1947 ) 1937 1948 ) 1938 *17 3(CptPort1949 *175 (CptPort 1939 1950 uid 1181,0 1940 1951 ps "OnEdgeStrategy" … … 1967 1978 font "Courier New,8,0" 1968 1979 ) 1969 xt "44000,2800,72500,3600" 1970 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ; 1971 " 1980 xt "44000,2800,72000,3600" 1981 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ;" 1972 1982 ) 1973 1983 thePort (LogicalPort … … 1981 1991 ) 1982 1992 ) 1983 *17 4(CptPort1993 *176 (CptPort 1984 1994 uid 1186,0 1985 1995 ps "OnEdgeStrategy" … … 2012 2022 font "Courier New,8,0" 2013 2023 ) 2014 xt "44000,3600,72500,4400" 2015 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ; 2016 " 2024 xt "44000,3600,72000,4400" 2025 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ;" 2017 2026 ) 2018 2027 thePort (LogicalPort … … 2026 2035 ) 2027 2036 ) 2028 *17 5(CptPort2037 *177 (CptPort 2029 2038 uid 1191,0 2030 2039 ps "OnEdgeStrategy" … … 2057 2066 font "Courier New,8,0" 2058 2067 ) 2059 xt "44000,4400,72500,5200" 2060 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ; 2061 " 2068 xt "44000,4400,72000,5200" 2069 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ;" 2062 2070 ) 2063 2071 thePort (LogicalPort … … 2071 2079 ) 2072 2080 ) 2073 *17 6(CptPort2081 *178 (CptPort 2074 2082 uid 1227,0 2075 2083 ps "OnEdgeStrategy" … … 2103 2111 font "Courier New,8,0" 2104 2112 ) 2105 xt "44000,19600,62000,20400" 2106 st "D0_SRCLK : OUT STD_LOGIC ; 2107 " 2113 xt "44000,20400,61500,21200" 2114 st "D0_SRCLK : OUT STD_LOGIC ;" 2108 2115 ) 2109 2116 thePort (LogicalPort … … 2112 2119 n "D0_SRCLK" 2113 2120 t "STD_LOGIC" 2114 o 2 32121 o 24 2115 2122 suid 24,0 2116 2123 ) 2117 2124 ) 2118 2125 ) 2119 *17 7(CptPort2126 *179 (CptPort 2120 2127 uid 1232,0 2121 2128 ps "OnEdgeStrategy" … … 2149 2156 font "Courier New,8,0" 2150 2157 ) 2151 xt "44000,20400,62000,21200" 2152 st "D1_SRCLK : OUT STD_LOGIC ; 2153 " 2158 xt "44000,21200,61500,22000" 2159 st "D1_SRCLK : OUT STD_LOGIC ;" 2154 2160 ) 2155 2161 thePort (LogicalPort … … 2158 2164 n "D1_SRCLK" 2159 2165 t "STD_LOGIC" 2160 o 2 42166 o 25 2161 2167 suid 25,0 2162 2168 ) 2163 2169 ) 2164 2170 ) 2165 *1 78(CptPort2171 *180 (CptPort 2166 2172 uid 1237,0 2167 2173 ps "OnEdgeStrategy" … … 2195 2201 font "Courier New,8,0" 2196 2202 ) 2197 xt "44000,21200,62000,22000" 2198 st "D2_SRCLK : OUT STD_LOGIC ; 2199 " 2203 xt "44000,22000,61500,22800" 2204 st "D2_SRCLK : OUT STD_LOGIC ;" 2200 2205 ) 2201 2206 thePort (LogicalPort … … 2204 2209 n "D2_SRCLK" 2205 2210 t "STD_LOGIC" 2206 o 2 52211 o 26 2207 2212 suid 26,0 2208 2213 ) 2209 2214 ) 2210 2215 ) 2211 *1 79(CptPort2216 *181 (CptPort 2212 2217 uid 1242,0 2213 2218 ps "OnEdgeStrategy" … … 2241 2246 font "Courier New,8,0" 2242 2247 ) 2243 xt "44000,22000,62000,22800" 2244 st "D3_SRCLK : OUT STD_LOGIC ; 2245 " 2248 xt "44000,22800,61500,23600" 2249 st "D3_SRCLK : OUT STD_LOGIC ;" 2246 2250 ) 2247 2251 thePort (LogicalPort … … 2250 2254 n "D3_SRCLK" 2251 2255 t "STD_LOGIC" 2252 o 2 62256 o 27 2253 2257 suid 27,0 2254 2258 ) 2255 2259 ) 2256 2260 ) 2257 *18 0(CptPort2261 *182 (CptPort 2258 2262 uid 1282,0 2259 2263 ps "OnEdgeStrategy" … … 2286 2290 font "Courier New,8,0" 2287 2291 ) 2288 xt "44000,6000,62000,6800" 2289 st "D0_SROUT : IN std_logic ; 2290 " 2292 xt "44000,6000,61500,6800" 2293 st "D0_SROUT : IN std_logic ;" 2291 2294 ) 2292 2295 thePort (LogicalPort … … 2299 2302 ) 2300 2303 ) 2301 *18 1(CptPort2304 *183 (CptPort 2302 2305 uid 1287,0 2303 2306 ps "OnEdgeStrategy" … … 2330 2333 font "Courier New,8,0" 2331 2334 ) 2332 xt "44000,6800,62000,7600" 2333 st "D1_SROUT : IN std_logic ; 2334 " 2335 xt "44000,6800,61500,7600" 2336 st "D1_SROUT : IN std_logic ;" 2335 2337 ) 2336 2338 thePort (LogicalPort … … 2343 2345 ) 2344 2346 ) 2345 *18 2(CptPort2347 *184 (CptPort 2346 2348 uid 1292,0 2347 2349 ps "OnEdgeStrategy" … … 2374 2376 font "Courier New,8,0" 2375 2377 ) 2376 xt "44000,7600,62000,8400" 2377 st "D2_SROUT : IN std_logic ; 2378 " 2378 xt "44000,7600,61500,8400" 2379 st "D2_SROUT : IN std_logic ;" 2379 2380 ) 2380 2381 thePort (LogicalPort … … 2387 2388 ) 2388 2389 ) 2389 *18 3(CptPort2390 *185 (CptPort 2390 2391 uid 1297,0 2391 2392 ps "OnEdgeStrategy" … … 2418 2419 font "Courier New,8,0" 2419 2420 ) 2420 xt "44000,8400,62000,9200" 2421 st "D3_SROUT : IN std_logic ; 2422 " 2421 xt "44000,8400,61500,9200" 2422 st "D3_SROUT : IN std_logic ;" 2423 2423 ) 2424 2424 thePort (LogicalPort … … 2431 2431 ) 2432 2432 ) 2433 *18 4(CptPort2433 *186 (CptPort 2434 2434 uid 1302,0 2435 2435 ps "OnEdgeStrategy" … … 2473 2473 font "Courier New,8,0" 2474 2474 ) 2475 xt "44000,25200,81500,26000" 2476 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 2477 " 2475 xt "44000,26000,81000,26800" 2476 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 2478 2477 ) 2479 2478 thePort (LogicalPort … … 2483 2482 t "std_logic_vector" 2484 2483 b "(3 DOWNTO 0)" 2485 o 3 02484 o 31 2486 2485 suid 32,0 2487 2486 i "(others => '0')" … … 2489 2488 ) 2490 2489 ) 2491 *18 5(CptPort2490 *187 (CptPort 2492 2491 uid 1308,0 2493 2492 ps "OnEdgeStrategy" … … 2531 2530 font "Courier New,8,0" 2532 2531 ) 2533 xt "44000,24400,75500,25200" 2534 st "DWRITE : OUT std_logic := '0' ; 2535 " 2532 xt "44000,25200,75000,26000" 2533 st "DWRITE : OUT std_logic := '0' ;" 2536 2534 ) 2537 2535 thePort (LogicalPort … … 2540 2538 n "DWRITE" 2541 2539 t "std_logic" 2542 o 292540 o 30 2543 2541 suid 33,0 2544 2542 i "'0'" … … 2546 2544 ) 2547 2545 ) 2548 *18 6(CptPort2546 *188 (CptPort 2549 2547 uid 1363,0 2550 2548 ps "OnEdgeStrategy" … … 2578 2576 font "Courier New,8,0" 2579 2577 ) 2580 xt "44000,22800,62000,23600" 2581 st "DAC_CS : OUT std_logic ; 2582 " 2578 xt "44000,23600,61500,24400" 2579 st "DAC_CS : OUT std_logic ;" 2583 2580 ) 2584 2581 thePort (LogicalPort … … 2587 2584 n "DAC_CS" 2588 2585 t "std_logic" 2589 o 2 72586 o 28 2590 2587 suid 34,0 2591 2588 ) 2592 2589 ) 2593 2590 ) 2594 *18 7(CptPort2591 *189 (CptPort 2595 2592 uid 1368,0 2596 2593 ps "OnEdgeStrategy" … … 2624 2621 font "Courier New,8,0" 2625 2622 ) 2626 xt "44000,38000,62000,38800" 2627 st "T0_CS : OUT std_logic ; 2628 " 2623 xt "44000,38800,61500,39600" 2624 st "T0_CS : OUT std_logic ;" 2629 2625 ) 2630 2626 thePort (LogicalPort … … 2633 2629 n "T0_CS" 2634 2630 t "std_logic" 2635 o 4 62631 o 47 2636 2632 suid 35,0 2637 2633 ) 2638 2634 ) 2639 2635 ) 2640 *1 88(CptPort2636 *190 (CptPort 2641 2637 uid 1373,0 2642 2638 ps "OnEdgeStrategy" … … 2670 2666 font "Courier New,8,0" 2671 2667 ) 2672 xt "44000,38800,62000,39600" 2673 st "T1_CS : OUT std_logic ; 2674 " 2668 xt "44000,39600,61500,40400" 2669 st "T1_CS : OUT std_logic ;" 2675 2670 ) 2676 2671 thePort (LogicalPort … … 2679 2674 n "T1_CS" 2680 2675 t "std_logic" 2681 o 4 72676 o 48 2682 2677 suid 36,0 2683 2678 ) 2684 2679 ) 2685 2680 ) 2686 *1 89(CptPort2681 *191 (CptPort 2687 2682 uid 1378,0 2688 2683 ps "OnEdgeStrategy" … … 2716 2711 font "Courier New,8,0" 2717 2712 ) 2718 xt "44000,39600,62000,40400" 2719 st "T2_CS : OUT std_logic ; 2720 " 2713 xt "44000,40400,61500,41200" 2714 st "T2_CS : OUT std_logic ;" 2721 2715 ) 2722 2716 thePort (LogicalPort … … 2725 2719 n "T2_CS" 2726 2720 t "std_logic" 2727 o 4 82721 o 49 2728 2722 suid 37,0 2729 2723 ) 2730 2724 ) 2731 2725 ) 2732 *19 0(CptPort2726 *192 (CptPort 2733 2727 uid 1383,0 2734 2728 ps "OnEdgeStrategy" … … 2762 2756 font "Courier New,8,0" 2763 2757 ) 2764 xt "44000,40400,62000,41200" 2765 st "T3_CS : OUT std_logic ; 2766 " 2758 xt "44000,41200,61500,42000" 2759 st "T3_CS : OUT std_logic ;" 2767 2760 ) 2768 2761 thePort (LogicalPort … … 2771 2764 n "T3_CS" 2772 2765 t "std_logic" 2773 o 492766 o 50 2774 2767 suid 38,0 2775 2768 ) 2776 2769 ) 2777 2770 ) 2778 *19 1(CptPort2771 *193 (CptPort 2779 2772 uid 1388,0 2780 2773 ps "OnEdgeStrategy" … … 2808 2801 font "Courier New,8,0" 2809 2802 ) 2810 xt "44000,37200,62000,38000" 2811 st "S_CLK : OUT std_logic ; 2812 " 2803 xt "44000,38000,61500,38800" 2804 st "S_CLK : OUT std_logic ;" 2813 2805 ) 2814 2806 thePort (LogicalPort … … 2817 2809 n "S_CLK" 2818 2810 t "std_logic" 2819 o 4 52811 o 46 2820 2812 suid 39,0 2821 2813 ) 2822 2814 ) 2823 2815 ) 2824 *19 2(CptPort2816 *194 (CptPort 2825 2817 uid 1393,0 2826 2818 ps "OnEdgeStrategy" … … 2854 2846 font "Courier New,8,0" 2855 2847 ) 2856 xt "44000,42000,72000,42800" 2857 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ; 2858 " 2848 xt "44000,42800,71500,43600" 2849 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ;" 2859 2850 ) 2860 2851 thePort (LogicalPort … … 2864 2855 t "std_logic_vector" 2865 2856 b "(9 DOWNTO 0)" 2866 o 5 12857 o 52 2867 2858 suid 40,0 2868 2859 ) 2869 2860 ) 2870 2861 ) 2871 *19 3(CptPort2862 *195 (CptPort 2872 2863 uid 1398,0 2873 2864 ps "OnEdgeStrategy" … … 2901 2892 font "Courier New,8,0" 2902 2893 ) 2903 xt "44000,46800,71500,47600" 2904 st "W_D : INOUT std_logic_vector (15 DOWNTO 0) 2905 " 2894 xt "44000,47600,71000,48400" 2895 st "W_D : INOUT std_logic_vector (15 DOWNTO 0)" 2906 2896 ) 2907 2897 thePort (LogicalPort … … 2911 2901 t "std_logic_vector" 2912 2902 b "(15 DOWNTO 0)" 2913 o 5 72903 o 58 2914 2904 suid 41,0 2915 2905 ) 2916 2906 ) 2917 2907 ) 2918 *19 4(CptPort2908 *196 (CptPort 2919 2909 uid 1403,0 2920 2910 ps "OnEdgeStrategy" … … 2958 2948 font "Courier New,8,0" 2959 2949 ) 2960 xt "44000,44400,75500,45200" 2961 st "W_RES : OUT std_logic := '1' ; 2962 " 2950 xt "44000,45200,75000,46000" 2951 st "W_RES : OUT std_logic := '1' ;" 2963 2952 ) 2964 2953 thePort (LogicalPort … … 2967 2956 n "W_RES" 2968 2957 t "std_logic" 2969 o 5 42958 o 55 2970 2959 suid 42,0 2971 2960 i "'1'" … … 2973 2962 ) 2974 2963 ) 2975 *19 5(CptPort2964 *197 (CptPort 2976 2965 uid 1409,0 2977 2966 ps "OnEdgeStrategy" … … 3015 3004 font "Courier New,8,0" 3016 3005 ) 3017 xt "44000,43600,75500,44400" 3018 st "W_RD : OUT std_logic := '1' ; 3019 " 3006 xt "44000,44400,75000,45200" 3007 st "W_RD : OUT std_logic := '1' ;" 3020 3008 ) 3021 3009 thePort (LogicalPort … … 3024 3012 n "W_RD" 3025 3013 t "std_logic" 3026 o 5 33014 o 54 3027 3015 suid 43,0 3028 3016 i "'1'" … … 3030 3018 ) 3031 3019 ) 3032 *19 6(CptPort3020 *198 (CptPort 3033 3021 uid 1415,0 3034 3022 ps "OnEdgeStrategy" … … 3072 3060 font "Courier New,8,0" 3073 3061 ) 3074 xt "44000,45200,75500,46000" 3075 st "W_WR : OUT std_logic := '1' ; 3076 " 3062 xt "44000,46000,75000,46800" 3063 st "W_WR : OUT std_logic := '1' ;" 3077 3064 ) 3078 3065 thePort (LogicalPort … … 3081 3068 n "W_WR" 3082 3069 t "std_logic" 3083 o 5 53070 o 56 3084 3071 suid 44,0 3085 3072 i "'1'" … … 3087 3074 ) 3088 3075 ) 3089 *19 7(CptPort3076 *199 (CptPort 3090 3077 uid 1421,0 3091 3078 ps "OnEdgeStrategy" … … 3118 3105 font "Courier New,8,0" 3119 3106 ) 3120 xt "44000,14800,62000,15600" 3121 st "W_INT : IN std_logic ; 3122 " 3107 xt "44000,15600,61500,16400" 3108 st "W_INT : IN std_logic ;" 3123 3109 ) 3124 3110 thePort (LogicalPort … … 3126 3112 n "W_INT" 3127 3113 t "std_logic" 3128 o 1 73114 o 18 3129 3115 suid 45,0 3130 3116 ) 3131 3117 ) 3132 3118 ) 3133 * 198(CptPort3119 *200 (CptPort 3134 3120 uid 1426,0 3135 3121 ps "OnEdgeStrategy" … … 3173 3159 font "Courier New,8,0" 3174 3160 ) 3175 xt "44000,42800,75500,43600" 3176 st "W_CS : OUT std_logic := '1' ; 3177 " 3161 xt "44000,43600,75000,44400" 3162 st "W_CS : OUT std_logic := '1' ;" 3178 3163 ) 3179 3164 thePort (LogicalPort … … 3182 3167 n "W_CS" 3183 3168 t "std_logic" 3184 o 5 23169 o 53 3185 3170 suid 46,0 3186 3171 i "'1'" … … 3188 3173 ) 3189 3174 ) 3190 * 199(CptPort3175 *201 (CptPort 3191 3176 uid 1620,0 3192 3177 ps "OnEdgeStrategy" … … 3230 3215 font "Courier New,8,0" 3231 3216 ) 3232 xt "44000,29200,75500,30000" 3233 st "MOSI : OUT std_logic := '0' ; 3234 " 3217 xt "44000,30000,75000,30800" 3218 st "MOSI : OUT std_logic := '0' ;" 3235 3219 ) 3236 3220 thePort (LogicalPort … … 3239 3223 n "MOSI" 3240 3224 t "std_logic" 3241 o 3 53225 o 36 3242 3226 suid 47,0 3243 3227 i "'0'" … … 3245 3229 ) 3246 3230 ) 3247 *20 0(CptPort3231 *202 (CptPort 3248 3232 uid 1626,0 3249 3233 ps "OnEdgeStrategy" … … 3277 3261 font "Courier New,8,0" 3278 3262 ) 3279 xt "44000,46000,62000,46800" 3280 st "MISO : INOUT std_logic ; 3281 " 3263 xt "44000,46800,61500,47600" 3264 st "MISO : INOUT std_logic ;" 3282 3265 ) 3283 3266 thePort (LogicalPort … … 3288 3271 preAdd 0 3289 3272 posAdd 0 3290 o 5 63273 o 57 3291 3274 suid 48,0 3292 3275 ) 3293 3276 ) 3294 3277 ) 3295 *20 1(CptPort3278 *203 (CptPort 3296 3279 uid 1676,0 3297 3280 ps "OnEdgeStrategy" … … 3325 3308 font "Courier New,8,0" 3326 3309 ) 3327 xt "44000,41200,62000,42000" 3328 st "TRG_V : OUT std_logic ; 3329 " 3310 xt "44000,42000,61500,42800" 3311 st "TRG_V : OUT std_logic ;" 3330 3312 ) 3331 3313 thePort (LogicalPort … … 3334 3316 n "TRG_V" 3335 3317 t "std_logic" 3336 o 5 03318 o 51 3337 3319 suid 49,0 3338 3320 ) 3339 3321 ) 3340 3322 ) 3341 *20 2(CptPort3323 *204 (CptPort 3342 3324 uid 1681,0 3343 3325 ps "OnEdgeStrategy" … … 3371 3353 font "Courier New,8,0" 3372 3354 ) 3373 xt "44000,33200,62000,34000" 3374 st "RS485_C_RE : OUT std_logic ; 3375 " 3355 xt "44000,34000,61500,34800" 3356 st "RS485_C_RE : OUT std_logic ;" 3376 3357 ) 3377 3358 thePort (LogicalPort … … 3380 3361 n "RS485_C_RE" 3381 3362 t "std_logic" 3382 o 4 03363 o 41 3383 3364 suid 50,0 3384 3365 ) 3385 3366 ) 3386 3367 ) 3387 *20 3(CptPort3368 *205 (CptPort 3388 3369 uid 1686,0 3389 3370 ps "OnEdgeStrategy" … … 3417 3398 font "Courier New,8,0" 3418 3399 ) 3419 xt "44000,31600,62000,32400" 3420 st "RS485_C_DE : OUT std_logic ; 3421 " 3400 xt "44000,32400,61500,33200" 3401 st "RS485_C_DE : OUT std_logic ;" 3422 3402 ) 3423 3403 thePort (LogicalPort … … 3426 3406 n "RS485_C_DE" 3427 3407 t "std_logic" 3428 o 3 83408 o 39 3429 3409 suid 51,0 3430 3410 ) 3431 3411 ) 3432 3412 ) 3433 *20 4(CptPort3413 *206 (CptPort 3434 3414 uid 1691,0 3435 3415 ps "OnEdgeStrategy" … … 3463 3443 font "Courier New,8,0" 3464 3444 ) 3465 xt "44000,34800,62000,35600" 3466 st "RS485_E_RE : OUT std_logic ; 3467 " 3445 xt "44000,35600,61500,36400" 3446 st "RS485_E_RE : OUT std_logic ;" 3468 3447 ) 3469 3448 thePort (LogicalPort … … 3472 3451 n "RS485_E_RE" 3473 3452 t "std_logic" 3474 o 4 23453 o 43 3475 3454 suid 52,0 3476 3455 ) 3477 3456 ) 3478 3457 ) 3479 *20 5(CptPort3458 *207 (CptPort 3480 3459 uid 1696,0 3481 3460 ps "OnEdgeStrategy" … … 3509 3488 font "Courier New,8,0" 3510 3489 ) 3511 xt "44000,34000,62000,34800" 3512 st "RS485_E_DE : OUT std_logic ; 3513 " 3490 xt "44000,34800,61500,35600" 3491 st "RS485_E_DE : OUT std_logic ;" 3514 3492 ) 3515 3493 thePort (LogicalPort … … 3518 3496 n "RS485_E_DE" 3519 3497 t "std_logic" 3520 o 4 13498 o 42 3521 3499 suid 53,0 3522 3500 ) 3523 3501 ) 3524 3502 ) 3525 *20 6(CptPort3503 *208 (CptPort 3526 3504 uid 1701,0 3527 3505 ps "OnEdgeStrategy" … … 3565 3543 font "Courier New,8,0" 3566 3544 ) 3567 xt "44000,23600,75500,24400" 3568 st "DENABLE : OUT std_logic := '0' ; 3569 " 3545 xt "44000,24400,75000,25200" 3546 st "DENABLE : OUT std_logic := '0' ;" 3570 3547 ) 3571 3548 thePort (LogicalPort … … 3574 3551 n "DENABLE" 3575 3552 t "std_logic" 3576 o 2 83553 o 29 3577 3554 suid 54,0 3578 3555 i "'0'" … … 3580 3557 ) 3581 3558 ) 3582 *20 7(CptPort3559 *209 (CptPort 3583 3560 uid 1706,0 3584 3561 ps "OnEdgeStrategy" … … 3622 3599 font "Courier New,8,0" 3623 3600 ) 3624 xt "44000,36400,75500,37200" 3625 st "SRIN : OUT std_logic := '0' ; 3626 " 3601 xt "44000,37200,75000,38000" 3602 st "SRIN : OUT std_logic := '0' ;" 3627 3603 ) 3628 3604 thePort (LogicalPort … … 3631 3607 n "SRIN" 3632 3608 t "std_logic" 3633 o 4 43609 o 45 3634 3610 suid 55,0 3635 3611 i "'0'" … … 3637 3613 ) 3638 3614 ) 3639 *2 08(CptPort3615 *210 (CptPort 3640 3616 uid 1711,0 3641 3617 ps "OnEdgeStrategy" … … 3669 3645 font "Courier New,8,0" 3670 3646 ) 3671 xt "44000,27600,62000,28400" 3672 st "EE_CS : OUT std_logic ; 3673 " 3647 xt "44000,28400,61500,29200" 3648 st "EE_CS : OUT std_logic ;" 3674 3649 ) 3675 3650 thePort (LogicalPort … … 3678 3653 n "EE_CS" 3679 3654 t "std_logic" 3680 o 3 33655 o 34 3681 3656 suid 56,0 3682 3657 ) 3683 3658 ) 3684 3659 ) 3685 *2 09(CptPort3660 *211 (CptPort 3686 3661 uid 2068,0 3687 3662 ps "OnEdgeStrategy" … … 3704 3679 ) 3705 3680 xt "28500,91500,33000,92500" 3706 st "D_T : ( 7:0)"3681 st "D_T : (5:0)" 3707 3682 ju 2 3708 3683 blo "33000,92300" … … 3725 3700 font "Courier New,8,0" 3726 3701 ) 3727 xt "44000,26000,81500,26800" 3728 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3729 " 3702 xt "44000,26800,81000,27600" 3703 st "D_T : OUT std_logic_vector (5 DOWNTO 0) := (OTHERS => '0') ;" 3730 3704 ) 3731 3705 thePort (LogicalPort … … 3734 3708 n "D_T" 3735 3709 t "std_logic_vector" 3736 b "( 7DOWNTO 0)"3737 o 3 13710 b "(5 DOWNTO 0)" 3711 o 32 3738 3712 suid 61,0 3739 3713 i "(OTHERS => '0')" … … 3741 3715 ) 3742 3716 ) 3743 *21 0(CptPort3717 *212 (CptPort 3744 3718 uid 2919,0 3745 3719 ps "OnEdgeStrategy" … … 3772 3746 font "Courier New,8,0" 3773 3747 ) 3774 xt "44000,9200,72000,10000" 3775 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ; 3776 " 3748 xt "44000,9200,71500,10000" 3749 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ;" 3777 3750 ) 3778 3751 thePort (LogicalPort … … 3786 3759 ) 3787 3760 ) 3788 *21 1(CptPort3761 *213 (CptPort 3789 3762 uid 2949,0 3790 3763 ps "OnEdgeStrategy" … … 3828 3801 font "Courier New,8,0" 3829 3802 ) 3830 xt "44000,26800,81500,27600" 3831 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 3832 " 3803 xt "44000,27600,81000,28400" 3804 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 3833 3805 ) 3834 3806 thePort (LogicalPort … … 3838 3810 t "std_logic_vector" 3839 3811 b "(3 DOWNTO 0)" 3840 o 3 23812 o 33 3841 3813 suid 65,0 3842 3814 i "(others => '0')" … … 3844 3816 ) 3845 3817 ) 3846 *21 2(CptPort3818 *214 (CptPort 3847 3819 uid 3026,0 3848 3820 ps "OnEdgeStrategy" … … 3886 3858 font "Courier New,8,0" 3887 3859 ) 3888 xt "44000,17200,81500,18000" 3889 st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3890 " 3860 xt "44000,18000,81000,18800" 3861 st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" 3891 3862 ) 3892 3863 thePort (LogicalPort … … 3896 3867 t "std_logic_vector" 3897 3868 b "(7 DOWNTO 0)" 3898 o 2 03869 o 21 3899 3870 suid 66,0 3900 3871 i "(OTHERS => '0')" … … 3902 3873 ) 3903 3874 ) 3904 *21 3(CptPort3875 *215 (CptPort 3905 3876 uid 3456,0 3906 3877 ps "OnEdgeStrategy" … … 3944 3915 font "Courier New,8,0" 3945 3916 ) 3946 xt "44000,16400,81500,17200" 3947 st "A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0') ; 3948 " 3917 xt "44000,17200,81000,18000" 3918 st "A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0') ;" 3949 3919 ) 3950 3920 thePort (LogicalPort … … 3954 3924 t "std_logic_vector" 3955 3925 b "(7 DOWNTO 0)" 3956 o 193926 o 20 3957 3927 suid 68,0 3958 3928 i "(others => '0')" … … 3960 3930 ) 3961 3931 ) 3962 *21 4(CptPort3932 *216 (CptPort 3963 3933 uid 3581,0 3964 3934 ps "OnEdgeStrategy" … … 3991 3961 font "Courier New,8,0" 3992 3962 ) 3993 xt "44000,11600,62000,12400" 3994 st "RS485_C_DI : IN std_logic ; 3995 " 3963 xt "44000,12400,61500,13200" 3964 st "RS485_C_DI : IN std_logic ;" 3996 3965 ) 3997 3966 thePort (LogicalPort … … 3999 3968 n "RS485_C_DI" 4000 3969 t "std_logic" 4001 o 1 33970 o 14 4002 3971 suid 69,0 4003 3972 ) 4004 3973 ) 4005 3974 ) 4006 *21 5(CptPort3975 *217 (CptPort 4007 3976 uid 3586,0 4008 3977 ps "OnEdgeStrategy" … … 4036 4005 font "Courier New,8,0" 4037 4006 ) 4038 xt "44000,32400,62000,33200" 4039 st "RS485_C_DO : OUT std_logic ; 4040 " 4007 xt "44000,33200,61500,34000" 4008 st "RS485_C_DO : OUT std_logic ;" 4041 4009 ) 4042 4010 thePort (LogicalPort … … 4045 4013 n "RS485_C_DO" 4046 4014 t "std_logic" 4047 o 394015 o 40 4048 4016 suid 70,0 4049 4017 ) 4050 4018 ) 4051 4019 ) 4052 *21 6(CptPort4020 *218 (CptPort 4053 4021 uid 3687,0 4054 4022 ps "OnEdgeStrategy" … … 4081 4049 font "Courier New,8,0" 4082 4050 ) 4083 xt "44000,12400,62000,13200" 4084 st "RS485_E_DI : IN std_logic ; 4085 " 4051 xt "44000,13200,61500,14000" 4052 st "RS485_E_DI : IN std_logic ;" 4086 4053 ) 4087 4054 thePort (LogicalPort … … 4089 4056 n "RS485_E_DI" 4090 4057 t "std_logic" 4091 o 1 44058 o 15 4092 4059 suid 71,0 4093 4060 ) 4094 4061 ) 4095 4062 ) 4096 *21 7(CptPort4063 *219 (CptPort 4097 4064 uid 3692,0 4098 4065 ps "OnEdgeStrategy" … … 4125 4092 font "Courier New,8,0" 4126 4093 ) 4127 xt "44000,13200,62000,14000" 4128 st "RS485_E_DO : IN std_logic ; 4129 " 4094 xt "44000,14000,61500,14800" 4095 st "RS485_E_DO : IN std_logic ;" 4130 4096 ) 4131 4097 thePort (LogicalPort … … 4133 4099 n "RS485_E_DO" 4134 4100 t "std_logic" 4135 o 1 54101 o 16 4136 4102 suid 72,0 4137 4103 ) 4138 4104 ) 4139 4105 ) 4140 *2 18(CptPort4106 *220 (CptPort 4141 4107 uid 4033,0 4142 4108 ps "OnEdgeStrategy" … … 4170 4136 font "Courier New,8,0" 4171 4137 ) 4172 xt "44000,18000,62000,18800" 4173 st "AMBER_LED : OUT std_logic ; 4174 " 4138 xt "44000,18800,61500,19600" 4139 st "AMBER_LED : OUT std_logic ;" 4175 4140 ) 4176 4141 thePort (LogicalPort … … 4179 4144 n "AMBER_LED" 4180 4145 t "std_logic" 4181 o 2 14146 o 22 4182 4147 suid 77,0 4183 4148 ) 4184 4149 ) 4185 4150 ) 4186 *2 19(CptPort4151 *221 (CptPort 4187 4152 uid 4038,0 4188 4153 ps "OnEdgeStrategy" … … 4216 4181 font "Courier New,8,0" 4217 4182 ) 4218 xt "44000,28400,62000,29200" 4219 st "GREEN_LED : OUT std_logic ; 4220 " 4183 xt "44000,29200,61500,30000" 4184 st "GREEN_LED : OUT std_logic ;" 4221 4185 ) 4222 4186 thePort (LogicalPort … … 4225 4189 n "GREEN_LED" 4226 4190 t "std_logic" 4227 o 3 44191 o 35 4228 4192 suid 78,0 4229 4193 ) 4230 4194 ) 4231 4195 ) 4232 *22 0(CptPort4196 *222 (CptPort 4233 4197 uid 4043,0 4234 4198 ps "OnEdgeStrategy" … … 4262 4226 font "Courier New,8,0" 4263 4227 ) 4264 xt "44000,30800,62000,31600" 4265 st "RED_LED : OUT std_logic ; 4266 " 4228 xt "44000,31600,61500,32400" 4229 st "RED_LED : OUT std_logic ;" 4267 4230 ) 4268 4231 thePort (LogicalPort … … 4271 4234 n "RED_LED" 4272 4235 t "std_logic" 4273 o 3 74236 o 38 4274 4237 suid 79,0 4275 4238 ) 4276 4239 ) 4277 4240 ) 4278 *221 (CptPort 4279 uid 4165,0 4280 ps "OnEdgeStrategy" 4281 shape (Triangle 4282 uid 4166,0 4283 ro 90 4284 va (VaSet 4285 vasetType 1 4286 fg "0,65535,0" 4287 ) 4288 xt "14250,53625,15000,54375" 4289 ) 4290 tg (CPTG 4291 uid 4167,0 4292 ps "CptPortTextPlaceStrategy" 4293 stg "VerticalLayoutStrategy" 4294 f (Text 4295 uid 4168,0 4296 va (VaSet 4297 ) 4298 xt "16000,53500,23900,54500" 4299 st "POSITION_ID : (5:0)" 4300 blo "16000,54300" 4301 tm "CptPortNameMgr" 4302 ) 4303 ) 4304 dt (MLText 4305 uid 4169,0 4306 va (VaSet 4307 font "Courier New,8,0" 4308 ) 4309 xt "44000,10000,73000,10800" 4310 st "POSITION_ID : IN std_logic_vector ( 5 DOWNTO 0 ) ; 4311 " 4312 ) 4313 thePort (LogicalPort 4314 decl (Decl 4315 n "POSITION_ID" 4316 t "std_logic_vector" 4317 b "( 5 DOWNTO 0 )" 4318 o 11 4319 suid 80,0 4320 ) 4321 ) 4322 ) 4323 *222 (CptPort 4241 *223 (CptPort 4324 4242 uid 4264,0 4325 4243 ps "OnEdgeStrategy" … … 4352 4270 font "Courier New,8,0" 4353 4271 ) 4354 xt "44000,10800,62000,11600" 4355 st "REFCLK : IN std_logic ; 4356 " 4272 xt "44000,11600,61500,12400" 4273 st "REFCLK : IN std_logic ;" 4357 4274 ) 4358 4275 thePort (LogicalPort … … 4360 4277 n "REFCLK" 4361 4278 t "std_logic" 4279 o 13 4280 suid 81,0 4281 ) 4282 ) 4283 ) 4284 *224 (CptPort 4285 uid 4294,0 4286 ps "OnEdgeStrategy" 4287 shape (Triangle 4288 uid 4295,0 4289 ro 90 4290 va (VaSet 4291 vasetType 1 4292 fg "0,65535,0" 4293 ) 4294 xt "14250,57625,15000,58375" 4295 ) 4296 tg (CPTG 4297 uid 4296,0 4298 ps "CptPortTextPlaceStrategy" 4299 stg "VerticalLayoutStrategy" 4300 f (Text 4301 uid 4297,0 4302 va (VaSet 4303 ) 4304 xt "16000,57500,20700,58500" 4305 st "LINE : (5:0)" 4306 blo "16000,58300" 4307 tm "CptPortNameMgr" 4308 ) 4309 ) 4310 dt (MLText 4311 uid 4298,0 4312 va (VaSet 4313 font "Courier New,8,0" 4314 ) 4315 xt "44000,10800,72500,11600" 4316 st "LINE : IN std_logic_vector ( 5 DOWNTO 0 ) ;" 4317 ) 4318 thePort (LogicalPort 4319 decl (Decl 4320 n "LINE" 4321 t "std_logic_vector" 4322 b "( 5 DOWNTO 0 )" 4362 4323 o 12 4363 suid 81,0 4324 suid 82,0 4325 ) 4326 ) 4327 ) 4328 *225 (CptPort 4329 uid 4324,0 4330 ps "OnEdgeStrategy" 4331 shape (Triangle 4332 uid 4325,0 4333 ro 90 4334 va (VaSet 4335 vasetType 1 4336 fg "0,65535,0" 4337 ) 4338 xt "14250,59625,15000,60375" 4339 ) 4340 tg (CPTG 4341 uid 4326,0 4342 ps "CptPortTextPlaceStrategy" 4343 stg "VerticalLayoutStrategy" 4344 f (Text 4345 uid 4327,0 4346 va (VaSet 4347 ) 4348 xt "16000,59500,21500,60500" 4349 st "D_T_in : (1:0)" 4350 blo "16000,60300" 4351 tm "CptPortNameMgr" 4352 ) 4353 ) 4354 dt (MLText 4355 uid 4328,0 4356 va (VaSet 4357 font "Courier New,8,0" 4358 ) 4359 xt "44000,10000,71500,10800" 4360 st "D_T_in : IN std_logic_vector (1 DOWNTO 0) ;" 4361 ) 4362 thePort (LogicalPort 4363 decl (Decl 4364 n "D_T_in" 4365 t "std_logic_vector" 4366 b "(1 DOWNTO 0)" 4367 o 11 4368 suid 83,0 4364 4369 ) 4365 4370 ) … … 4400 4405 ) 4401 4406 ) 4402 gi *22 3(GenericInterface4407 gi *226 (GenericInterface 4403 4408 uid 13,0 4404 4409 ps "CenterOffsetStrategy" … … 4427 4432 ) 4428 4433 ) 4429 *22 4(Grouping4434 *227 (Grouping 4430 4435 uid 16,0 4431 4436 optionalChildren [ 4432 *22 5(CommentText4437 *228 (CommentText 4433 4438 uid 18,0 4434 4439 shape (Rectangle … … 4448 4453 bg "0,0,32768" 4449 4454 ) 4450 xt "36200,48000,45 800,49000"4455 xt "36200,48000,45700,49000" 4451 4456 st " 4452 4457 by %user on %dd %month %year … … 4461 4466 titleBlock 1 4462 4467 ) 4463 *22 6(CommentText4468 *229 (CommentText 4464 4469 uid 21,0 4465 4470 shape (Rectangle … … 4492 4497 titleBlock 1 4493 4498 ) 4494 *2 27(CommentText4499 *230 (CommentText 4495 4500 uid 24,0 4496 4501 shape (Rectangle … … 4523 4528 titleBlock 1 4524 4529 ) 4525 *2 28(CommentText4530 *231 (CommentText 4526 4531 uid 27,0 4527 4532 shape (Rectangle … … 4554 4559 titleBlock 1 4555 4560 ) 4556 *2 29(CommentText4561 *232 (CommentText 4557 4562 uid 30,0 4558 4563 shape (Rectangle … … 4584 4589 titleBlock 1 4585 4590 ) 4586 *23 0(CommentText4591 *233 (CommentText 4587 4592 uid 33,0 4588 4593 shape (Rectangle … … 4615 4620 titleBlock 1 4616 4621 ) 4617 *23 1(CommentText4622 *234 (CommentText 4618 4623 uid 36,0 4619 4624 shape (Rectangle … … 4647 4652 titleBlock 1 4648 4653 ) 4649 *23 2(CommentText4654 *235 (CommentText 4650 4655 uid 39,0 4651 4656 shape (Rectangle … … 4678 4683 titleBlock 1 4679 4684 ) 4680 *23 3(CommentText4685 *236 (CommentText 4681 4686 uid 42,0 4682 4687 shape (Rectangle … … 4709 4714 titleBlock 1 4710 4715 ) 4711 *23 4(CommentText4716 *237 (CommentText 4712 4717 uid 45,0 4713 4718 shape (Rectangle … … 4765 4770 color "26368,26368,26368" 4766 4771 ) 4767 packageList *23 5(PackageList4772 packageList *238 (PackageList 4768 4773 uid 48,0 4769 4774 stg "VerticalLayoutStrategy" 4770 4775 textVec [ 4771 *23 6(Text4776 *239 (Text 4772 4777 uid 49,0 4773 4778 va (VaSet … … 4778 4783 blo "0,800" 4779 4784 ) 4780 *2 37(MLText4785 *240 (MLText 4781 4786 uid 50,0 4782 4787 va (VaSet … … 4876 4881 ) 4877 4882 ) 4878 gi *2 38(GenericInterface4883 gi *241 (GenericInterface 4879 4884 ps "CenterOffsetStrategy" 4880 4885 matrix (Matrix … … 4973 4978 ) 4974 4979 ) 4975 DeclarativeBlock *2 39(SymDeclBlock4980 DeclarativeBlock *242 (SymDeclBlock 4976 4981 uid 1,0 4977 4982 stg "SymDeclLayoutStrategy" … … 4999 5004 font "Arial,8,1" 5000 5005 ) 5001 xt "42000,4 7600,44400,48600"5006 xt "42000,48400,44400,49400" 5002 5007 st "User:" 5003 blo "42000,4 8400"5008 blo "42000,49200" 5004 5009 ) 5005 5010 internalLabel (Text … … 5018 5023 font "Courier New,8,0" 5019 5024 ) 5020 xt "44000,4 8600,44000,48600"5025 xt "44000,49400,44000,49400" 5021 5026 tm "SyDeclarativeTextMgr" 5022 5027 ) … … 5031 5036 ) 5032 5037 ) 5033 lastUid 4 268,05038 lastUid 4627,0 5034 5039 activeModelName "Symbol:CDM" 5035 5040 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r10121 r10123 302 302 (vvPair 303 303 variable "HDLDir" 304 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"304 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 305 305 ) 306 306 (vvPair 307 307 variable "HDSDir" 308 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"308 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 309 309 ) 310 310 (vvPair 311 311 variable "SideDataDesignDir" 312 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"312 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" 313 313 ) 314 314 (vvPair 315 315 variable "SideDataUserDir" 316 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"316 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" 317 317 ) 318 318 (vvPair 319 319 variable "SourceDir" 320 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"320 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 321 321 ) 322 322 (vvPair … … 334 334 (vvPair 335 335 variable "d" 336 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main"336 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main" 337 337 ) 338 338 (vvPair 339 339 variable "d_logical" 340 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main"340 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main" 341 341 ) 342 342 (vvPair 343 343 variable "date" 344 value "2 6.01.2011"344 value "27.01.2011" 345 345 ) 346 346 (vvPair 347 347 variable "day" 348 value " Mi"348 value "Do" 349 349 ) 350 350 (vvPair 351 351 variable "day_long" 352 value " Mittwoch"352 value "Donnerstag" 353 353 ) 354 354 (vvPair 355 355 variable "dd" 356 value "2 6"356 value "27" 357 357 ) 358 358 (vvPair … … 434 434 (vvPair 435 435 variable "p" 436 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"436 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" 437 437 ) 438 438 (vvPair 439 439 variable "p_logical" 440 value "C:\\ FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"440 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" 441 441 ) 442 442 (vvPair … … 494 494 (vvPair 495 495 variable "time" 496 value "1 6:46:14"496 value "15:46:22" 497 497 ) 498 498 (vvPair … … 585 585 font "Courier New,8,0" 586 586 ) 587 xt "-102000,126400,-58500,127200" 588 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 587 xt "-102000,127200,-58500,128000" 588 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 589 " 589 590 ) 590 591 ) … … 603 604 font "Courier New,8,0" 604 605 ) 605 xt "-102000,62400,-62000,63200" 606 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 606 xt "-102000,63200,-62000,64000" 607 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 608 " 607 609 ) 608 610 ) … … 621 623 font "Courier New,8,0" 622 624 ) 623 xt "-102000,81600,-69500,82400" 624 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 625 xt "-102000,82400,-69500,83200" 626 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 627 " 625 628 ) 626 629 ) … … 639 642 font "Courier New,8,0" 640 643 ) 641 xt "-102000,100000,-62000,100800" 642 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 644 xt "-102000,100800,-62000,101600" 645 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 646 " 643 647 ) 644 648 ) … … 657 661 font "Courier New,8,0" 658 662 ) 659 xt "-102000,100800,-69500,101600" 660 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 663 xt "-102000,101600,-69500,102400" 664 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 665 " 661 666 ) 662 667 ) … … 675 680 font "Courier New,8,0" 676 681 ) 677 xt "-102000,54000,-62000,54800" 678 st "wiz_reset : std_logic := '1'" 682 xt "-102000,54800,-62000,55600" 683 st "wiz_reset : std_logic := '1' 684 " 679 685 ) 680 686 ) … … 693 699 font "Courier New,8,0" 694 700 ) 695 xt "-102000,51600,-73500,52400" 696 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 701 xt "-102000,52400,-73500,53200" 702 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 703 " 697 704 ) 698 705 ) … … 711 718 font "Courier New,8,0" 712 719 ) 713 xt "-102000,56400,-73000,57200" 714 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 720 xt "-102000,57200,-73000,58000" 721 st "wiz_data : std_logic_vector(15 DOWNTO 0) 722 " 715 723 ) 716 724 ) … … 729 737 font "Courier New,8,0" 730 738 ) 731 xt "-102000,52400,-62000,53200" 732 st "wiz_cs : std_logic := '1'" 739 xt "-102000,53200,-62000,54000" 740 st "wiz_cs : std_logic := '1' 741 " 733 742 ) 734 743 ) … … 747 756 font "Courier New,8,0" 748 757 ) 749 xt "-102000,54800,-62000,55600" 750 st "wiz_wr : std_logic := '1'" 758 xt "-102000,55600,-62000,56400" 759 st "wiz_wr : std_logic := '1' 760 " 751 761 ) 752 762 ) … … 765 775 font "Courier New,8,0" 766 776 ) 767 xt "-102000,53200,-62000,54000" 768 st "wiz_rd : std_logic := '1'" 777 xt "-102000,54000,-62000,54800" 778 st "wiz_rd : std_logic := '1' 779 " 769 780 ) 770 781 ) … … 782 793 font "Courier New,8,0" 783 794 ) 784 xt "-102000,25200,-83500,26000" 785 st "wiz_int : std_logic" 795 xt "-102000,26000,-83500,26800" 796 st "wiz_int : std_logic 797 " 786 798 ) 787 799 ) … … 799 811 sl 0 800 812 ro 270 801 xt "1 54500,51625,156000,52375"813 xt "168500,50625,170000,51375" 802 814 ) 803 815 (Line … … 805 817 sl 0 806 818 ro 270 807 xt "1 54000,52000,154500,52000"808 pts [ 809 "1 54000,52000"810 "1 54500,52000"819 xt "168000,51000,168500,51000" 820 pts [ 821 "168000,51000" 822 "168500,51000" 811 823 ] 812 824 ) … … 822 834 va (VaSet 823 835 ) 824 xt "1 57000,51500,160600,52500"836 xt "171000,50500,174600,51500" 825 837 st "wiz_reset" 826 blo "1 57000,52300"838 blo "171000,51300" 827 839 tm "WireNameMgr" 828 840 ) … … 842 854 sl 0 843 855 ro 270 844 xt "1 54500,59625,156000,60375"856 xt "168500,58625,170000,59375" 845 857 ) 846 858 (Line … … 848 860 sl 0 849 861 ro 270 850 xt "1 54000,60000,154500,60000"851 pts [ 852 "1 54000,60000"853 "1 54500,60000"862 xt "168000,59000,168500,59000" 863 pts [ 864 "168000,59000" 865 "168500,59000" 854 866 ] 855 867 ) … … 865 877 va (VaSet 866 878 ) 867 xt "1 57000,59500,163000,60500"879 xt "171000,58500,177000,59500" 868 880 st "wiz_addr : (9:0)" 869 blo "1 57000,60300"881 blo "171000,59300" 870 882 tm "WireNameMgr" 871 883 ) … … 884 896 uid 468,0 885 897 sl 0 886 xt "1 54500,60625,156000,61375"898 xt "168500,59625,170000,60375" 887 899 ) 888 900 (Line 889 901 uid 469,0 890 902 sl 0 891 xt "1 54000,61000,154500,61000"892 pts [ 893 "1 54000,61000"894 "1 54500,61000"903 xt "168000,60000,168500,60000" 904 pts [ 905 "168000,60000" 906 "168500,60000" 895 907 ] 896 908 ) … … 906 918 va (VaSet 907 919 ) 908 xt "1 57000,60500,163300,61500"920 xt "171000,59500,177300,60500" 909 921 st "wiz_data : (15:0)" 910 blo "1 57000,61300"922 blo "171000,60300" 911 923 tm "WireNameMgr" 912 924 ) … … 926 938 sl 0 927 939 ro 270 928 xt "1 54500,52625,156000,53375"940 xt "168500,51625,170000,52375" 929 941 ) 930 942 (Line … … 932 944 sl 0 933 945 ro 270 934 xt "1 54000,53000,154500,53000"935 pts [ 936 "1 54000,53000"937 "1 54500,53000"946 xt "168000,52000,168500,52000" 947 pts [ 948 "168000,52000" 949 "168500,52000" 938 950 ] 939 951 ) … … 950 962 va (VaSet 951 963 ) 952 xt "1 57000,52500,159700,53500"964 xt "171000,51500,173700,52500" 953 965 st "wiz_cs" 954 blo "1 57000,53300"966 blo "171000,52300" 955 967 tm "WireNameMgr" 956 968 ) … … 970 982 sl 0 971 983 ro 270 972 xt "1 54500,53625,156000,54375"984 xt "168500,52625,170000,53375" 973 985 ) 974 986 (Line … … 976 988 sl 0 977 989 ro 270 978 xt "1 54000,54000,154500,54000"979 pts [ 980 "1 54000,54000"981 "1 54500,54000"990 xt "168000,53000,168500,53000" 991 pts [ 992 "168000,53000" 993 "168500,53000" 982 994 ] 983 995 ) … … 994 1006 va (VaSet 995 1007 ) 996 xt "1 57000,53500,159700,54500"1008 xt "171000,52500,173700,53500" 997 1009 st "wiz_wr" 998 blo "1 57000,54300"1010 blo "171000,53300" 999 1011 tm "WireNameMgr" 1000 1012 ) … … 1014 1026 sl 0 1015 1027 ro 270 1016 xt "1 54500,70625,156000,71375"1028 xt "170500,69625,172000,70375" 1017 1029 ) 1018 1030 (Line … … 1020 1032 sl 0 1021 1033 ro 270 1022 xt "1 54000,71000,154500,71000"1023 pts [ 1024 "1 54000,71000"1025 "1 54500,71000"1034 xt "170000,70000,170500,70000" 1035 pts [ 1036 "170000,70000" 1037 "170500,70000" 1026 1038 ] 1027 1039 ) … … 1037 1049 va (VaSet 1038 1050 ) 1039 xt "1 57000,70500,161000,71500"1051 xt "173000,69500,177000,70500" 1040 1052 st "led : (7:0)" 1041 blo "1 57000,71300"1053 blo "173000,70300" 1042 1054 tm "WireNameMgr" 1043 1055 ) … … 1057 1069 sl 0 1058 1070 ro 270 1059 xt "1 54500,54625,156000,55375"1071 xt "168500,53625,170000,54375" 1060 1072 ) 1061 1073 (Line … … 1063 1075 sl 0 1064 1076 ro 270 1065 xt "1 54000,55000,154500,55000"1066 pts [ 1067 "1 54000,55000"1068 "1 54500,55000"1077 xt "168000,54000,168500,54000" 1078 pts [ 1079 "168000,54000" 1080 "168500,54000" 1069 1081 ] 1070 1082 ) … … 1081 1093 va (VaSet 1082 1094 ) 1083 xt "1 57000,54500,159600,55500"1095 xt "171000,53500,173600,54500" 1084 1096 st "wiz_rd" 1085 blo "1 57000,55300"1097 blo "171000,54300" 1086 1098 tm "WireNameMgr" 1087 1099 ) … … 1101 1113 sl 0 1102 1114 ro 90 1103 xt "1 54500,55625,156000,56375"1115 xt "168500,54625,170000,55375" 1104 1116 ) 1105 1117 (Line … … 1107 1119 sl 0 1108 1120 ro 90 1109 xt "1 54000,56000,154500,56000"1110 pts [ 1111 "1 54500,56000"1112 "1 54000,56000"1121 xt "168000,55000,168500,55000" 1122 pts [ 1123 "168500,55000" 1124 "168000,55000" 1113 1125 ] 1114 1126 ) … … 1125 1137 va (VaSet 1126 1138 ) 1127 xt "1 57000,55500,159700,56500"1139 xt "171000,54500,173700,55500" 1128 1140 st "wiz_int" 1129 blo "1 57000,56300"1141 blo "171000,55300" 1130 1142 tm "WireNameMgr" 1131 1143 ) … … 2869 2881 n "board_id" 2870 2882 t "std_logic_vector" 2871 b "(3 downto 0)" 2872 preAdd 0 2873 posAdd 0 2883 b "(3 DOWNTO 0)" 2874 2884 o 8 2875 2885 suid 28,0 … … 2880 2890 font "Courier New,8,0" 2881 2891 ) 2882 xt "-102000,22800,-73500,23600" 2883 st "board_id : std_logic_vector(3 downto 0)" 2892 xt "-102000,23600,-73500,24400" 2893 st "board_id : std_logic_vector(3 DOWNTO 0) 2894 " 2884 2895 ) 2885 2896 ) … … 2899 2910 font "Courier New,8,0" 2900 2911 ) 2901 xt "-102000,24400,-83500,25200" 2902 st "trigger : std_logic" 2912 xt "-102000,25200,-83500,26000" 2913 st "trigger : std_logic 2914 " 2903 2915 ) 2904 2916 ) … … 2961 2973 fg "0,65535,0" 2962 2974 ) 2963 xt "127250,5 1625,128000,52375"2975 xt "127250,50625,128000,51375" 2964 2976 ) 2965 2977 tg (CPTG … … 2971 2983 va (VaSet 2972 2984 ) 2973 xt "129000,5 1500,130300,52500"2985 xt "129000,50500,130300,51500" 2974 2986 st "clk" 2975 blo "129000,5 2300"2987 blo "129000,51300" 2976 2988 ) 2977 2989 ) … … 2997 3009 fg "0,65535,0" 2998 3010 ) 2999 xt "164000,5 1625,164750,52375"3011 xt "164000,50625,164750,51375" 3000 3012 ) 3001 3013 tg (CPTG … … 3007 3019 va (VaSet 3008 3020 ) 3009 xt "159400,5 1500,163000,52500"3021 xt "159400,50500,163000,51500" 3010 3022 st "wiz_reset" 3011 3023 ju 2 3012 blo "163000,5 2300"3024 blo "163000,51300" 3013 3025 ) 3014 3026 ) … … 3036 3048 fg "0,65535,0" 3037 3049 ) 3038 xt "164000,5 9625,164750,60375"3050 xt "164000,58625,164750,59375" 3039 3051 ) 3040 3052 tg (CPTG … … 3046 3058 va (VaSet 3047 3059 ) 3048 xt "158500,5 9500,163000,60500"3060 xt "158500,58500,163000,59500" 3049 3061 st "addr : (9:0)" 3050 3062 ju 2 3051 blo "163000, 60300"3063 blo "163000,59300" 3052 3064 ) 3053 3065 ) … … 3075 3087 fg "0,65535,0" 3076 3088 ) 3077 xt "164000, 60625,164750,61375"3089 xt "164000,59625,164750,60375" 3078 3090 ) 3079 3091 tg (CPTG … … 3085 3097 va (VaSet 3086 3098 ) 3087 xt "158200, 60500,163000,61500"3099 xt "158200,59500,163000,60500" 3088 3100 st "data : (15:0)" 3089 3101 ju 2 3090 blo "163000,6 1300"3102 blo "163000,60300" 3091 3103 ) 3092 3104 ) … … 3114 3126 fg "0,65535,0" 3115 3127 ) 3116 xt "164000,5 2625,164750,53375"3128 xt "164000,51625,164750,52375" 3117 3129 ) 3118 3130 tg (CPTG … … 3124 3136 va (VaSet 3125 3137 ) 3126 xt "161800,5 2500,163000,53500"3138 xt "161800,51500,163000,52500" 3127 3139 st "cs" 3128 3140 ju 2 3129 blo "163000,5 3300"3141 blo "163000,52300" 3130 3142 ) 3131 3143 ) … … 3153 3165 fg "0,65535,0" 3154 3166 ) 3155 xt "164000,5 3625,164750,54375"3167 xt "164000,52625,164750,53375" 3156 3168 ) 3157 3169 tg (CPTG … … 3163 3175 va (VaSet 3164 3176 ) 3165 xt "161800,5 3500,163000,54500"3177 xt "161800,52500,163000,53500" 3166 3178 st "wr" 3167 3179 ju 2 3168 blo "163000,5 4300"3180 blo "163000,53300" 3169 3181 ) 3170 3182 ) … … 3192 3204 fg "0,65535,0" 3193 3205 ) 3194 xt "164000,5 4625,164750,55375"3206 xt "164000,53625,164750,54375" 3195 3207 ) 3196 3208 tg (CPTG … … 3202 3214 va (VaSet 3203 3215 ) 3204 xt "161900,5 4500,163000,55500"3216 xt "161900,53500,163000,54500" 3205 3217 st "rd" 3206 3218 ju 2 3207 blo "163000,5 5300"3219 blo "163000,54300" 3208 3220 ) 3209 3221 ) … … 3231 3243 fg "0,65535,0" 3232 3244 ) 3233 xt "164000,5 5625,164750,56375"3245 xt "164000,54625,164750,55375" 3234 3246 ) 3235 3247 tg (CPTG … … 3241 3253 va (VaSet 3242 3254 ) 3243 xt "161800,5 5500,163000,56500"3255 xt "161800,54500,163000,55500" 3244 3256 st "int" 3245 3257 ju 2 3246 blo "163000,5 6300"3258 blo "163000,55300" 3247 3259 ) 3248 3260 ) … … 3268 3280 fg "0,65535,0" 3269 3281 ) 3270 xt "127250,6 9625,128000,70375"3282 xt "127250,68625,128000,69375" 3271 3283 ) 3272 3284 tg (CPTG … … 3278 3290 va (VaSet 3279 3291 ) 3280 xt "129000,6 9500,136900,70500"3292 xt "129000,68500,136900,69500" 3281 3293 st "write_length : (16:0)" 3282 blo "129000, 70300"3294 blo "129000,69300" 3283 3295 ) 3284 3296 ) … … 3305 3317 fg "0,65535,0" 3306 3318 ) 3307 xt "127250, 70625,128000,71375"3319 xt "127250,69625,128000,70375" 3308 3320 ) 3309 3321 tg (CPTG … … 3315 3327 va (VaSet 3316 3328 ) 3317 xt "129000, 70500,145300,71500"3329 xt "129000,69500,145300,70500" 3318 3330 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)" 3319 blo "129000,7 1300"3331 blo "129000,70300" 3320 3332 ) 3321 3333 ) … … 3342 3354 fg "0,65535,0" 3343 3355 ) 3344 xt "127250,5 4625,128000,55375"3356 xt "127250,53625,128000,54375" 3345 3357 ) 3346 3358 tg (CPTG … … 3352 3364 va (VaSet 3353 3365 ) 3354 xt "129000,5 4500,135500,55500"3366 xt "129000,53500,135500,54500" 3355 3367 st "ram_data : (15:0)" 3356 blo "129000,5 5300"3368 blo "129000,54300" 3357 3369 ) 3358 3370 ) … … 3379 3391 fg "0,65535,0" 3380 3392 ) 3381 xt "127250,5 3625,128000,54375"3393 xt "127250,52625,128000,53375" 3382 3394 ) 3383 3395 tg (CPTG … … 3389 3401 va (VaSet 3390 3402 ) 3391 xt "129000,5 3500,143400,54500"3403 xt "129000,52500,143400,53500" 3392 3404 st "ram_addr : (RAM_ADDR_WIDTH-1:0)" 3393 blo "129000,5 4300"3405 blo "129000,53300" 3394 3406 ) 3395 3407 ) … … 3417 3429 fg "0,65535,0" 3418 3430 ) 3419 xt "127250,6 8625,128000,69375"3431 xt "127250,67625,128000,68375" 3420 3432 ) 3421 3433 tg (CPTG … … 3427 3439 va (VaSet 3428 3440 ) 3429 xt "129000,6 8500,133100,69500"3441 xt "129000,67500,133100,68500" 3430 3442 st "data_valid" 3431 blo "129000,6 9300"3443 blo "129000,68300" 3432 3444 ) 3433 3445 ) … … 3453 3465 fg "0,65535,0" 3454 3466 ) 3455 xt "127250,6 7625,128000,68375"3467 xt "127250,66625,128000,67375" 3456 3468 ) 3457 3469 tg (CPTG … … 3463 3475 va (VaSet 3464 3476 ) 3465 xt "129000,6 7500,130900,68500"3477 xt "129000,66500,130900,67500" 3466 3478 st "busy" 3467 blo "129000,6 8300"3479 blo "129000,67300" 3468 3480 ) 3469 3481 ) … … 3491 3503 fg "0,65535,0" 3492 3504 ) 3493 xt "127250,7 1625,128000,72375"3505 xt "127250,70625,128000,71375" 3494 3506 ) 3495 3507 tg (CPTG … … 3501 3513 va (VaSet 3502 3514 ) 3503 xt "129000,7 1500,136800,72500"3515 xt "129000,70500,136800,71500" 3504 3516 st "fifo_channels : (3:0)" 3505 blo "129000,7 2300"3517 blo "129000,71300" 3506 3518 ) 3507 3519 ) … … 3527 3539 fg "0,65535,0" 3528 3540 ) 3529 xt "127250,7 2625,128000,73375"3541 xt "127250,71625,128000,72375" 3530 3542 ) 3531 3543 tg (CPTG … … 3537 3549 va (VaSet 3538 3550 ) 3539 xt "129000,7 2500,134700,73500"3551 xt "129000,71500,134700,72500" 3540 3552 st "write_end_flag" 3541 blo "129000,7 3300"3553 blo "129000,72300" 3542 3554 ) 3543 3555 ) … … 3561 3573 fg "0,65535,0" 3562 3574 ) 3563 xt "127250,7 3625,128000,74375"3575 xt "127250,72625,128000,73375" 3564 3576 ) 3565 3577 tg (CPTG … … 3571 3583 va (VaSet 3572 3584 ) 3573 xt "129000,7 3500,135800,74500"3585 xt "129000,72500,135800,73500" 3574 3586 st "write_header_flag" 3575 blo "129000,7 4300"3587 blo "129000,73300" 3576 3588 ) 3577 3589 ) … … 3595 3607 fg "0,65535,0" 3596 3608 ) 3597 xt "164000, 70625,164750,71375"3609 xt "164000,69625,164750,70375" 3598 3610 ) 3599 3611 tg (CPTG … … 3605 3617 va (VaSet 3606 3618 ) 3607 xt "159000, 70500,163000,71500"3619 xt "159000,69500,163000,70500" 3608 3620 st "led : (7:0)" 3609 3621 ju 2 3610 blo "163000,7 1300"3622 blo "163000,70300" 3611 3623 ) 3612 3624 ) … … 3634 3646 fg "0,65535,0" 3635 3647 ) 3636 xt "127250,6 3625,128000,64375"3648 xt "127250,62625,128000,63375" 3637 3649 ) 3638 3650 tg (CPTG … … 3644 3656 va (VaSet 3645 3657 ) 3646 xt "129000,6 3500,132600,64500"3658 xt "129000,62500,132600,63500" 3647 3659 st "s_trigger" 3648 blo "129000,6 4300"3660 blo "129000,63300" 3649 3661 ) 3650 3662 ) … … 3672 3684 fg "0,65535,0" 3673 3685 ) 3674 xt "127250,7 8625,128000,79375"3686 xt "127250,77625,128000,78375" 3675 3687 ) 3676 3688 tg (CPTG … … 3682 3694 va (VaSet 3683 3695 ) 3684 xt "129000,7 8500,136000,79500"3696 xt "129000,77500,136000,78500" 3685 3697 st "config_addr : (7:0)" 3686 blo "129000,7 9300"3698 blo "129000,78300" 3687 3699 ) 3688 3700 ) … … 3708 3720 fg "0,65535,0" 3709 3721 ) 3710 xt "127250,8 3625,128000,84375"3722 xt "127250,82625,128000,83375" 3711 3723 ) 3712 3724 tg (CPTG … … 3718 3730 va (VaSet 3719 3731 ) 3720 xt "129000,8 3500,133800,84500"3732 xt "129000,82500,133800,83500" 3721 3733 st "config_busy" 3722 blo "129000,8 4300"3734 blo "129000,83300" 3723 3735 ) 3724 3736 ) … … 3744 3756 fg "0,65535,0" 3745 3757 ) 3746 xt "127250,7 9625,128000,80375"3758 xt "127250,78625,128000,79375" 3747 3759 ) 3748 3760 tg (CPTG … … 3754 3766 va (VaSet 3755 3767 ) 3756 xt "129000,7 9500,136700,80500"3768 xt "129000,78500,136700,79500" 3757 3769 st "config_data : (15:0)" 3758 blo "129000, 80300"3770 blo "129000,79300" 3759 3771 ) 3760 3772 ) … … 3781 3793 fg "0,65535,0" 3782 3794 ) 3783 xt "127250, 60625,128000,61375"3795 xt "127250,59625,128000,60375" 3784 3796 ) 3785 3797 tg (CPTG … … 3791 3803 va (VaSet 3792 3804 ) 3793 xt "129000, 60500,134600,61500"3805 xt "129000,59500,134600,60500" 3794 3806 st "config_started" 3795 blo "129000,6 1300"3807 blo "129000,60300" 3796 3808 ) 3797 3809 ) … … 3815 3827 fg "0,65535,0" 3816 3828 ) 3817 xt "127250,8 1625,128000,82375"3829 xt "127250,80625,128000,81375" 3818 3830 ) 3819 3831 tg (CPTG … … 3825 3837 va (VaSet 3826 3838 ) 3827 xt "129000,8 1500,134300,82500"3839 xt "129000,80500,134300,81500" 3828 3840 st "config_wr_en" 3829 blo "129000,8 2300"3841 blo "129000,81300" 3830 3842 ) 3831 3843 ) … … 3851 3863 fg "0,65535,0" 3852 3864 ) 3853 xt "127250,5 9625,128000,60375"3865 xt "127250,58625,128000,59375" 3854 3866 ) 3855 3867 tg (CPTG … … 3861 3873 va (VaSet 3862 3874 ) 3863 xt "129000,5 9500,133600,60500"3875 xt "129000,58500,133600,59500" 3864 3876 st "new_config" 3865 blo "129000, 60300"3877 blo "129000,59300" 3866 3878 ) 3867 3879 ) … … 3889 3901 fg "0,65535,0" 3890 3902 ) 3891 xt "127250,8 2625,128000,83375"3903 xt "127250,81625,128000,82375" 3892 3904 ) 3893 3905 tg (CPTG … … 3899 3911 va (VaSet 3900 3912 ) 3901 xt "129000,8 2500,134200,83500"3913 xt "129000,81500,134200,82500" 3902 3914 st "config_rd_en" 3903 blo "129000,8 3300"3915 blo "129000,82300" 3904 3916 ) 3905 3917 ) … … 3926 3938 fg "0,65535,0" 3927 3939 ) 3928 xt "164000,7 4625,164750,75375"3940 xt "164000,73625,164750,74375" 3929 3941 ) 3930 3942 tg (CPTG … … 3936 3948 va (VaSet 3937 3949 ) 3938 xt "160000,7 4500,163000,75500"3950 xt "160000,73500,163000,74500" 3939 3951 st "denable" 3940 3952 ju 2 3941 blo "163000,7 5300"3953 blo "163000,74300" 3942 3954 ) 3943 3955 ) … … 3949 3961 eolc "-- default domino wave off" 3950 3962 posAdd 0 3951 o 3 23963 o 35 3952 3964 suid 31,0 3953 3965 i "'0'" … … 3965 3977 fg "0,65535,0" 3966 3978 ) 3967 xt "164000,7 5625,164750,76375"3979 xt "164000,74625,164750,75375" 3968 3980 ) 3969 3981 tg (CPTG … … 3975 3987 va (VaSet 3976 3988 ) 3977 xt "157600,7 5500,163000,76500"3989 xt "157600,74500,163000,75500" 3978 3990 st "dwrite_enable" 3979 3991 ju 2 3980 blo "163000,7 6300"3992 blo "163000,75300" 3981 3993 ) 3982 3994 ) … … 3989 4001 preAdd 0 3990 4002 posAdd 0 3991 o 3 34003 o 36 3992 4004 suid 32,0 3993 4005 i "'0'" … … 4005 4017 fg "0,65535,0" 4006 4018 ) 4007 xt "127250,7 4625,128000,75375"4019 xt "127250,73625,128000,74375" 4008 4020 ) 4009 4021 tg (CPTG … … 4015 4027 va (VaSet 4016 4028 ) 4017 xt "129000,7 4500,134600,75500"4029 xt "129000,73500,134600,74500" 4018 4030 st "data_valid_ack" 4019 blo "129000,7 5300"4031 blo "129000,74300" 4020 4032 ) 4021 4033 ) … … 4041 4053 fg "0,65535,0" 4042 4054 ) 4043 xt "164000,7 6625,164750,77375"4055 xt "164000,75625,164750,76375" 4044 4056 ) 4045 4057 tg (CPTG … … 4051 4063 va (VaSet 4052 4064 ) 4053 xt "158300,7 6500,163000,77500"4065 xt "158300,75500,163000,76500" 4054 4066 st "sclk_enable" 4055 4067 ju 2 4056 blo "163000,7 7300"4068 blo "163000,76300" 4057 4069 ) 4058 4070 ) … … 4064 4076 eolc "-- default DWRITE HIGH." 4065 4077 posAdd 0 4066 o 3 44078 o 37 4067 4079 suid 35,0 4068 4080 i "'1'" … … 4080 4092 fg "0,65535,0" 4081 4093 ) 4082 xt "164000, 80625,164750,81375"4094 xt "164000,79625,164750,80375" 4083 4095 ) 4084 4096 tg (CPTG … … 4090 4102 va (VaSet 4091 4103 ) 4092 xt "158100, 80500,163000,81500"4104 xt "158100,79500,163000,80500" 4093 4105 st "ps_direction" 4094 4106 ju 2 4095 blo "163000,8 1300"4107 blo "163000,80300" 4096 4108 ) 4097 4109 ) … … 4103 4115 eolc "-- default phase shift upwards" 4104 4116 posAdd 0 4105 o 3 54117 o 38 4106 4118 suid 36,0 4107 4119 i "'1'" … … 4119 4131 fg "0,65535,0" 4120 4132 ) 4121 xt "164000,8 1625,164750,82375"4133 xt "164000,80625,164750,81375" 4122 4134 ) 4123 4135 tg (CPTG … … 4129 4141 va (VaSet 4130 4142 ) 4131 xt "156000,8 1500,163000,82500"4143 xt "156000,80500,163000,81500" 4132 4144 st "ps_do_phase_shift" 4133 4145 ju 2 4134 blo "163000,8 2300"4146 blo "163000,81300" 4135 4147 ) 4136 4148 ) … … 4143 4155 preAdd 0 4144 4156 posAdd 0 4145 o 3 64157 o 39 4146 4158 suid 37,0 4147 4159 i "'0'" … … 4159 4171 fg "0,65535,0" 4160 4172 ) 4161 xt "164000,8 2625,164750,83375"4173 xt "164000,81625,164750,82375" 4162 4174 ) 4163 4175 tg (CPTG … … 4169 4181 va (VaSet 4170 4182 ) 4171 xt "159700,8 2500,163000,83500"4183 xt "159700,81500,163000,82500" 4172 4184 st "ps_reset" 4173 4185 ju 2 4174 blo "163000,8 3300"4186 blo "163000,82300" 4175 4187 ) 4176 4188 ) … … 4182 4194 eolc "-- pulse this to reset the variable phase shift" 4183 4195 posAdd 0 4184 o 374196 o 40 4185 4197 suid 38,0 4186 4198 i "'0'" … … 4198 4210 fg "0,65535,0" 4199 4211 ) 4200 xt "164000,8 4625,164750,85375"4212 xt "164000,83625,164750,84375" 4201 4213 ) 4202 4214 tg (CPTG … … 4208 4220 va (VaSet 4209 4221 ) 4210 xt "158000,8 4500,163000,85500"4222 xt "158000,83500,163000,84500" 4211 4223 st "srclk_enable" 4212 4224 ju 2 4213 blo "163000,8 5300"4225 blo "163000,84300" 4214 4226 ) 4215 4227 ) … … 4221 4233 eolc "-- default SRCLK on." 4222 4234 posAdd 0 4223 o 384235 o 41 4224 4236 suid 39,0 4225 4237 i "'1'" … … 4237 4249 fg "0,65535,0" 4238 4250 ) 4239 xt "127250,8 4625,128000,85375"4251 xt "127250,83625,128000,84375" 4240 4252 ) 4241 4253 tg (CPTG … … 4247 4259 va (VaSet 4248 4260 ) 4249 xt "129000,8 4500,134600,85500"4261 xt "129000,83500,134600,84500" 4250 4262 st "config_rw_ack" 4251 blo "129000,8 5300"4263 blo "129000,84300" 4252 4264 ) 4253 4265 ) … … 4274 4286 fg "0,65535,0" 4275 4287 ) 4276 xt "127250,8 5625,128000,86375"4288 xt "127250,84625,128000,85375" 4277 4289 ) 4278 4290 tg (CPTG … … 4284 4296 va (VaSet 4285 4297 ) 4286 xt "129000,8 5500,135300,86500"4298 xt "129000,84500,135300,85500" 4287 4299 st "config_rw_ready" 4288 blo "129000,8 6300"4300 blo "129000,85300" 4289 4301 ) 4290 4302 ) … … 4311 4323 fg "0,65535,0" 4312 4324 ) 4313 xt "164000,8 8625,164750,89375"4325 xt "164000,87625,164750,88375" 4314 4326 ) 4315 4327 tg (CPTG … … 4321 4333 va (VaSet 4322 4334 ) 4323 xt "156500,8 8500,163000,89500"4335 xt "156500,87500,163000,88500" 4324 4336 st "socks_connected" 4325 4337 ju 2 4326 blo "163000,8 9300"4338 blo "163000,88300" 4327 4339 ) 4328 4340 ) … … 4332 4344 n "socks_connected" 4333 4345 t "std_logic" 4334 o 4 14346 o 44 4335 4347 suid 42,0 4336 4348 ) … … 4347 4359 fg "0,65535,0" 4348 4360 ) 4349 xt "164000,8 9625,164750,90375"4361 xt "164000,88625,164750,89375" 4350 4362 ) 4351 4363 tg (CPTG … … 4357 4369 va (VaSet 4358 4370 ) 4359 xt "157500,8 9500,163000,90500"4371 xt "157500,88500,163000,89500" 4360 4372 st "socks_waiting" 4361 4373 ju 2 4362 blo "163000, 90300"4374 blo "163000,89300" 4363 4375 ) 4364 4376 ) … … 4369 4381 t "std_logic" 4370 4382 preAdd 0 4371 o 4 04383 o 43 4372 4384 suid 43,0 4373 4385 ) … … 4384 4396 fg "0,65535,0" 4385 4397 ) 4386 xt "164000, 90625,164750,91375"4398 xt "164000,89625,164750,90375" 4387 4399 ) 4388 4400 tg (CPTG … … 4394 4406 va (VaSet 4395 4407 ) 4396 xt "157200, 90500,163000,91500"4408 xt "157200,89500,163000,90500" 4397 4409 st "trigger_enable" 4398 4410 ju 2 4399 blo "163000,9 1300"4411 blo "163000,90300" 4400 4412 ) 4401 4413 ) … … 4407 4419 eolc "-- default triggers are NOT accepted" 4408 4420 posAdd 0 4409 o 394421 o 42 4410 4422 suid 44,0 4411 4423 i "'0'" … … 4423 4435 fg "0,65535,0" 4424 4436 ) 4425 xt "127250,6 4625,128000,65375"4437 xt "127250,63625,128000,64375" 4426 4438 ) 4427 4439 tg (CPTG … … 4433 4445 va (VaSet 4434 4446 ) 4435 xt "129000,6 4500,135600,65500"4447 xt "129000,63500,135600,64500" 4436 4448 st "c_trigger_enable" 4437 blo "129000,6 5300"4449 blo "129000,64300" 4438 4450 ) 4439 4451 ) … … 4459 4471 fg "0,65535,0" 4460 4472 ) 4461 xt "127250,6 5625,128000,66375"4473 xt "127250,64625,128000,65375" 4462 4474 ) 4463 4475 tg (CPTG … … 4469 4481 va (VaSet 4470 4482 ) 4471 xt "129000,6 5500,137400,66500"4483 xt "129000,64500,137400,65500" 4472 4484 st "c_trigger_mult : (7:0)" 4473 blo "129000,6 6300"4485 blo "129000,65300" 4474 4486 ) 4475 4487 ) … … 4488 4500 ) 4489 4501 ) 4502 *116 (CptPort 4503 uid 13806,0 4504 ps "OnEdgeStrategy" 4505 shape (Triangle 4506 uid 13807,0 4507 ro 90 4508 va (VaSet 4509 vasetType 1 4510 fg "0,65535,0" 4511 ) 4512 xt "127250,91625,128000,92375" 4513 ) 4514 tg (CPTG 4515 uid 13808,0 4516 ps "CptPortTextPlaceStrategy" 4517 stg "VerticalLayoutStrategy" 4518 f (Text 4519 uid 13809,0 4520 va (VaSet 4521 ) 4522 xt "129000,91500,136500,92500" 4523 st "MAC_jumper : (1:0)" 4524 blo "129000,92300" 4525 ) 4526 ) 4527 thePort (LogicalPort 4528 decl (Decl 4529 n "MAC_jumper" 4530 t "std_logic_vector" 4531 b "(1 downto 0)" 4532 o 32 4533 suid 48,0 4534 ) 4535 ) 4536 ) 4537 *117 (CptPort 4538 uid 13911,0 4539 ps "OnEdgeStrategy" 4540 shape (Triangle 4541 uid 13912,0 4542 ro 90 4543 va (VaSet 4544 vasetType 1 4545 fg "0,65535,0" 4546 ) 4547 xt "127250,92625,128000,93375" 4548 ) 4549 tg (CPTG 4550 uid 13913,0 4551 ps "CptPortTextPlaceStrategy" 4552 stg "VerticalLayoutStrategy" 4553 f (Text 4554 uid 13914,0 4555 va (VaSet 4556 ) 4557 xt "129000,92500,134800,93500" 4558 st "BoardID : (3:0)" 4559 blo "129000,93300" 4560 ) 4561 ) 4562 thePort (LogicalPort 4563 decl (Decl 4564 n "BoardID" 4565 t "std_logic_vector" 4566 b "(3 downto 0)" 4567 o 33 4568 suid 49,0 4569 ) 4570 ) 4571 ) 4572 *118 (CptPort 4573 uid 13915,0 4574 ps "OnEdgeStrategy" 4575 shape (Triangle 4576 uid 13916,0 4577 ro 90 4578 va (VaSet 4579 vasetType 1 4580 fg "0,65535,0" 4581 ) 4582 xt "127250,93625,128000,94375" 4583 ) 4584 tg (CPTG 4585 uid 13917,0 4586 ps "CptPortTextPlaceStrategy" 4587 stg "VerticalLayoutStrategy" 4588 f (Text 4589 uid 13918,0 4590 va (VaSet 4591 ) 4592 xt "129000,93500,134700,94500" 4593 st "CrateID : (1:0)" 4594 blo "129000,94300" 4595 ) 4596 ) 4597 thePort (LogicalPort 4598 decl (Decl 4599 n "CrateID" 4600 t "std_logic_vector" 4601 b "(1 downto 0)" 4602 o 34 4603 suid 50,0 4604 ) 4605 ) 4606 ) 4490 4607 ] 4491 4608 shape (Rectangle … … 4497 4614 lineWidth 2 4498 4615 ) 4499 xt "128000,5 1000,164000,94000"4616 xt "128000,50000,164000,99000" 4500 4617 ) 4501 4618 oxt "43000,2000,56000,22000" … … 4505 4622 stg "VerticalLayoutStrategy" 4506 4623 textVec [ 4507 *11 6(Text4624 *119 (Text 4508 4625 uid 1609,0 4509 4626 va (VaSet 4510 4627 font "Arial,8,1" 4511 4628 ) 4512 xt "1 27700,92000,133900,93000"4629 xt "132700,99000,138900,100000" 4513 4630 st "FACT_FAD_lib" 4514 blo "1 27700,92800"4631 blo "132700,99800" 4515 4632 tm "BdLibraryNameMgr" 4516 4633 ) 4517 *1 17(Text4634 *120 (Text 4518 4635 uid 1610,0 4519 4636 va (VaSet 4520 4637 font "Arial,8,1" 4521 4638 ) 4522 xt "1 27700,93000,133400,94000"4639 xt "132700,100000,138400,101000" 4523 4640 st "w5300_modul" 4524 blo "1 27700,93800"4641 blo "132700,100800" 4525 4642 tm "CptNameMgr" 4526 4643 ) 4527 *1 18(Text4644 *121 (Text 4528 4645 uid 1611,0 4529 4646 va (VaSet 4530 4647 font "Arial,8,1" 4531 4648 ) 4532 xt "1 27700,94000,134400,95000"4649 xt "132700,101000,139400,102000" 4533 4650 st "I_main_ethernet" 4534 blo "1 27700,94800"4651 blo "132700,101800" 4535 4652 tm "InstanceNameMgr" 4536 4653 ) … … 4547 4664 font "Courier New,8,0" 4548 4665 ) 4549 xt "128000, 50200,155500,51000"4666 xt "128000,49200,155500,50000" 4550 4667 st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2 ( integer ) " 4551 4668 ) … … 4567 4684 fg "49152,49152,49152" 4568 4685 ) 4569 xt "128250,9 2250,129750,93750"4686 xt "128250,97250,129750,98750" 4570 4687 iconName "VhdlFileViewIcon.png" 4571 4688 iconMaskName "VhdlFileViewIcon.msk" … … 4578 4695 archFileType "UNKNOWN" 4579 4696 ) 4580 *1 19(Net4697 *122 (Net 4581 4698 uid 1680,0 4582 4699 decl (Decl 4583 4700 n "crate_id" 4584 4701 t "std_logic_vector" 4585 b "(1 downto0)"4702 b "(1 DOWNTO 0)" 4586 4703 o 9 4587 4704 suid 30,0 … … 4592 4709 font "Courier New,8,0" 4593 4710 ) 4594 xt "-102000,23600,-73500,24400" 4595 st "crate_id : std_logic_vector(1 downto 0)" 4596 ) 4597 ) 4598 *120 (SaComponent 4711 xt "-102000,24400,-73500,25200" 4712 st "crate_id : std_logic_vector(1 DOWNTO 0) 4713 " 4714 ) 4715 ) 4716 *123 (SaComponent 4599 4717 uid 1768,0 4600 4718 optionalChildren [ 4601 *12 1(CptPort4719 *124 (CptPort 4602 4720 uid 1760,0 4603 4721 ps "OnEdgeStrategy" … … 4639 4757 ) 4640 4758 ) 4641 *12 2(CptPort4759 *125 (CptPort 4642 4760 uid 1764,0 4643 4761 ps "OnEdgeStrategy" … … 4676 4794 ) 4677 4795 ) 4678 *12 3(CptPort4796 *126 (CptPort 4679 4797 uid 6207,0 4680 4798 ps "OnEdgeStrategy" … … 4728 4846 stg "VerticalLayoutStrategy" 4729 4847 textVec [ 4730 *12 4(Text4848 *127 (Text 4731 4849 uid 1771,0 4732 4850 va (VaSet … … 4738 4856 tm "BdLibraryNameMgr" 4739 4857 ) 4740 *12 5(Text4858 *128 (Text 4741 4859 uid 1772,0 4742 4860 va (VaSet … … 4748 4866 tm "CptNameMgr" 4749 4867 ) 4750 *12 6(Text4868 *129 (Text 4751 4869 uid 1773,0 4752 4870 va (VaSet … … 4796 4914 archFileType "UNKNOWN" 4797 4915 ) 4798 *1 27(Net4916 *130 (Net 4799 4917 uid 1981,0 4800 4918 lang 2 … … 4813 4931 font "Courier New,8,0" 4814 4932 ) 4815 xt "-102000,118400,-69500,119200" 4816 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 4817 ) 4818 ) 4819 *128 (Net 4933 xt "-102000,119200,-69500,120000" 4934 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 4935 " 4936 ) 4937 ) 4938 *131 (Net 4820 4939 uid 2297,0 4821 4940 decl (Decl … … 4833 4952 font "Courier New,8,0" 4834 4953 ) 4835 xt "-102000,101600,-62000,102400" 4836 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 4837 ) 4838 ) 4839 *129 (SaComponent 4954 xt "-102000,102400,-62000,103200" 4955 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 4956 " 4957 ) 4958 ) 4959 *132 (SaComponent 4840 4960 uid 2311,0 4841 4961 optionalChildren [ 4842 *13 0(CptPort4962 *133 (CptPort 4843 4963 uid 2307,0 4844 4964 ps "OnEdgeStrategy" … … 4881 5001 ) 4882 5002 ) 4883 *13 1(CptPort5003 *134 (CptPort 4884 5004 uid 2351,0 4885 5005 ps "OnEdgeStrategy" … … 4917 5037 ) 4918 5038 ) 4919 *13 2(CptPort5039 *135 (CptPort 4920 5040 uid 2361,0 4921 5041 ps "OnEdgeStrategy" … … 4955 5075 ) 4956 5076 ) 4957 *13 3(CptPort5077 *136 (CptPort 4958 5078 uid 2365,0 4959 5079 ps "OnEdgeStrategy" … … 4991 5111 ) 4992 5112 ) 4993 *13 4(CptPort5113 *137 (CptPort 4994 5114 uid 2369,0 4995 5115 ps "OnEdgeStrategy" … … 5029 5149 ) 5030 5150 ) 5031 *13 5(CptPort5151 *138 (CptPort 5032 5152 uid 2373,0 5033 5153 ps "OnEdgeStrategy" … … 5066 5186 ) 5067 5187 ) 5068 *13 6(CptPort5188 *139 (CptPort 5069 5189 uid 2377,0 5070 5190 ps "OnEdgeStrategy" … … 5105 5225 ) 5106 5226 ) 5107 *1 37(CptPort5227 *140 (CptPort 5108 5228 uid 2381,0 5109 5229 ps "OnEdgeStrategy" … … 5142 5262 ) 5143 5263 ) 5144 *1 38(CptPort5264 *141 (CptPort 5145 5265 uid 2385,0 5146 5266 ps "OnEdgeStrategy" … … 5182 5302 ) 5183 5303 ) 5184 *1 39(CptPort5304 *142 (CptPort 5185 5305 uid 2389,0 5186 5306 ps "OnEdgeStrategy" … … 5223 5343 ) 5224 5344 ) 5225 *14 0(CptPort5345 *143 (CptPort 5226 5346 uid 2393,0 5227 5347 ps "OnEdgeStrategy" … … 5262 5382 ) 5263 5383 ) 5264 *14 1(CptPort5384 *144 (CptPort 5265 5385 uid 2397,0 5266 5386 ps "OnEdgeStrategy" … … 5301 5421 ) 5302 5422 ) 5303 *14 2(CptPort5423 *145 (CptPort 5304 5424 uid 2401,0 5305 5425 ps "OnEdgeStrategy" … … 5340 5460 ) 5341 5461 ) 5342 *14 3(CptPort5462 *146 (CptPort 5343 5463 uid 2405,0 5344 5464 ps "OnEdgeStrategy" … … 5380 5500 ) 5381 5501 ) 5382 *14 4(CptPort5502 *147 (CptPort 5383 5503 uid 2454,0 5384 5504 ps "OnEdgeStrategy" … … 5418 5538 ) 5419 5539 ) 5420 *14 5(CptPort5540 *148 (CptPort 5421 5541 uid 2628,0 5422 5542 ps "OnEdgeStrategy" … … 5457 5577 ) 5458 5578 ) 5459 *14 6(CptPort5579 *149 (CptPort 5460 5580 uid 5991,0 5461 5581 ps "OnEdgeStrategy" … … 5495 5615 ) 5496 5616 ) 5497 *1 47(CptPort5617 *150 (CptPort 5498 5618 uid 8410,0 5499 5619 ps "OnEdgeStrategy" … … 5532 5652 ) 5533 5653 ) 5534 *1 48(CptPort5654 *151 (CptPort 5535 5655 uid 10232,0 5536 5656 ps "OnEdgeStrategy" … … 5590 5710 stg "VerticalLayoutStrategy" 5591 5711 textVec [ 5592 *1 49(Text5712 *152 (Text 5593 5713 uid 2314,0 5594 5714 va (VaSet … … 5600 5720 tm "BdLibraryNameMgr" 5601 5721 ) 5602 *15 0(Text5722 *153 (Text 5603 5723 uid 2315,0 5604 5724 va (VaSet … … 5610 5730 tm "CptNameMgr" 5611 5731 ) 5612 *15 1(Text5732 *154 (Text 5613 5733 uid 2316,0 5614 5734 va (VaSet … … 5669 5789 archFileType "UNKNOWN" 5670 5790 ) 5671 *15 2(Net5791 *155 (Net 5672 5792 uid 2468,0 5673 5793 lang 2 … … 5683 5803 font "Courier New,8,0" 5684 5804 ) 5685 xt "-102000,120800,-79500,121600" 5686 st "SIGNAL wiz_busy : std_logic" 5687 ) 5688 ) 5689 *153 (Net 5805 xt "-102000,121600,-79500,122400" 5806 st "SIGNAL wiz_busy : std_logic 5807 " 5808 ) 5809 ) 5810 *156 (Net 5690 5811 uid 2474,0 5691 5812 lang 2 … … 5702 5823 font "Courier New,8,0" 5703 5824 ) 5704 xt "-102000,123200,-58500,124000" 5705 st "SIGNAL wiz_write_ea : std_logic := '0'" 5706 ) 5707 ) 5708 *154 (Net 5825 xt "-102000,124000,-58500,124800" 5826 st "SIGNAL wiz_write_ea : std_logic := '0' 5827 " 5828 ) 5829 ) 5830 *157 (Net 5709 5831 uid 2480,0 5710 5832 lang 2 … … 5722 5844 font "Courier New,8,0" 5723 5845 ) 5724 xt "-102000,125600,-52500,126400" 5725 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 5726 ) 5727 ) 5728 *155 (Net 5846 xt "-102000,126400,-52500,127200" 5847 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5848 " 5849 ) 5850 ) 5851 *158 (Net 5729 5852 uid 2486,0 5730 5853 lang 2 … … 5743 5866 font "Courier New,8,0" 5744 5867 ) 5745 xt "-102000,122400,-52500,123200" 5746 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 5747 ) 5748 ) 5749 *156 (Net 5868 xt "-102000,123200,-52500,124000" 5869 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5870 " 5871 ) 5872 ) 5873 *159 (Net 5750 5874 uid 2492,0 5751 5875 lang 2 … … 5763 5887 font "Courier New,8,0" 5764 5888 ) 5765 xt "-102000,121600,-52500,122400" 5766 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 5767 ) 5768 ) 5769 *157 (Net 5889 xt "-102000,122400,-52500,123200" 5890 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5891 " 5892 ) 5893 ) 5894 *160 (Net 5770 5895 uid 2498,0 5771 5896 lang 2 … … 5782 5907 font "Courier New,8,0" 5783 5908 ) 5784 xt "-102000,124000,-58500,124800" 5785 st "SIGNAL wiz_write_end : std_logic := '0'" 5786 ) 5787 ) 5788 *158 (Net 5909 xt "-102000,124800,-58500,125600" 5910 st "SIGNAL wiz_write_end : std_logic := '0' 5911 " 5912 ) 5913 ) 5914 *161 (Net 5789 5915 uid 2504,0 5790 5916 lang 2 … … 5801 5927 font "Courier New,8,0" 5802 5928 ) 5803 xt "-102000,124800,-58500,125600" 5804 st "SIGNAL wiz_write_header : std_logic := '0'" 5805 ) 5806 ) 5807 *159 (Net 5929 xt "-102000,125600,-58500,126400" 5930 st "SIGNAL wiz_write_header : std_logic := '0' 5931 " 5932 ) 5933 ) 5934 *162 (Net 5808 5935 uid 2574,0 5809 5936 decl (Decl … … 5818 5945 font "Courier New,8,0" 5819 5946 ) 5820 xt "-102000,102400,-79500,103200" 5821 st "SIGNAL ram_write_ea : std_logic" 5822 ) 5823 ) 5824 *160 (Net 5947 xt "-102000,103200,-79500,104000" 5948 st "SIGNAL ram_write_ea : std_logic 5949 " 5950 ) 5951 ) 5952 *163 (Net 5825 5953 uid 2580,0 5826 5954 decl (Decl … … 5836 5964 font "Courier New,8,0" 5837 5965 ) 5838 xt "-102000,103200,-58500,104000" 5839 st "SIGNAL ram_write_ready : std_logic := '0'" 5840 ) 5841 ) 5842 *161 (Net 5966 xt "-102000,104000,-58500,104800" 5967 st "SIGNAL ram_write_ready : std_logic := '0' 5968 " 5969 ) 5970 ) 5971 *164 (Net 5843 5972 uid 2586,0 5844 5973 decl (Decl … … 5854 5983 font "Courier New,8,0" 5855 5984 ) 5856 xt "-102000,74400,-58500,75200" 5857 st "SIGNAL config_start : std_logic := '0'" 5858 ) 5859 ) 5860 *162 (Net 5985 xt "-102000,75200,-58500,76000" 5986 st "SIGNAL config_start : std_logic := '0' 5987 " 5988 ) 5989 ) 5990 *165 (Net 5861 5991 uid 2592,0 5862 5992 decl (Decl … … 5871 6001 font "Courier New,8,0" 5872 6002 ) 5873 xt "-102000,68800,-79500,69600" 5874 st "SIGNAL config_ready : std_logic" 5875 ) 5876 ) 5877 *163 (Net 6003 xt "-102000,69600,-79500,70400" 6004 st "SIGNAL config_ready : std_logic 6005 " 6006 ) 6007 ) 6008 *166 (Net 5878 6009 uid 2598,0 5879 6010 decl (Decl … … 5888 6019 font "Courier New,8,0" 5889 6020 ) 5890 xt "-102000,106400,-78000,107200" 5891 st "SIGNAL roi_max : roi_max_type" 5892 ) 5893 ) 5894 *164 (Net 6021 xt "-102000,107200,-78000,108000" 6022 st "SIGNAL roi_max : roi_max_type 6023 " 6024 ) 6025 ) 6026 *167 (Net 5895 6027 uid 2640,0 5896 6028 decl (Decl … … 5906 6038 font "Courier New,8,0" 5907 6039 ) 5908 xt "-102000,96800,-69500,97600" 5909 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 5910 ) 5911 ) 5912 *165 (Net 6040 xt "-102000,97600,-69500,98400" 6041 st "SIGNAL package_length : std_logic_vector(15 downto 0) 6042 " 6043 ) 6044 ) 6045 *168 (Net 5913 6046 uid 2776,0 5914 6047 decl (Decl … … 5924 6057 font "Courier New,8,0" 5925 6058 ) 5926 xt "-102000,38000,-62000,38800" 5927 st "adc_oeb : std_logic := '1'" 5928 ) 5929 ) 5930 *166 (PortIoOut 6059 xt "-102000,38800,-62000,39600" 6060 st "adc_oeb : std_logic := '1' 6061 " 6062 ) 6063 ) 6064 *169 (PortIoOut 5931 6065 uid 2798,0 5932 6066 shape (CompositeShape … … 5973 6107 ) 5974 6108 ) 5975 *1 67(PortIoIn6109 *170 (PortIoIn 5976 6110 uid 2804,0 5977 6111 shape (CompositeShape … … 6018 6152 ) 6019 6153 ) 6020 *1 68(Net6154 *171 (Net 6021 6155 uid 2924,0 6022 6156 decl (Decl … … 6031 6165 font "Courier New,8,0" 6032 6166 ) 6033 xt "-102000,105600,-77000,106400" 6034 st "SIGNAL roi_array : roi_array_type" 6035 ) 6036 ) 6037 *169 (PortIoIn 6167 xt "-102000,106400,-77000,107200" 6168 st "SIGNAL roi_array : roi_array_type 6169 " 6170 ) 6171 ) 6172 *172 (PortIoIn 6038 6173 uid 2950,0 6039 6174 shape (CompositeShape … … 6080 6215 ) 6081 6216 ) 6082 *17 0(PortIoIn6217 *173 (PortIoIn 6083 6218 uid 2956,0 6084 6219 shape (CompositeShape … … 6125 6260 ) 6126 6261 ) 6127 *17 1(Grouping6262 *174 (Grouping 6128 6263 uid 3137,0 6129 6264 optionalChildren [ 6130 *17 2(CommentText6265 *175 (CommentText 6131 6266 uid 3139,0 6132 6267 shape (Rectangle … … 6159 6294 titleBlock 1 6160 6295 ) 6161 *17 3(CommentText6296 *176 (CommentText 6162 6297 uid 3142,0 6163 6298 shape (Rectangle … … 6190 6325 titleBlock 1 6191 6326 ) 6192 *17 4(CommentText6327 *177 (CommentText 6193 6328 uid 3145,0 6194 6329 shape (Rectangle … … 6221 6356 titleBlock 1 6222 6357 ) 6223 *17 5(CommentText6358 *178 (CommentText 6224 6359 uid 3148,0 6225 6360 shape (Rectangle … … 6252 6387 titleBlock 1 6253 6388 ) 6254 *17 6(CommentText6389 *179 (CommentText 6255 6390 uid 3151,0 6256 6391 shape (Rectangle … … 6282 6417 titleBlock 1 6283 6418 ) 6284 *1 77(CommentText6419 *180 (CommentText 6285 6420 uid 3154,0 6286 6421 shape (Rectangle … … 6313 6448 titleBlock 1 6314 6449 ) 6315 *1 78(CommentText6450 *181 (CommentText 6316 6451 uid 3157,0 6317 6452 shape (Rectangle … … 6345 6480 titleBlock 1 6346 6481 ) 6347 *1 79(CommentText6482 *182 (CommentText 6348 6483 uid 3160,0 6349 6484 shape (Rectangle … … 6376 6511 titleBlock 1 6377 6512 ) 6378 *18 0(CommentText6513 *183 (CommentText 6379 6514 uid 3163,0 6380 6515 shape (Rectangle … … 6407 6542 titleBlock 1 6408 6543 ) 6409 *18 1(CommentText6544 *184 (CommentText 6410 6545 uid 3166,0 6411 6546 shape (Rectangle … … 6451 6586 oxt "14000,66000,55000,71000" 6452 6587 ) 6453 *18 2(Net6588 *185 (Net 6454 6589 uid 3894,0 6455 6590 decl (Decl … … 6464 6599 font "Courier New,8,0" 6465 6600 ) 6466 xt "-102000,28400,-83500,29200" 6467 st "CLK_25_PS : std_logic" 6468 ) 6469 ) 6470 *183 (PortIoOut 6601 xt "-102000,29200,-83500,30000" 6602 st "CLK_25_PS : std_logic 6603 " 6604 ) 6605 ) 6606 *186 (PortIoOut 6471 6607 uid 3978,0 6472 6608 shape (CompositeShape … … 6513 6649 ) 6514 6650 ) 6515 *18 4(Net6651 *187 (Net 6516 6652 uid 4068,0 6517 6653 decl (Decl … … 6526 6662 font "Courier New,8,0" 6527 6663 ) 6528 xt "-102000,29200,-83500,30000" 6529 st "CLK_50 : std_logic" 6530 ) 6531 ) 6532 *185 (Net 6664 xt "-102000,30000,-83500,30800" 6665 st "CLK_50 : std_logic 6666 " 6667 ) 6668 ) 6669 *188 (Net 6533 6670 uid 4204,0 6534 6671 decl (Decl … … 6543 6680 font "Courier New,8,0" 6544 6681 ) 6545 xt "-102000,59200,-79500,60000" 6546 st "SIGNAL CLK_25 : std_logic" 6547 ) 6548 ) 6549 *186 (PortIoOut 6682 xt "-102000,60000,-79500,60800" 6683 st "SIGNAL CLK_25 : std_logic 6684 " 6685 ) 6686 ) 6687 *189 (PortIoOut 6550 6688 uid 4220,0 6551 6689 shape (CompositeShape … … 6592 6730 ) 6593 6731 ) 6594 *1 87(Net6732 *190 (Net 6595 6733 uid 4232,0 6596 6734 decl (Decl … … 6606 6744 ) 6607 6745 xt "-102000,17200,-83500,18000" 6608 st "CLK : std_logic" 6609 ) 6610 ) 6611 *188 (Net 6746 st "CLK : std_logic 6747 " 6748 ) 6749 ) 6750 *191 (Net 6612 6751 uid 4260,0 6613 6752 decl (Decl … … 6623 6762 font "Courier New,8,0" 6624 6763 ) 6625 xt "-102000,22000,-73500,22800" 6626 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 6627 ) 6628 ) 6629 *189 (Net 6764 xt "-102000,22800,-73500,23600" 6765 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 6766 " 6767 ) 6768 ) 6769 *192 (Net 6630 6770 uid 4270,0 6631 6771 decl (Decl … … 6640 6780 font "Courier New,8,0" 6641 6781 ) 6642 xt "-102000,21200,-78000,22000" 6643 st "adc_data_array : adc_data_array_type" 6644 ) 6645 ) 6646 *190 (PortIoIn 6782 xt "-102000,22000,-78000,22800" 6783 st "adc_data_array : adc_data_array_type 6784 " 6785 ) 6786 ) 6787 *193 (PortIoIn 6647 6788 uid 4307,0 6648 6789 shape (CompositeShape … … 6689 6830 ) 6690 6831 ) 6691 *19 1(Net6832 *194 (Net 6692 6833 uid 4399,0 6693 6834 decl (Decl … … 6703 6844 font "Courier New,8,0" 6704 6845 ) 6705 xt "-102000,86400,-58500,87200" 6706 st "SIGNAL drs_clk_en : std_logic := '0'" 6707 ) 6708 ) 6709 *192 (Net 6846 xt "-102000,87200,-58500,88000" 6847 st "SIGNAL drs_clk_en : std_logic := '0' 6848 " 6849 ) 6850 ) 6851 *195 (Net 6710 6852 uid 4405,0 6711 6853 decl (Decl … … 6720 6862 font "Courier New,8,0" 6721 6863 ) 6722 xt "-102000,92800,-73500,93600" 6723 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6724 ) 6725 ) 6726 *193 (Net 6864 xt "-102000,93600,-73500,94400" 6865 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6866 " 6867 ) 6868 ) 6869 *196 (Net 6727 6870 uid 4417,0 6728 6871 decl (Decl … … 6738 6881 font "Courier New,8,0" 6739 6882 ) 6740 xt "-102000,87200,-58500,88000" 6741 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6742 ) 6743 ) 6744 *194 (Net 6883 xt "-102000,88000,-58500,88800" 6884 st "SIGNAL drs_read_s_cell : std_logic := '0' 6885 " 6886 ) 6887 ) 6888 *197 (Net 6745 6889 uid 4535,0 6746 6890 decl (Decl … … 6757 6901 font "Courier New,8,0" 6758 6902 ) 6759 xt "-102000,42000,-56000,42800" 6760 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6761 ) 6762 ) 6763 *195 (Net 6903 xt "-102000,42800,-56000,43600" 6904 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6905 " 6906 ) 6907 ) 6908 *198 (Net 6764 6909 uid 4543,0 6765 6910 decl (Decl … … 6775 6920 font "Courier New,8,0" 6776 6921 ) 6777 xt "-102000,42800,-62000,43600" 6778 st "drs_dwrite : std_logic := '1'" 6779 ) 6780 ) 6781 *196 (PortIoOut 6922 xt "-102000,43600,-62000,44400" 6923 st "drs_dwrite : std_logic := '1' 6924 " 6925 ) 6926 ) 6927 *199 (PortIoOut 6782 6928 uid 4551,0 6783 6929 shape (CompositeShape … … 6824 6970 ) 6825 6971 ) 6826 * 197(PortIoOut6972 *200 (PortIoOut 6827 6973 uid 4557,0 6828 6974 shape (CompositeShape … … 6869 7015 ) 6870 7016 ) 6871 * 198(Net7017 *201 (Net 6872 7018 uid 4669,0 6873 7019 decl (Decl … … 6882 7028 font "Courier New,8,0" 6883 7029 ) 6884 xt "-102000,18000,-83500,18800" 6885 st "SROUT_in_0 : std_logic" 6886 ) 6887 ) 6888 *199 (Net 7030 xt "-102000,18800,-83500,19600" 7031 st "SROUT_in_0 : std_logic 7032 " 7033 ) 7034 ) 7035 *202 (Net 6889 7036 uid 4677,0 6890 7037 decl (Decl … … 6899 7046 font "Courier New,8,0" 6900 7047 ) 6901 xt "-102000,18800,-83500,19600" 6902 st "SROUT_in_1 : std_logic" 6903 ) 6904 ) 6905 *200 (Net 7048 xt "-102000,19600,-83500,20400" 7049 st "SROUT_in_1 : std_logic 7050 " 7051 ) 7052 ) 7053 *203 (Net 6906 7054 uid 4685,0 6907 7055 decl (Decl … … 6916 7064 font "Courier New,8,0" 6917 7065 ) 6918 xt "-102000,19600,-83500,20400" 6919 st "SROUT_in_2 : std_logic" 6920 ) 6921 ) 6922 *201 (Net 7066 xt "-102000,20400,-83500,21200" 7067 st "SROUT_in_2 : std_logic 7068 " 7069 ) 7070 ) 7071 *204 (Net 6923 7072 uid 4693,0 6924 7073 decl (Decl … … 6933 7082 font "Courier New,8,0" 6934 7083 ) 6935 xt "-102000,20400,-83500,21200" 6936 st "SROUT_in_3 : std_logic" 6937 ) 6938 ) 6939 *202 (PortIoIn 7084 xt "-102000,21200,-83500,22000" 7085 st "SROUT_in_3 : std_logic 7086 " 7087 ) 7088 ) 7089 *205 (PortIoIn 6940 7090 uid 4701,0 6941 7091 shape (CompositeShape … … 6982 7132 ) 6983 7133 ) 6984 *20 3(PortIoIn7134 *206 (PortIoIn 6985 7135 uid 4707,0 6986 7136 shape (CompositeShape … … 7027 7177 ) 7028 7178 ) 7029 *20 4(PortIoIn7179 *207 (PortIoIn 7030 7180 uid 4713,0 7031 7181 shape (CompositeShape … … 7072 7222 ) 7073 7223 ) 7074 *20 5(PortIoIn7224 *208 (PortIoIn 7075 7225 uid 4719,0 7076 7226 shape (CompositeShape … … 7117 7267 ) 7118 7268 ) 7119 *20 6(Net7269 *209 (Net 7120 7270 uid 4741,0 7121 7271 decl (Decl … … 7130 7280 font "Courier New,8,0" 7131 7281 ) 7132 xt "-102000,88000,-79500,88800" 7133 st "SIGNAL drs_read_s_cell_ready : std_logic" 7134 ) 7135 ) 7136 *207 (SaComponent 7282 xt "-102000,88800,-79500,89600" 7283 st "SIGNAL drs_read_s_cell_ready : std_logic 7284 " 7285 ) 7286 ) 7287 *210 (SaComponent 7137 7288 uid 4903,0 7138 7289 optionalChildren [ 7139 *2 08(CptPort7290 *211 (CptPort 7140 7291 uid 4867,0 7141 7292 ps "OnEdgeStrategy" … … 7170 7321 ) 7171 7322 ) 7172 *2 09(CptPort7323 *212 (CptPort 7173 7324 uid 4871,0 7174 7325 ps "OnEdgeStrategy" … … 7204 7355 ) 7205 7356 ) 7206 *21 0(CptPort7357 *213 (CptPort 7207 7358 uid 4875,0 7208 7359 ps "OnEdgeStrategy" … … 7238 7389 ) 7239 7390 ) 7240 *21 1(CptPort7391 *214 (CptPort 7241 7392 uid 4879,0 7242 7393 ps "OnEdgeStrategy" … … 7271 7422 ) 7272 7423 ) 7273 *21 2(CptPort7424 *215 (CptPort 7274 7425 uid 4883,0 7275 7426 ps "OnEdgeStrategy" … … 7304 7455 ) 7305 7456 ) 7306 *21 3(CptPort7457 *216 (CptPort 7307 7458 uid 4887,0 7308 7459 ps "OnEdgeStrategy" … … 7337 7488 ) 7338 7489 ) 7339 *21 4(CptPort7490 *217 (CptPort 7340 7491 uid 4891,0 7341 7492 ps "OnEdgeStrategy" … … 7370 7521 ) 7371 7522 ) 7372 *21 5(CptPort7523 *218 (CptPort 7373 7524 uid 4895,0 7374 7525 ps "OnEdgeStrategy" … … 7405 7556 ) 7406 7557 ) 7407 *21 6(CptPort7558 *219 (CptPort 7408 7559 uid 4899,0 7409 7560 ps "OnEdgeStrategy" … … 7441 7592 ) 7442 7593 ) 7443 *2 17(CptPort7594 *220 (CptPort 7444 7595 uid 4938,0 7445 7596 ps "OnEdgeStrategy" … … 7476 7627 ) 7477 7628 ) 7478 *2 18(CptPort7629 *221 (CptPort 7479 7630 uid 4942,0 7480 7631 ps "OnEdgeStrategy" … … 7511 7662 ) 7512 7663 ) 7513 *2 19(CptPort7664 *222 (CptPort 7514 7665 uid 10272,0 7515 7666 ps "OnEdgeStrategy" … … 7546 7697 ) 7547 7698 ) 7548 *22 0(CptPort7699 *223 (CptPort 7549 7700 uid 10276,0 7550 7701 ps "OnEdgeStrategy" … … 7581 7732 ) 7582 7733 ) 7583 *22 1(CptPort7734 *224 (CptPort 7584 7735 uid 10280,0 7585 7736 ps "OnEdgeStrategy" … … 7617 7768 ) 7618 7769 ) 7619 *22 2(CptPort7770 *225 (CptPort 7620 7771 uid 10284,0 7621 7772 ps "OnEdgeStrategy" … … 7653 7804 ) 7654 7805 ) 7655 *22 3(CptPort7806 *226 (CptPort 7656 7807 uid 10288,0 7657 7808 ps "OnEdgeStrategy" … … 7704 7855 stg "VerticalLayoutStrategy" 7705 7856 textVec [ 7706 *22 4(Text7857 *227 (Text 7707 7858 uid 4906,0 7708 7859 va (VaSet … … 7714 7865 tm "BdLibraryNameMgr" 7715 7866 ) 7716 *22 5(Text7867 *228 (Text 7717 7868 uid 4907,0 7718 7869 va (VaSet … … 7724 7875 tm "CptNameMgr" 7725 7876 ) 7726 *22 6(Text7877 *229 (Text 7727 7878 uid 4908,0 7728 7879 va (VaSet … … 7771 7922 archFileType "UNKNOWN" 7772 7923 ) 7773 *2 27(Net7924 *230 (Net 7774 7925 uid 4946,0 7775 7926 decl (Decl … … 7785 7936 font "Courier New,8,0" 7786 7937 ) 7787 xt "-102000,34800,-62000,35600" 7788 st "RSRLOAD : std_logic := '0'" 7789 ) 7790 ) 7791 *228 (PortIoOut 7938 xt "-102000,35600,-62000,36400" 7939 st "RSRLOAD : std_logic := '0' 7940 " 7941 ) 7942 ) 7943 *231 (PortIoOut 7792 7944 uid 4954,0 7793 7945 shape (CompositeShape … … 7834 7986 ) 7835 7987 ) 7836 *2 29(Net7988 *232 (Net 7837 7989 uid 4960,0 7838 7990 decl (Decl … … 7848 8000 font "Courier New,8,0" 7849 8001 ) 7850 xt "-102000,35600,-62000,36400" 7851 st "SRCLK : std_logic := '0'" 7852 ) 7853 ) 7854 *230 (PortIoOut 8002 xt "-102000,36400,-62000,37200" 8003 st "SRCLK : std_logic := '0' 8004 " 8005 ) 8006 ) 8007 *233 (PortIoOut 7855 8008 uid 4968,0 7856 8009 shape (CompositeShape … … 7897 8050 ) 7898 8051 ) 7899 *23 1(SaComponent8052 *234 (SaComponent 7900 8053 uid 5072,0 7901 8054 optionalChildren [ 7902 *23 2(CptPort8055 *235 (CptPort 7903 8056 uid 5028,0 7904 8057 ps "OnEdgeStrategy" … … 7934 8087 ) 7935 8088 ) 7936 *23 3(CptPort8089 *236 (CptPort 7937 8090 uid 5032,0 7938 8091 ps "OnEdgeStrategy" … … 7970 8123 ) 7971 8124 ) 7972 *23 4(CptPort8125 *237 (CptPort 7973 8126 uid 5036,0 7974 8127 ps "OnEdgeStrategy" … … 8006 8159 ) 8007 8160 ) 8008 *23 5(CptPort8161 *238 (CptPort 8009 8162 uid 5040,0 8010 8163 ps "OnEdgeStrategy" … … 8042 8195 ) 8043 8196 ) 8044 *23 6(CptPort8197 *239 (CptPort 8045 8198 uid 5044,0 8046 8199 ps "OnEdgeStrategy" … … 8079 8232 ) 8080 8233 ) 8081 *2 37(CptPort8234 *240 (CptPort 8082 8235 uid 5048,0 8083 8236 ps "OnEdgeStrategy" … … 8114 8267 ) 8115 8268 ) 8116 *2 38(CptPort8269 *241 (CptPort 8117 8270 uid 5052,0 8118 8271 ps "OnEdgeStrategy" … … 8149 8302 ) 8150 8303 ) 8151 *2 39(CptPort8304 *242 (CptPort 8152 8305 uid 5056,0 8153 8306 ps "OnEdgeStrategy" … … 8184 8337 ) 8185 8338 ) 8186 *24 0(CptPort8339 *243 (CptPort 8187 8340 uid 5060,0 8188 8341 ps "OnEdgeStrategy" … … 8219 8372 ) 8220 8373 ) 8221 *24 1(CptPort8374 *244 (CptPort 8222 8375 uid 5064,0 8223 8376 ps "OnEdgeStrategy" … … 8253 8406 ) 8254 8407 ) 8255 *24 2(CptPort8408 *245 (CptPort 8256 8409 uid 5068,0 8257 8410 ps "OnEdgeStrategy" … … 8288 8441 ) 8289 8442 ) 8290 *24 3(CptPort8443 *246 (CptPort 8291 8444 uid 5995,0 8292 8445 ps "OnEdgeStrategy" … … 8324 8477 ) 8325 8478 ) 8326 *24 4(CptPort8479 *247 (CptPort 8327 8480 uid 10184,0 8328 8481 ps "OnEdgeStrategy" … … 8364 8517 ) 8365 8518 ) 8366 *24 5(CptPort8519 *248 (CptPort 8367 8520 uid 10188,0 8368 8521 ps "OnEdgeStrategy" … … 8421 8574 stg "VerticalLayoutStrategy" 8422 8575 textVec [ 8423 *24 6(Text8576 *249 (Text 8424 8577 uid 5075,0 8425 8578 va (VaSet … … 8431 8584 tm "BdLibraryNameMgr" 8432 8585 ) 8433 *2 47(Text8586 *250 (Text 8434 8587 uid 5076,0 8435 8588 va (VaSet … … 8441 8594 tm "CptNameMgr" 8442 8595 ) 8443 *2 48(Text8596 *251 (Text 8444 8597 uid 5077,0 8445 8598 va (VaSet … … 8487 8640 archFileType "UNKNOWN" 8488 8641 ) 8489 *2 49(Net8642 *252 (Net 8490 8643 uid 5088,0 8491 8644 decl (Decl … … 8501 8654 font "Courier New,8,0" 8502 8655 ) 8503 xt "-102000,64800,-70000,65600" 8504 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 8505 ) 8506 ) 8507 *250 (Net 8656 xt "-102000,65600,-70000,66400" 8657 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 8658 " 8659 ) 8660 ) 8661 *253 (Net 8508 8662 uid 5096,0 8509 8663 decl (Decl … … 8518 8672 font "Courier New,8,0" 8519 8673 ) 8520 xt "-102000,67200,-79500,68000" 8521 st "SIGNAL config_data_valid : std_logic" 8522 ) 8523 ) 8524 *251 (Net 8674 xt "-102000,68000,-79500,68800" 8675 st "SIGNAL config_data_valid : std_logic 8676 " 8677 ) 8678 ) 8679 *254 (Net 8525 8680 uid 5104,0 8526 8681 decl (Decl … … 8535 8690 font "Courier New,8,0" 8536 8691 ) 8537 xt "-102000,65600,-79500,66400" 8538 st "SIGNAL config_busy : std_logic" 8539 ) 8540 ) 8541 *252 (Net 8692 xt "-102000,66400,-79500,67200" 8693 st "SIGNAL config_busy : std_logic 8694 " 8695 ) 8696 ) 8697 *255 (Net 8542 8698 uid 5112,0 8543 8699 decl (Decl … … 8553 8709 font "Courier New,8,0" 8554 8710 ) 8555 xt "-102000,66400,-69500,67200" 8556 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 8557 ) 8558 ) 8559 *253 (Net 8711 xt "-102000,67200,-69500,68000" 8712 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 8713 " 8714 ) 8715 ) 8716 *256 (Net 8560 8717 uid 5120,0 8561 8718 decl (Decl … … 8570 8727 font "Courier New,8,0" 8571 8728 ) 8572 xt "-102000,80000,-79500,80800" 8573 st "SIGNAL config_wr_en : std_logic" 8574 ) 8575 ) 8576 *254 (Net 8729 xt "-102000,80800,-79500,81600" 8730 st "SIGNAL config_wr_en : std_logic 8731 " 8732 ) 8733 ) 8734 *257 (Net 8577 8735 uid 5128,0 8578 8736 decl (Decl … … 8587 8745 font "Courier New,8,0" 8588 8746 ) 8589 xt "-102000,68000,-79500,68800" 8590 st "SIGNAL config_rd_en : std_logic" 8591 ) 8592 ) 8593 *255 (Net 8747 xt "-102000,68800,-79500,69600" 8748 st "SIGNAL config_rd_en : std_logic 8749 " 8750 ) 8751 ) 8752 *258 (Net 8594 8753 uid 5144,0 8595 8754 decl (Decl … … 8604 8763 font "Courier New,8,0" 8605 8764 ) 8606 xt "-102000,80800,-77000,81600" 8607 st "SIGNAL dac_array : dac_array_type" 8608 ) 8609 ) 8610 *256 (Net 8765 xt "-102000,81600,-77000,82400" 8766 st "SIGNAL dac_array : dac_array_type 8767 " 8768 ) 8769 ) 8770 *259 (Net 8611 8771 uid 5194,0 8612 8772 decl (Decl … … 8621 8781 font "Courier New,8,0" 8622 8782 ) 8623 xt "-102000,75200,-79500,76000" 8624 st "SIGNAL config_start_cm : std_logic" 8625 ) 8626 ) 8627 *257 (Net 8783 xt "-102000,76000,-79500,76800" 8784 st "SIGNAL config_start_cm : std_logic 8785 " 8786 ) 8787 ) 8788 *260 (Net 8628 8789 uid 5196,0 8629 8790 decl (Decl … … 8638 8799 font "Courier New,8,0" 8639 8800 ) 8640 xt "-102000,69600,-79500,70400" 8641 st "SIGNAL config_ready_cm : std_logic" 8642 ) 8643 ) 8644 *258 (Net 8801 xt "-102000,70400,-79500,71200" 8802 st "SIGNAL config_ready_cm : std_logic 8803 " 8804 ) 8805 ) 8806 *261 (Net 8645 8807 uid 5220,0 8646 8808 decl (Decl … … 8658 8820 font "Courier New,8,0" 8659 8821 ) 8660 xt "-102000,44400,-56000,45200" 8661 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8662 ) 8663 ) 8664 *259 (Net 8822 xt "-102000,45200,-56000,46000" 8823 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 8824 " 8825 ) 8826 ) 8827 *262 (Net 8665 8828 uid 5472,0 8666 8829 decl (Decl … … 8675 8838 font "Courier New,8,0" 8676 8839 ) 8677 xt "-102000,111200,-79500,112000" 8678 st "SIGNAL sensor_ready : std_logic" 8679 ) 8680 ) 8681 *260 (Net 8840 xt "-102000,112000,-79500,112800" 8841 st "SIGNAL sensor_ready : std_logic 8842 " 8843 ) 8844 ) 8845 *263 (Net 8682 8846 uid 5478,0 8683 8847 decl (Decl … … 8692 8856 font "Courier New,8,0" 8693 8857 ) 8694 xt "-102000,110400,-75500,111200" 8695 st "SIGNAL sensor_array : sensor_array_type" 8696 ) 8697 ) 8698 *261 (Net 8858 xt "-102000,111200,-75500,112000" 8859 st "SIGNAL sensor_array : sensor_array_type 8860 " 8861 ) 8862 ) 8863 *264 (Net 8699 8864 uid 5588,0 8700 8865 decl (Decl … … 8709 8874 font "Courier New,8,0" 8710 8875 ) 8711 xt "-102000,70400,-79500,71200" 8712 st "SIGNAL config_ready_spi : std_logic" 8713 ) 8714 ) 8715 *262 (Net 8876 xt "-102000,71200,-79500,72000" 8877 st "SIGNAL config_ready_spi : std_logic 8878 " 8879 ) 8880 ) 8881 *265 (Net 8716 8882 uid 5632,0 8717 8883 lang 10 … … 8728 8894 font "Courier New,8,0" 8729 8895 ) 8730 xt "-102000,61600,-70000,62400" 8731 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 8732 ) 8733 ) 8734 *263 (Net 8896 xt "-102000,62400,-70000,63200" 8897 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 8898 " 8899 ) 8900 ) 8901 *266 (Net 8735 8902 uid 5640,0 8736 8903 decl (Decl … … 8745 8912 font "Courier New,8,0" 8746 8913 ) 8747 xt "-102000,60800,-74500,61600" 8748 st "SIGNAL adc_data_array_int : adc_data_array_type" 8749 ) 8750 ) 8751 *264 (SaComponent 8914 xt "-102000,61600,-74500,62400" 8915 st "SIGNAL adc_data_array_int : adc_data_array_type 8916 " 8917 ) 8918 ) 8919 *267 (SaComponent 8752 8920 uid 5678,0 8753 8921 optionalChildren [ 8754 *26 5(CptPort8922 *268 (CptPort 8755 8923 uid 5658,0 8756 8924 ps "OnEdgeStrategy" … … 8787 8955 ) 8788 8956 ) 8789 *26 6(CptPort8957 *269 (CptPort 8790 8958 uid 5662,0 8791 8959 ps "OnEdgeStrategy" … … 8824 8992 ) 8825 8993 ) 8826 *2 67(CptPort8994 *270 (CptPort 8827 8995 uid 5666,0 8828 8996 ps "OnEdgeStrategy" … … 8863 9031 ) 8864 9032 ) 8865 *2 68(CptPort9033 *271 (CptPort 8866 9034 uid 5670,0 8867 9035 ps "OnEdgeStrategy" … … 8899 9067 ) 8900 9068 ) 8901 *2 69(CptPort9069 *272 (CptPort 8902 9070 uid 5674,0 8903 9071 ps "OnEdgeStrategy" … … 8952 9120 stg "VerticalLayoutStrategy" 8953 9121 textVec [ 8954 *27 0(Text9122 *273 (Text 8955 9123 uid 5681,0 8956 9124 va (VaSet … … 8962 9130 tm "BdLibraryNameMgr" 8963 9131 ) 8964 *27 1(Text9132 *274 (Text 8965 9133 uid 5682,0 8966 9134 va (VaSet … … 8972 9140 tm "CptNameMgr" 8973 9141 ) 8974 *27 2(Text9142 *275 (Text 8975 9143 uid 5683,0 8976 9144 va (VaSet … … 9021 9189 archFileType "UNKNOWN" 9022 9190 ) 9023 *27 3(Net9191 *276 (Net 9024 9192 uid 5743,0 9025 9193 decl (Decl … … 9035 9203 font "Courier New,8,0" 9036 9204 ) 9037 xt "-102000,76000,-58500,76800" 9038 st "SIGNAL config_start_spi : std_logic := '0'" 9039 ) 9040 ) 9041 *274 (SaComponent 9205 xt "-102000,76800,-58500,77600" 9206 st "SIGNAL config_start_spi : std_logic := '0' 9207 " 9208 ) 9209 ) 9210 *277 (SaComponent 9042 9211 uid 5793,0 9043 9212 optionalChildren [ 9044 *27 5(CptPort9213 *278 (CptPort 9045 9214 uid 5753,0 9046 9215 ps "OnEdgeStrategy" … … 9077 9246 ) 9078 9247 ) 9079 *27 6(CptPort9248 *279 (CptPort 9080 9249 uid 5761,0 9081 9250 ps "OnEdgeStrategy" … … 9112 9281 ) 9113 9282 ) 9114 *2 77(CptPort9283 *280 (CptPort 9115 9284 uid 5765,0 9116 9285 ps "OnEdgeStrategy" … … 9148 9317 ) 9149 9318 ) 9150 *2 78(CptPort9319 *281 (CptPort 9151 9320 uid 5769,0 9152 9321 ps "OnEdgeStrategy" … … 9183 9352 ) 9184 9353 ) 9185 *2 79(CptPort9354 *282 (CptPort 9186 9355 uid 5773,0 9187 9356 ps "OnEdgeStrategy" … … 9219 9388 ) 9220 9389 ) 9221 *28 0(CptPort9390 *283 (CptPort 9222 9391 uid 5777,0 9223 9392 ps "OnEdgeStrategy" … … 9255 9424 ) 9256 9425 ) 9257 *28 1(CptPort9426 *284 (CptPort 9258 9427 uid 5781,0 9259 9428 ps "OnEdgeStrategy" … … 9290 9459 ) 9291 9460 ) 9292 *28 2(CptPort9461 *285 (CptPort 9293 9462 uid 5785,0 9294 9463 ps "OnEdgeStrategy" … … 9326 9495 ) 9327 9496 ) 9328 *28 3(CptPort9497 *286 (CptPort 9329 9498 uid 5789,0 9330 9499 ps "OnEdgeStrategy" … … 9362 9531 ) 9363 9532 ) 9364 *28 4(CptPort9533 *287 (CptPort 9365 9534 uid 5986,0 9366 9535 ps "OnEdgeStrategy" … … 9399 9568 ) 9400 9569 ) 9401 *28 5(CptPort9570 *288 (CptPort 9402 9571 uid 6154,0 9403 9572 ps "OnEdgeStrategy" … … 9435 9604 ) 9436 9605 ) 9437 *28 6(CptPort9606 *289 (CptPort 9438 9607 uid 6317,0 9439 9608 ps "OnEdgeStrategy" … … 9489 9658 stg "VerticalLayoutStrategy" 9490 9659 textVec [ 9491 *2 87(Text9660 *290 (Text 9492 9661 uid 5796,0 9493 9662 va (VaSet … … 9499 9668 tm "BdLibraryNameMgr" 9500 9669 ) 9501 *2 88(Text9670 *291 (Text 9502 9671 uid 5797,0 9503 9672 va (VaSet … … 9509 9678 tm "CptNameMgr" 9510 9679 ) 9511 *2 89(Text9680 *292 (Text 9512 9681 uid 5798,0 9513 9682 va (VaSet … … 9555 9724 archFileType "UNKNOWN" 9556 9725 ) 9557 *29 0(Net9726 *293 (Net 9558 9727 uid 5811,0 9559 9728 decl (Decl … … 9568 9737 font "Courier New,8,0" 9569 9738 ) 9570 xt "-102000,48400,-83500,49200" 9571 st "sclk : std_logic" 9572 ) 9573 ) 9574 *291 (Net 9739 xt "-102000,49200,-83500,50000" 9740 st "sclk : std_logic 9741 " 9742 ) 9743 ) 9744 *294 (Net 9575 9745 uid 5819,0 9576 9746 decl (Decl … … 9587 9757 font "Courier New,8,0" 9588 9758 ) 9589 xt "-102000,55600,-83500,56400" 9590 st "sio : std_logic" 9591 ) 9592 ) 9593 *292 (Net 9759 xt "-102000,56400,-83500,57200" 9760 st "sio : std_logic 9761 " 9762 ) 9763 ) 9764 *295 (Net 9594 9765 uid 5827,0 9595 9766 decl (Decl … … 9604 9775 font "Courier New,8,0" 9605 9776 ) 9606 xt "-102000,40400,-83500,41200" 9607 st "dac_cs : std_logic" 9608 ) 9609 ) 9610 *293 (Net 9777 xt "-102000,41200,-83500,42000" 9778 st "dac_cs : std_logic 9779 " 9780 ) 9781 ) 9782 *296 (Net 9611 9783 uid 5835,0 9612 9784 decl (Decl … … 9622 9794 font "Courier New,8,0" 9623 9795 ) 9624 xt "-102000,49200,-73500,50000" 9625 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 9626 ) 9627 ) 9628 *294 (PortIoOut 9796 xt "-102000,50000,-73500,50800" 9797 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 9798 " 9799 ) 9800 ) 9801 *297 (PortIoOut 9629 9802 uid 5843,0 9630 9803 shape (CompositeShape … … 9671 9844 ) 9672 9845 ) 9673 *29 5(PortIoInOut9846 *298 (PortIoInOut 9674 9847 uid 5849,0 9675 9848 shape (CompositeShape … … 9716 9889 ) 9717 9890 ) 9718 *29 6(PortIoOut9891 *299 (PortIoOut 9719 9892 uid 5855,0 9720 9893 shape (CompositeShape … … 9761 9934 ) 9762 9935 ) 9763 * 297(PortIoOut9936 *300 (PortIoOut 9764 9937 uid 5861,0 9765 9938 shape (CompositeShape … … 9806 9979 ) 9807 9980 ) 9808 * 298(Net9981 *301 (Net 9809 9982 uid 5948,0 9810 9983 decl (Decl … … 9820 9993 font "Courier New,8,0" 9821 9994 ) 9822 xt "-102000,96000,-58500,96800" 9823 st "SIGNAL new_config : std_logic := '0'" 9824 ) 9825 ) 9826 *299 (Net 9995 xt "-102000,96800,-58500,97600" 9996 st "SIGNAL new_config : std_logic := '0' 9997 " 9998 ) 9999 ) 10000 *302 (Net 9827 10001 uid 5960,0 9828 10002 decl (Decl … … 9837 10011 font "Courier New,8,0" 9838 10012 ) 9839 xt "-102000,76800,-79500,77600" 9840 st "SIGNAL config_started : std_logic" 9841 ) 9842 ) 9843 *300 (Net 10013 xt "-102000,77600,-79500,78400" 10014 st "SIGNAL config_started : std_logic 10015 " 10016 ) 10017 ) 10018 *303 (Net 9844 10019 uid 6012,0 9845 10020 decl (Decl … … 9855 10030 font "Courier New,8,0" 9856 10031 ) 9857 xt "-102000,79200,-58500,80000" 9858 st "SIGNAL config_started_spi : std_logic := '0'" 9859 ) 9860 ) 9861 *301 (Net 10032 xt "-102000,80000,-58500,80800" 10033 st "SIGNAL config_started_spi : std_logic := '0' 10034 " 10035 ) 10036 ) 10037 *304 (Net 9862 10038 uid 6014,0 9863 10039 decl (Decl … … 9873 10049 font "Courier New,8,0" 9874 10050 ) 9875 xt "-102000,77600,-58500,78400" 9876 st "SIGNAL config_started_cu : std_logic := '0'" 9877 ) 9878 ) 9879 *302 (Net 10051 xt "-102000,78400,-58500,79200" 10052 st "SIGNAL config_started_cu : std_logic := '0' 10053 " 10054 ) 10055 ) 10056 *305 (Net 9880 10057 uid 6016,0 9881 10058 decl (Decl … … 9890 10067 font "Courier New,8,0" 9891 10068 ) 9892 xt "-102000,78400,-79500,79200" 9893 st "SIGNAL config_started_mm : std_logic" 9894 ) 9895 ) 9896 *303 (Net 10069 xt "-102000,79200,-79500,80000" 10070 st "SIGNAL config_started_mm : std_logic 10071 " 10072 ) 10073 ) 10074 *306 (Net 9897 10075 uid 6158,0 9898 10076 decl (Decl … … 9908 10086 font "Courier New,8,0" 9909 10087 ) 9910 xt "-102000,45200,-62000,46000" 9911 st "mosi : std_logic := '0'" 9912 ) 9913 ) 9914 *304 (PortIoOut 10088 xt "-102000,46000,-62000,46800" 10089 st "mosi : std_logic := '0' 10090 " 10091 ) 10092 ) 10093 *307 (PortIoOut 9915 10094 uid 6166,0 9916 10095 shape (CompositeShape … … 9957 10136 ) 9958 10137 ) 9959 *30 5(Net10138 *308 (Net 9960 10139 uid 6360,0 9961 10140 decl (Decl … … 9973 10152 font "Courier New,8,0" 9974 10153 ) 9975 xt "-102000,41200,-48500,42000" 9976 st "denable : std_logic := '0' -- default domino wave off" 9977 ) 9978 ) 9979 *306 (PortIoOut 10154 xt "-102000,42000,-48500,42800" 10155 st "denable : std_logic := '0' -- default domino wave off 10156 " 10157 ) 10158 ) 10159 *309 (PortIoOut 9980 10160 uid 6368,0 9981 10161 shape (CompositeShape … … 9990 10170 sl 0 9991 10171 ro 270 9992 xt "1 54500,74625,156000,75375"10172 xt "169500,73625,171000,74375" 9993 10173 ) 9994 10174 (Line … … 9996 10176 sl 0 9997 10177 ro 270 9998 xt "1 54000,75000,154500,75000"9999 pts [ 10000 "1 54000,75000"10001 "1 54500,75000"10178 xt "169000,74000,169500,74000" 10179 pts [ 10180 "169000,74000" 10181 "169500,74000" 10002 10182 ] 10003 10183 ) … … 10014 10194 va (VaSet 10015 10195 ) 10016 xt "1 57000,74500,160000,75500"10196 xt "172000,73500,175000,74500" 10017 10197 st "denable" 10018 blo "1 57000,75300"10198 blo "172000,74300" 10019 10199 tm "WireNameMgr" 10020 10200 ) 10021 10201 ) 10022 10202 ) 10023 *3 07(Net10203 *310 (Net 10024 10204 uid 6450,0 10025 10205 decl (Decl … … 10035 10215 font "Courier New,8,0" 10036 10216 ) 10037 xt "-102000,95200,-58500,96000" 10038 st "SIGNAL dwrite_enable : std_logic := '1'" 10039 ) 10040 ) 10041 *308 (MWC 10217 xt "-102000,96000,-58500,96800" 10218 st "SIGNAL dwrite_enable : std_logic := '1' 10219 " 10220 ) 10221 ) 10222 *311 (MWC 10042 10223 uid 6529,0 10043 10224 optionalChildren [ 10044 *3 09(CptPort10225 *312 (CptPort 10045 10226 uid 6501,0 10046 10227 optionalChildren [ 10047 *31 0(Line10228 *313 (Line 10048 10229 uid 6505,0 10049 10230 layer 5 … … 10058 10239 ] 10059 10240 ) 10060 *31 1(Property10241 *314 (Property 10061 10242 uid 6506,0 10062 10243 pclass "_MW_GEOM_" … … 10103 10284 ) 10104 10285 ) 10105 *31 2(CptPort10286 *315 (CptPort 10106 10287 uid 6507,0 10107 10288 optionalChildren [ 10108 *31 3(Line10289 *316 (Line 10109 10290 uid 6511,0 10110 10291 layer 5 … … 10158 10339 ) 10159 10340 ) 10160 *31 4(CptPort10341 *317 (CptPort 10161 10342 uid 6512,0 10162 10343 optionalChildren [ 10163 *31 5(Line10344 *318 (Line 10164 10345 uid 6516,0 10165 10346 layer 5 … … 10213 10394 ) 10214 10395 ) 10215 *31 6(CommentGraphic10396 *319 (CommentGraphic 10216 10397 uid 6517,0 10217 10398 optionalChildren [ 10218 *3 17(Property10399 *320 (Property 10219 10400 uid 6519,0 10220 10401 pclass "_MW_GEOM_" … … 10240 10421 oxt "11000,10000,11000,10000" 10241 10422 ) 10242 *3 18(CommentGraphic10423 *321 (CommentGraphic 10243 10424 uid 6520,0 10244 10425 optionalChildren [ 10245 *3 19(Property10426 *322 (Property 10246 10427 uid 6522,0 10247 10428 pclass "_MW_GEOM_" … … 10267 10448 oxt "11000,6000,11000,6000" 10268 10449 ) 10269 *32 0(Grouping10450 *323 (Grouping 10270 10451 uid 6523,0 10271 10452 optionalChildren [ 10272 *32 1(CommentGraphic10453 *324 (CommentGraphic 10273 10454 uid 6525,0 10274 10455 shape (PolyLine2D … … 10291 10472 oxt "9000,6000,11000,10000" 10292 10473 ) 10293 *32 2(CommentGraphic10474 *325 (CommentGraphic 10294 10475 uid 6527,0 10295 10476 shape (Arc2D … … 10344 10525 stg "VerticalLayoutStrategy" 10345 10526 textVec [ 10346 *32 3(Text10527 *326 (Text 10347 10528 uid 6532,0 10348 10529 va (VaSet … … 10354 10535 blo "3500,59300" 10355 10536 ) 10356 *32 4(Text10537 *327 (Text 10357 10538 uid 6533,0 10358 10539 va (VaSet … … 10363 10544 blo "3500,60300" 10364 10545 ) 10365 *32 5(Text10546 *328 (Text 10366 10547 uid 6534,0 10367 10548 va (VaSet … … 10408 10589 ) 10409 10590 ) 10410 *32 6(Net10591 *329 (Net 10411 10592 uid 6544,0 10412 10593 decl (Decl … … 10422 10603 font "Courier New,8,0" 10423 10604 ) 10424 xt "-102000,94400,-58500,95200" 10425 st "SIGNAL dwrite : std_logic := '1'" 10426 ) 10427 ) 10428 *327 (SaComponent 10605 xt "-102000,95200,-58500,96000" 10606 st "SIGNAL dwrite : std_logic := '1' 10607 " 10608 ) 10609 ) 10610 *330 (SaComponent 10429 10611 uid 8277,0 10430 10612 optionalChildren [ 10431 *3 28(CptPort10613 *331 (CptPort 10432 10614 uid 8246,0 10433 10615 ps "OnEdgeStrategy" … … 10466 10648 ) 10467 10649 ) 10468 *3 29(CptPort10650 *332 (CptPort 10469 10651 uid 8250,0 10470 10652 ps "OnEdgeStrategy" … … 10504 10686 ) 10505 10687 ) 10506 *33 0(CptPort10688 *333 (CptPort 10507 10689 uid 8254,0 10508 10690 ps "OnEdgeStrategy" … … 10542 10724 ) 10543 10725 ) 10544 *33 1(CptPort10726 *334 (CptPort 10545 10727 uid 8258,0 10546 10728 ps "OnEdgeStrategy" … … 10580 10762 ) 10581 10763 ) 10582 *33 2(CptPort10764 *335 (CptPort 10583 10765 uid 8262,0 10584 10766 ps "OnEdgeStrategy" … … 10618 10800 ) 10619 10801 ) 10620 *33 3(CptPort10802 *336 (CptPort 10621 10803 uid 8266,0 10622 10804 ps "OnEdgeStrategy" … … 10657 10839 ) 10658 10840 ) 10659 *33 4(CptPort10841 *337 (CptPort 10660 10842 uid 8270,0 10661 10843 ps "OnEdgeStrategy" … … 10714 10896 stg "VerticalLayoutStrategy" 10715 10897 textVec [ 10716 *33 5(Text10898 *338 (Text 10717 10899 uid 8280,0 10718 10900 va (VaSet … … 10724 10906 tm "BdLibraryNameMgr" 10725 10907 ) 10726 *33 6(Text10908 *339 (Text 10727 10909 uid 8281,0 10728 10910 va (VaSet … … 10734 10916 tm "CptNameMgr" 10735 10917 ) 10736 *3 37(Text10918 *340 (Text 10737 10919 uid 8282,0 10738 10920 va (VaSet … … 10782 10964 archFileType "UNKNOWN" 10783 10965 ) 10784 *3 38(Net10966 *341 (Net 10785 10967 uid 8414,0 10786 10968 lang 2 … … 10796 10978 font "Courier New,8,0" 10797 10979 ) 10798 xt "-102000,120000,-79500,120800" 10799 st "SIGNAL wiz_ack : std_logic" 10800 ) 10801 ) 10802 *339 (Net 10980 xt "-102000,120800,-79500,121600" 10981 st "SIGNAL wiz_ack : std_logic 10982 " 10983 ) 10984 ) 10985 *342 (Net 10803 10986 uid 8508,0 10804 10987 decl (Decl … … 10815 10998 font "Courier New,8,0" 10816 10999 ) 10817 xt "-102000,84000,-52500,84800" 10818 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0')" 10819 ) 10820 ) 10821 *340 (Net 11000 xt "-102000,84800,-52500,85600" 11001 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') 11002 " 11003 ) 11004 ) 11005 *343 (Net 10822 11006 uid 8516,0 10823 11007 decl (Decl … … 10832 11016 font "Courier New,8,0" 10833 11017 ) 10834 xt "-102000,84800,-79500,85600" 10835 st "SIGNAL drs_address_mode : std_logic" 10836 ) 10837 ) 10838 *341 (MWC 11018 xt "-102000,85600,-79500,86400" 11019 st "SIGNAL drs_address_mode : std_logic 11020 " 11021 ) 11022 ) 11023 *344 (MWC 10839 11024 uid 8562,0 10840 11025 optionalChildren [ 10841 *34 2(CptPort11026 *345 (CptPort 10842 11027 uid 8524,0 10843 11028 optionalChildren [ 10844 *34 3(Line11029 *346 (Line 10845 11030 uid 8528,0 10846 11031 layer 5 … … 10906 11091 ) 10907 11092 ) 10908 *34 4(CptPort11093 *347 (CptPort 10909 11094 uid 8529,0 10910 11095 optionalChildren [ 10911 *34 5(Line11096 *348 (Line 10912 11097 uid 8533,0 10913 11098 layer 5 … … 10923 11108 ] 10924 11109 ) 10925 *34 6(Property11110 *349 (Property 10926 11111 uid 8534,0 10927 11112 pclass "_MW_GEOM_" … … 10978 11163 ) 10979 11164 ) 10980 *3 47(CptPort11165 *350 (CptPort 10981 11166 uid 8535,0 10982 11167 optionalChildren [ 10983 *3 48(Line11168 *351 (Line 10984 11169 uid 8539,0 10985 11170 layer 5 … … 11045 11230 ) 11046 11231 ) 11047 *3 49(CptPort11232 *352 (CptPort 11048 11233 uid 8540,0 11049 11234 optionalChildren [ 11050 *35 0(Line11235 *353 (Line 11051 11236 uid 8544,0 11052 11237 layer 5 … … 11108 11293 ) 11109 11294 ) 11110 *35 1(CommentGraphic11295 *354 (CommentGraphic 11111 11296 uid 8545,0 11112 11297 shape (CustomPolygon … … 11131 11316 oxt "7000,7000,9000,11000" 11132 11317 ) 11133 *35 2(CommentGraphic11318 *355 (CommentGraphic 11134 11319 uid 8547,0 11135 11320 optionalChildren [ 11136 *35 3(Property11321 *356 (Property 11137 11322 uid 8549,0 11138 11323 pclass "_MW_GEOM_" … … 11158 11343 oxt "9000,7000,9000,7000" 11159 11344 ) 11160 *35 4(CommentGraphic11345 *357 (CommentGraphic 11161 11346 uid 8550,0 11162 11347 optionalChildren [ 11163 *35 5(Property11348 *358 (Property 11164 11349 uid 8552,0 11165 11350 pclass "_MW_GEOM_" … … 11185 11370 oxt "9000,11000,9000,11000" 11186 11371 ) 11187 *35 6(CommentText11372 *359 (CommentText 11188 11373 uid 8553,0 11189 11374 shape (Rectangle … … 11216 11401 ) 11217 11402 ) 11218 *3 57(CommentText11403 *360 (CommentText 11219 11404 uid 8556,0 11220 11405 shape (Rectangle … … 11248 11433 ) 11249 11434 ) 11250 *3 58(CommentText11435 *361 (CommentText 11251 11436 uid 8559,0 11252 11437 shape (Rectangle … … 11299 11484 stg "VerticalLayoutStrategy" 11300 11485 textVec [ 11301 *3 59(Text11486 *362 (Text 11302 11487 uid 8565,0 11303 11488 va (VaSet … … 11309 11494 blo "-30650,102900" 11310 11495 ) 11311 *36 0(Text11496 *363 (Text 11312 11497 uid 8566,0 11313 11498 va (VaSet … … 11318 11503 blo "-30650,103900" 11319 11504 ) 11320 *36 1(Text11505 *364 (Text 11321 11506 uid 8567,0 11322 11507 va (VaSet … … 11364 11549 ) 11365 11550 ) 11366 *36 2(Net11551 *365 (Net 11367 11552 uid 8583,0 11368 11553 decl (Decl … … 11379 11564 font "Courier New,8,0" 11380 11565 ) 11381 xt "-102000,85600,-52500,86400" 11382 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0')" 11383 ) 11384 ) 11385 *363 (MWC 11566 xt "-102000,86400,-52500,87200" 11567 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') 11568 " 11569 ) 11570 ) 11571 *366 (MWC 11386 11572 uid 8721,0 11387 11573 optionalChildren [ 11388 *36 4(CptPort11574 *367 (CptPort 11389 11575 uid 8693,0 11390 11576 optionalChildren [ 11391 *36 5(Line11577 *368 (Line 11392 11578 uid 8697,0 11393 11579 layer 5 … … 11402 11588 ] 11403 11589 ) 11404 *36 6(Property11590 *369 (Property 11405 11591 uid 8698,0 11406 11592 pclass "_MW_GEOM_" … … 11446 11632 ) 11447 11633 ) 11448 *3 67(CptPort11634 *370 (CptPort 11449 11635 uid 8699,0 11450 11636 optionalChildren [ 11451 *3 68(Line11637 *371 (Line 11452 11638 uid 8703,0 11453 11639 layer 5 … … 11500 11686 ) 11501 11687 ) 11502 *3 69(CptPort11688 *372 (CptPort 11503 11689 uid 8704,0 11504 11690 optionalChildren [ 11505 *37 0(Line11691 *373 (Line 11506 11692 uid 8708,0 11507 11693 layer 5 … … 11554 11740 ) 11555 11741 ) 11556 *37 1(CommentGraphic11742 *374 (CommentGraphic 11557 11743 uid 8709,0 11558 11744 optionalChildren [ 11559 *37 2(Property11745 *375 (Property 11560 11746 uid 8711,0 11561 11747 pclass "_MW_GEOM_" … … 11581 11767 oxt "11000,6000,11000,6000" 11582 11768 ) 11583 *37 3(CommentGraphic11769 *376 (CommentGraphic 11584 11770 uid 8712,0 11585 11771 optionalChildren [ 11586 *37 4(Property11772 *377 (Property 11587 11773 uid 8714,0 11588 11774 pclass "_MW_GEOM_" … … 11608 11794 oxt "11000,10000,11000,10000" 11609 11795 ) 11610 *37 5(Grouping11796 *378 (Grouping 11611 11797 uid 8715,0 11612 11798 optionalChildren [ 11613 *37 6(CommentGraphic11799 *379 (CommentGraphic 11614 11800 uid 8717,0 11615 11801 shape (PolyLine2D … … 11632 11818 oxt "9000,6000,11000,10000" 11633 11819 ) 11634 *3 77(CommentGraphic11820 *380 (CommentGraphic 11635 11821 uid 8719,0 11636 11822 shape (Arc2D … … 11685 11871 stg "VerticalLayoutStrategy" 11686 11872 textVec [ 11687 *3 78(Text11873 *381 (Text 11688 11874 uid 8724,0 11689 11875 va (VaSet … … 11695 11881 blo "-11500,113300" 11696 11882 ) 11697 *3 79(Text11883 *382 (Text 11698 11884 uid 8725,0 11699 11885 va (VaSet … … 11704 11890 blo "-11500,114300" 11705 11891 ) 11706 *38 0(Text11892 *383 (Text 11707 11893 uid 8726,0 11708 11894 va (VaSet … … 11749 11935 ) 11750 11936 ) 11751 *38 1(Net11937 *384 (Net 11752 11938 uid 8730,0 11753 11939 decl (Decl … … 11762 11948 font "Courier New,8,0" 11763 11949 ) 11764 xt "-102000,108800,-79500,109600" 11765 st "SIGNAL sclk1 : std_logic" 11766 ) 11767 ) 11768 *382 (Net 11950 xt "-102000,109600,-79500,110400" 11951 st "SIGNAL sclk1 : std_logic 11952 " 11953 ) 11954 ) 11955 *385 (Net 11769 11956 uid 8746,0 11770 11957 decl (Decl … … 11779 11966 font "Courier New,8,0" 11780 11967 ) 11781 xt "-102000,109600,-79500,110400" 11782 st "SIGNAL sclk_enable : std_logic" 11783 ) 11784 ) 11785 *383 (Net 11968 xt "-102000,110400,-79500,111200" 11969 st "SIGNAL sclk_enable : std_logic 11970 " 11971 ) 11972 ) 11973 *386 (Net 11786 11974 uid 9004,0 11787 11975 decl (Decl … … 11797 11985 font "Courier New,8,0" 11798 11986 ) 11799 xt "-102000,37200,-62000,38000" 11800 st "adc_clk_en : std_logic := '0'" 11801 ) 11802 ) 11803 *384 (PortIoOut 11987 xt "-102000,38000,-62000,38800" 11988 st "adc_clk_en : std_logic := '0' 11989 " 11990 ) 11991 ) 11992 *387 (PortIoOut 11804 11993 uid 9012,0 11805 11994 shape (CompositeShape … … 11846 12035 ) 11847 12036 ) 11848 *38 5(SaComponent12037 *388 (SaComponent 11849 12038 uid 9175,0 11850 12039 optionalChildren [ 11851 *38 6(CptPort12040 *389 (CptPort 11852 12041 uid 9120,0 11853 12042 ps "OnEdgeStrategy" … … 11886 12075 ) 11887 12076 ) 11888 *3 87(CptPort12077 *390 (CptPort 11889 12078 uid 9124,0 11890 12079 ps "OnEdgeStrategy" … … 11923 12112 ) 11924 12113 ) 11925 *3 88(CptPort12114 *391 (CptPort 11926 12115 uid 9128,0 11927 12116 ps "OnEdgeStrategy" … … 11958 12147 ) 11959 12148 ) 11960 *3 89(CptPort12149 *392 (CptPort 11961 12150 uid 9132,0 11962 12151 ps "OnEdgeStrategy" … … 12008 12197 ) 12009 12198 ) 12010 *39 0(CptPort12199 *393 (CptPort 12011 12200 uid 9137,0 12012 12201 ps "OnEdgeStrategy" … … 12059 12248 ) 12060 12249 ) 12061 *39 1(CptPort12250 *394 (CptPort 12062 12251 uid 9142,0 12063 12252 ps "OnEdgeStrategy" … … 12110 12299 ) 12111 12300 ) 12112 *39 2(CptPort12301 *395 (CptPort 12113 12302 uid 9147,0 12114 12303 ps "OnEdgeStrategy" … … 12149 12338 ) 12150 12339 ) 12151 *39 3(CptPort12340 *396 (CptPort 12152 12341 uid 9155,0 12153 12342 ps "OnEdgeStrategy" … … 12186 12375 ) 12187 12376 ) 12188 *39 4(CptPort12377 *397 (CptPort 12189 12378 uid 9163,0 12190 12379 ps "OnEdgeStrategy" … … 12223 12412 ) 12224 12413 ) 12225 *39 5(CptPort12414 *398 (CptPort 12226 12415 uid 9167,0 12227 12416 ps "OnEdgeStrategy" … … 12260 12449 ) 12261 12450 ) 12262 *39 6(CptPort12451 *399 (CptPort 12263 12452 uid 9171,0 12264 12453 ps "OnEdgeStrategy" … … 12297 12486 ) 12298 12487 ) 12299 * 397(CptPort12488 *400 (CptPort 12300 12489 uid 9211,0 12301 12490 ps "OnEdgeStrategy" … … 12334 12523 ) 12335 12524 ) 12336 * 398(CptPort12525 *401 (CptPort 12337 12526 uid 9215,0 12338 12527 ps "OnEdgeStrategy" … … 12369 12558 ) 12370 12559 ) 12371 * 399(CptPort12560 *402 (CptPort 12372 12561 uid 9219,0 12373 12562 ps "OnEdgeStrategy" … … 12404 12593 ) 12405 12594 ) 12406 *40 0(CptPort12595 *403 (CptPort 12407 12596 uid 10030,0 12408 12597 ps "OnEdgeStrategy" … … 12456 12645 stg "VerticalLayoutStrategy" 12457 12646 textVec [ 12458 *40 1(Text12647 *404 (Text 12459 12648 uid 9178,0 12460 12649 va (VaSet … … 12466 12655 tm "BdLibraryNameMgr" 12467 12656 ) 12468 *40 2(Text12657 *405 (Text 12469 12658 uid 9179,0 12470 12659 va (VaSet … … 12476 12665 tm "CptNameMgr" 12477 12666 ) 12478 *40 3(Text12667 *406 (Text 12479 12668 uid 9180,0 12480 12669 va (VaSet … … 12523 12712 archFileType "UNKNOWN" 12524 12713 ) 12525 *40 4(Net12714 *407 (Net 12526 12715 uid 9231,0 12527 12716 decl (Decl … … 12539 12728 font "Courier New,8,0" 12540 12729 ) 12541 xt "-102000,97600,-43000,98400" 12542 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" 12543 ) 12544 ) 12545 *405 (Net 12730 xt "-102000,98400,-43000,99200" 12731 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards 12732 " 12733 ) 12734 ) 12735 *408 (Net 12546 12736 uid 9239,0 12547 12737 decl (Decl … … 12560 12750 font "Courier New,8,0" 12561 12751 ) 12562 xt "-102000,98400,-42000,99200" 12563 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" 12564 ) 12565 ) 12566 *406 (Net 12752 xt "-102000,99200,-42000,100000" 12753 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once 12754 " 12755 ) 12756 ) 12757 *409 (Net 12567 12758 uid 9267,0 12568 12759 decl (Decl … … 12577 12768 font "Courier New,8,0" 12578 12769 ) 12579 xt "-102000,30800,-83500,31600" 12580 st "LOCKED_extraOUT : std_logic" 12581 ) 12582 ) 12583 *407 (PortIoOut 12770 xt "-102000,31600,-83500,32400" 12771 st "LOCKED_extraOUT : std_logic 12772 " 12773 ) 12774 ) 12775 *410 (PortIoOut 12584 12776 uid 9275,0 12585 12777 shape (CompositeShape … … 12625 12817 ) 12626 12818 ) 12627 *4 08(Net12819 *411 (Net 12628 12820 uid 9281,0 12629 12821 decl (Decl … … 12638 12830 font "Courier New,8,0" 12639 12831 ) 12640 xt "-102000,32400,-83500,33200" 12641 st "PSDONE_extraOUT : std_logic" 12642 ) 12643 ) 12644 *409 (PortIoOut 12832 xt "-102000,33200,-83500,34000" 12833 st "PSDONE_extraOUT : std_logic 12834 " 12835 ) 12836 ) 12837 *412 (PortIoOut 12645 12838 uid 9289,0 12646 12839 shape (CompositeShape … … 12686 12879 ) 12687 12880 ) 12688 *41 0(Net12881 *413 (Net 12689 12882 uid 9295,0 12690 12883 decl (Decl … … 12699 12892 font "Courier New,8,0" 12700 12893 ) 12701 xt "-102000,33200,-83500,34000" 12702 st "PSINCDEC_OUT : std_logic" 12703 ) 12704 ) 12705 *411 (PortIoOut 12894 xt "-102000,34000,-83500,34800" 12895 st "PSINCDEC_OUT : std_logic 12896 " 12897 ) 12898 ) 12899 *414 (PortIoOut 12706 12900 uid 9303,0 12707 12901 shape (CompositeShape … … 12747 12941 ) 12748 12942 ) 12749 *41 2(Net12943 *415 (Net 12750 12944 uid 9323,0 12751 12945 decl (Decl … … 12760 12954 font "Courier New,8,0" 12761 12955 ) 12762 xt "-102000,31600,-83500,32400" 12763 st "PSCLK_OUT : std_logic" 12764 ) 12765 ) 12766 *413 (PortIoOut 12956 xt "-102000,32400,-83500,33200" 12957 st "PSCLK_OUT : std_logic 12958 " 12959 ) 12960 ) 12961 *416 (PortIoOut 12767 12962 uid 9331,0 12768 12963 shape (CompositeShape … … 12808 13003 ) 12809 13004 ) 12810 *41 4(Net13005 *417 (Net 12811 13006 uid 9351,0 12812 13007 decl (Decl … … 12823 13018 font "Courier New,8,0" 12824 13019 ) 12825 xt "-102000,30000,-83500,30800" 12826 st "DCM_locked : std_logic" 12827 ) 12828 ) 12829 *415 (PortIoOut 13020 xt "-102000,30800,-83500,31600" 13021 st "DCM_locked : std_logic 13022 " 13023 ) 13024 ) 13025 *418 (PortIoOut 12830 13026 uid 9359,0 12831 13027 shape (CompositeShape … … 12871 13067 ) 12872 13068 ) 12873 *41 6(Net13069 *419 (Net 12874 13070 uid 9365,0 12875 13071 decl (Decl … … 12888 13084 font "Courier New,8,0" 12889 13085 ) 12890 xt "-102000,46000,-56000,46800" 12891 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0')" 12892 ) 12893 ) 12894 *417 (PortIoOut 13086 xt "-102000,46800,-56000,47600" 13087 st "offset : std_logic_vector(7 downto 0) := (OTHERS => '0') 13088 " 13089 ) 13090 ) 13091 *420 (PortIoOut 12895 13092 uid 9374,0 12896 13093 shape (CompositeShape … … 12936 13133 ) 12937 13134 ) 12938 *4 18(Net13135 *421 (Net 12939 13136 uid 9380,0 12940 13137 decl (Decl … … 12953 13150 font "Courier New,8,0" 12954 13151 ) 12955 xt "-102000,50 000,-62000,51600"13152 xt "-102000,50800,-62000,52400" 12956 13153 st "-- status: 12957 shifting : std_logic := '0'" 12958 ) 12959 ) 12960 *419 (PortIoOut 13154 shifting : std_logic := '0' 13155 " 13156 ) 13157 ) 13158 *422 (PortIoOut 12961 13159 uid 9389,0 12962 13160 shape (CompositeShape … … 13002 13200 ) 13003 13201 ) 13004 *42 0(Net13202 *423 (Net 13005 13203 uid 9395,0 13006 13204 decl (Decl … … 13018 13216 font "Courier New,8,0" 13019 13217 ) 13020 xt "-102000,46800,-62000,47600" 13021 st "ready : std_logic := '0'" 13022 ) 13023 ) 13024 *421 (PortIoOut 13218 xt "-102000,47600,-62000,48400" 13219 st "ready : std_logic := '0' 13220 " 13221 ) 13222 ) 13223 *424 (PortIoOut 13025 13224 uid 9404,0 13026 13225 shape (CompositeShape … … 13066 13265 ) 13067 13266 ) 13068 *42 2(MWC13267 *425 (MWC 13069 13268 uid 9472,0 13070 13269 optionalChildren [ 13071 *42 3(CptPort13270 *426 (CptPort 13072 13271 uid 9481,0 13073 13272 optionalChildren [ 13074 *42 4(Line13273 *427 (Line 13075 13274 uid 9486,0 13076 13275 layer 5 … … 13133 13332 ) 13134 13333 ) 13135 *42 5(CptPort13334 *428 (CptPort 13136 13335 uid 9487,0 13137 13336 optionalChildren [ 13138 *42 6(Line13337 *429 (Line 13139 13338 uid 9492,0 13140 13339 layer 5 … … 13197 13396 ) 13198 13397 ) 13199 *4 27(CommentGraphic13398 *430 (CommentGraphic 13200 13399 uid 9493,0 13201 13400 shape (PolyLine2D … … 13218 13417 oxt "6000,6000,7000,7000" 13219 13418 ) 13220 *4 28(CommentGraphic13419 *431 (CommentGraphic 13221 13420 uid 9495,0 13222 13421 shape (PolyLine2D … … 13239 13438 oxt "6000,7000,7000,8000" 13240 13439 ) 13241 *4 29(CommentGraphic13440 *432 (CommentGraphic 13242 13441 uid 9497,0 13243 13442 shape (PolyLine2D … … 13260 13459 oxt "6988,7329,7988,7329" 13261 13460 ) 13262 *43 0(CommentGraphic13461 *433 (CommentGraphic 13263 13462 uid 9499,0 13264 13463 shape (PolyLine2D … … 13279 13478 oxt "8000,7000,9000,7000" 13280 13479 ) 13281 *43 1(CommentGraphic13480 *434 (CommentGraphic 13282 13481 uid 9501,0 13283 13482 shape (PolyLine2D … … 13320 13519 stg "VerticalLayoutStrategy" 13321 13520 textVec [ 13322 *43 2(Text13521 *435 (Text 13323 13522 uid 9475,0 13324 13523 va (VaSet … … 13330 13529 blo "-2650,-7100" 13331 13530 ) 13332 *43 3(Text13531 *436 (Text 13333 13532 uid 9476,0 13334 13533 va (VaSet … … 13339 13538 blo "-2650,-6100" 13340 13539 ) 13341 *43 4(Text13540 *437 (Text 13342 13541 uid 9477,0 13343 13542 va (VaSet … … 13384 13583 ) 13385 13584 ) 13386 *43 5(PortIoOut13585 *438 (PortIoOut 13387 13586 uid 9545,0 13388 13587 shape (CompositeShape … … 13428 13627 ) 13429 13628 ) 13430 *43 6(Net13629 *439 (Net 13431 13630 uid 9551,0 13432 13631 decl (Decl … … 13441 13640 font "Courier New,8,0" 13442 13641 ) 13443 xt "-102000,34000,-83500,34800" 13444 st "PS_DIR_IN : std_logic" 13445 ) 13446 ) 13447 *437 (MWC 13642 xt "-102000,34800,-83500,35600" 13643 st "PS_DIR_IN : std_logic 13644 " 13645 ) 13646 ) 13647 *440 (MWC 13448 13648 uid 9662,0 13449 13649 optionalChildren [ 13450 *4 38(CptPort13650 *441 (CptPort 13451 13651 uid 9642,0 13452 13652 optionalChildren [ 13453 *4 39(Line13653 *442 (Line 13454 13654 uid 9646,0 13455 13655 layer 5 … … 13510 13710 ) 13511 13711 ) 13512 *44 0(CptPort13712 *443 (CptPort 13513 13713 uid 9647,0 13514 13714 optionalChildren [ 13515 *44 1(Line13715 *444 (Line 13516 13716 uid 9651,0 13517 13717 layer 5 … … 13575 13775 ) 13576 13776 ) 13577 *44 2(CommentGraphic13777 *445 (CommentGraphic 13578 13778 uid 9652,0 13579 13779 shape (PolyLine2D … … 13596 13796 oxt "6000,6000,7000,7000" 13597 13797 ) 13598 *44 3(CommentGraphic13798 *446 (CommentGraphic 13599 13799 uid 9654,0 13600 13800 shape (PolyLine2D … … 13617 13817 oxt "6000,7000,7000,8000" 13618 13818 ) 13619 *44 4(CommentGraphic13819 *447 (CommentGraphic 13620 13820 uid 9656,0 13621 13821 shape (PolyLine2D … … 13638 13838 oxt "6988,7329,7988,7329" 13639 13839 ) 13640 *44 5(CommentGraphic13840 *448 (CommentGraphic 13641 13841 uid 9658,0 13642 13842 shape (PolyLine2D … … 13657 13857 oxt "8000,7000,9000,7000" 13658 13858 ) 13659 *44 6(CommentGraphic13859 *449 (CommentGraphic 13660 13860 uid 9660,0 13661 13861 shape (PolyLine2D … … 13698 13898 stg "VerticalLayoutStrategy" 13699 13899 textVec [ 13700 *4 47(Text13900 *450 (Text 13701 13901 uid 9665,0 13702 13902 va (VaSet … … 13708 13908 blo "28350,900" 13709 13909 ) 13710 *4 48(Text13910 *451 (Text 13711 13911 uid 9666,0 13712 13912 va (VaSet … … 13717 13917 blo "28350,1900" 13718 13918 ) 13719 *4 49(Text13919 *452 (Text 13720 13920 uid 9667,0 13721 13921 va (VaSet … … 13762 13962 ) 13763 13963 ) 13764 *45 0(MWC13964 *453 (MWC 13765 13965 uid 9679,0 13766 13966 optionalChildren [ 13767 *45 1(CptPort13967 *454 (CptPort 13768 13968 uid 9688,0 13769 13969 optionalChildren [ 13770 *45 2(Line13970 *455 (Line 13771 13971 uid 9693,0 13772 13972 layer 5 … … 13826 14026 ) 13827 14027 ) 13828 *45 3(CptPort14028 *456 (CptPort 13829 14029 uid 9694,0 13830 14030 optionalChildren [ 13831 *45 4(Line14031 *457 (Line 13832 14032 uid 9699,0 13833 14033 layer 5 … … 13890 14090 ) 13891 14091 ) 13892 *45 5(CommentGraphic14092 *458 (CommentGraphic 13893 14093 uid 9700,0 13894 14094 shape (PolyLine2D … … 13911 14111 oxt "6000,6000,7000,7000" 13912 14112 ) 13913 *45 6(CommentGraphic14113 *459 (CommentGraphic 13914 14114 uid 9702,0 13915 14115 shape (PolyLine2D … … 13932 14132 oxt "6000,7000,7000,8000" 13933 14133 ) 13934 *4 57(CommentGraphic14134 *460 (CommentGraphic 13935 14135 uid 9704,0 13936 14136 shape (PolyLine2D … … 13953 14153 oxt "6988,7329,7988,7329" 13954 14154 ) 13955 *4 58(CommentGraphic14155 *461 (CommentGraphic 13956 14156 uid 9706,0 13957 14157 shape (PolyLine2D … … 13972 14172 oxt "8000,7000,9000,7000" 13973 14173 ) 13974 *4 59(CommentGraphic14174 *462 (CommentGraphic 13975 14175 uid 9708,0 13976 14176 shape (PolyLine2D … … 14013 14213 stg "VerticalLayoutStrategy" 14014 14214 textVec [ 14015 *46 0(Text14215 *463 (Text 14016 14216 uid 9682,0 14017 14217 va (VaSet … … 14023 14223 blo "28350,5900" 14024 14224 ) 14025 *46 1(Text14225 *464 (Text 14026 14226 uid 9683,0 14027 14227 va (VaSet … … 14032 14232 blo "28350,6900" 14033 14233 ) 14034 *46 2(Text14234 *465 (Text 14035 14235 uid 9684,0 14036 14236 va (VaSet … … 14077 14277 ) 14078 14278 ) 14079 *46 3(MWC14279 *466 (MWC 14080 14280 uid 9710,0 14081 14281 optionalChildren [ 14082 *46 4(CptPort14282 *467 (CptPort 14083 14283 uid 9719,0 14084 14284 optionalChildren [ 14085 *46 5(Line14285 *468 (Line 14086 14286 uid 9724,0 14087 14287 layer 5 … … 14141 14341 ) 14142 14342 ) 14143 *46 6(CptPort14343 *469 (CptPort 14144 14344 uid 9725,0 14145 14345 optionalChildren [ 14146 *4 67(Line14346 *470 (Line 14147 14347 uid 9730,0 14148 14348 layer 5 … … 14205 14405 ) 14206 14406 ) 14207 *4 68(CommentGraphic14407 *471 (CommentGraphic 14208 14408 uid 9731,0 14209 14409 shape (PolyLine2D … … 14226 14426 oxt "6000,6000,7000,7000" 14227 14427 ) 14228 *4 69(CommentGraphic14428 *472 (CommentGraphic 14229 14429 uid 9733,0 14230 14430 shape (PolyLine2D … … 14247 14447 oxt "6000,7000,7000,8000" 14248 14448 ) 14249 *47 0(CommentGraphic14449 *473 (CommentGraphic 14250 14450 uid 9735,0 14251 14451 shape (PolyLine2D … … 14268 14468 oxt "6988,7329,7988,7329" 14269 14469 ) 14270 *47 1(CommentGraphic14470 *474 (CommentGraphic 14271 14471 uid 9737,0 14272 14472 shape (PolyLine2D … … 14287 14487 oxt "8000,7000,9000,7000" 14288 14488 ) 14289 *47 2(CommentGraphic14489 *475 (CommentGraphic 14290 14490 uid 9739,0 14291 14491 shape (PolyLine2D … … 14328 14528 stg "VerticalLayoutStrategy" 14329 14529 textVec [ 14330 *47 3(Text14530 *476 (Text 14331 14531 uid 9713,0 14332 14532 va (VaSet … … 14338 14538 blo "28350,9900" 14339 14539 ) 14340 *47 4(Text14540 *477 (Text 14341 14541 uid 9714,0 14342 14542 va (VaSet … … 14347 14547 blo "28350,10900" 14348 14548 ) 14349 *47 5(Text14549 *478 (Text 14350 14550 uid 9715,0 14351 14551 va (VaSet … … 14392 14592 ) 14393 14593 ) 14394 *47 6(PortIoOut14594 *479 (PortIoOut 14395 14595 uid 9761,0 14396 14596 shape (CompositeShape … … 14436 14636 ) 14437 14637 ) 14438 *4 77(Net14638 *480 (Net 14439 14639 uid 9767,0 14440 14640 decl (Decl … … 14449 14649 font "Courier New,8,0" 14450 14650 ) 14451 xt "-102000,27600,-83500,28400" 14452 st "CLK50_OUT : std_logic" 14453 ) 14454 ) 14455 *478 (PortIoOut 14651 xt "-102000,28400,-83500,29200" 14652 st "CLK50_OUT : std_logic 14653 " 14654 ) 14655 ) 14656 *481 (PortIoOut 14456 14657 uid 9777,0 14457 14658 shape (CompositeShape … … 14497 14698 ) 14498 14699 ) 14499 *4 79(Net14700 *482 (Net 14500 14701 uid 9783,0 14501 14702 decl (Decl … … 14510 14711 font "Courier New,8,0" 14511 14712 ) 14512 xt "-102000,26000,-83500,26800" 14513 st "CLK25_OUT : std_logic" 14514 ) 14515 ) 14516 *480 (PortIoOut 14713 xt "-102000,26800,-83500,27600" 14714 st "CLK25_OUT : std_logic 14715 " 14716 ) 14717 ) 14718 *483 (PortIoOut 14517 14719 uid 9793,0 14518 14720 shape (CompositeShape … … 14558 14760 ) 14559 14761 ) 14560 *48 1(Net14762 *484 (Net 14561 14763 uid 9799,0 14562 14764 decl (Decl … … 14571 14773 font "Courier New,8,0" 14572 14774 ) 14573 xt "-102000,26800,-83500,27600" 14574 st "CLK25_PSOUT : std_logic" 14575 ) 14576 ) 14577 *482 (Net 14775 xt "-102000,27600,-83500,28400" 14776 st "CLK25_PSOUT : std_logic 14777 " 14778 ) 14779 ) 14780 *485 (Net 14578 14781 uid 9941,0 14579 14782 decl (Decl … … 14591 14794 font "Courier New,8,0" 14592 14795 ) 14593 xt "-102000,99200,-34500,100000" 14594 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" 14595 ) 14596 ) 14597 *483 (Net 14796 xt "-102000,100000,-34500,100800" 14797 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift 14798 " 14799 ) 14800 ) 14801 *486 (Net 14598 14802 uid 9949,0 14599 14803 decl (Decl … … 14609 14813 font "Courier New,8,0" 14610 14814 ) 14611 xt "-102000,113600,-58500,114400" 14612 st "SIGNAL srclk_enable : std_logic := '0'" 14613 ) 14614 ) 14615 *484 (MWC 14815 xt "-102000,114400,-58500,115200" 14816 st "SIGNAL srclk_enable : std_logic := '0' 14817 " 14818 ) 14819 ) 14820 *487 (MWC 14616 14821 uid 9957,0 14617 14822 optionalChildren [ 14618 *48 5(CptPort14823 *488 (CptPort 14619 14824 uid 9966,0 14620 14825 optionalChildren [ 14621 *48 6(Line14826 *489 (Line 14622 14827 uid 9970,0 14623 14828 layer 5 … … 14632 14837 ] 14633 14838 ) 14634 *4 87(Property14839 *490 (Property 14635 14840 uid 9971,0 14636 14841 pclass "_MW_GEOM_" … … 14676 14881 ) 14677 14882 ) 14678 *4 88(CptPort14883 *491 (CptPort 14679 14884 uid 9972,0 14680 14885 optionalChildren [ 14681 *4 89(Line14886 *492 (Line 14682 14887 uid 9976,0 14683 14888 layer 5 … … 14730 14935 ) 14731 14936 ) 14732 *49 0(CptPort14937 *493 (CptPort 14733 14938 uid 9977,0 14734 14939 optionalChildren [ 14735 *49 1(Line14940 *494 (Line 14736 14941 uid 9981,0 14737 14942 layer 5 … … 14784 14989 ) 14785 14990 ) 14786 *49 2(CommentGraphic14991 *495 (CommentGraphic 14787 14992 uid 9982,0 14788 14993 optionalChildren [ 14789 *49 3(Property14994 *496 (Property 14790 14995 uid 9984,0 14791 14996 pclass "_MW_GEOM_" … … 14811 15016 oxt "11000,10000,11000,10000" 14812 15017 ) 14813 *49 4(CommentGraphic15018 *497 (CommentGraphic 14814 15019 uid 9985,0 14815 15020 optionalChildren [ 14816 *49 5(Property15021 *498 (Property 14817 15022 uid 9987,0 14818 15023 pclass "_MW_GEOM_" … … 14838 15043 oxt "11000,6000,11000,6000" 14839 15044 ) 14840 *49 6(Grouping15045 *499 (Grouping 14841 15046 uid 9988,0 14842 15047 optionalChildren [ 14843 * 497(CommentGraphic15048 *500 (CommentGraphic 14844 15049 uid 9990,0 14845 15050 shape (PolyLine2D … … 14862 15067 oxt "9000,6000,11000,10000" 14863 15068 ) 14864 * 498(CommentGraphic15069 *501 (CommentGraphic 14865 15070 uid 9992,0 14866 15071 shape (Arc2D … … 14915 15120 stg "VerticalLayoutStrategy" 14916 15121 textVec [ 14917 * 499(Text15122 *502 (Text 14918 15123 uid 9960,0 14919 15124 va (VaSet … … 14925 15130 blo "-29500,53300" 14926 15131 ) 14927 *50 0(Text15132 *503 (Text 14928 15133 uid 9961,0 14929 15134 va (VaSet … … 14934 15139 blo "-29500,54300" 14935 15140 ) 14936 *50 1(Text15141 *504 (Text 14937 15142 uid 9962,0 14938 15143 va (VaSet … … 14979 15184 ) 14980 15185 ) 14981 *50 2(Net15186 *505 (Net 14982 15187 uid 10008,0 14983 15188 decl (Decl … … 14993 15198 font "Courier New,8,0" 14994 15199 ) 14995 xt "-102000,60000,-58500,60800" 14996 st "SIGNAL SRCLK1 : std_logic := '0'" 14997 ) 14998 ) 14999 *503 (Net 15200 xt "-102000,60800,-58500,61600" 15201 st "SIGNAL SRCLK1 : std_logic := '0' 15202 " 15203 ) 15204 ) 15205 *506 (Net 15000 15206 uid 10192,0 15001 15207 decl (Decl … … 15014 15220 font "Courier New,8,0" 15015 15221 ) 15016 xt "-102000,7 1200,-58500,72800"15222 xt "-102000,72000,-58500,73600" 15017 15223 st "-- -- 15018 SIGNAL config_rw_ack : std_logic := '0'" 15019 ) 15020 ) 15021 *504 (Net 15224 SIGNAL config_rw_ack : std_logic := '0' 15225 " 15226 ) 15227 ) 15228 *507 (Net 15022 15229 uid 10200,0 15023 15230 decl (Decl … … 15036 15243 font "Courier New,8,0" 15037 15244 ) 15038 xt "-102000,7 2800,-58500,74400"15245 xt "-102000,73600,-58500,75200" 15039 15246 st "-- -- 15040 SIGNAL config_rw_ready : std_logic := '0'" 15041 ) 15042 ) 15043 *505 (Net 15247 SIGNAL config_rw_ready : std_logic := '0' 15248 " 15249 ) 15250 ) 15251 *508 (Net 15044 15252 uid 10264,0 15045 15253 decl (Decl … … 15054 15262 font "Courier New,8,0" 15055 15263 ) 15056 xt "-102000,107200,-79500,108000" 15057 st "SIGNAL s_trigger : std_logic" 15058 ) 15059 ) 15060 *506 (Net 15264 xt "-102000,108000,-79500,108800" 15265 st "SIGNAL s_trigger : std_logic 15266 " 15267 ) 15268 ) 15269 *509 (Net 15061 15270 uid 10296,0 15062 15271 decl (Decl … … 15071 15280 font "Courier New,8,0" 15072 15281 ) 15073 xt "-102000,116000,-79500,116800" 15074 st "SIGNAL start_srin_write_8b : std_logic" 15075 ) 15076 ) 15077 *507 (Net 15282 xt "-102000,116800,-79500,117600" 15283 st "SIGNAL start_srin_write_8b : std_logic 15284 " 15285 ) 15286 ) 15287 *510 (Net 15078 15288 uid 10302,0 15079 15289 decl (Decl … … 15089 15299 font "Courier New,8,0" 15090 15300 ) 15091 xt "-102000,114400,-58500,115200" 15092 st "SIGNAL srin_write_ack : std_logic := '0'" 15093 ) 15094 ) 15095 *508 (Net 15301 xt "-102000,115200,-58500,116000" 15302 st "SIGNAL srin_write_ack : std_logic := '0' 15303 " 15304 ) 15305 ) 15306 *511 (Net 15096 15307 uid 10308,0 15097 15308 decl (Decl … … 15107 15318 font "Courier New,8,0" 15108 15319 ) 15109 xt "-102000,115200,-58500,116000" 15110 st "SIGNAL srin_write_ready : std_logic := '0'" 15111 ) 15112 ) 15113 *509 (Net 15320 xt "-102000,116000,-58500,116800" 15321 st "SIGNAL srin_write_ready : std_logic := '0' 15322 " 15323 ) 15324 ) 15325 *512 (Net 15114 15326 uid 10314,0 15115 15327 decl (Decl … … 15126 15338 font "Courier New,8,0" 15127 15339 ) 15128 xt "-102000,93600,-52500,94400" 15129 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" 15130 ) 15131 ) 15132 *510 (Net 15340 xt "-102000,94400,-52500,95200" 15341 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0') 15342 " 15343 ) 15344 ) 15345 *513 (Net 15133 15346 uid 10320,0 15134 15347 decl (Decl … … 15144 15357 font "Courier New,8,0" 15145 15358 ) 15146 xt "-102000,36400,-62000,37200" 15147 st "SRIN_out : std_logic := '0'" 15148 ) 15149 ) 15150 *511 (PortIoOut 15359 xt "-102000,37200,-62000,38000" 15360 st "SRIN_out : std_logic := '0' 15361 " 15362 ) 15363 ) 15364 *514 (PortIoOut 15151 15365 uid 10328,0 15152 15366 shape (CompositeShape … … 15193 15407 ) 15194 15408 ) 15195 *51 2(MWC15409 *515 (MWC 15196 15410 uid 10380,0 15197 15411 optionalChildren [ 15198 *51 3(CptPort15412 *516 (CptPort 15199 15413 uid 10344,0 15200 15414 optionalChildren [ 15201 *51 4(Line15415 *517 (Line 15202 15416 uid 10348,0 15203 15417 layer 5 … … 15251 15465 ) 15252 15466 ) 15253 *51 5(CptPort15467 *518 (CptPort 15254 15468 uid 10349,0 15255 15469 optionalChildren [ 15256 *51 6(Property15470 *519 (Property 15257 15471 uid 10353,0 15258 15472 pclass "_MW_GEOM_" … … 15260 15474 ptn "String" 15261 15475 ) 15262 *5 17(Line15476 *520 (Line 15263 15477 uid 10354,0 15264 15478 layer 5 … … 15314 15528 ) 15315 15529 ) 15316 *5 18(CptPort15530 *521 (CptPort 15317 15531 uid 10355,0 15318 15532 optionalChildren [ 15319 *5 19(Line15533 *522 (Line 15320 15534 uid 10359,0 15321 15535 layer 5 … … 15367 15581 ) 15368 15582 ) 15369 *52 0(CommentGraphic15583 *523 (CommentGraphic 15370 15584 uid 10360,0 15371 15585 shape (Arc2D … … 15388 15602 oxt "7000,6003,11000,8000" 15389 15603 ) 15390 *52 1(CommentGraphic15604 *524 (CommentGraphic 15391 15605 uid 10362,0 15392 15606 shape (Arc2D … … 15409 15623 oxt "6996,8005,11000,10000" 15410 15624 ) 15411 *52 2(Grouping15625 *525 (Grouping 15412 15626 uid 10364,0 15413 15627 optionalChildren [ 15414 *52 3(CommentGraphic15628 *526 (CommentGraphic 15415 15629 uid 10366,0 15416 15630 optionalChildren [ 15417 *52 4(Property15631 *527 (Property 15418 15632 uid 10368,0 15419 15633 pclass "_MW_GEOM_" … … 15446 15660 oxt "7000,6000,11000,9998" 15447 15661 ) 15448 *52 5(CommentGraphic15662 *528 (CommentGraphic 15449 15663 uid 10369,0 15450 15664 optionalChildren [ 15451 *52 6(Property15665 *529 (Property 15452 15666 uid 10371,0 15453 15667 pclass "_MW_GEOM_" … … 15491 15705 oxt "7000,6000,11000,10000" 15492 15706 ) 15493 *5 27(CommentGraphic15707 *530 (CommentGraphic 15494 15708 uid 10372,0 15495 15709 shape (PolyLine2D … … 15510 15724 oxt "11000,8000,11000,8000" 15511 15725 ) 15512 *5 28(CommentGraphic15726 *531 (CommentGraphic 15513 15727 uid 10374,0 15514 15728 optionalChildren [ 15515 *5 29(Property15729 *532 (Property 15516 15730 uid 10376,0 15517 15731 pclass "_MW_GEOM_" … … 15537 15751 oxt "7000,6000,7000,6000" 15538 15752 ) 15539 *53 0(CommentGraphic15753 *533 (CommentGraphic 15540 15754 uid 10377,0 15541 15755 optionalChildren [ 15542 *53 1(Property15756 *534 (Property 15543 15757 uid 10379,0 15544 15758 pclass "_MW_GEOM_" … … 15583 15797 stg "VerticalLayoutStrategy" 15584 15798 textVec [ 15585 *53 2(Text15799 *535 (Text 15586 15800 uid 10383,0 15587 15801 va (VaSet … … 15593 15807 blo "-46500,67300" 15594 15808 ) 15595 *53 3(Text15809 *536 (Text 15596 15810 uid 10384,0 15597 15811 va (VaSet … … 15602 15816 blo "-46500,68300" 15603 15817 ) 15604 *53 4(Text15818 *537 (Text 15605 15819 uid 10385,0 15606 15820 va (VaSet … … 15647 15861 ) 15648 15862 ) 15649 *53 5(Net15863 *538 (Net 15650 15864 uid 10449,0 15651 15865 decl (Decl … … 15662 15876 font "Courier New,8,0" 15663 15877 ) 15664 xt "-102000,119200,-79500,120000" 15665 st "SIGNAL trigger_out : std_logic" 15666 ) 15667 ) 15668 *536 (Net 15878 xt "-102000,120000,-79500,120800" 15879 st "SIGNAL trigger_out : std_logic 15880 " 15881 ) 15882 ) 15883 *539 (Net 15669 15884 uid 10465,0 15670 15885 lang 2 … … 15684 15899 font "Courier New,8,0" 15685 15900 ) 15686 xt "-102000,104 000,-58500,105600"15901 xt "-102000,104800,-58500,106400" 15687 15902 st "-- -- 15688 SIGNAL ram_write_ready_ack : std_logic := '0'" 15689 ) 15690 ) 15691 *537 (Net 15903 SIGNAL ram_write_ready_ack : std_logic := '0' 15904 " 15905 ) 15906 ) 15907 *540 (Net 15692 15908 uid 10627,0 15693 15909 decl (Decl … … 15702 15918 font "Courier New,8,0" 15703 15919 ) 15704 xt "-102000,112000,-79500,112800" 15705 st "SIGNAL socks_connected : std_logic" 15706 ) 15707 ) 15708 *538 (Net 15920 xt "-102000,112800,-79500,113600" 15921 st "SIGNAL socks_connected : std_logic 15922 " 15923 ) 15924 ) 15925 *541 (Net 15709 15926 uid 10635,0 15710 15927 decl (Decl … … 15719 15936 font "Courier New,8,0" 15720 15937 ) 15721 xt "-102000,112800,-79500,113600" 15722 st "SIGNAL socks_waiting : std_logic" 15723 ) 15724 ) 15725 *539 (Net 15938 xt "-102000,113600,-79500,114400" 15939 st "SIGNAL socks_waiting : std_logic 15940 " 15941 ) 15942 ) 15943 *542 (Net 15726 15944 uid 10721,0 15727 15945 decl (Decl … … 15736 15954 font "Courier New,8,0" 15737 15955 ) 15738 xt "-102000,43600,-83500,44400" 15739 st "green : std_logic" 15740 ) 15741 ) 15742 *540 (PortIoOut 15956 xt "-102000,44400,-83500,45200" 15957 st "green : std_logic 15958 " 15959 ) 15960 ) 15961 *543 (PortIoOut 15743 15962 uid 10729,0 15744 15963 shape (CompositeShape … … 15784 16003 ) 15785 16004 ) 15786 *54 1(Net16005 *544 (Net 15787 16006 uid 10735,0 15788 16007 decl (Decl … … 15797 16016 font "Courier New,8,0" 15798 16017 ) 15799 xt "-102000,39600,-83500,40400" 15800 st "amber : std_logic" 15801 ) 15802 ) 15803 *542 (PortIoOut 16018 xt "-102000,40400,-83500,41200" 16019 st "amber : std_logic 16020 " 16021 ) 16022 ) 16023 *545 (PortIoOut 15804 16024 uid 10743,0 15805 16025 shape (CompositeShape … … 15845 16065 ) 15846 16066 ) 15847 *54 3(Net16067 *546 (Net 15848 16068 uid 10749,0 15849 16069 decl (Decl … … 15858 16078 font "Courier New,8,0" 15859 16079 ) 15860 xt "-102000,47600,-83500,48400" 15861 st "red : std_logic" 15862 ) 15863 ) 15864 *544 (PortIoOut 16080 xt "-102000,48400,-83500,49200" 16081 st "red : std_logic 16082 " 16083 ) 16084 ) 16085 *547 (PortIoOut 15865 16086 uid 10757,0 15866 16087 shape (CompositeShape … … 15906 16127 ) 15907 16128 ) 15908 *54 5(SaComponent16129 *548 (SaComponent 15909 16130 uid 11209,0 15910 16131 optionalChildren [ 15911 *54 6(CptPort16132 *549 (CptPort 15912 16133 uid 11181,0 15913 16134 ps "OnEdgeStrategy" … … 15942 16163 ) 15943 16164 ) 15944 *5 47(CptPort16165 *550 (CptPort 15945 16166 uid 11185,0 15946 16167 ps "OnEdgeStrategy" … … 15977 16198 ) 15978 16199 ) 15979 *5 48(CptPort16200 *551 (CptPort 15980 16201 uid 11189,0 15981 16202 ps "OnEdgeStrategy" … … 16012 16233 ) 16013 16234 ) 16014 *5 49(CptPort16235 *552 (CptPort 16015 16236 uid 11193,0 16016 16237 ps "OnEdgeStrategy" … … 16047 16268 ) 16048 16269 ) 16049 *55 0(CptPort16270 *553 (CptPort 16050 16271 uid 11197,0 16051 16272 ps "OnEdgeStrategy" … … 16080 16301 ) 16081 16302 ) 16082 *55 1(CptPort16303 *554 (CptPort 16083 16304 uid 11201,0 16084 16305 ps "OnEdgeStrategy" … … 16113 16334 ) 16114 16335 ) 16115 *55 2(CptPort16336 *555 (CptPort 16116 16337 uid 11205,0 16117 16338 ps "OnEdgeStrategy" … … 16146 16367 ) 16147 16368 ) 16148 *55 3(CptPort16369 *556 (CptPort 16149 16370 uid 12693,0 16150 16371 ps "OnEdgeStrategy" … … 16198 16419 stg "VerticalLayoutStrategy" 16199 16420 textVec [ 16200 *55 4(Text16421 *557 (Text 16201 16422 uid 11212,0 16202 16423 va (VaSet … … 16208 16429 tm "BdLibraryNameMgr" 16209 16430 ) 16210 *55 5(Text16431 *558 (Text 16211 16432 uid 11213,0 16212 16433 va (VaSet … … 16218 16439 tm "CptNameMgr" 16219 16440 ) 16220 *55 6(Text16441 *559 (Text 16221 16442 uid 11214,0 16222 16443 va (VaSet … … 16285 16506 archFileType "UNKNOWN" 16286 16507 ) 16287 *5 57(Net16508 *560 (Net 16288 16509 uid 11403,0 16289 16510 decl (Decl … … 16298 16519 font "Courier New,8,0" 16299 16520 ) 16300 xt "-102000,92000,-79500,92800" 16301 st "SIGNAL drs_readout_started : std_logic" 16302 ) 16303 ) 16304 *558 (Net 16521 xt "-102000,92800,-79500,93600" 16522 st "SIGNAL drs_readout_started : std_logic 16523 " 16524 ) 16525 ) 16526 *561 (Net 16305 16527 uid 11856,0 16306 16528 decl (Decl … … 16315 16537 font "Courier New,8,0" 16316 16538 ) 16317 xt "-102000,117600,-79500,118400" 16318 st "SIGNAL trigger_enable : std_logic" 16319 ) 16320 ) 16321 *559 (MWC 16539 xt "-102000,118400,-79500,119200" 16540 st "SIGNAL trigger_enable : std_logic 16541 " 16542 ) 16543 ) 16544 *562 (MWC 16322 16545 uid 12295,0 16323 16546 optionalChildren [ 16324 *56 0(CptPort16547 *563 (CptPort 16325 16548 uid 12267,0 16326 16549 optionalChildren [ 16327 *56 1(Line16550 *564 (Line 16328 16551 uid 12271,0 16329 16552 layer 5 … … 16338 16561 ] 16339 16562 ) 16340 *56 2(Property16563 *565 (Property 16341 16564 uid 12272,0 16342 16565 pclass "_MW_GEOM_" … … 16385 16608 ) 16386 16609 ) 16387 *56 3(CptPort16610 *566 (CptPort 16388 16611 uid 12273,0 16389 16612 optionalChildren [ 16390 *56 4(Line16613 *567 (Line 16391 16614 uid 12277,0 16392 16615 layer 5 … … 16440 16663 ) 16441 16664 ) 16442 *56 5(CptPort16665 *568 (CptPort 16443 16666 uid 12278,0 16444 16667 optionalChildren [ 16445 *56 6(Line16668 *569 (Line 16446 16669 uid 12282,0 16447 16670 layer 5 … … 16493 16716 ) 16494 16717 ) 16495 *5 67(CommentGraphic16718 *570 (CommentGraphic 16496 16719 uid 12283,0 16497 16720 optionalChildren [ 16498 *5 68(Property16721 *571 (Property 16499 16722 uid 12285,0 16500 16723 pclass "_MW_GEOM_" … … 16520 16743 oxt "7000,10000,7000,10000" 16521 16744 ) 16522 *5 69(CommentGraphic16745 *572 (CommentGraphic 16523 16746 uid 12286,0 16524 16747 optionalChildren [ 16525 *57 0(Property16748 *573 (Property 16526 16749 uid 12288,0 16527 16750 pclass "_MW_GEOM_" … … 16547 16770 oxt "7000,6000,7000,6000" 16548 16771 ) 16549 *57 1(Grouping16772 *574 (Grouping 16550 16773 uid 12289,0 16551 16774 optionalChildren [ 16552 *57 2(CommentGraphic16775 *575 (CommentGraphic 16553 16776 uid 12291,0 16554 16777 shape (PolyLine2D … … 16571 16794 oxt "7000,6000,9000,10000" 16572 16795 ) 16573 *57 3(CommentGraphic16796 *576 (CommentGraphic 16574 16797 uid 12293,0 16575 16798 shape (Arc2D … … 16624 16847 stg "VerticalLayoutStrategy" 16625 16848 textVec [ 16626 *57 4(Text16849 *577 (Text 16627 16850 uid 12298,0 16628 16851 va (VaSet … … 16634 16857 blo "-40500,70300" 16635 16858 ) 16636 *57 5(Text16859 *578 (Text 16637 16860 uid 12299,0 16638 16861 va (VaSet … … 16643 16866 blo "-40500,71300" 16644 16867 ) 16645 *57 6(Text16868 *579 (Text 16646 16869 uid 12300,0 16647 16870 va (VaSet … … 16688 16911 ) 16689 16912 ) 16690 *5 77(Net16913 *580 (Net 16691 16914 uid 12304,0 16692 16915 decl (Decl … … 16703 16926 font "Courier New,8,0" 16704 16927 ) 16705 xt "-102000,82400,-79500,83200" 16706 st "SIGNAL dout : std_logic" 16707 ) 16708 ) 16709 *578 (SaComponent 16928 xt "-102000,83200,-79500,84000" 16929 st "SIGNAL dout : std_logic 16930 " 16931 ) 16932 ) 16933 *581 (SaComponent 16710 16934 uid 12625,0 16711 16935 optionalChildren [ 16712 *5 79(CptPort16936 *582 (CptPort 16713 16937 uid 12605,0 16714 16938 ps "OnEdgeStrategy" … … 16743 16967 ) 16744 16968 ) 16745 *58 0(CptPort16969 *583 (CptPort 16746 16970 uid 12609,0 16747 16971 ps "OnEdgeStrategy" … … 16779 17003 ) 16780 17004 ) 16781 *58 1(CptPort17005 *584 (CptPort 16782 17006 uid 12613,0 16783 17007 ps "OnEdgeStrategy" … … 16814 17038 ) 16815 17039 ) 16816 *58 2(CptPort17040 *585 (CptPort 16817 17041 uid 12617,0 16818 17042 ps "OnEdgeStrategy" … … 16848 17072 ) 16849 17073 ) 16850 *58 3(CptPort17074 *586 (CptPort 16851 17075 uid 12621,0 16852 17076 ps "OnEdgeStrategy" … … 16884 17108 ) 16885 17109 ) 16886 *58 4(CptPort17110 *587 (CptPort 16887 17111 uid 12673,0 16888 17112 ps "OnEdgeStrategy" … … 16934 17158 stg "VerticalLayoutStrategy" 16935 17159 textVec [ 16936 *58 5(Text17160 *588 (Text 16937 17161 uid 12628,0 16938 17162 va (VaSet … … 16944 17168 tm "BdLibraryNameMgr" 16945 17169 ) 16946 *58 6(Text17170 *589 (Text 16947 17171 uid 12629,0 16948 17172 va (VaSet … … 16954 17178 tm "CptNameMgr" 16955 17179 ) 16956 *5 87(Text17180 *590 (Text 16957 17181 uid 12630,0 16958 17182 va (VaSet … … 17001 17225 archFileType "UNKNOWN" 17002 17226 ) 17003 *5 88(Net17227 *591 (Net 17004 17228 uid 12641,0 17005 17229 decl (Decl … … 17016 17240 font "Courier New,8,0" 17017 17241 ) 17018 xt "-102000,83200,-79500,84000" 17019 st "SIGNAL dout1 : std_logic" 17020 ) 17021 ) 17022 *589 (Net 17242 xt "-102000,84000,-79500,84800" 17243 st "SIGNAL dout1 : std_logic 17244 " 17245 ) 17246 ) 17247 *592 (Net 17023 17248 uid 12647,0 17024 17249 decl (Decl … … 17038 17263 font "Courier New,8,0" 17039 17264 ) 17040 xt "-102000,8 8800,-58500,91200"17265 xt "-102000,89600,-58500,92000" 17041 17266 st "-- -- 17042 17267 -- drs_dwrite : out std_logic := '1'; 17043 SIGNAL drs_readout_ready : std_logic := '0'" 17044 ) 17045 ) 17046 *590 (Net 17268 SIGNAL drs_readout_ready : std_logic := '0' 17269 " 17270 ) 17271 ) 17272 *593 (Net 17047 17273 uid 12653,0 17048 17274 decl (Decl … … 17057 17283 font "Courier New,8,0" 17058 17284 ) 17059 xt "-102000,91200,-79500,92000" 17060 st "SIGNAL drs_readout_ready_ack : std_logic" 17061 ) 17062 ) 17063 *591 (Net 17285 xt "-102000,92000,-79500,92800" 17286 st "SIGNAL drs_readout_ready_ack : std_logic 17287 " 17288 ) 17289 ) 17290 *594 (Net 17064 17291 uid 12705,0 17065 17292 decl (Decl … … 17074 17301 font "Courier New,8,0" 17075 17302 ) 17076 xt "-102000,38800,-83500,39600" 17077 st "additional_flasher_out : std_logic" 17078 ) 17079 ) 17080 *592 (PortIoOut 17303 xt "-102000,39600,-83500,40400" 17304 st "additional_flasher_out : std_logic 17305 " 17306 ) 17307 ) 17308 *595 (PortIoOut 17081 17309 uid 12713,0 17082 17310 shape (CompositeShape … … 17122 17350 ) 17123 17351 ) 17124 *59 3(SaComponent17352 *596 (SaComponent 17125 17353 uid 13117,0 17126 17354 optionalChildren [ 17127 *59 4(CptPort17355 *597 (CptPort 17128 17356 uid 13101,0 17129 17357 ps "OnEdgeStrategy" … … 17159 17387 ) 17160 17388 ) 17161 *59 5(CptPort17389 *598 (CptPort 17162 17390 uid 13105,0 17163 17391 ps "OnEdgeStrategy" … … 17193 17421 ) 17194 17422 ) 17195 *59 6(CptPort17423 *599 (CptPort 17196 17424 uid 13109,0 17197 17425 ps "OnEdgeStrategy" … … 17228 17456 ) 17229 17457 ) 17230 * 597(CptPort17458 *600 (CptPort 17231 17459 uid 13113,0 17232 17460 ps "OnEdgeStrategy" … … 17279 17507 stg "VerticalLayoutStrategy" 17280 17508 textVec [ 17281 * 598(Text17509 *601 (Text 17282 17510 uid 13120,0 17283 17511 va (VaSet … … 17289 17517 tm "BdLibraryNameMgr" 17290 17518 ) 17291 * 599(Text17519 *602 (Text 17292 17520 uid 13121,0 17293 17521 va (VaSet … … 17299 17527 tm "CptNameMgr" 17300 17528 ) 17301 *60 0(Text17529 *603 (Text 17302 17530 uid 13122,0 17303 17531 va (VaSet … … 17322 17550 ) 17323 17551 xt "84000,57200,111500,58000" 17324 st "MINIMAL_TRIGGER_WAIT_TIME = 250000 ( integer ) 17325 " 17552 st "MINIMAL_TRIGGER_WAIT_TIME = 250000 ( integer ) " 17326 17553 ) 17327 17554 header "" … … 17353 17580 archFileType "UNKNOWN" 17354 17581 ) 17355 *60 1(Net17582 *604 (Net 17356 17583 uid 13157,0 17357 17584 decl (Decl … … 17367 17594 font "Courier New,8,0" 17368 17595 ) 17369 xt "-102000,63200,-58500,64000" 17370 st "SIGNAL c_trigger_enable : std_logic := '0'" 17371 ) 17372 ) 17373 *602 (Net 17596 xt "-102000,64000,-58500,64800" 17597 st "SIGNAL c_trigger_enable : std_logic := '0' 17598 " 17599 ) 17600 ) 17601 *605 (Net 17374 17602 uid 13163,0 17375 17603 decl (Decl … … 17388 17616 font "Courier New,8,0" 17389 17617 ) 17390 xt "-102000,64000,-42000,64800" 17391 st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes" 17392 ) 17393 ) 17394 *603 (Net 17618 xt "-102000,64800,-42000,65600" 17619 st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes 17620 " 17621 ) 17622 ) 17623 *606 (Net 17395 17624 uid 13206,0 17396 17625 decl (Decl … … 17405 17634 font "Courier New,8,0" 17406 17635 ) 17407 xt "-102000,108000,-79500,108800" 17408 st "SIGNAL s_trigger_0 : std_logic" 17409 ) 17410 ) 17411 *604 (Net 17636 xt "-102000,108800,-79500,109600" 17637 st "SIGNAL s_trigger_0 : std_logic 17638 " 17639 ) 17640 ) 17641 *607 (Net 17412 17642 uid 13208,0 17413 17643 decl (Decl … … 17422 17652 font "Courier New,8,0" 17423 17653 ) 17424 xt "-102000,116800,-79500,117600" 17425 st "SIGNAL trigger1 : std_logic" 17426 ) 17427 ) 17428 *605 (MWC 17654 xt "-102000,117600,-79500,118400" 17655 st "SIGNAL trigger1 : std_logic 17656 " 17657 ) 17658 ) 17659 *608 (MWC 17429 17660 uid 13266,0 17430 17661 optionalChildren [ 17431 *60 6(CptPort17662 *609 (CptPort 17432 17663 uid 13230,0 17433 17664 optionalChildren [ 17434 *6 07(Line17665 *610 (Line 17435 17666 uid 13234,0 17436 17667 layer 5 … … 17483 17714 ) 17484 17715 ) 17485 *6 08(CptPort17716 *611 (CptPort 17486 17717 uid 13235,0 17487 17718 optionalChildren [ 17488 *6 09(Property17719 *612 (Property 17489 17720 uid 13239,0 17490 17721 pclass "_MW_GEOM_" … … 17492 17723 ptn "String" 17493 17724 ) 17494 *61 0(Line17725 *613 (Line 17495 17726 uid 13240,0 17496 17727 layer 5 … … 17543 17774 ) 17544 17775 ) 17545 *61 1(CptPort17776 *614 (CptPort 17546 17777 uid 13241,0 17547 17778 optionalChildren [ 17548 *61 2(Line17779 *615 (Line 17549 17780 uid 13245,0 17550 17781 layer 5 … … 17597 17828 ) 17598 17829 ) 17599 *61 3(CommentGraphic17830 *616 (CommentGraphic 17600 17831 uid 13246,0 17601 17832 shape (Arc2D … … 17618 17849 oxt "7000,6003,11000,8000" 17619 17850 ) 17620 *61 4(CommentGraphic17851 *617 (CommentGraphic 17621 17852 uid 13248,0 17622 17853 shape (Arc2D … … 17639 17870 oxt "7000,8005,11004,10000" 17640 17871 ) 17641 *61 5(Grouping17872 *618 (Grouping 17642 17873 uid 13250,0 17643 17874 optionalChildren [ 17644 *61 6(CommentGraphic17875 *619 (CommentGraphic 17645 17876 uid 13252,0 17646 17877 optionalChildren [ 17647 *6 17(Property17878 *620 (Property 17648 17879 uid 13254,0 17649 17880 pclass "_MW_GEOM_" … … 17676 17907 oxt "7000,6000,11000,9998" 17677 17908 ) 17678 *6 18(CommentGraphic17909 *621 (CommentGraphic 17679 17910 uid 13255,0 17680 17911 optionalChildren [ 17681 *6 19(Property17912 *622 (Property 17682 17913 uid 13257,0 17683 17914 pclass "_MW_GEOM_" … … 17721 17952 oxt "7000,6000,11000,10000" 17722 17953 ) 17723 *62 0(CommentGraphic17954 *623 (CommentGraphic 17724 17955 uid 13258,0 17725 17956 shape (PolyLine2D … … 17740 17971 oxt "7000,8000,7000,8000" 17741 17972 ) 17742 *62 1(CommentGraphic17973 *624 (CommentGraphic 17743 17974 uid 13260,0 17744 17975 optionalChildren [ 17745 *62 2(Property17976 *625 (Property 17746 17977 uid 13262,0 17747 17978 pclass "_MW_GEOM_" … … 17767 17998 oxt "11000,6000,11000,6000" 17768 17999 ) 17769 *62 3(CommentGraphic18000 *626 (CommentGraphic 17770 18001 uid 13263,0 17771 18002 optionalChildren [ 17772 *62 4(Property18003 *627 (Property 17773 18004 uid 13265,0 17774 18005 pclass "_MW_GEOM_" … … 17813 18044 stg "VerticalLayoutStrategy" 17814 18045 textVec [ 17815 *62 5(Text18046 *628 (Text 17816 18047 uid 13269,0 17817 18048 va (VaSet … … 17823 18054 blo "77500,59300" 17824 18055 ) 17825 *62 6(Text18056 *629 (Text 17826 18057 uid 13270,0 17827 18058 va (VaSet … … 17832 18063 blo "77500,60300" 17833 18064 ) 17834 *6 27(Text18065 *630 (Text 17835 18066 uid 13271,0 17836 18067 va (VaSet … … 17877 18108 ) 17878 18109 ) 17879 *628 (Wire 18110 *631 (PortIoIn 18111 uid 13689,0 18112 shape (CompositeShape 18113 uid 13690,0 18114 va (VaSet 18115 vasetType 1 18116 fg "0,0,32768" 18117 ) 18118 optionalChildren [ 18119 (Pentagon 18120 uid 13691,0 18121 sl 0 18122 ro 270 18123 xt "125000,91625,126500,92375" 18124 ) 18125 (Line 18126 uid 13692,0 18127 sl 0 18128 ro 270 18129 xt "126500,92000,127000,92000" 18130 pts [ 18131 "126500,92000" 18132 "127000,92000" 18133 ] 18134 ) 18135 ] 18136 ) 18137 stc 0 18138 sf 1 18139 tg (WTG 18140 uid 13693,0 18141 ps "PortIoTextPlaceStrategy" 18142 stg "STSignalDisplayStrategy" 18143 f (Text 18144 uid 13694,0 18145 va (VaSet 18146 ) 18147 xt "121100,91500,124000,92500" 18148 st "D_T_in" 18149 ju 2 18150 blo "124000,92300" 18151 tm "WireNameMgr" 18152 ) 18153 ) 18154 ) 18155 *632 (Net 18156 uid 13701,0 18157 decl (Decl 18158 n "D_T_in" 18159 t "std_logic_vector" 18160 b "(1 DOWNTO 0)" 18161 o 130 18162 suid 281,0 18163 ) 18164 declText (MLText 18165 uid 13702,0 18166 va (VaSet 18167 font "Courier New,8,0" 18168 ) 18169 xt "-102000,18000,-73500,18800" 18170 st "D_T_in : std_logic_vector(1 DOWNTO 0) 18171 " 18172 ) 18173 ) 18174 *633 (Wire 17880 18175 uid 322,0 17881 18176 shape (OrthoPolyLine … … 17893 18188 ) 17894 18189 start &26 17895 end &33 118190 end &334 17896 18191 sat 32 17897 18192 eat 32 … … 17916 18211 on &2 17917 18212 ) 17918 *6 29(Wire18213 *634 (Wire 17919 18214 uid 328,0 17920 18215 shape (OrthoPolyLine … … 17932 18227 ) 17933 18228 start &25 17934 end &33 018229 end &333 17935 18230 sat 32 17936 18231 eat 32 … … 17955 18250 on &3 17956 18251 ) 17957 *63 0(Wire18252 *635 (Wire 17958 18253 uid 334,0 17959 18254 shape (OrthoPolyLine … … 17971 18266 ) 17972 18267 start &24 17973 end &3 2918268 end &332 17974 18269 sat 32 17975 18270 eat 32 … … 17994 18289 on &4 17995 18290 ) 17996 *63 1(Wire18291 *636 (Wire 17997 18292 uid 364,0 17998 18293 shape (OrthoPolyLine … … 18002 18297 lineWidth 2 18003 18298 ) 18004 xt "91750,49000,127250,5 4000"18005 pts [ 18006 "127250,5 4000"18007 "123000,5 4000"18299 xt "91750,49000,127250,53000" 18300 pts [ 18301 "127250,53000" 18302 "123000,53000" 18008 18303 "123000,49000" 18009 18304 "91750,49000" … … 18011 18306 ) 18012 18307 start &86 18013 end &33 318308 end &336 18014 18309 sat 32 18015 18310 eat 32 … … 18034 18329 on &5 18035 18330 ) 18036 *63 2(Wire18331 *637 (Wire 18037 18332 uid 370,0 18038 18333 shape (OrthoPolyLine … … 18042 18337 lineWidth 2 18043 18338 ) 18044 xt "91750,50000,127250,5 5000"18045 pts [ 18046 "127250,5 5000"18047 "12 4000,55000"18048 "12 4000,50000"18339 xt "91750,50000,127250,54000" 18340 pts [ 18341 "127250,54000" 18342 "122000,54000" 18343 "122000,50000" 18049 18344 "91750,50000" 18050 18345 ] 18051 18346 ) 18052 18347 start &85 18053 end &33 418348 end &337 18054 18349 sat 32 18055 18350 eat 32 … … 18074 18369 on &6 18075 18370 ) 18076 *63 3(Wire18371 *638 (Wire 18077 18372 uid 376,0 18078 18373 shape (OrthoPolyLine … … 18081 18376 vasetType 3 18082 18377 ) 18083 xt "154000,52000,164750,52000" 18084 pts [ 18085 "164750,52000" 18086 "159000,52000" 18087 "154000,52000" 18378 xt "164750,51000,168000,51000" 18379 pts [ 18380 "164750,51000" 18381 "168000,51000" 18088 18382 ] 18089 18383 ) … … 18105 18399 isHidden 1 18106 18400 ) 18107 xt "1 66000,51000,169600,52000"18401 xt "183000,50000,186600,51000" 18108 18402 st "wiz_reset" 18109 blo "1 66000,51800"18403 blo "183000,50800" 18110 18404 tm "WireNameMgr" 18111 18405 ) … … 18113 18407 on &7 18114 18408 ) 18115 *63 4(Wire18409 *639 (Wire 18116 18410 uid 384,0 18117 18411 shape (OrthoPolyLine … … 18121 18415 lineWidth 2 18122 18416 ) 18123 xt "154000,60000,164750,60000" 18124 pts [ 18125 "164750,60000" 18126 "159000,60000" 18127 "154000,60000" 18417 xt "164750,59000,168000,59000" 18418 pts [ 18419 "164750,59000" 18420 "168000,59000" 18128 18421 ] 18129 18422 ) … … 18146 18439 isHidden 1 18147 18440 ) 18148 xt "1 66000,59000,169400,60000"18441 xt "182000,58000,185400,59000" 18149 18442 st "wiz_addr" 18150 blo "1 66000,59800"18443 blo "182000,58800" 18151 18444 tm "WireNameMgr" 18152 18445 ) … … 18154 18447 on &8 18155 18448 ) 18156 *6 35(Wire18449 *640 (Wire 18157 18450 uid 392,0 18158 18451 shape (OrthoPolyLine … … 18162 18455 lineWidth 2 18163 18456 ) 18164 xt "154000,61000,164750,61000" 18165 pts [ 18166 "164750,61000" 18167 "159000,61000" 18168 "154000,61000" 18457 xt "164750,60000,168000,60000" 18458 pts [ 18459 "164750,60000" 18460 "168000,60000" 18169 18461 ] 18170 18462 ) … … 18187 18479 isHidden 1 18188 18480 ) 18189 xt "1 66000,60000,169300,61000"18481 xt "181000,59000,184300,60000" 18190 18482 st "wiz_data" 18191 blo "1 66000,60800"18483 blo "181000,59800" 18192 18484 tm "WireNameMgr" 18193 18485 ) … … 18195 18487 on &9 18196 18488 ) 18197 *6 36(Wire18489 *641 (Wire 18198 18490 uid 400,0 18199 18491 shape (OrthoPolyLine … … 18202 18494 vasetType 3 18203 18495 ) 18204 xt "154000,53000,164750,53000" 18205 pts [ 18206 "164750,53000" 18207 "159000,53000" 18208 "154000,53000" 18496 xt "164750,52000,168000,52000" 18497 pts [ 18498 "164750,52000" 18499 "168000,52000" 18209 18500 ] 18210 18501 ) … … 18226 18517 isHidden 1 18227 18518 ) 18228 xt "1 66000,52000,168700,53000"18519 xt "182000,51000,184700,52000" 18229 18520 st "wiz_cs" 18230 blo "1 66000,52800"18521 blo "182000,51800" 18231 18522 tm "WireNameMgr" 18232 18523 ) … … 18234 18525 on &10 18235 18526 ) 18236 *6 37(Wire18527 *642 (Wire 18237 18528 uid 408,0 18238 18529 shape (OrthoPolyLine … … 18241 18532 vasetType 3 18242 18533 ) 18243 xt "154000,54000,164750,54000" 18244 pts [ 18245 "164750,54000" 18246 "159000,54000" 18247 "154000,54000" 18534 xt "164750,53000,168000,53000" 18535 pts [ 18536 "164750,53000" 18537 "168000,53000" 18248 18538 ] 18249 18539 ) … … 18265 18555 isHidden 1 18266 18556 ) 18267 xt "1 66000,53000,168700,54000"18557 xt "182000,52000,184700,53000" 18268 18558 st "wiz_wr" 18269 blo "1 66000,53800"18559 blo "182000,52800" 18270 18560 tm "WireNameMgr" 18271 18561 ) … … 18273 18563 on &11 18274 18564 ) 18275 *6 38(Wire18565 *643 (Wire 18276 18566 uid 424,0 18277 18567 shape (OrthoPolyLine … … 18280 18570 vasetType 3 18281 18571 ) 18282 xt "154000,55000,164750,55000" 18283 pts [ 18284 "164750,55000" 18285 "159000,55000" 18286 "154000,55000" 18572 xt "164750,54000,168000,54000" 18573 pts [ 18574 "164750,54000" 18575 "168000,54000" 18287 18576 ] 18288 18577 ) … … 18304 18593 isHidden 1 18305 18594 ) 18306 xt "1 66000,54000,168600,55000"18595 xt "182000,53000,184600,54000" 18307 18596 st "wiz_rd" 18308 blo "1 66000,54800"18597 blo "182000,53800" 18309 18598 tm "WireNameMgr" 18310 18599 ) … … 18312 18601 on &12 18313 18602 ) 18314 *6 39(Wire18603 *644 (Wire 18315 18604 uid 432,0 18316 18605 shape (OrthoPolyLine … … 18319 18608 vasetType 3 18320 18609 ) 18321 xt "154000,56000,164750,56000" 18322 pts [ 18323 "154000,56000" 18324 "159000,56000" 18325 "164750,56000" 18610 xt "164750,55000,168000,55000" 18611 pts [ 18612 "168000,55000" 18613 "164750,55000" 18326 18614 ] 18327 18615 ) … … 18343 18631 isHidden 1 18344 18632 ) 18345 xt "1 66000,55000,168700,56000"18633 xt "181000,54000,183700,55000" 18346 18634 st "wiz_int" 18347 blo "1 66000,55800"18635 blo "181000,54800" 18348 18636 tm "WireNameMgr" 18349 18637 ) … … 18351 18639 on &13 18352 18640 ) 18353 *64 0(Wire18641 *645 (Wire 18354 18642 uid 1411,0 18355 18643 shape (OrthoPolyLine … … 18365 18653 ] 18366 18654 ) 18367 start &1 6918655 start &172 18368 18656 end &28 18369 18657 sat 32 … … 18390 18678 on &71 18391 18679 ) 18392 *64 1(Wire18680 *646 (Wire 18393 18681 uid 1425,0 18394 18682 shape (OrthoPolyLine … … 18404 18692 ) 18405 18693 start &73 18406 end &51 318694 end &516 18407 18695 es 0 18408 18696 sat 32 … … 18429 18717 on &72 18430 18718 ) 18431 *64 2(Wire18719 *647 (Wire 18432 18720 uid 1682,0 18433 18721 shape (OrthoPolyLine … … 18443 18731 ] 18444 18732 ) 18445 start &17 018733 start &173 18446 18734 end &31 18447 18735 sat 32 … … 18466 18754 ) 18467 18755 ) 18468 on &1 1918469 ) 18470 *64 3(Wire18756 on &122 18757 ) 18758 *648 (Wire 18471 18759 uid 1983,0 18472 18760 shape (OrthoPolyLine … … 18484 18772 ] 18485 18773 ) 18486 start &12 118774 start &124 18487 18775 end &29 18488 18776 sat 32 … … 18505 18793 ) 18506 18794 ) 18507 on &1 2718508 ) 18509 *64 4(Wire18795 on &130 18796 ) 18797 *649 (Wire 18510 18798 uid 2299,0 18511 18799 shape (OrthoPolyLine … … 18523 18811 ] 18524 18812 ) 18525 start &13 018813 start &133 18526 18814 end &27 18527 18815 sat 32 … … 18545 18833 ) 18546 18834 ) 18547 on &1 2818548 ) 18549 *6 45(Wire18835 on &131 18836 ) 18837 *650 (Wire 18550 18838 uid 2470,0 18551 18839 shape (OrthoPolyLine … … 18554 18842 vasetType 3 18555 18843 ) 18556 xt "103750,6 8000,127250,68000"18844 xt "103750,67000,127250,68000" 18557 18845 pts [ 18558 18846 "103750,68000" 18559 "127250,68000" 18560 ] 18561 ) 18562 start &137 18847 "118000,68000" 18848 "118000,67000" 18849 "127250,67000" 18850 ] 18851 ) 18852 start &140 18563 18853 end &88 18564 18854 sat 32 … … 18581 18871 ) 18582 18872 ) 18583 on &15 218584 ) 18585 *6 46(Wire18873 on &155 18874 ) 18875 *651 (Wire 18586 18876 uid 2476,0 18587 18877 shape (OrthoPolyLine … … 18590 18880 vasetType 3 18591 18881 ) 18592 xt "103750,6 9000,127250,69000"18882 xt "103750,68000,127250,69000" 18593 18883 pts [ 18594 18884 "103750,69000" 18595 "127250,69000" 18596 ] 18597 ) 18598 start &140 18885 "124000,69000" 18886 "124000,68000" 18887 "127250,68000" 18888 ] 18889 ) 18890 start &143 18599 18891 end &87 18600 18892 sat 32 … … 18617 18909 ) 18618 18910 ) 18619 on &15 318620 ) 18621 *6 47(Wire18911 on &156 18912 ) 18913 *652 (Wire 18622 18914 uid 2482,0 18623 18915 shape (OrthoPolyLine … … 18627 18919 lineWidth 2 18628 18920 ) 18629 xt "103750, 70000,127250,70000"18921 xt "103750,69000,127250,76000" 18630 18922 pts [ 18631 18923 "103750,70000" 18632 "127250,70000" 18633 ] 18634 ) 18635 start &143 18924 "107000,70000" 18925 "107000,76000" 18926 "125000,76000" 18927 "125000,69000" 18928 "127250,69000" 18929 ] 18930 ) 18931 start &146 18636 18932 end &83 18637 18933 sat 32 … … 18655 18951 ) 18656 18952 ) 18657 on &15 418658 ) 18659 *6 48(Wire18953 on &157 18954 ) 18955 *653 (Wire 18660 18956 uid 2488,0 18661 18957 shape (OrthoPolyLine … … 18665 18961 lineWidth 2 18666 18962 ) 18667 xt "103750,7 1000,127250,71000"18963 xt "103750,70000,127250,71000" 18668 18964 pts [ 18669 18965 "103750,71000" 18670 "127250,71000" 18671 ] 18672 ) 18673 start &139 18966 "124000,71000" 18967 "124000,70000" 18968 "127250,70000" 18969 ] 18970 ) 18971 start &142 18674 18972 end &84 18675 18973 sat 32 … … 18693 18991 ) 18694 18992 ) 18695 on &15 518696 ) 18697 *6 49(Wire18993 on &158 18994 ) 18995 *654 (Wire 18698 18996 uid 2494,0 18699 18997 shape (OrthoPolyLine … … 18703 19001 lineWidth 2 18704 19002 ) 18705 xt "103750,7 2000,127250,72000"19003 xt "103750,71000,127250,77000" 18706 19004 pts [ 18707 19005 "103750,72000" 18708 "127250,72000" 18709 ] 18710 ) 18711 start &138 19006 "106000,72000" 19007 "106000,77000" 19008 "126000,77000" 19009 "126000,71000" 19010 "127250,71000" 19011 ] 19012 ) 19013 start &141 18712 19014 end &89 18713 19015 sat 32 … … 18731 19033 ) 18732 19034 ) 18733 on &15 618734 ) 18735 *65 0(Wire19035 on &159 19036 ) 19037 *655 (Wire 18736 19038 uid 2500,0 18737 19039 shape (OrthoPolyLine … … 18740 19042 vasetType 3 18741 19043 ) 18742 xt "103750,7 3000,127250,73000"19044 xt "103750,72000,127250,73000" 18743 19045 pts [ 18744 19046 "103750,73000" 18745 "127250,73000" 18746 ] 18747 ) 18748 start &141 19047 "124000,73000" 19048 "124000,72000" 19049 "127250,72000" 19050 ] 19051 ) 19052 start &144 18749 19053 end &90 18750 19054 sat 32 … … 18767 19071 ) 18768 19072 ) 18769 on &1 5718770 ) 18771 *65 1(Wire19073 on &160 19074 ) 19075 *656 (Wire 18772 19076 uid 2506,0 18773 19077 shape (OrthoPolyLine … … 18776 19080 vasetType 3 18777 19081 ) 18778 xt "103750,7 4000,127250,74000"19082 xt "103750,73000,127250,74000" 18779 19083 pts [ 18780 19084 "103750,74000" 18781 "127250,74000" 18782 ] 18783 ) 18784 start &142 19085 "111000,74000" 19086 "111000,73000" 19087 "127250,73000" 19088 ] 19089 ) 19090 start &145 18785 19091 end &91 18786 19092 sat 32 … … 18803 19109 ) 18804 19110 ) 18805 on &1 5818806 ) 18807 *65 2(Wire19111 on &161 19112 ) 19113 *657 (Wire 18808 19114 uid 2576,0 18809 19115 shape (OrthoPolyLine … … 18821 19127 ) 18822 19128 start &32 18823 end &13 419129 end &137 18824 19130 sat 32 18825 19131 eat 32 … … 18841 19147 ) 18842 19148 ) 18843 on &1 5918844 ) 18845 *65 3(Wire19149 on &162 19150 ) 19151 *658 (Wire 18846 19152 uid 2582,0 18847 19153 shape (OrthoPolyLine … … 18859 19165 ) 18860 19166 start &33 18861 end &13 519167 end &138 18862 19168 sat 32 18863 19169 eat 32 … … 18879 19185 ) 18880 19186 ) 18881 on &16 018882 ) 18883 *65 4(Wire19187 on &163 19188 ) 19189 *659 (Wire 18884 19190 uid 2588,0 18885 19191 shape (OrthoPolyLine … … 18897 19203 ) 18898 19204 start &51 18899 end &13 319205 end &136 18900 19206 ss 0 18901 19207 sat 32 … … 18918 19224 ) 18919 19225 ) 18920 on &16 118921 ) 18922 *6 55(Wire19226 on &164 19227 ) 19228 *660 (Wire 18923 19229 uid 2594,0 18924 19230 shape (OrthoPolyLine … … 18936 19242 ) 18937 19243 start &47 18938 end &13 219244 end &135 18939 19245 sat 32 18940 19246 eat 32 … … 18956 19262 ) 18957 19263 ) 18958 on &16 218959 ) 18960 *6 56(Wire19264 on &165 19265 ) 19266 *661 (Wire 18961 19267 uid 2600,0 18962 19268 shape (OrthoPolyLine … … 18974 19280 ) 18975 19281 start &34 18976 end &13 619282 end &139 18977 19283 sat 32 18978 19284 eat 32 … … 18994 19300 ) 18995 19301 ) 18996 on &16 318997 ) 18998 *6 57(Wire19302 on &166 19303 ) 19304 *662 (Wire 18999 19305 uid 2642,0 19000 19306 shape (OrthoPolyLine … … 19013 19319 ) 19014 19320 start &36 19015 end &14 519321 end &148 19016 19322 sat 32 19017 19323 eat 32 … … 19034 19340 ) 19035 19341 ) 19036 on &16 419037 ) 19038 *6 58(Wire19342 on &167 19343 ) 19344 *663 (Wire 19039 19345 uid 2778,0 19040 19346 shape (OrthoPolyLine … … 19050 19356 ) 19051 19357 start &37 19052 end &16 619358 end &169 19053 19359 sat 32 19054 19360 eat 32 … … 19072 19378 ) 19073 19379 ) 19074 on &16 519075 ) 19076 *6 59(Wire19380 on &168 19381 ) 19382 *664 (Wire 19077 19383 uid 2786,0 19078 19384 shape (OrthoPolyLine … … 19088 19394 ] 19089 19395 ) 19090 start &1 6719091 end &2 6819396 start &170 19397 end &271 19092 19398 sat 32 19093 19399 eat 32 … … 19112 19418 ) 19113 19419 ) 19114 on &1 8819115 ) 19116 *66 0(Wire19420 on &191 19421 ) 19422 *665 (Wire 19117 19423 uid 3888,0 19118 19424 optionalChildren [ 19119 *66 1(BdJunction19425 *666 (BdJunction 19120 19426 uid 4230,0 19121 19427 ps "OnConnectorStrategy" … … 19129 19435 ) 19130 19436 ) 19131 *66 2(BdJunction19437 *667 (BdJunction 19132 19438 uid 4244,0 19133 19439 ps "OnConnectorStrategy" … … 19137 19443 vasetType 1 19138 19444 ) 19139 xt "108600, 51600,109400,52400"19445 xt "108600,18600,109400,19400" 19140 19446 radius 400 19141 19447 ) 19142 19448 ) 19143 *66 3(BdJunction19449 *668 (BdJunction 19144 19450 uid 9677,0 19145 19451 ps "OnConnectorStrategy" … … 19160 19466 lineColor "0,0,65535" 19161 19467 ) 19162 xt "-1250,19000,127250,5 2000"19468 xt "-1250,19000,127250,51000" 19163 19469 pts [ 19164 19470 "-1250,19000" 19165 "1 06000,19000"19166 "1 06000,52000"19167 "127250,5 2000"19168 ] 19169 ) 19170 start &38 619471 "124000,19000" 19472 "124000,51000" 19473 "127250,51000" 19474 ] 19475 ) 19476 start &389 19171 19477 end &75 19172 19478 sat 32 … … 19190 19496 ) 19191 19497 ) 19192 on &18 419193 ) 19194 *66 4(Wire19498 on &187 19499 ) 19500 *669 (Wire 19195 19501 uid 3984,0 19196 19502 optionalChildren [ 19197 *6 65(BdJunction19503 *670 (BdJunction 19198 19504 uid 9751,0 19199 19505 ps "OnConnectorStrategy" … … 19222 19528 ] 19223 19529 ) 19224 start &18 319225 end & 39719530 start &186 19531 end &400 19226 19532 sat 32 19227 19533 eat 32 … … 19245 19551 ) 19246 19552 ) 19247 on &18 219248 ) 19249 *6 66(Wire19553 on &185 19554 ) 19555 *671 (Wire 19250 19556 uid 4042,0 19251 19557 shape (OrthoPolyLine … … 19261 19567 ) 19262 19568 start &1 19263 end &3 8819569 end &391 19264 19570 sat 32 19265 19571 eat 32 … … 19283 19589 ) 19284 19590 ) 19285 on &1 8719286 ) 19287 *6 67(Wire19591 on &190 19592 ) 19593 *672 (Wire 19288 19594 uid 4226,0 19289 19595 shape (OrthoPolyLine … … 19300 19606 ] 19301 19607 ) 19302 start &18 619303 end &66 119608 start &189 19609 end &666 19304 19610 sat 32 19305 19611 eat 32 … … 19323 19629 ) 19324 19630 ) 19325 on &18 419326 ) 19327 *6 68(Wire19631 on &187 19632 ) 19633 *673 (Wire 19328 19634 uid 4240,0 19329 19635 shape (OrthoPolyLine … … 19333 19639 lineColor "0,0,65535" 19334 19640 ) 19335 xt "91750, 44000,109000,52000"19641 xt "91750,19000,109000,44000" 19336 19642 pts [ 19337 19643 "91750,44000" 19338 19644 "109000,44000" 19339 "109000, 52000"19340 ] 19341 ) 19342 start &33 219343 end &66 219645 "109000,19000" 19646 ] 19647 ) 19648 start &335 19649 end &667 19344 19650 sat 32 19345 19651 eat 32 … … 19362 19668 ) 19363 19669 ) 19364 on &18 419365 ) 19366 *6 69(Wire19670 on &187 19671 ) 19672 *674 (Wire 19367 19673 uid 4272,0 19368 19674 shape (OrthoPolyLine … … 19377 19683 ] 19378 19684 ) 19379 start &19 019380 end &26 519685 start &193 19686 end &268 19381 19687 sat 32 19382 19688 eat 32 … … 19400 19706 ) 19401 19707 ) 19402 on &1 8919403 ) 19404 *67 0(Wire19708 on &192 19709 ) 19710 *675 (Wire 19405 19711 uid 4401,0 19406 19712 shape (OrthoPolyLine … … 19418 19724 ) 19419 19725 start &40 19420 end &2 0919726 end &212 19421 19727 sat 32 19422 19728 eat 32 … … 19438 19744 ) 19439 19745 ) 19440 on &19 119441 ) 19442 *67 1(Wire19746 on &194 19747 ) 19748 *676 (Wire 19443 19749 uid 4407,0 19444 19750 shape (OrthoPolyLine … … 19456 19762 ) 19457 19763 start &43 19458 end &21 519764 end &218 19459 19765 sat 32 19460 19766 eat 32 … … 19476 19782 ) 19477 19783 ) 19478 on &19 219479 ) 19480 *67 2(Wire19784 on &195 19785 ) 19786 *677 (Wire 19481 19787 uid 4419,0 19482 19788 shape (OrthoPolyLine … … 19494 19800 ) 19495 19801 start &41 19496 end &21 019802 end &213 19497 19803 sat 32 19498 19804 eat 32 … … 19514 19820 ) 19515 19821 ) 19516 on &19 319517 ) 19518 *67 3(Wire19822 on &196 19823 ) 19824 *678 (Wire 19519 19825 uid 4537,0 19520 19826 shape (OrthoPolyLine … … 19530 19836 ] 19531 19837 ) 19532 start &34 419533 end &19 619838 start &347 19839 end &199 19534 19840 sat 32 19535 19841 eat 32 … … 19554 19860 ) 19555 19861 ) 19556 on &19 419557 ) 19558 *67 4(Wire19862 on &197 19863 ) 19864 *679 (Wire 19559 19865 uid 4545,0 19560 19866 shape (OrthoPolyLine … … 19569 19875 ] 19570 19876 ) 19571 start &3 0919572 end & 19719877 start &312 19878 end &200 19573 19879 sat 32 19574 19880 eat 32 … … 19591 19897 ) 19592 19898 ) 19593 on &19 519594 ) 19595 *6 75(Wire19899 on &198 19900 ) 19901 *680 (Wire 19596 19902 uid 4671,0 19597 19903 shape (OrthoPolyLine … … 19606 19912 ] 19607 19913 ) 19608 start &20 219609 end &21 119914 start &205 19915 end &214 19610 19916 sat 32 19611 19917 eat 32 … … 19629 19935 ) 19630 19936 ) 19631 on & 19819632 ) 19633 *6 76(Wire19937 on &201 19938 ) 19939 *681 (Wire 19634 19940 uid 4679,0 19635 19941 shape (OrthoPolyLine … … 19644 19950 ] 19645 19951 ) 19646 start &20 319647 end &21 219952 start &206 19953 end &215 19648 19954 sat 32 19649 19955 eat 32 … … 19667 19973 ) 19668 19974 ) 19669 on & 19919670 ) 19671 *6 77(Wire19975 on &202 19976 ) 19977 *682 (Wire 19672 19978 uid 4687,0 19673 19979 shape (OrthoPolyLine … … 19682 19988 ] 19683 19989 ) 19684 start &20 419685 end &21 319990 start &207 19991 end &216 19686 19992 sat 32 19687 19993 eat 32 … … 19705 20011 ) 19706 20012 ) 19707 on &20 019708 ) 19709 *6 78(Wire20013 on &203 20014 ) 20015 *683 (Wire 19710 20016 uid 4695,0 19711 20017 shape (OrthoPolyLine … … 19720 20026 ] 19721 20027 ) 19722 start &20 519723 end &21 420028 start &208 20029 end &217 19724 20030 sat 32 19725 20031 eat 32 … … 19743 20049 ) 19744 20050 ) 19745 on &20 119746 ) 19747 *6 79(Wire20051 on &204 20052 ) 20053 *684 (Wire 19748 20054 uid 4743,0 19749 20055 shape (OrthoPolyLine … … 19760 20066 ] 19761 20067 ) 19762 start &21 620068 start &219 19763 20069 end &42 19764 20070 sat 32 … … 19781 20087 ) 19782 20088 ) 19783 on &20 619784 ) 19785 *68 0(Wire20089 on &209 20090 ) 20091 *685 (Wire 19786 20092 uid 4757,0 19787 20093 optionalChildren [ 19788 *68 1(BdJunction20094 *686 (BdJunction 19789 20095 uid 6076,0 19790 20096 ps "OnConnectorStrategy" … … 19813 20119 ] 19814 20120 ) 19815 start &2 0819816 end *68 2(BdJunction20121 start &211 20122 end *687 (BdJunction 19817 20123 uid 6080,0 19818 20124 ps "OnConnectorStrategy" … … 19846 20152 ) 19847 20153 ) 19848 on &18 519849 ) 19850 *68 3(Wire20154 on &188 20155 ) 20156 *688 (Wire 19851 20157 uid 4948,0 19852 20158 shape (OrthoPolyLine … … 19861 20167 ] 19862 20168 ) 19863 start &2 1719864 end &2 2820169 start &220 20170 end &231 19865 20171 sat 32 19866 20172 eat 32 … … 19884 20190 ) 19885 20191 ) 19886 on &2 2719887 ) 19888 *68 4(Wire20192 on &230 20193 ) 20194 *689 (Wire 19889 20195 uid 4962,0 19890 20196 shape (OrthoPolyLine … … 19899 20205 ] 19900 20206 ) 19901 start &48 519902 end &23 020207 start &488 20208 end &233 19903 20209 sat 32 19904 20210 eat 32 … … 19922 20228 ) 19923 20229 ) 19924 on &2 2919925 ) 19926 *6 85(Wire20230 on &232 20231 ) 20232 *690 (Wire 19927 20233 uid 5090,0 19928 20234 shape (OrthoPolyLine … … 19932 20238 lineWidth 2 19933 20239 ) 19934 xt "92750,7 9000,127250,100000"19935 pts [ 19936 "127250,7 9000"19937 "1 20000,79000"19938 "1 20000,100000"20240 xt "92750,78000,127250,100000" 20241 pts [ 20242 "127250,78000" 20243 "110000,78000" 20244 "110000,100000" 19939 20245 "92750,100000" 19940 20246 ] 19941 20247 ) 19942 20248 start &94 19943 end &23 320249 end &236 19944 20250 sat 32 19945 20251 eat 32 … … 19955 20261 va (VaSet 19956 20262 ) 19957 xt "120000,7 8000,127000,79000"20263 xt "120000,77000,127000,78000" 19958 20264 st "config_addr : (7:0)" 19959 blo "120000,7 8800"20265 blo "120000,77800" 19960 20266 tm "WireNameMgr" 19961 20267 ) 19962 20268 ) 19963 on &2 4919964 ) 19965 *6 86(Wire20269 on &252 20270 ) 20271 *691 (Wire 19966 20272 uid 5098,0 19967 20273 shape (OrthoPolyLine … … 19976 20282 ] 19977 20283 ) 19978 start &23 420284 start &237 19979 20285 sat 32 19980 20286 eat 16 … … 19995 20301 ) 19996 20302 ) 19997 on &25 019998 ) 19999 *6 87(Wire20303 on &253 20304 ) 20305 *692 (Wire 20000 20306 uid 5106,0 20001 20307 shape (OrthoPolyLine … … 20004 20310 vasetType 3 20005 20311 ) 20006 xt "92750,8 4000,127250,106000"20312 xt "92750,83000,127250,106000" 20007 20313 pts [ 20008 20314 "92750,106000" 20009 "1 24000,106000"20010 "1 24000,84000"20011 "127250,8 4000"20012 ] 20013 ) 20014 start &23 520315 "105000,106000" 20316 "105000,83000" 20317 "127250,83000" 20318 ] 20319 ) 20320 start &238 20015 20321 end &95 20016 20322 sat 32 … … 20032 20338 ) 20033 20339 ) 20034 on &25 120035 ) 20036 *6 88(Wire20340 on &254 20341 ) 20342 *693 (Wire 20037 20343 uid 5114,0 20038 20344 shape (OrthoPolyLine … … 20042 20348 lineWidth 2 20043 20349 ) 20044 xt "92750, 80000,127250,101000"20350 xt "92750,79000,127250,101000" 20045 20351 pts [ 20046 20352 "92750,101000" 20047 "1 21000,101000"20048 "1 21000,80000"20049 "127250, 80000"20050 ] 20051 ) 20052 start &23 620353 "108000,101000" 20354 "108000,79000" 20355 "127250,79000" 20356 ] 20357 ) 20358 start &239 20053 20359 end &96 20054 20360 sat 32 … … 20071 20377 ) 20072 20378 ) 20073 on &25 220074 ) 20075 *6 89(Wire20379 on &255 20380 ) 20381 *694 (Wire 20076 20382 uid 5122,0 20077 20383 shape (OrthoPolyLine … … 20080 20386 vasetType 3 20081 20387 ) 20082 xt "92750,8 2000,127250,104000"20083 pts [ 20084 "127250,8 2000"20085 "1 22000,82000"20086 "1 22000,104000"20388 xt "92750,81000,127250,104000" 20389 pts [ 20390 "127250,81000" 20391 "107000,81000" 20392 "107000,104000" 20087 20393 "92750,104000" 20088 20394 ] 20089 20395 ) 20090 20396 start &98 20091 end &2 3820397 end &241 20092 20398 sat 32 20093 20399 eat 32 … … 20102 20408 va (VaSet 20103 20409 ) 20104 xt "122000,8 1000,127300,82000"20410 xt "122000,80000,127300,81000" 20105 20411 st "config_wr_en" 20106 blo "122000,8 1800"20412 blo "122000,80800" 20107 20413 tm "WireNameMgr" 20108 20414 ) 20109 20415 ) 20110 on &25 320111 ) 20112 *69 0(Wire20416 on &256 20417 ) 20418 *695 (Wire 20113 20419 uid 5130,0 20114 20420 shape (OrthoPolyLine … … 20117 20423 vasetType 3 20118 20424 ) 20119 xt "92750,8 3000,127250,105000"20120 pts [ 20121 "127250,8 3000"20122 "1 23000,83000"20123 "1 23000,105000"20425 xt "92750,82000,127250,105000" 20426 pts [ 20427 "127250,82000" 20428 "106000,82000" 20429 "106000,105000" 20124 20430 "92750,105000" 20125 20431 ] 20126 20432 ) 20127 20433 start &100 20128 end &24 020434 end &243 20129 20435 sat 32 20130 20436 eat 32 … … 20139 20445 va (VaSet 20140 20446 ) 20141 xt "122000,8 2000,127200,83000"20447 xt "122000,81000,127200,82000" 20142 20448 st "config_rd_en" 20143 blo "122000,8 2800"20449 blo "122000,81800" 20144 20450 tm "WireNameMgr" 20145 20451 ) 20146 20452 ) 20147 on &25 420148 ) 20149 *69 1(Wire20453 on &257 20454 ) 20455 *696 (Wire 20150 20456 uid 5138,0 20151 20457 optionalChildren [ 20152 *69 2(BdJunction20458 *697 (BdJunction 20153 20459 uid 5400,0 20154 20460 ps "OnConnectorStrategy" … … 20176 20482 ] 20177 20483 ) 20178 start &2 3720484 start &240 20179 20485 end &35 20180 20486 ss 0 … … 20198 20504 ) 20199 20505 ) 20200 on &1 6820201 ) 20202 *69 3(Wire20506 on &171 20507 ) 20508 *698 (Wire 20203 20509 uid 5146,0 20204 20510 shape (OrthoPolyLine … … 20213 20519 ] 20214 20520 ) 20215 start &2 3920216 end &27 620521 start &242 20522 end &279 20217 20523 es 0 20218 20524 sat 32 … … 20234 20540 ) 20235 20541 ) 20236 on &25 520237 ) 20238 *69 4(Wire20542 on &258 20543 ) 20544 *699 (Wire 20239 20545 uid 5168,0 20240 20546 shape (OrthoPolyLine … … 20249 20555 ] 20250 20556 ) 20251 start &69 220252 end &14 420557 start &697 20558 end &147 20253 20559 sat 32 20254 20560 eat 32 … … 20270 20576 ) 20271 20577 ) 20272 on &1 6820273 ) 20274 * 695(Wire20578 on &171 20579 ) 20580 *700 (Wire 20275 20581 uid 5184,0 20276 20582 shape (OrthoPolyLine … … 20287 20593 ] 20288 20594 ) 20289 start &24 120595 start &244 20290 20596 end &46 20291 20597 sat 32 … … 20307 20613 ) 20308 20614 ) 20309 on &25 620310 ) 20311 * 696(Wire20615 on &259 20616 ) 20617 *701 (Wire 20312 20618 uid 5190,0 20313 20619 shape (OrthoPolyLine … … 20324 20630 ] 20325 20631 ) 20326 start &24 220632 start &245 20327 20633 end &45 20328 20634 sat 32 … … 20344 20650 ) 20345 20651 ) 20346 on &2 5720347 ) 20348 * 697(Wire20652 on &260 20653 ) 20654 *702 (Wire 20349 20655 uid 5222,0 20350 20656 shape (OrthoPolyLine … … 20354 20660 lineWidth 2 20355 20661 ) 20356 xt "154000,71000,164750,71000" 20357 pts [ 20358 "164750,71000" 20359 "159000,71000" 20360 "154000,71000" 20662 xt "164750,70000,170000,70000" 20663 pts [ 20664 "164750,70000" 20665 "170000,70000" 20361 20666 ] 20362 20667 ) … … 20379 20684 isHidden 1 20380 20685 ) 20381 xt "1 66750,70000,168150,71000"20686 xt "182750,69000,184150,70000" 20382 20687 st "led" 20383 blo "1 66750,70800"20688 blo "182750,69800" 20384 20689 tm "WireNameMgr" 20385 20690 ) 20386 20691 ) 20387 on &2 5820388 ) 20389 * 698(Wire20692 on &261 20693 ) 20694 *703 (Wire 20390 20695 uid 5404,0 20391 20696 shape (OrthoPolyLine … … 20402 20707 ] 20403 20708 ) 20404 start &2 7720709 start &280 20405 20710 end &48 20406 20711 sat 32 … … 20422 20727 ) 20423 20728 ) 20424 on &26 120425 ) 20426 * 699(Wire20729 on &264 20730 ) 20731 *704 (Wire 20427 20732 uid 5474,0 20428 20733 shape (OrthoPolyLine … … 20439 20744 ] 20440 20745 ) 20441 start &28 020746 start &283 20442 20747 end &50 20443 20748 sat 32 … … 20459 20764 ) 20460 20765 ) 20461 on &2 5920462 ) 20463 *70 0(Wire20766 on &262 20767 ) 20768 *705 (Wire 20464 20769 uid 5480,0 20465 20770 shape (OrthoPolyLine … … 20476 20781 ] 20477 20782 ) 20478 start &2 7920783 start &282 20479 20784 end &49 20480 20785 sat 32 … … 20496 20801 ) 20497 20802 ) 20498 on &26 020499 ) 20500 *70 1(Wire20803 on &263 20804 ) 20805 *706 (Wire 20501 20806 uid 5582,0 20502 20807 shape (OrthoPolyLine … … 20512 20817 ] 20513 20818 ) 20514 end &23 220819 end &235 20515 20820 sat 16 20516 20821 eat 32 … … 20531 20836 ) 20532 20837 ) 20533 on &18 420534 ) 20535 *70 2(Wire20838 on &187 20839 ) 20840 *707 (Wire 20536 20841 uid 5602,0 20537 20842 optionalChildren [ 20538 &68 220539 *70 3(BdJunction20843 &687 20844 *708 (BdJunction 20540 20845 uid 6086,0 20541 20846 ps "OnConnectorStrategy" … … 20567 20872 ) 20568 20873 start &23 20569 end &3 2820874 end &331 20570 20875 sat 32 20571 20876 eat 32 … … 20588 20893 ) 20589 20894 ) 20590 on &18 520591 ) 20592 *70 4(Wire20895 on &188 20896 ) 20897 *709 (Wire 20593 20898 uid 5626,0 20594 20899 shape (OrthoPolyLine … … 20604 20909 ) 20605 20910 start &44 20606 end &26 620911 end &269 20607 20912 sat 32 20608 20913 eat 32 … … 20624 20929 ) 20625 20930 ) 20626 on &26 320627 ) 20628 *7 05(Wire20931 on &266 20932 ) 20933 *710 (Wire 20629 20934 uid 5634,0 20630 20935 shape (OrthoPolyLine … … 20641 20946 ) 20642 20947 start &38 20643 end &2 6720948 end &270 20644 20949 sat 32 20645 20950 eat 32 … … 20662 20967 ) 20663 20968 ) 20664 on &26 220665 ) 20666 *7 06(Wire20969 on &265 20970 ) 20971 *711 (Wire 20667 20972 uid 5646,0 20668 20973 shape (OrthoPolyLine … … 20678 20983 ] 20679 20984 ) 20680 end &2 6920985 end &272 20681 20986 sat 16 20682 20987 eat 32 … … 20698 21003 ) 20699 21004 ) 20700 on &18 220701 ) 20702 *7 07(Wire21005 on &185 21006 ) 21007 *712 (Wire 20703 21008 uid 5745,0 20704 21009 shape (OrthoPolyLine … … 20716 21021 ) 20717 21022 start &52 20718 end &2 7821023 end &281 20719 21024 sat 32 20720 21025 eat 32 … … 20736 21041 ) 20737 21042 ) 20738 on &27 320739 ) 20740 *7 08(Wire21043 on &276 21044 ) 21045 *713 (Wire 20741 21046 uid 5805,0 20742 21047 shape (OrthoPolyLine … … 20751 21056 ] 20752 21057 ) 20753 end &28 321058 end &286 20754 21059 sat 16 20755 21060 eat 32 … … 20770 21075 ) 20771 21076 ) 20772 on &18 420773 ) 20774 *7 09(Wire21077 on &187 21078 ) 21079 *714 (Wire 20775 21080 uid 5813,0 20776 21081 shape (OrthoPolyLine … … 20785 21090 ] 20786 21091 ) 20787 start &36 420788 end &29 421092 start &367 21093 end &297 20789 21094 sat 32 20790 21095 eat 32 … … 20808 21113 ) 20809 21114 ) 20810 on &29 020811 ) 20812 *71 0(Wire21115 on &293 21116 ) 21117 *715 (Wire 20813 21118 uid 5821,0 20814 21119 shape (OrthoPolyLine … … 20823 21128 ] 20824 21129 ) 20825 start &28 620826 end &29 521130 start &289 21131 end &298 20827 21132 sat 32 20828 21133 eat 32 … … 20846 21151 ) 20847 21152 ) 20848 on &29 120849 ) 20850 *71 1(Wire21153 on &294 21154 ) 21155 *716 (Wire 20851 21156 uid 5829,0 20852 21157 shape (OrthoPolyLine … … 20861 21166 ] 20862 21167 ) 20863 start &28 120864 end &29 621168 start &284 21169 end &299 20865 21170 sat 32 20866 21171 eat 32 … … 20884 21189 ) 20885 21190 ) 20886 on &29 220887 ) 20888 *71 2(Wire21191 on &295 21192 ) 21193 *717 (Wire 20889 21194 uid 5837,0 20890 21195 shape (OrthoPolyLine … … 20900 21205 ] 20901 21206 ) 20902 start &28 220903 end & 29721207 start &285 21208 end &300 20904 21209 sat 32 20905 21210 eat 32 … … 20924 21229 ) 20925 21230 ) 20926 on &29 320927 ) 20928 *71 3(Wire21231 on &296 21232 ) 21233 *718 (Wire 20929 21234 uid 5950,0 20930 21235 shape (OrthoPolyLine … … 20933 21238 vasetType 3 20934 21239 ) 20935 xt "40750,54000,127250, 60000"20936 pts [ 20937 "127250, 60000"20938 "1 10000,60000"20939 "1 10000,54000"21240 xt "40750,54000,127250,59000" 21241 pts [ 21242 "127250,59000" 21243 "121000,59000" 21244 "121000,54000" 20940 21245 "40750,54000" 20941 21246 ] … … 20956 21261 va (VaSet 20957 21262 ) 20958 xt "121250,5 9000,125850,60000"21263 xt "121250,58000,125850,59000" 20959 21264 st "new_config" 20960 blo "121250,5 9800"21265 blo "121250,58800" 20961 21266 tm "WireNameMgr" 20962 21267 ) 20963 21268 ) 20964 on & 29820965 ) 20966 *71 4(Wire21269 on &301 21270 ) 21271 *719 (Wire 20967 21272 uid 5962,0 20968 21273 shape (OrthoPolyLine … … 20971 21276 vasetType 3 20972 21277 ) 20973 xt "40750,55000,127250,6 1000"20974 pts [ 20975 "127250,6 1000"20976 "1 11000,61000"20977 "1 11000,55000"21278 xt "40750,55000,127250,60000" 21279 pts [ 21280 "127250,60000" 21281 "120000,60000" 21282 "120000,55000" 20978 21283 "40750,55000" 20979 21284 ] … … 20994 21299 va (VaSet 20995 21300 ) 20996 xt "120250, 60000,125850,61000"21301 xt "120250,59000,125850,60000" 20997 21302 st "config_started" 20998 blo "120250, 60800"21303 blo "120250,59800" 20999 21304 tm "WireNameMgr" 21000 21305 ) 21001 21306 ) 21002 on & 29921003 ) 21004 *7 15(Wire21307 on &302 21308 ) 21309 *720 (Wire 21005 21310 uid 6002,0 21006 21311 shape (OrthoPolyLine … … 21017 21322 ] 21018 21323 ) 21019 start &24 321324 start &246 21020 21325 end &55 21021 21326 sat 32 … … 21038 21343 ) 21039 21344 ) 21040 on &30 121041 ) 21042 *7 16(Wire21345 on &304 21346 ) 21347 *721 (Wire 21043 21348 uid 6008,0 21044 21349 shape (OrthoPolyLine … … 21055 21360 ] 21056 21361 ) 21057 start &28 421362 start &287 21058 21363 end &57 21059 21364 sat 32 … … 21076 21381 ) 21077 21382 ) 21078 on &30 021079 ) 21080 *7 17(Wire21383 on &303 21384 ) 21385 *722 (Wire 21081 21386 uid 6018,0 21082 21387 shape (OrthoPolyLine … … 21094 21399 ) 21095 21400 start &56 21096 end &14 621401 end &149 21097 21402 sat 32 21098 21403 eat 32 … … 21114 21419 ) 21115 21420 ) 21116 on &30 221117 ) 21118 *7 18(Wire21421 on &305 21422 ) 21423 *723 (Wire 21119 21424 uid 6064,0 21120 21425 shape (OrthoPolyLine … … 21149 21454 ) 21150 21455 ) 21151 on &25 521152 ) 21153 *7 19(Wire21456 on &258 21457 ) 21458 *724 (Wire 21154 21459 uid 6072,0 21155 21460 optionalChildren [ 21156 *72 0(BdJunction21461 *725 (BdJunction 21157 21462 uid 9745,0 21158 21463 ps "OnConnectorStrategy" … … 21180 21485 ] 21181 21486 ) 21182 start &3 8721183 end &68 121487 start &390 21488 end &686 21184 21489 sat 32 21185 21490 eat 32 … … 21202 21507 ) 21203 21508 ) 21204 on &18 521205 ) 21206 *72 1(Wire21509 on &188 21510 ) 21511 *726 (Wire 21207 21512 uid 6082,0 21208 21513 shape (OrthoPolyLine … … 21219 21524 ] 21220 21525 ) 21221 start &13 121222 end &70 321526 start &134 21527 end &708 21223 21528 sat 32 21224 21529 eat 32 … … 21241 21546 ) 21242 21547 ) 21243 on &18 521244 ) 21245 *72 2(Wire21548 on &188 21549 ) 21550 *727 (Wire 21246 21551 uid 6160,0 21247 21552 shape (OrthoPolyLine … … 21256 21561 ] 21257 21562 ) 21258 start &28 521259 end &30 421563 start &288 21564 end &307 21260 21565 sat 32 21261 21566 eat 32 … … 21279 21584 ) 21280 21585 ) 21281 on &30 321282 ) 21283 *72 3(Wire21586 on &306 21587 ) 21588 *728 (Wire 21284 21589 uid 6276,0 21285 21590 shape (OrthoPolyLine … … 21294 21599 ] 21295 21600 ) 21296 end &12 321601 end &126 21297 21602 sat 16 21298 21603 eat 32 … … 21313 21618 ) 21314 21619 ) 21315 on &18 221316 ) 21317 *72 4(Wire21620 on &185 21621 ) 21622 *729 (Wire 21318 21623 uid 6362,0 21319 21624 shape (OrthoPolyLine … … 21322 21627 vasetType 3 21323 21628 ) 21324 xt "154000,75000,164750,75000" 21325 pts [ 21326 "164750,75000" 21327 "159000,75000" 21328 "154000,75000" 21629 xt "164750,74000,169000,74000" 21630 pts [ 21631 "164750,74000" 21632 "169000,74000" 21329 21633 ] 21330 21634 ) 21331 21635 start &101 21332 end &30 621636 end &309 21333 21637 sat 32 21334 21638 eat 32 … … 21346 21650 isHidden 1 21347 21651 ) 21348 xt "1 66000,74000,169000,75000"21652 xt "185000,73000,188000,74000" 21349 21653 st "denable" 21350 blo "1 66000,74800"21654 blo "185000,73800" 21351 21655 tm "WireNameMgr" 21352 21656 ) 21353 21657 ) 21354 on &30 521355 ) 21356 *7 25(Wire21658 on &308 21659 ) 21660 *730 (Wire 21357 21661 uid 6452,0 21358 21662 shape (OrthoPolyLine … … 21361 21665 vasetType 3 21362 21666 ) 21363 xt "164750,7 6000,170000,76000"21364 pts [ 21365 "164750,7 6000"21366 "170000,7 6000"21667 xt "164750,75000,170000,75000" 21668 pts [ 21669 "164750,75000" 21670 "170000,75000" 21367 21671 ] 21368 21672 ) … … 21382 21686 va (VaSet 21383 21687 ) 21384 xt "171000,7 6000,176400,77000"21688 xt "171000,75000,176400,76000" 21385 21689 st "dwrite_enable" 21386 blo "171000,7 6800"21690 blo "171000,75800" 21387 21691 tm "WireNameMgr" 21388 21692 ) 21389 21693 ) 21390 on &3 0721391 ) 21392 *7 26(Wire21694 on &310 21695 ) 21696 *731 (Wire 21393 21697 uid 6540,0 21394 21698 shape (OrthoPolyLine … … 21403 21707 ] 21404 21708 ) 21405 start &31 221709 start &315 21406 21710 sat 32 21407 21711 eat 16 … … 21424 21728 ) 21425 21729 ) 21426 on &32 621427 ) 21428 *7 27(Wire21730 on &329 21731 ) 21732 *732 (Wire 21429 21733 uid 6548,0 21430 21734 shape (OrthoPolyLine … … 21439 21743 ] 21440 21744 ) 21441 end &31 421745 end &317 21442 21746 es 0 21443 21747 sat 16 … … 21461 21765 ) 21462 21766 ) 21463 on &3 0721464 ) 21465 *7 28(Wire21767 on &310 21768 ) 21769 *733 (Wire 21466 21770 uid 8416,0 21467 21771 shape (OrthoPolyLine … … 21470 21774 vasetType 3 21471 21775 ) 21472 xt "103750,7 5000,127250,75000"21776 xt "103750,74000,127250,75000" 21473 21777 pts [ 21474 21778 "103750,75000" 21475 "127250,75000" 21476 ] 21477 ) 21478 start &147 21779 "124000,75000" 21780 "124000,74000" 21781 "127250,74000" 21782 ] 21783 ) 21784 start &150 21479 21785 end &103 21480 21786 sat 32 … … 21497 21803 ) 21498 21804 ) 21499 on &3 3821500 ) 21501 *7 29(Wire21805 on &341 21806 ) 21807 *734 (Wire 21502 21808 uid 8577,0 21503 21809 shape (OrthoPolyLine … … 21535 21841 ) 21536 21842 ) 21537 on &36 221538 ) 21539 *73 0(Wire21843 on &365 21844 ) 21845 *735 (Wire 21540 21846 uid 8587,0 21541 21847 shape (OrthoPolyLine … … 21551 21857 ] 21552 21858 ) 21553 end &34 221859 end &345 21554 21860 sat 16 21555 21861 eat 32 … … 21573 21879 ) 21574 21880 ) 21575 on &36 221576 ) 21577 *73 1(Wire21881 on &365 21882 ) 21883 *736 (Wire 21578 21884 uid 8595,0 21579 21885 shape (OrthoPolyLine … … 21589 21895 ] 21590 21896 ) 21591 end &3 4721897 end &350 21592 21898 sat 16 21593 21899 eat 32 … … 21611 21917 ) 21612 21918 ) 21613 on &3 3921614 ) 21615 *73 2(Wire21919 on &342 21920 ) 21921 *737 (Wire 21616 21922 uid 8603,0 21617 21923 shape (OrthoPolyLine … … 21627 21933 ] 21628 21934 ) 21629 end &3 4921935 end &352 21630 21936 sat 16 21631 21937 eat 32 … … 21648 21954 ) 21649 21955 ) 21650 on &34 021651 ) 21652 *73 3(Wire21956 on &343 21957 ) 21958 *738 (Wire 21653 21959 uid 8732,0 21654 21960 shape (OrthoPolyLine … … 21665 21971 ] 21666 21972 ) 21667 start &27 521668 end &3 6921973 start &278 21974 end &372 21669 21975 sat 32 21670 21976 eat 32 … … 21686 21992 ) 21687 21993 ) 21688 on &38 121689 ) 21690 *73 4(Wire21994 on &384 21995 ) 21996 *739 (Wire 21691 21997 uid 8738,0 21692 21998 shape (OrthoPolyLine … … 21701 22007 ] 21702 22008 ) 21703 end &3 6722009 end &370 21704 22010 sat 16 21705 22011 eat 32 … … 21722 22028 ) 21723 22029 ) 21724 on &38 221725 ) 21726 *7 35(Wire22030 on &385 22031 ) 22032 *740 (Wire 21727 22033 uid 8752,0 21728 22034 shape (OrthoPolyLine … … 21731 22037 vasetType 3 21732 22038 ) 21733 xt "164750,7 7000,170000,77000"21734 pts [ 21735 "164750,7 7000"21736 "170000,7 7000"22039 xt "164750,76000,170000,76000" 22040 pts [ 22041 "164750,76000" 22042 "170000,76000" 21737 22043 ] 21738 22044 ) … … 21751 22057 va (VaSet 21752 22058 ) 21753 xt "171000,7 7000,175700,78000"22059 xt "171000,76000,175700,77000" 21754 22060 st "sclk_enable" 21755 blo "171000,7 7800"22061 blo "171000,76800" 21756 22062 tm "WireNameMgr" 21757 22063 ) 21758 22064 ) 21759 on &38 221760 ) 21761 *7 36(Wire22065 on &385 22066 ) 22067 *741 (Wire 21762 22068 uid 9006,0 21763 22069 shape (OrthoPolyLine … … 21773 22079 ) 21774 22080 start &59 21775 end &38 422081 end &387 21776 22082 sat 32 21777 22083 eat 32 … … 21795 22101 ) 21796 22102 ) 21797 on &38 321798 ) 21799 *7 37(Wire22103 on &386 22104 ) 22105 *742 (Wire 21800 22106 uid 9233,0 21801 22107 shape (OrthoPolyLine … … 21804 22110 vasetType 3 21805 22111 ) 21806 xt "164750,8 1000,170000,81000"21807 pts [ 21808 "164750,8 1000"21809 "170000,8 1000"22112 xt "164750,80000,170000,80000" 22113 pts [ 22114 "164750,80000" 22115 "170000,80000" 21810 22116 ] 21811 22117 ) … … 21824 22130 va (VaSet 21825 22131 ) 21826 xt "171000,8 1000,175900,82000"22132 xt "171000,80000,175900,81000" 21827 22133 st "ps_direction" 21828 blo "171000,8 1800"22134 blo "171000,80800" 21829 22135 tm "WireNameMgr" 21830 22136 ) 21831 22137 ) 21832 on &40 421833 ) 21834 *7 38(Wire22138 on &407 22139 ) 22140 *743 (Wire 21835 22141 uid 9241,0 21836 22142 shape (OrthoPolyLine … … 21839 22145 vasetType 3 21840 22146 ) 21841 xt "164750,8 2000,170000,82000"21842 pts [ 21843 "164750,8 2000"21844 "170000,8 2000"22147 xt "164750,81000,170000,81000" 22148 pts [ 22149 "164750,81000" 22150 "170000,81000" 21845 22151 ] 21846 22152 ) … … 21859 22165 va (VaSet 21860 22166 ) 21861 xt "171000,8 2000,178000,83000"22167 xt "171000,81000,178000,82000" 21862 22168 st "ps_do_phase_shift" 21863 blo "171000,8 2800"22169 blo "171000,81800" 21864 22170 tm "WireNameMgr" 21865 22171 ) 21866 22172 ) 21867 on &40 521868 ) 21869 *7 39(Wire22173 on &408 22174 ) 22175 *744 (Wire 21870 22176 uid 9253,0 21871 22177 optionalChildren [ 21872 *74 0(BdJunction22178 *745 (BdJunction 21873 22179 uid 9507,0 21874 22180 ps "OnConnectorStrategy" … … 21894 22200 ] 21895 22201 ) 21896 end & 39822202 end &401 21897 22203 sat 16 21898 22204 eat 32 … … 21913 22219 ) 21914 22220 ) 21915 on &40 421916 ) 21917 *74 1(Wire22221 on &407 22222 ) 22223 *746 (Wire 21918 22224 uid 9261,0 21919 22225 shape (OrthoPolyLine … … 21928 22234 ] 21929 22235 ) 21930 end & 39922236 end &402 21931 22237 sat 16 21932 22238 eat 32 … … 21947 22253 ) 21948 22254 ) 21949 on &40 521950 ) 21951 *74 2(Wire22255 on &408 22256 ) 22257 *747 (Wire 21952 22258 uid 9269,0 21953 22259 shape (OrthoPolyLine … … 21962 22268 ] 21963 22269 ) 21964 start &39 621965 end &4 0722270 start &399 22271 end &410 21966 22272 sat 32 21967 22273 eat 32 … … 21985 22291 ) 21986 22292 ) 21987 on &40 621988 ) 21989 *74 3(Wire22293 on &409 22294 ) 22295 *748 (Wire 21990 22296 uid 9283,0 21991 22297 shape (OrthoPolyLine … … 22000 22306 ] 22001 22307 ) 22002 start &39 522003 end &4 0922308 start &398 22309 end &412 22004 22310 sat 32 22005 22311 eat 32 … … 22023 22329 ) 22024 22330 ) 22025 on &4 0822026 ) 22027 *74 4(Wire22331 on &411 22332 ) 22333 *749 (Wire 22028 22334 uid 9297,0 22029 22335 shape (OrthoPolyLine … … 22038 22344 ] 22039 22345 ) 22040 start &39 422041 end &41 122346 start &397 22347 end &414 22042 22348 sat 32 22043 22349 eat 32 … … 22061 22367 ) 22062 22368 ) 22063 on &41 022064 ) 22065 *7 45(Wire22369 on &413 22370 ) 22371 *750 (Wire 22066 22372 uid 9325,0 22067 22373 shape (OrthoPolyLine … … 22076 22382 ] 22077 22383 ) 22078 start &39 322079 end &41 322384 start &396 22385 end &416 22080 22386 sat 32 22081 22387 eat 32 … … 22099 22405 ) 22100 22406 ) 22101 on &41 222102 ) 22103 *7 46(Wire22407 on &415 22408 ) 22409 *751 (Wire 22104 22410 uid 9353,0 22105 22411 shape (OrthoPolyLine … … 22114 22420 ] 22115 22421 ) 22116 start &39 222117 end &41 522422 start &395 22423 end &418 22118 22424 sat 32 22119 22425 eat 32 … … 22137 22443 ) 22138 22444 ) 22139 on &41 422140 ) 22141 *7 47(Wire22445 on &417 22446 ) 22447 *752 (Wire 22142 22448 uid 9367,0 22143 22449 shape (OrthoPolyLine … … 22153 22459 ] 22154 22460 ) 22155 start &39 122156 end &4 1722461 start &394 22462 end &420 22157 22463 sat 32 22158 22464 eat 32 … … 22177 22483 ) 22178 22484 ) 22179 on &41 622180 ) 22181 *7 48(Wire22485 on &419 22486 ) 22487 *753 (Wire 22182 22488 uid 9382,0 22183 22489 shape (OrthoPolyLine … … 22192 22498 ] 22193 22499 ) 22194 start &39 022195 end &4 1922500 start &393 22501 end &422 22196 22502 sat 32 22197 22503 eat 32 … … 22215 22521 ) 22216 22522 ) 22217 on &4 1822218 ) 22219 *7 49(Wire22523 on &421 22524 ) 22525 *754 (Wire 22220 22526 uid 9397,0 22221 22527 shape (OrthoPolyLine … … 22230 22536 ] 22231 22537 ) 22232 start &3 8922233 end &42 122538 start &392 22539 end &424 22234 22540 sat 32 22235 22541 eat 32 … … 22253 22559 ) 22254 22560 ) 22255 on &42 022256 ) 22257 *75 0(Wire22561 on &423 22562 ) 22563 *755 (Wire 22258 22564 uid 9503,0 22259 22565 shape (OrthoPolyLine … … 22269 22575 ] 22270 22576 ) 22271 start &74 022272 end &42 322577 start &745 22578 end &426 22273 22579 sat 32 22274 22580 eat 32 … … 22291 22597 ) 22292 22598 ) 22293 on &40 422294 ) 22295 *75 1(Wire22599 on &407 22600 ) 22601 *756 (Wire 22296 22602 uid 9539,0 22297 22603 shape (OrthoPolyLine … … 22308 22614 ] 22309 22615 ) 22310 start &42 522311 end &43 522616 start &428 22617 end &438 22312 22618 sat 32 22313 22619 eat 32 … … 22331 22637 ) 22332 22638 ) 22333 on &43 622334 ) 22335 *75 2(Wire22639 on &439 22640 ) 22641 *757 (Wire 22336 22642 uid 9673,0 22337 22643 shape (OrthoPolyLine … … 22347 22653 ] 22348 22654 ) 22349 start &66 322350 end &4 3822655 start &668 22656 end &441 22351 22657 sat 32 22352 22658 eat 32 … … 22369 22675 ) 22370 22676 ) 22371 on &18 422372 ) 22373 *75 3(Wire22677 on &187 22678 ) 22679 *758 (Wire 22374 22680 uid 9741,0 22375 22681 shape (OrthoPolyLine … … 22386 22692 ] 22387 22693 ) 22388 start &72 022389 end &45 122694 start &725 22695 end &454 22390 22696 sat 32 22391 22697 eat 32 … … 22408 22714 ) 22409 22715 ) 22410 on &18 522411 ) 22412 *75 4(Wire22716 on &188 22717 ) 22718 *759 (Wire 22413 22719 uid 9747,0 22414 22720 shape (OrthoPolyLine … … 22425 22731 ] 22426 22732 ) 22427 start &6 6522428 end &46 422733 start &670 22734 end &467 22429 22735 sat 32 22430 22736 eat 32 … … 22447 22753 ) 22448 22754 ) 22449 on &18 222450 ) 22451 *7 55(Wire22755 on &185 22756 ) 22757 *760 (Wire 22452 22758 uid 9755,0 22453 22759 shape (OrthoPolyLine … … 22462 22768 ] 22463 22769 ) 22464 start &44 022465 end &47 622770 start &443 22771 end &479 22466 22772 sat 32 22467 22773 eat 32 … … 22485 22791 ) 22486 22792 ) 22487 on &4 7722488 ) 22489 *7 56(Wire22793 on &480 22794 ) 22795 *761 (Wire 22490 22796 uid 9771,0 22491 22797 shape (OrthoPolyLine … … 22500 22806 ] 22501 22807 ) 22502 start &45 322503 end &4 7822808 start &456 22809 end &481 22504 22810 sat 32 22505 22811 eat 32 … … 22523 22829 ) 22524 22830 ) 22525 on &4 7922526 ) 22527 *7 57(Wire22831 on &482 22832 ) 22833 *762 (Wire 22528 22834 uid 9787,0 22529 22835 shape (OrthoPolyLine … … 22538 22844 ] 22539 22845 ) 22540 start &46 622541 end &48 022846 start &469 22847 end &483 22542 22848 sat 32 22543 22849 eat 32 … … 22561 22867 ) 22562 22868 ) 22563 on &48 122564 ) 22565 *7 58(Wire22869 on &484 22870 ) 22871 *763 (Wire 22566 22872 uid 9943,0 22567 22873 shape (OrthoPolyLine … … 22570 22876 vasetType 3 22571 22877 ) 22572 xt "164750,8 3000,170000,83000"22573 pts [ 22574 "164750,8 3000"22575 "170000,8 3000"22878 xt "164750,82000,170000,82000" 22879 pts [ 22880 "164750,82000" 22881 "170000,82000" 22576 22882 ] 22577 22883 ) … … 22590 22896 va (VaSet 22591 22897 ) 22592 xt "171000,8 3000,174300,84000"22898 xt "171000,82000,174300,83000" 22593 22899 st "ps_reset" 22594 blo "171000,8 3800"22900 blo "171000,82800" 22595 22901 tm "WireNameMgr" 22596 22902 ) 22597 22903 ) 22598 on &48 222599 ) 22600 *7 59(Wire22904 on &485 22905 ) 22906 *764 (Wire 22601 22907 uid 9951,0 22602 22908 shape (OrthoPolyLine … … 22605 22911 vasetType 3 22606 22912 ) 22607 xt "164750,8 5000,170000,85000"22608 pts [ 22609 "164750,8 5000"22610 "170000,8 5000"22913 xt "164750,84000,170000,84000" 22914 pts [ 22915 "164750,84000" 22916 "170000,84000" 22611 22917 ] 22612 22918 ) … … 22625 22931 va (VaSet 22626 22932 ) 22627 xt "171000,8 5000,176000,86000"22933 xt "171000,84000,176000,85000" 22628 22934 st "srclk_enable" 22629 blo "171000,8 5800"22935 blo "171000,84800" 22630 22936 tm "WireNameMgr" 22631 22937 ) 22632 22938 ) 22633 on &48 322634 ) 22635 *76 0(Wire22939 on &486 22940 ) 22941 *765 (Wire 22636 22942 uid 10010,0 22637 22943 shape (OrthoPolyLine … … 22648 22954 ] 22649 22955 ) 22650 start &2 1822651 end &4 8822956 start &221 22957 end &491 22652 22958 sat 32 22653 22959 eat 32 … … 22669 22975 ) 22670 22976 ) 22671 on &50 222672 ) 22673 *76 1(Wire22977 on &505 22978 ) 22979 *766 (Wire 22674 22980 uid 10018,0 22675 22981 shape (OrthoPolyLine … … 22684 22990 ] 22685 22991 ) 22686 end &49 022992 end &493 22687 22993 sat 16 22688 22994 eat 32 … … 22705 23011 ) 22706 23012 ) 22707 on &48 322708 ) 22709 *76 2(Wire23013 on &486 23014 ) 23015 *767 (Wire 22710 23016 uid 10036,0 22711 23017 shape (OrthoPolyLine … … 22720 23026 ] 22721 23027 ) 22722 end &40 023028 end &403 22723 23029 sat 16 22724 23030 eat 32 … … 22739 23045 ) 22740 23046 ) 22741 on &48 222742 ) 22743 *76 3(Wire23047 on &485 23048 ) 23049 *768 (Wire 22744 23050 uid 10194,0 22745 23051 shape (OrthoPolyLine … … 22748 23054 vasetType 3 22749 23055 ) 22750 xt "92750,8 5000,127250,110000"23056 xt "92750,84000,127250,110000" 22751 23057 pts [ 22752 23058 "92750,110000" 22753 "1 25000,110000"22754 "1 25000,85000"22755 "127250,8 5000"22756 ] 22757 ) 22758 start &24 423059 "104000,110000" 23060 "104000,84000" 23061 "127250,84000" 23062 ] 23063 ) 23064 start &247 22759 23065 end &109 22760 23066 ss 0 … … 22779 23085 ) 22780 23086 ) 22781 on &50 322782 ) 22783 *76 4(Wire23087 on &506 23088 ) 23089 *769 (Wire 22784 23090 uid 10202,0 22785 23091 shape (OrthoPolyLine … … 22788 23094 vasetType 3 22789 23095 ) 22790 xt "92750,8 6000,127250,111000"23096 xt "92750,85000,127250,111000" 22791 23097 pts [ 22792 23098 "92750,111000" 22793 "1 26000,111000"22794 "1 26000,86000"22795 "127250,8 6000"22796 ] 22797 ) 22798 start &24 523099 "111000,111000" 23100 "111000,85000" 23101 "127250,85000" 23102 ] 23103 ) 23104 start &248 22799 23105 end &110 22800 23106 sat 32 … … 22817 23123 ) 22818 23124 ) 22819 on &50 422820 ) 22821 *7 65(Wire23125 on &507 23126 ) 23127 *770 (Wire 22822 23128 uid 10266,0 22823 23129 shape (OrthoPolyLine … … 22826 23132 vasetType 3 22827 23133 ) 22828 xt "121000,64000,127250,64000" 22829 pts [ 22830 "127250,64000" 22831 "124000,64000" 22832 "121000,64000" 23134 xt "121000,63000,127250,63000" 23135 pts [ 23136 "127250,63000" 23137 "121000,63000" 22833 23138 ] 22834 23139 ) … … 22847 23152 va (VaSet 22848 23153 ) 22849 xt "122000,6 3000,126800,64000"23154 xt "122000,62000,126800,63000" 22850 23155 st "s_trigger_0" 22851 blo "122000,6 3800"23156 blo "122000,62800" 22852 23157 tm "WireNameMgr" 22853 23158 ) 22854 23159 ) 22855 on &60 322856 ) 22857 *7 66(Wire23160 on &606 23161 ) 23162 *771 (Wire 22858 23163 uid 10298,0 22859 23164 shape (OrthoPolyLine … … 22868 23173 ] 22869 23174 ) 22870 start &22 323175 start &226 22871 23176 end &61 22872 23177 sat 32 … … 22889 23194 ) 22890 23195 ) 22891 on &50 622892 ) 22893 *7 67(Wire23196 on &509 23197 ) 23198 *772 (Wire 22894 23199 uid 10304,0 22895 23200 shape (OrthoPolyLine … … 22904 23209 ] 22905 23210 ) 22906 start &22 123211 start &224 22907 23212 end &62 22908 23213 sat 32 … … 22925 23230 ) 22926 23231 ) 22927 on &5 0722928 ) 22929 *7 68(Wire23232 on &510 23233 ) 23234 *773 (Wire 22930 23235 uid 10310,0 22931 23236 shape (OrthoPolyLine … … 22940 23245 ] 22941 23246 ) 22942 start &22 223247 start &225 22943 23248 end &63 22944 23249 sat 32 … … 22961 23266 ) 22962 23267 ) 22963 on &5 0822964 ) 22965 *7 69(Wire23268 on &511 23269 ) 23270 *774 (Wire 22966 23271 uid 10316,0 22967 23272 shape (OrthoPolyLine … … 22978 23283 ) 22979 23284 start &60 22980 end &2 1923285 end &222 22981 23286 sat 32 22982 23287 eat 32 … … 22999 23304 ) 23000 23305 ) 23001 on &5 0923002 ) 23003 *77 0(Wire23306 on &512 23307 ) 23308 *775 (Wire 23004 23309 uid 10322,0 23005 23310 shape (OrthoPolyLine … … 23014 23319 ] 23015 23320 ) 23016 start &22 023017 end &51 123321 start &223 23322 end &514 23018 23323 sat 32 23019 23324 eat 32 … … 23037 23342 ) 23038 23343 ) 23039 on &51 023040 ) 23041 *77 1(Wire23344 on &513 23345 ) 23346 *776 (Wire 23042 23347 uid 10431,0 23043 23348 shape (OrthoPolyLine … … 23052 23357 ] 23053 23358 ) 23054 end &5 1823359 end &521 23055 23360 es 0 23056 23361 sat 16 … … 23074 23379 ) 23075 23380 ) 23076 on &50 523077 ) 23078 *77 2(Wire23381 on &508 23382 ) 23383 *777 (Wire 23079 23384 uid 10439,0 23080 23385 optionalChildren [ 23081 *77 3(BdJunction23386 *778 (BdJunction 23082 23387 uid 12639,0 23083 23388 ps "OnConnectorStrategy" … … 23106 23411 ) 23107 23412 start &30 23108 end &12 223413 end &125 23109 23414 sat 32 23110 23415 eat 32 … … 23126 23431 ) 23127 23432 ) 23128 on &53 523129 ) 23130 *77 4(Wire23433 on &538 23434 ) 23435 *779 (Wire 23131 23436 uid 10467,0 23132 23437 shape (OrthoPolyLine … … 23143 23448 ] 23144 23449 ) 23145 start &1 4823450 start &151 23146 23451 end &64 23147 23452 es 0 … … 23165 23470 ) 23166 23471 ) 23167 on &53 623168 ) 23169 *7 75(Wire23472 on &539 23473 ) 23474 *780 (Wire 23170 23475 uid 10629,0 23171 23476 shape (OrthoPolyLine … … 23174 23479 vasetType 3 23175 23480 ) 23176 xt "164750,8 9000,174000,89000"23177 pts [ 23178 "164750,8 9000"23179 "174000,8 9000"23481 xt "164750,88000,174000,88000" 23482 pts [ 23483 "164750,88000" 23484 "174000,88000" 23180 23485 ] 23181 23486 ) … … 23194 23499 va (VaSet 23195 23500 ) 23196 xt "166000,8 8000,172500,89000"23501 xt "166000,87000,172500,88000" 23197 23502 st "socks_connected" 23198 blo "166000,8 8800"23503 blo "166000,87800" 23199 23504 tm "WireNameMgr" 23200 23505 ) 23201 23506 ) 23202 on &5 3723203 ) 23204 *7 76(Wire23507 on &540 23508 ) 23509 *781 (Wire 23205 23510 uid 10637,0 23206 23511 shape (OrthoPolyLine … … 23209 23514 vasetType 3 23210 23515 ) 23211 xt "164750, 90000,173000,90000"23212 pts [ 23213 "164750, 90000"23214 "173000, 90000"23516 xt "164750,89000,173000,89000" 23517 pts [ 23518 "164750,89000" 23519 "173000,89000" 23215 23520 ] 23216 23521 ) … … 23229 23534 va (VaSet 23230 23535 ) 23231 xt "166000,8 9000,171500,90000"23536 xt "166000,88000,171500,89000" 23232 23537 st "socks_waiting" 23233 blo "166000,8 9800"23538 blo "166000,88800" 23234 23539 tm "WireNameMgr" 23235 23540 ) 23236 23541 ) 23237 on &5 3823238 ) 23239 *7 77(Wire23542 on &541 23543 ) 23544 *782 (Wire 23240 23545 uid 10685,0 23241 23546 shape (OrthoPolyLine … … 23250 23555 ] 23251 23556 ) 23252 end &55 123557 end &554 23253 23558 sat 16 23254 23559 eat 32 … … 23270 23575 ) 23271 23576 ) 23272 on &5 3823273 ) 23274 *7 78(Wire23577 on &541 23578 ) 23579 *783 (Wire 23275 23580 uid 10691,0 23276 23581 shape (OrthoPolyLine … … 23285 23590 ] 23286 23591 ) 23287 end &55 223592 end &555 23288 23593 sat 16 23289 23594 eat 32 … … 23305 23610 ) 23306 23611 ) 23307 on &5 3723308 ) 23309 *7 79(Wire23612 on &540 23613 ) 23614 *784 (Wire 23310 23615 uid 10699,0 23311 23616 shape (OrthoPolyLine … … 23321 23626 ] 23322 23627 ) 23323 end &54 623628 end &549 23324 23629 sat 16 23325 23630 eat 32 … … 23341 23646 ) 23342 23647 ) 23343 on &18 423344 ) 23345 *78 0(Wire23648 on &187 23649 ) 23650 *785 (Wire 23346 23651 uid 10707,0 23347 23652 shape (OrthoPolyLine … … 23356 23661 ] 23357 23662 ) 23358 end &55 023663 end &553 23359 23664 sat 16 23360 23665 eat 32 … … 23376 23681 ) 23377 23682 ) 23378 on &5 5723379 ) 23380 *78 1(Wire23683 on &560 23684 ) 23685 *786 (Wire 23381 23686 uid 10723,0 23382 23687 shape (OrthoPolyLine … … 23391 23696 ] 23392 23697 ) 23393 start &5 4723394 end &54 023698 start &550 23699 end &543 23395 23700 sat 32 23396 23701 eat 32 … … 23414 23719 ) 23415 23720 ) 23416 on &5 3923417 ) 23418 *78 2(Wire23721 on &542 23722 ) 23723 *787 (Wire 23419 23724 uid 10737,0 23420 23725 shape (OrthoPolyLine … … 23429 23734 ] 23430 23735 ) 23431 start &5 4823432 end &54 223736 start &551 23737 end &545 23433 23738 sat 32 23434 23739 eat 32 … … 23452 23757 ) 23453 23758 ) 23454 on &54 123455 ) 23456 *78 3(Wire23759 on &544 23760 ) 23761 *788 (Wire 23457 23762 uid 10751,0 23458 23763 shape (OrthoPolyLine … … 23467 23772 ] 23468 23773 ) 23469 start &5 4923470 end &54 423774 start &552 23775 end &547 23471 23776 sat 32 23472 23777 eat 32 … … 23490 23795 ) 23491 23796 ) 23492 on &54 323493 ) 23494 *78 4(Wire23797 on &546 23798 ) 23799 *789 (Wire 23495 23800 uid 11405,0 23496 23801 shape (OrthoPolyLine … … 23526 23831 ) 23527 23832 ) 23528 on &5 5723529 ) 23530 *7 85(Wire23833 on &560 23834 ) 23835 *790 (Wire 23531 23836 uid 11858,0 23532 23837 shape (OrthoPolyLine … … 23535 23840 vasetType 3 23536 23841 ) 23537 xt "164750,9 1000,173000,91000"23538 pts [ 23539 "164750,9 1000"23540 "173000,9 1000"23842 xt "164750,90000,173000,90000" 23843 pts [ 23844 "164750,90000" 23845 "173000,90000" 23541 23846 ] 23542 23847 ) … … 23555 23860 va (VaSet 23556 23861 ) 23557 xt "166000, 90000,171800,91000"23862 xt "166000,89000,171800,90000" 23558 23863 st "trigger_enable" 23559 blo "166000, 90800"23864 blo "166000,89800" 23560 23865 tm "WireNameMgr" 23561 23866 ) 23562 23867 ) 23563 on &5 5823564 ) 23565 *7 86(Wire23868 on &561 23869 ) 23870 *791 (Wire 23566 23871 uid 11952,0 23567 23872 shape (OrthoPolyLine … … 23576 23881 ] 23577 23882 ) 23578 end &56 523883 end &568 23579 23884 sat 16 23580 23885 eat 32 … … 23597 23902 ) 23598 23903 ) 23599 on &5 5823600 ) 23601 *7 87(Wire23904 on &561 23905 ) 23906 *792 (Wire 23602 23907 uid 12306,0 23603 23908 shape (OrthoPolyLine … … 23612 23917 ] 23613 23918 ) 23614 start &51 523615 end &56 323919 start &518 23920 end &566 23616 23921 sat 32 23617 23922 eat 32 … … 23635 23940 ) 23636 23941 ) 23637 on &5 7723638 ) 23639 *7 88(Wire23942 on &580 23943 ) 23944 *793 (Wire 23640 23945 uid 12635,0 23641 23946 shape (OrthoPolyLine … … 23651 23956 ] 23652 23957 ) 23653 start &77 323654 end &58 023958 start &778 23959 end &583 23655 23960 sat 32 23656 23961 eat 32 … … 23673 23978 ) 23674 23979 ) 23675 on &53 523676 ) 23677 *7 89(Wire23980 on &538 23981 ) 23982 *794 (Wire 23678 23983 uid 12643,0 23679 23984 shape (OrthoPolyLine … … 23690 23995 ] 23691 23996 ) 23692 start &56 023693 end &5 7923997 start &563 23998 end &582 23694 23999 sat 32 23695 24000 eat 32 … … 23713 24018 ) 23714 24019 ) 23715 on &5 8823716 ) 23717 *79 0(Wire24020 on &591 24021 ) 24022 *795 (Wire 23718 24023 uid 12649,0 23719 24024 shape (OrthoPolyLine … … 23730 24035 ) 23731 24036 start &66 23732 end &58 224037 end &585 23733 24038 sat 32 23734 24039 eat 32 … … 23750 24055 ) 23751 24056 ) 23752 on &5 8923753 ) 23754 *79 1(Wire24057 on &592 24058 ) 24059 *796 (Wire 23755 24060 uid 12655,0 23756 24061 shape (OrthoPolyLine … … 23767 24072 ) 23768 24073 start &67 23769 end &58 324074 end &586 23770 24075 sat 32 23771 24076 eat 32 … … 23787 24092 ) 23788 24093 ) 23789 on &59 023790 ) 23791 *79 2(Wire24094 on &593 24095 ) 24096 *797 (Wire 23792 24097 uid 12667,0 23793 24098 shape (OrthoPolyLine … … 23802 24107 ] 23803 24108 ) 23804 start &58 124109 start &584 23805 24110 sat 32 23806 24111 eat 16 … … 23822 24127 ) 23823 24128 ) 23824 on &32 623825 ) 23826 *79 3(Wire24129 on &329 24130 ) 24131 *798 (Wire 23827 24132 uid 12687,0 23828 24133 shape (OrthoPolyLine … … 23840 24145 ] 23841 24146 ) 23842 end &58 424147 end &587 23843 24148 sat 16 23844 24149 eat 32 … … 23860 24165 ) 23861 24166 ) 23862 on &18 523863 ) 23864 *79 4(Wire24167 on &188 24168 ) 24169 *799 (Wire 23865 24170 uid 12707,0 23866 24171 shape (OrthoPolyLine … … 23875 24180 ] 23876 24181 ) 23877 start &55 323878 end &59 224182 start &556 24183 end &595 23879 24184 sat 32 23880 24185 eat 32 … … 23898 24203 ) 23899 24204 ) 23900 on &59 123901 ) 23902 * 795(Wire24205 on &594 24206 ) 24207 *800 (Wire 23903 24208 uid 13143,0 23904 24209 shape (OrthoPolyLine … … 23913 24218 ] 23914 24219 ) 23915 end &59 424220 end &597 23916 24221 sat 16 23917 24222 eat 32 … … 23933 24238 ) 23934 24239 ) 23935 on &18 523936 ) 23937 * 796(Wire24240 on &188 24241 ) 24242 *801 (Wire 23938 24243 uid 13159,0 23939 24244 shape (OrthoPolyLine … … 23942 24247 vasetType 3 23943 24248 ) 23944 xt "103750,60000,127250,6 5000"23945 pts [ 23946 "127250,6 5000"23947 "1 08000,65000"23948 "1 08000,60000"24249 xt "103750,60000,127250,64000" 24250 pts [ 24251 "127250,64000" 24252 "119000,64000" 24253 "119000,60000" 23949 24254 "103750,60000" 23950 24255 ] 23951 24256 ) 23952 24257 start &114 23953 end &59 524258 end &598 23954 24259 sat 32 23955 24260 eat 32 … … 23965 24270 va (VaSet 23966 24271 ) 23967 xt "119250,6 4000,125850,65000"24272 xt "119250,63000,125850,64000" 23968 24273 st "c_trigger_enable" 23969 blo "119250,6 4800"24274 blo "119250,63800" 23970 24275 tm "WireNameMgr" 23971 24276 ) 23972 24277 ) 23973 on &60 123974 ) 23975 * 797(Wire24278 on &604 24279 ) 24280 *802 (Wire 23976 24281 uid 13165,0 23977 24282 shape (OrthoPolyLine … … 23981 24286 lineWidth 2 23982 24287 ) 23983 xt "103750,61000,127250,6 6000"23984 pts [ 23985 "127250,6 6000"23986 "1 07000,66000"23987 "1 07000,61000"24288 xt "103750,61000,127250,65000" 24289 pts [ 24290 "127250,65000" 24291 "118000,65000" 24292 "118000,61000" 23988 24293 "103750,61000" 23989 24294 ] 23990 24295 ) 23991 24296 start &115 23992 end &59 624297 end &599 23993 24298 sat 32 23994 24299 eat 32 … … 24005 24310 va (VaSet 24006 24311 ) 24007 xt "118250,6 5000,126650,66000"24312 xt "118250,64000,126650,65000" 24008 24313 st "c_trigger_mult : (7:0)" 24009 blo "118250,6 5800"24314 blo "118250,64800" 24010 24315 tm "WireNameMgr" 24011 24316 ) 24012 24317 ) 24013 on &60 224014 ) 24015 * 798(Wire24318 on &605 24319 ) 24320 *803 (Wire 24016 24321 uid 13210,0 24017 24322 shape (OrthoPolyLine … … 24026 24331 ] 24027 24332 ) 24028 start & 59724029 end &60 624333 start &600 24334 end &609 24030 24335 sat 32 24031 24336 eat 32 … … 24047 24352 ) 24048 24353 ) 24049 on &60 424050 ) 24051 * 799(Wire24354 on &607 24355 ) 24356 *804 (Wire 24052 24357 uid 13216,0 24053 24358 shape (OrthoPolyLine … … 24062 24367 ] 24063 24368 ) 24064 end &61 124369 end &614 24065 24370 sat 16 24066 24371 eat 32 … … 24084 24389 ) 24085 24390 ) 24086 on &60 324087 ) 24088 *80 0(Wire24391 on &606 24392 ) 24393 *805 (Wire 24089 24394 uid 13224,0 24090 24395 shape (OrthoPolyLine … … 24099 24404 ] 24100 24405 ) 24101 start &6 0824406 start &611 24102 24407 sat 32 24103 24408 eat 16 … … 24121 24426 ) 24122 24427 ) 24123 on &505 24428 on &508 24429 ) 24430 *806 (Wire 24431 uid 13695,0 24432 shape (OrthoPolyLine 24433 uid 13696,0 24434 va (VaSet 24435 vasetType 3 24436 lineWidth 2 24437 ) 24438 xt "127000,92000,127250,92000" 24439 pts [ 24440 "127000,92000" 24441 "127250,92000" 24442 ] 24443 ) 24444 start &631 24445 end &116 24446 sat 32 24447 eat 32 24448 sty 1 24449 st 0 24450 sf 1 24451 si 0 24452 tg (WTG 24453 uid 13699,0 24454 ps "ConnStartEndStrategy" 24455 stg "STSignalDisplayStrategy" 24456 f (Text 24457 uid 13700,0 24458 va (VaSet 24459 isHidden 1 24460 ) 24461 xt "129000,91000,134500,92000" 24462 st "D_T_in : (1:0)" 24463 blo "129000,91800" 24464 tm "WireNameMgr" 24465 ) 24466 ) 24467 on &632 24468 ) 24469 *807 (Wire 24470 uid 13921,0 24471 shape (OrthoPolyLine 24472 uid 13922,0 24473 va (VaSet 24474 vasetType 3 24475 lineWidth 2 24476 ) 24477 xt "119000,93000,127250,93000" 24478 pts [ 24479 "119000,93000" 24480 "127250,93000" 24481 ] 24482 ) 24483 end &117 24484 sat 16 24485 eat 32 24486 sty 1 24487 st 0 24488 sf 1 24489 si 0 24490 tg (WTG 24491 uid 13925,0 24492 ps "ConnStartEndStrategy" 24493 stg "STSignalDisplayStrategy" 24494 f (Text 24495 uid 13926,0 24496 va (VaSet 24497 ) 24498 xt "120000,92000,125900,93000" 24499 st "board_id : (3:0)" 24500 blo "120000,92800" 24501 tm "WireNameMgr" 24502 ) 24503 ) 24504 on &71 24505 ) 24506 *808 (Wire 24507 uid 13929,0 24508 shape (OrthoPolyLine 24509 uid 13930,0 24510 va (VaSet 24511 vasetType 3 24512 lineWidth 2 24513 ) 24514 xt "119000,94000,127250,94000" 24515 pts [ 24516 "119000,94000" 24517 "127250,94000" 24518 ] 24519 ) 24520 end &118 24521 sat 16 24522 eat 32 24523 sty 1 24524 st 0 24525 sf 1 24526 si 0 24527 tg (WTG 24528 uid 13933,0 24529 ps "ConnStartEndStrategy" 24530 stg "STSignalDisplayStrategy" 24531 f (Text 24532 uid 13934,0 24533 va (VaSet 24534 ) 24535 xt "120000,93000,125700,94000" 24536 st "crate_id : (1:0)" 24537 blo "120000,93800" 24538 tm "WireNameMgr" 24539 ) 24540 ) 24541 on &122 24124 24542 ) 24125 24543 ] … … 24135 24553 color "26368,26368,26368" 24136 24554 ) 24137 packageList *80 1(PackageList24555 packageList *809 (PackageList 24138 24556 uid 41,0 24139 24557 stg "VerticalLayoutStrategy" 24140 24558 textVec [ 24141 *8 02(Text24559 *810 (Text 24142 24560 uid 42,0 24143 24561 va (VaSet … … 24148 24566 blo "-87000,1800" 24149 24567 ) 24150 *8 03(MLText24568 *811 (MLText 24151 24569 uid 43,0 24152 24570 va (VaSet … … 24173 24591 stg "VerticalLayoutStrategy" 24174 24592 textVec [ 24175 *8 04(Text24593 *812 (Text 24176 24594 uid 45,0 24177 24595 va (VaSet … … 24183 24601 blo "20000,800" 24184 24602 ) 24185 *8 05(Text24603 *813 (Text 24186 24604 uid 46,0 24187 24605 va (VaSet … … 24193 24611 blo "20000,1800" 24194 24612 ) 24195 *8 06(MLText24613 *814 (MLText 24196 24614 uid 47,0 24197 24615 va (VaSet … … 24203 24621 tm "BdCompilerDirectivesTextMgr" 24204 24622 ) 24205 *8 07(Text24623 *815 (Text 24206 24624 uid 48,0 24207 24625 va (VaSet … … 24213 24631 blo "20000,4800" 24214 24632 ) 24215 *8 08(MLText24633 *816 (MLText 24216 24634 uid 49,0 24217 24635 va (VaSet … … 24221 24639 tm "BdCompilerDirectivesTextMgr" 24222 24640 ) 24223 *8 09(Text24641 *817 (Text 24224 24642 uid 50,0 24225 24643 va (VaSet … … 24231 24649 blo "20000,5800" 24232 24650 ) 24233 *81 0(MLText24651 *818 (MLText 24234 24652 uid 51,0 24235 24653 va (VaSet … … 24243 24661 ) 24244 24662 windowSize "0,0,1281,1024" 24245 viewArea " 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