Changeset 10127

Timestamp:

02/03/11 10:51:52 (14 years ago)

Author:

weitzel

Message:

ftm library file added and small bug fix in FTM test bench

Location:

firmware/FTM

Files:

• FTM_top_tb.vhd (modified) (2 diffs)
• ftm_definitions.vhd (added)

firmware/FTM/FTM_top_tb.vhd

@@ -34 +34 @@
 use UNISIM.VComponents.all;
 
-entity FTU_top_tb is
-end FTU_top_tb;
-
-architecture behavior of FTU_top_tb is 
+entity FTM_top_tb is
+end FTM_top_tb;
+
+architecture behavior of FTM_top_tb is 
 
   -- Component Declaration for the Unit Under Test (UUT)
@@ -353 +353 @@
   uut: FTM_top
     port map(     
-      clk           =>clk_sig,
-      W_D           =>W_D_sig,
-      W_A           =>W_A_sig,
-      W_CS          =>W_CS_sig,
-      W_INT         =>W_INT_sig,
-      W_RD          =>W_RD_sig,
-      W_WR          =>W_WR_sig,
-      W_RES         =>W_RES_sig,
-      W_BRDY        =>W_BRDY_sig, 
-      W_T           =>W_T_sig,  
-      S_CLK         =>S_CLK_sig,
-      SIO           =>SIO_sig,
-      TS_CS         =>TS_CS_sig,
-      Trig_Prim_A   =>Trig_Prim_A_sig,
-      Trig_Prim_B   =>Trig_Prim_B_sig,
-      Trig_Prim_C   =>Trig_Prim_C_sig,
-      Trig_Prim_D   =>Trig_Prim_D_sig,
-      ext_Trig      =>ext_Trig_sig,
-      Veto          =>Veto_sig, 
-      NIM_In        =>NIM_In_sig, 
-      NIM_In3_GCLK  =>NIM_In3_GCLK_sig, 
-      LED_red       =>LED_red_sig,
-      LED_ye        =>LED_ye_sig,
-      LED_gn        =>LED_gn_sig,
-      CLK_Clk_Cond  =>CLK_Clk_Cond_sig,
-      LE_Clk_Cond   =>LE_Clk_Cond_sig,
-      DATA_Clk_Cond =>DATA_Clk_Cond_sig,
-      SYNC_Clk_Cond =>SYNC_Clk_Cond_sig,
-      LD_Clk_Cond   =>LD_Clk_Cond_sig,               
-      Bus1_Tx_En    =>Bus1_Tx_En_sig,                               
-      Bus1_Rx_En    =>Bus1_Rx_En_sig,
-      Bus1_RxD_0    =>Bus1_RxD_0_sig,
-      Bus1_TxD_0    =>Bus1_TxD_0_sig,
-      Bus1_RxD_1    =>Bus1_RxD_1_sig,
-      Bus1_TxD_1    =>Bus1_TxD_1_sig,
-      Bus1_RxD_2    =>Bus1_RxD_2_sig,
-      Bus1_TxD_2    =>Bus1_TxD_2_sig,
-      Bus1_RxD_3    =>Bus1_RxD_3_sig,
-      Bus1_TxD_3    =>Bus1_TxD_3_sig,  
-      Bus2_Tx_En    =>Bus2_Tx_En_sig,                               
-      Bus2_Rx_En    =>Bus2_Rx_En_sig,
-      Bus2_RxD_0    =>Bus2_RxD_0_sig,
-      Bus2_TxD_0    =>Bus2_TxD_0_sig,
-      Bus2_RxD_1    =>Bus2_RxD_1_sig,
-      Bus2_TxD_1    =>Bus2_TxD_1_sig,
-      Bus2_RxD_2    =>Bus2_RxD_2_sig,
-      Bus2_TxD_2    =>Bus2_TxD_2_sig,
-      Bus2_RxD_3    =>Bus2_RxD_3_sig,
-      Bus2_TxD_3    =>Bus2_TxD_3_sig,
-      Crate_Res0    =>Crate_Res0_sig,
-      Crate_Res1    =>Crate_Res1_sig,
-      Crate_Res2    =>Crate_Res2_sig,
-      Crate_Res3    =>Crate_Res3_sig,
-      Busy0         =>Busy0_sig,
-      Busy1         =>Busy1_sig,
-      Busy2         =>Busy2_sig,
-      Busy3         =>Busy3_sig,
-      RES_p         =>RES_p_sig,
-      RES_n         =>RES_n_sig,
-      TRG_p         =>TRG_p_sig,
-      TRG_n         =>TRG_n_sig,
-      TIM_Run_p     =>TIM_Run_p_sig,
-      TIM_Run_n     =>TIM_Run_n_sig,
-      TIM_Sel       =>TIM_Sel_sig,
-      Cal_0_p       =>Cal_0_p_sig,  
-      Cal_0_n       =>Cal_0_n_sig,
-      Cal_1_p       =>Cal_1_p_sig,
-      Cal_1_n       =>Cal_1_n_sig,
-      Cal_2_p       =>Cal_2_p_sig,
-      Cal_2_n       =>Cal_2_n_sig,
-      Cal_3_p       =>Cal_3_p_sig,
-      Cal_3_n       =>Cal_3_n_sig,
-      Cal_4_p       =>Cal_4_p_sig,
-      Cal_4_n       =>Cal_4_n_sig,
-      Cal_5_p       =>Cal_5_p_sig,
-      Cal_5_n       =>Cal_5_n_sig,
-      Cal_6_p       =>Cal_6_p_sig,
-      Cal_6_n       =>Cal_6_n_sig, 
-      Cal_7_p       =>Cal_7_p_sig,
-      Cal_7_n       =>Cal_7_n_sig  
+      clk           => clk_sig,
+      W_D           => W_D_sig,
+      W_A           => W_A_sig,
+      W_CS          => W_CS_sig,
+      W_INT         => W_INT_sig,
+      W_RD          => W_RD_sig,
+      W_WR          => W_WR_sig,
+      W_RES         => W_RES_sig,
+      W_BRDY        => W_BRDY_sig, 
+      W_T           => W_T_sig,  
+      S_CLK         => S_CLK_sig,
+      SIO           => SIO_sig,
+      TS_CS         => TS_CS_sig,
+      Trig_Prim_A   => Trig_Prim_A_sig,
+      Trig_Prim_B   => Trig_Prim_B_sig,
+      Trig_Prim_C   => Trig_Prim_C_sig,
+      Trig_Prim_D   => Trig_Prim_D_sig,
+      ext_Trig      => ext_Trig_sig,
+      Veto          => Veto_sig, 
+      NIM_In        => NIM_In_sig, 
+      NIM_In3_GCLK  => NIM_In3_GCLK_sig, 
+      LED_red       => LED_red_sig,
+      LED_ye        => LED_ye_sig,
+      LED_gn        => LED_gn_sig,
+      CLK_Clk_Cond  => CLK_Clk_Cond_sig,
+      LE_Clk_Cond   => LE_Clk_Cond_sig,
+      DATA_Clk_Cond => DATA_Clk_Cond_sig,
+      SYNC_Clk_Cond => SYNC_Clk_Cond_sig,
+      LD_Clk_Cond   => LD_Clk_Cond_sig,               
+      Bus1_Tx_En    => Bus1_Tx_En_sig,                               
+      Bus1_Rx_En    => Bus1_Rx_En_sig,
+      Bus1_RxD_0    => Bus1_RxD_0_sig,
+      Bus1_TxD_0    => Bus1_TxD_0_sig,
+      Bus1_RxD_1    => Bus1_RxD_1_sig,
+      Bus1_TxD_1    => Bus1_TxD_1_sig,
+      Bus1_RxD_2    => Bus1_RxD_2_sig,
+      Bus1_TxD_2    => Bus1_TxD_2_sig,
+      Bus1_RxD_3    => Bus1_RxD_3_sig,
+      Bus1_TxD_3    => Bus1_TxD_3_sig,  
+      Bus2_Tx_En    => Bus2_Tx_En_sig,                               
+      Bus2_Rx_En    => Bus2_Rx_En_sig,
+      Bus2_RxD_0    => Bus2_RxD_0_sig,
+      Bus2_TxD_0    => Bus2_TxD_0_sig,
+      Bus2_RxD_1    => Bus2_RxD_1_sig,
+      Bus2_TxD_1    => Bus2_TxD_1_sig,
+      Bus2_RxD_2    => Bus2_RxD_2_sig,
+      Bus2_TxD_2    => Bus2_TxD_2_sig,
+      Bus2_RxD_3    => Bus2_RxD_3_sig,
+      Bus2_TxD_3    => Bus2_TxD_3_sig,
+      Crate_Res0    => Crate_Res0_sig,
+      Crate_Res1    => Crate_Res1_sig,
+      Crate_Res2    => Crate_Res2_sig,
+      Crate_Res3    => Crate_Res3_sig,
+      Busy0         => Busy0_sig,
+      Busy1         => Busy1_sig,
+      Busy2         => Busy2_sig,
+      Busy3         => Busy3_sig,
+      RES_p         => RES_p_sig,
+      RES_n         => RES_n_sig,
+      TRG_p         => TRG_p_sig,
+      TRG_n         => TRG_n_sig,
+      TIM_Run_p     => TIM_Run_p_sig,
+      TIM_Run_n     => TIM_Run_n_sig,
+      TIM_Sel       => TIM_Sel_sig,
+      Cal_0_p       => Cal_0_p_sig,  
+      Cal_0_n       => Cal_0_n_sig,
+      Cal_1_p       => Cal_1_p_sig,
+      Cal_1_n       => Cal_1_n_sig,
+      Cal_2_p       => Cal_2_p_sig,
+      Cal_2_n       => Cal_2_n_sig,
+      Cal_3_p       => Cal_3_p_sig,
+      Cal_3_n       => Cal_3_n_sig,
+      Cal_4_p       => Cal_4_p_sig,
+      Cal_4_n       => Cal_4_n_sig,
+      Cal_5_p       => Cal_5_p_sig,
+      Cal_5_n       => Cal_5_n_sig,
+      Cal_6_p       => Cal_6_p_sig,
+      Cal_6_n       => Cal_6_n_sig, 
+      Cal_7_p       => Cal_7_p_sig,
+      Cal_7_n       => Cal_7_n_sig  
     );