Changeset 10129


Ignore:
Timestamp:
02/04/11 14:35:11 (11 years ago)
Author:
neise
Message:
checking before change of Event Header structure.
added REFCLK counter and ADC CLK PS output.
In case of missing REFCLK, DENEABLE should be pulled low.
(untested)
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS
Files:
15 added
1 deleted
39 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

    r10121 r10129  
    44FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
    55FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
    6 secureip = D:\unisim/secureip
    7 simprim = D:\unisim/simprim
    8 unimacro = D:\unisim/unimacro
    9 unisim = D:\unisim/unisim
    10 XilinxCoreLib = D:\unisim/xilinxcorelib
     6secureip = D:/unisim/secureip
     7simprim = D:/unisim/simprim
     8unimacro = D:/unisim/unimacro
     9unisim = D:/unisim/unisim
     10XilinxCoreLib = D:/unisim/xilinxcorelib
    1111[QuestaSim]
    12 secureip = D:\unisim/secureip
    13 simprim = D:\unisim/simprim
    14 unimacro = D:\unisim/unimacro
    15 unisim = D:\unisim/unisim
    16 XilinxCoreLib = D:\unisim/xilinxcorelib
     12secureip = D:/unisim/secureip
     13simprim = D:/unisim/simprim
     14unimacro = D:/unisim/unimacro
     15unisim = D:/unisim/unisim
     16XilinxCoreLib = D:/unisim/xilinxcorelib
    1717[XilinxISE]
    1818FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
     19FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\ise
    1920[hdl]
    2021FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd

    r9912 r10129  
    3636 
    3737BEGIN
    38  
     38  sio <= 'Z';
    3939  spi_cnt_proc: process (sclk)
    4040  begin
     
    5353      sio <= 'Z';
    5454      if (spi_cycle_cnt = 1) then
    55         data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000";
     55        --data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000";
     56        data <= X"A059";
    5657      end if;
    5758      if (spi_cycle_cnt > 7) then
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak

    r9912 r10129  
    2020   );
    2121   PORT(
    22       sclk      : IN     std_logic;
    23       sio       : INOUT  std_logic;
    24       sensor_cs : IN     std_logic_vector (3 DOWNTO 0)
     22      sclk      : in     std_logic;
     23      sio       : inout  std_logic;
     24      sensor_cs : in     std_logic_vector (3 DOWNTO 0)
    2525   );
    2626
     
    3636 
    3737BEGIN
    38  
     38  sio <= 'Z';
    3939  spi_cnt_proc: process (sclk)
    4040  begin
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd

    r10123 r10129  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 09:36:36 27.01.2011
     5--          at - 15:27:49 04.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    1313ENTITY clock_generator_var_ps IS
    1414   PORT(
    15       CLK             : IN     std_logic;
    16       RST_IN          : IN     std_logic;
    17       direction       : IN     std_logic;
    18       do_shift        : IN     std_logic;
    19       CLK_25          : OUT    std_logic;
    20       CLK_25_PS       : OUT    std_logic;
    21       CLK_50          : OUT    std_logic;
    22       DCM_locked      : OUT    std_logic;
    23       LOCKED_extraOUT : OUT    std_logic;
    24       PSCLK_OUT       : OUT    std_logic;
    25       PSDONE_extraOUT : OUT    std_logic;
    26       PSINCDEC_OUT    : OUT    std_logic;
    27       offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    28       ready           : OUT    std_logic                     := '0';
    29       -- status:
    30       shifting        : OUT    std_logic                     := '0'
     15      CLK       : IN     std_logic;
     16      RST_IN    : IN     std_logic;
     17      direction : IN     std_logic;
     18      do_shift  : IN     std_logic;
     19      CLK_25    : OUT    std_logic;
     20      CLK_25_PS : OUT    std_logic;
     21      CLK_50    : OUT    std_logic;
     22      offset    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    3123   );
    3224
     
    4032-- Created:
    4133--          by - dneise.UNKNOWN (E5B-LABOR6)
    42 --          at - 09:36:36 27.01.2011
     34--          at - 15:27:49 04.02.2011
    4335--
    4436-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    9991   PORT (
    10092      CLK         : IN     std_logic ;
     93      rst         : IN     std_logic ;                                     --asynch in of DCM
    10194      -- interface to: clock_generator_variable_PS_struct.vhd
    10295      PSCLK       : OUT    std_logic ;
     
    127120BEGIN
    128121
    129    -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
    130    PSCLK_OUT <= PSCLK_IN;
    131 
    132    -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
    133    PSINCDEC_OUT <= PSINCDEC_IN;
    134 
    135    -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
    136    PSDONE_extraOUT <= PSDONE_OUT;
    137 
    138    -- ModuleWare code(v1.9) for instance 'U_9' of 'assignment'
    139    LOCKED_extraOUT <= LOCKED_OUT;
    140 
    141122   -- Instance port mappings.
    142123   U_0 : dcm_50_to_25
     
    166147      PORT MAP (
    167148         CLK         => CLK0_OUT,
     149         rst         => RST_IN,
    168150         PSCLK       => PSCLK_IN,
    169151         PSEN        => PSEN_IN,
     
    173155         shift_phase => do_shift,
    174156         direction   => direction,
    175          shifting    => shifting,
    176          ready       => ready,
     157         shifting    => OPEN,
     158         ready       => OPEN,
    177159         offset      => offset,
    178          DCM_locked  => DCM_locked
     160         DCM_locked  => OPEN
    179161      );
    180162
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd

    r10072 r10129  
    2424      clk               : IN     std_logic;
    2525      ram_data_out      : IN     std_logic_vector (15 DOWNTO 0);
    26       config_ready, config_started : OUT    std_logic := '0';
     26      config_ready      : OUT    std_logic := '0';
     27      config_started    : OUT    std_logic := '0';
    2728      config_start      : IN     std_logic;
    2829      config_data       : INOUT  std_logic_vector (15 DOWNTO 0) := (others => 'Z');
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd

    r10121 r10129  
    22--
    33-- Created:
    4 --          by - daqct3.UNKNOWN (IHP110)
    5 --          at - 12:52:19 06.01.2011
     4--          by - dneise.UNKNOWN (E5B-LABOR6)
     5--          at - 11:39:13 04.02.2011
    66--
    7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    88--
    99LIBRARY ieee;
     
    4141--
    4242-- Created:
    43 --          by - daqct3.UNKNOWN (IHP110)
    44 --          at - 12:52:20 06.01.2011
     43--          by - dneise.UNKNOWN (E5B-LABOR6)
     44--          at - 11:39:13 04.02.2011
    4545--
    46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     46-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    4747--
    4848LIBRARY ieee;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf

    r10123 r10129  
    125125NET RSRLOAD LOC  = H1 | IOSTANDARD=LVCMOS25;            #ok
    126126#
    127 NET D0_SRCLK LOC  = F2 | IOSTANDARD=LVCMOS25;           #ok
    128 NET D1_SRCLK LOC  = F3 | IOSTANDARD=LVCMOS25;           #ok
    129 NET D2_SRCLK LOC  = R3 | IOSTANDARD=LVCMOS25;           #ok
    130 NET D3_SRCLK LOC  = V1 | IOSTANDARD=LVCMOS25;           #ok
     127NET DSRCLK<0> LOC  = F2 | IOSTANDARD=LVCMOS25;          #ok
     128NET DSRCLK<1> LOC  = F3 | IOSTANDARD=LVCMOS25;          #ok
     129NET DSRCLK<2> LOC  = R3 | IOSTANDARD=LVCMOS25;          #ok
     130NET DSRCLK<3> LOC  = V1 | IOSTANDARD=LVCMOS25;          #ok
    131131
    132132# Testpoints near DRS Chips
     
    138138NET D_T<4> LOC  = K5 | IOSTANDARD=LVCMOS25;                     #ok
    139139NET D_T<5> LOC  = L4 | IOSTANDARD=LVCMOS25;                     #ok
    140 NET D_T_in<0> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                 #ok was: NET D_T<6> LOC  = M3
    141 NET D_T_in<1> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                 #ok was: NET D_T<7> LOC  = T3
    142 #NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;                    #ok
    143 #NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;                    #ok
     140#NET D_T_in<0> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                        #ok was: NET D_T<6> LOC  = M3
     141#NET D_T_in<1> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                        #ok was: NET D_T<7> LOC  = T3
     142NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;                     #ok
     143NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;                     #ok
    144144NET D_T2<0> LOC  = U2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<8>
    145145NET D_T2<1> LOC  = V2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<9>
    146 NET D_T2<2> LOC  = W3 | IOSTANDARD=LVCMOS25;            #ok aka D_TA  was D_T<10>
    147 NET D_T2<3> LOC  = AA3 | IOSTANDARD=LVCMOS25;           #ok aka D_TB  was D_T<11>
    148 
    149 
     146#NET D_T2<2> LOC  = W3 | IOSTANDARD=LVCMOS25;           #ok aka D_TA  was D_T<10>
     147#NET D_T2<3> LOC  = AA3 | IOSTANDARD=LVCMOS25;          #ok aka D_TB  was D_T<11>
     148NET D_T_in<0> LOC  = W3 | IOSTANDARD=LVCMOS25 | pullup;         #ok aka D_TA  was D_T<10>
     149NET D_T_in<1> LOC  = AA3 | IOSTANDARD=LVCMOS25 | pullup;                #ok aka D_TB  was D_T<11>
    150150
    151151# ADC Signals
     
    244244NET MISO LOC  = C12 | IOSTANDARD=LVCMOS33;                      #ok
    245245
    246 NET T0_CS LOC  = C15 | IOSTANDARD=LVCMOS33;                     #ok
    247 NET T1_CS LOC  = C16 | IOSTANDARD=LVCMOS33;                     #ok
    248 NET T2_CS LOC  = C17 | IOSTANDARD=LVCMOS33;                     #ok
    249 NET T3_CS LOC  = C18 | IOSTANDARD=LVCMOS33;                     #ok
     246NET TCS<0> LOC  = C15 | IOSTANDARD=LVCMOS33;                    #ok
     247NET TCS<1> LOC  = C16 | IOSTANDARD=LVCMOS33;                    #ok
     248NET TCS<2> LOC  = C17 | IOSTANDARD=LVCMOS33;                    #ok
     249NET TCS<3> LOC  = C18 | IOSTANDARD=LVCMOS33;                    #ok
    250250NET DAC_CS LOC  = C20 | IOSTANDARD=LVCMOS33;            #ok
    251251NET EE_CS LOC  = C21 | IOSTANDARD=LVCMOS33;             #ok
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak

    r10123 r10129  
    140140#NET D_T_in<0> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                        #ok was: NET D_T<6> LOC  = M3
    141141#NET D_T_in<1> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                        #ok was: NET D_T<7> LOC  = T3
    142 NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25 | pullup;                    #ok
    143 NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25 | pullup;                    #ok
     142NET D_T<6> LOC  = M3 | IOSTANDARD=LVCMOS25;                     #ok
     143NET D_T<7> LOC  = T3 | IOSTANDARD=LVCMOS25;                     #ok
    144144NET D_T2<0> LOC  = U2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<8>
    145145NET D_T2<1> LOC  = V2 | IOSTANDARD=LVCMOS25;                    #ok  was D_T<9>
    146 NET D_T2<2> LOC  = W3 | IOSTANDARD=LVCMOS25;            #ok aka D_TA  was D_T<10>
    147 NET D_T2<3> LOC  = AA3 | IOSTANDARD=LVCMOS25;           #ok aka D_TB  was D_T<11>
    148 
    149 
     146#NET D_T2<2> LOC  = W3 | IOSTANDARD=LVCMOS25;           #ok aka D_TA  was D_T<10>
     147#NET D_T2<3> LOC  = AA3 | IOSTANDARD=LVCMOS25;          #ok aka D_TB  was D_T<11>
     148NET D_T_in<0> LOC  = W3 | IOSTANDARD=LVCMOS25 | pullup;         #ok aka D_TA  was D_T<10>
     149NET D_T_in<1> LOC  = AA3 | IOSTANDARD=LVCMOS25 | pullup;                #ok aka D_TB  was D_T<11>
    150150
    151151# ADC Signals
     
    244244NET MISO LOC  = C12 | IOSTANDARD=LVCMOS33;                      #ok
    245245
    246 NET T0_CS LOC  = C15 | IOSTANDARD=LVCMOS33;                     #ok
    247 NET T1_CS LOC  = C16 | IOSTANDARD=LVCMOS33;                     #ok
    248 NET T2_CS LOC  = C17 | IOSTANDARD=LVCMOS33;                     #ok
    249 NET T3_CS LOC  = C18 | IOSTANDARD=LVCMOS33;                     #ok
     246NET TCS<0> LOC  = C15 | IOSTANDARD=LVCMOS33;                    #ok
     247NET TCS<1> LOC  = C16 | IOSTANDARD=LVCMOS33;                    #ok
     248NET TCS<2> LOC  = C17 | IOSTANDARD=LVCMOS33;                    #ok
     249NET TCS<3> LOC  = C18 | IOSTANDARD=LVCMOS33;                    #ok
    250250NET DAC_CS LOC  = C20 | IOSTANDARD=LVCMOS33;            #ok
    251251NET EE_CS LOC  = C21 | IOSTANDARD=LVCMOS33;             #ok
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10123 r10129  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:58:59 27.01.2011
     5--          at - 15:27:51 04.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    2828      RS485_C_DI : IN     std_logic;
    2929      RS485_E_DI : IN     std_logic;
    30       RS485_E_DO : IN     std_logic;
    3130      TRG        : IN     STD_LOGIC;
    3231      W_INT      : IN     std_logic;
     
    3635      AMBER_LED  : OUT    std_logic;
    3736      A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
    38       D0_SRCLK   : OUT    STD_LOGIC;
    39       D1_SRCLK   : OUT    STD_LOGIC;
    40       D2_SRCLK   : OUT    STD_LOGIC;
    41       D3_SRCLK   : OUT    STD_LOGIC;
    4237      DAC_CS     : OUT    std_logic;
    4338      DENABLE    : OUT    std_logic                     := '0';
     39      DSRCLK     : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    4440      DWRITE     : OUT    std_logic                     := '0';
    4541      D_A        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    46       D_T        : OUT    std_logic_vector (5 DOWNTO 0) := (OTHERS => '0');
    47       D_T2       : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     42      D_T        : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     43      D_T2       : OUT    std_logic_vector (1 DOWNTO 0) := (others => '0');
    4844      EE_CS      : OUT    std_logic;
    4945      GREEN_LED  : OUT    std_logic;
     
    5551      RS485_C_RE : OUT    std_logic;
    5652      RS485_E_DE : OUT    std_logic;
     53      RS485_E_DO : OUT    std_logic;
    5754      RS485_E_RE : OUT    std_logic;
    5855      RSRLOAD    : OUT    std_logic                     := '0';
    5956      SRIN       : OUT    std_logic                     := '0';
    6057      S_CLK      : OUT    std_logic;
    61       T0_CS      : OUT    std_logic;
    62       T1_CS      : OUT    std_logic;
    63       T2_CS      : OUT    std_logic;
    64       T3_CS      : OUT    std_logic;
     58      TCS        : OUT    std_logic_vector (3 DOWNTO 0);
    6559      TRG_V      : OUT    std_logic;
    6660      W_A        : OUT    std_logic_vector (9 DOWNTO 0);
     
    8276-- Created:
    8377--          by - dneise.UNKNOWN (E5B-LABOR6)
    84 --          at - 17:58:59 27.01.2011
     78--          at - 15:27:51 04.02.2011
    8579--
    8680-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    10296
    10397   -- Internal signal declarations
    104    SIGNAL CLK25_OUT       : std_logic;
    105    SIGNAL CLK25_PSOUT     : std_logic;
    106    SIGNAL CLK50_OUT       : std_logic;
    107    SIGNAL CLK_25_PS       : std_logic;
    108    SIGNAL CLK_25_PS1      : std_logic;
    109    SIGNAL CLK_50          : std_logic;
    110    SIGNAL DCM_locked      : std_logic;
    111    SIGNAL LOCKED_extraOUT : std_logic;
    112    SIGNAL PSCLK_OUT       : std_logic;
    113    SIGNAL PSDONE_extraOUT : std_logic;
    114    SIGNAL PSINCDEC_OUT    : std_logic;
    115    SIGNAL PS_DIR_IN       : std_logic;
    116    SIGNAL SRCLK           : std_logic                    := '0';
    117    SIGNAL adc_clk_en      : std_logic                    := '0';
    118    SIGNAL adc_data_array  : adc_data_array_type;
    119    SIGNAL board_id        : std_logic_vector(3 DOWNTO 0);
    120    SIGNAL crate_id        : std_logic_vector(1 DOWNTO 0);
    121    SIGNAL drs_channel_id  : std_logic_vector(3 DOWNTO 0) := (others => '0');
    122    SIGNAL dummy           : std_logic;
    123    SIGNAL led             : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
    124    SIGNAL ready           : std_logic                    := '0';
    125    SIGNAL sensor_cs       : std_logic_vector(3 DOWNTO 0);
    126    -- status:
    127    SIGNAL shifting        : std_logic                    := '0';
    128 
    129    -- Implicit buffer signal declarations
    130    SIGNAL SRIN_internal : std_logic;
     98   SIGNAL CLK_25_PS             : std_logic;
     99   SIGNAL CLK_25_PS1            : std_logic;
     100   SIGNAL CLK_50                : std_logic;
     101   SIGNAL SRCLK                 : std_logic                     := '0';
     102   SIGNAL adc_clk_en            : std_logic                     := '0';
     103   SIGNAL adc_data_array        : adc_data_array_type;
     104   SIGNAL alarm_refclk_too_high : std_logic                     := '0';
     105   SIGNAL alarm_refclk_too_low  : std_logic                     := '0';
     106   SIGNAL board_id              : std_logic_vector(3 DOWNTO 0);
     107   SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0) := (others => '0');
     108   SIGNAL crate_id              : std_logic_vector(1 DOWNTO 0);
     109   SIGNAL led                   : std_logic_vector(7 DOWNTO 0)  := (OTHERS => '0');
    131110
    132111
     
    147126      board_id               : IN     std_logic_vector (3 DOWNTO 0);
    148127      crate_id               : IN     std_logic_vector (1 DOWNTO 0);
     128      drs_refclk_in          : IN     std_logic ;                                      -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit
     129      plllock_in             : IN     std_logic_vector (3 DOWNTO 0);                   -- high level, if dominowave is running and DRS PLL locked
    149130      trigger                : IN     std_logic ;
    150131      wiz_int                : IN     std_logic ;
    151       CLK25_OUT              : OUT    std_logic ;
    152       CLK25_PSOUT            : OUT    std_logic ;
    153       CLK50_OUT              : OUT    std_logic ;
    154132      CLK_25_PS              : OUT    std_logic ;
    155133      CLK_50                 : OUT    std_logic ;
    156       DCM_locked             : OUT    std_logic ;
    157       LOCKED_extraOUT        : OUT    std_logic ;
    158       PSCLK_OUT              : OUT    std_logic ;
    159       PSDONE_extraOUT        : OUT    std_logic ;
    160       PSINCDEC_OUT           : OUT    std_logic ;
    161       PS_DIR_IN              : OUT    std_logic ;
    162       RSRLOAD                : OUT    std_logic                     := '0';
    163       SRCLK                  : OUT    std_logic                     := '0';
    164       SRIN_out               : OUT    std_logic                     := '0';
    165       adc_clk_en             : OUT    std_logic                     := '0';
    166       adc_oeb                : OUT    std_logic                     := '1';
     134      RSRLOAD                : OUT    std_logic                      := '0';
     135      SRCLK                  : OUT    std_logic                      := '0';
     136      SRIN_out               : OUT    std_logic                      := '0';
     137      adc_clk_en             : OUT    std_logic                      := '0';
     138      adc_oeb                : OUT    std_logic                      := '1';
    167139      additional_flasher_out : OUT    std_logic ;
     140      alarm_refclk_too_high  : OUT    std_logic                      := '0';           -- default domino wave off
     141      alarm_refclk_too_low   : OUT    std_logic                      := '0';           -- default domino wave off
    168142      amber                  : OUT    std_logic ;
     143      counter_result         : OUT    std_logic_vector (11 DOWNTO 0) := (others => '0');
    169144      dac_cs                 : OUT    std_logic ;
    170       denable                : OUT    std_logic                     := '0';           -- default domino wave off
    171       drs_channel_id         : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    172       drs_dwrite             : OUT    std_logic                     := '1';
     145      denable                : OUT    std_logic                      := '0';           -- default domino wave off
     146      drs_channel_id         : OUT    std_logic_vector (3 DOWNTO 0)  := (others => '0');
     147      drs_dwrite             : OUT    std_logic                      := '1';
    173148      green                  : OUT    std_logic ;
    174       led                    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    175       mosi                   : OUT    std_logic                     := '0';
    176       offset                 : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    177       ready                  : OUT    std_logic                     := '0';
     149      led                    : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '0');
     150      mosi                   : OUT    std_logic                      := '0';
    178151      red                    : OUT    std_logic ;
    179152      sclk                   : OUT    std_logic ;
    180153      sensor_cs              : OUT    std_logic_vector (3 DOWNTO 0);
    181       -- status:
    182       shifting               : OUT    std_logic                     := '0';
    183154      wiz_addr               : OUT    std_logic_vector (9 DOWNTO 0);
    184       wiz_cs                 : OUT    std_logic                     := '1';
    185       wiz_rd                 : OUT    std_logic                     := '1';
    186       wiz_reset              : OUT    std_logic                     := '1';
    187       wiz_wr                 : OUT    std_logic                     := '1';
     155      wiz_cs                 : OUT    std_logic                      := '1';
     156      wiz_rd                 : OUT    std_logic                      := '1';
     157      wiz_reset              : OUT    std_logic                      := '1';
     158      wiz_wr                 : OUT    std_logic                      := '1';
    188159      sio                    : INOUT  std_logic ;
    189160      wiz_data               : INOUT  std_logic_vector (15 DOWNTO 0)
     
    199170BEGIN
    200171   -- Architecture concurrent statements
    201    -- HDL Embedded Text Block 1 eb_ID
     172   -- HDL Embedded Text Block 1 SRCLK
     173   DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
     174
     175   -- HDL Embedded Text Block 2 ADC_CLK
     176   A_CLK <= (CLK_25_PS, CLK_25_PS, CLK_25_PS, CLK_25_PS);
     177
     178   -- HDL Embedded Text Block 3 ADC_DATA
     179   adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );
     180
     181   -- HDL Embedded Text Block 4 eb_ID
    202182   -- hard-wired IDs
    203183   board_id <= LINE(5 downto 2);
    204184   crate_id <= LINE(1 downto 0);
    205185
    206    -- HDL Embedded Text Block 2 ADC_CLK
    207    -- ADC_CLK 2
    208    A_CLK (0) <= CLK_25_PS;
    209    A_CLK (1) <= CLK_25_PS;
    210    A_CLK (2) <= CLK_25_PS;
    211    A_CLK (3) <= CLK_25_PS;                                       
    212 
    213    -- HDL Embedded Text Block 3 ADC_DATA
    214    -- ADC_DATA 3
    215    adc_data_array (0) <= A0_D;
    216    adc_data_array (1) <= A1_D;
    217    adc_data_array (2) <= A2_D;
    218    adc_data_array (3) <= A3_D;                                       
    219 
    220    -- HDL Embedded Text Block 4 SRCLK
    221    -- SRCLK 4         
    222    D0_SRCLK <= SRCLK;
    223    D1_SRCLK <= SRCLK;
    224    D2_SRCLK <= SRCLK;
    225    D3_SRCLK <= SRCLK;                               
    226 
    227    -- HDL Embedded Text Block 5 T_CS
    228    -- T_CS 5
    229    T0_CS <= sensor_cs (0);
    230    T1_CS <= sensor_cs (1);
    231    T2_CS <= sensor_cs (2);
    232    T3_CS <= sensor_cs (3);                                     
    233 
    234    -- HDL Embedded Text Block 6 MISC
    235    -- MISC 6     
    236    
    237    RS485_C_RE <= '0';
    238    RS485_C_DE <= '0';   
    239    RS485_C_DO <= RS485_C_DI;
    240    
    241    
    242    
    243    -- DENABLE <= '0'; -- domino wave stopped
    244    -- DENABLE <= '1'; -- domino wave running
    245    
    246    
    247    EE_CS <= '1';
    248 
    249    -- HDL Embedded Text Block 7 eb1
    250    D_T(5 downto 0) <= (others => '0');
    251 
    252    -- HDL Embedded Text Block 8 eb2
    253    -- eb2 8                                       
    254    D_A <= drs_channel_id;
    255 
    256186   -- HDL Embedded Text Block 9 eb3
    257    -- eb3 9                         
    258    --A0_T(0) <= ready;
    259    --A0_T(1) <= shifting;
    260    --A0_T(2) <= CLK25_PSOUT;
    261    --A0_T(3) <= PS_DIR_IN;
    262    --A0_T(4) <= PS_DO_IN;
    263    --A0_T(5) <= PSINCDEC_OUT;
    264    
    265    
    266    
    267    A1_T(0) <= SRIN_internal;
    268    A1_T(1) <= PSDONE_extraOUT;
    269    A1_T(2) <= PSCLK_OUT;
    270    A1_T(3) <= LOCKED_extraOUT;
    271    
    272    A1_T(4) <= drs_channel_id(0);
    273    A1_T(5) <= drs_channel_id(1);
    274    A1_T(6) <= drs_channel_id(2);
    275    A1_T(7) <= drs_channel_id(3);
    276    
    277    A0_T(5 downto 0) <= (others => '0');
    278    A0_T(6) <= REFCLK;
    279    A0_T(7) <= RS485_E_DI;
     187   -- testpins D_T2 are used as MAX3485 outputs.
     188   
     189   --D_T <= (others => '0');
     190   --D_T2 <= ( others => '0' );
     191   -- A0_T(7 downto 0) <= (others => '0');
     192   --A1_T(7 downto 0) <= (others => '0');
     193   
     194   A1_T <= counter_result ( 7 downto 0);
     195   D_T(3 downto 0) <=  counter_result ( 11 downto 8);
     196   D_T(4) <= alarm_refclk_too_low;
     197   D_T(5) <= alarm_refclk_too_high;
     198   D_T(6) <= '0';
     199   D_T(7) <= '0';
     200   
     201   -- led output is driven by w5300 modul
     202   -- for debugging only.
     203   A0_T <= led;
     204   
     205   -- MAX3485 for FTM trigger ID is switched into receive mode
    280206   RS485_E_RE <= '0';
    281207   RS485_E_DE <= '0';
    282    
    283    D_T2 <= D_PLLLCK;
     208   -- in receive mode, the DI input of this MAX is in 'don't care' state
     209   RS485_E_DO <= '0';
     210   -- the receive pin is fed out as well
     211   D_T2(1) <= RS485_E_DI;
     212   
     213   -- additional MAX3485 is switched to shutdown mode
     214   RS485_C_RE <= '1';  --inverted logic
     215   RS485_C_DE <= '0';   
     216   RS485_C_DO <= '0';
     217   -- MAX3485 receiver out pit is fed out... should be HIGH-Z
     218   D_T2(0) <= RS485_C_DI;
     219   
     220   -- EEPROM is not used on FAD. CS is always high.
     221   EE_CS <= '1';
    284222
    285223
    286224   -- ModuleWare code(v1.9) for instance 'I0' of 'and'
    287225   CLK_25_PS <= adc_clk_en AND CLK_25_PS1;
    288 
    289    -- ModuleWare code(v1.9) for instance 'I3' of 'assignment'
    290    DAC_CS <= dummy;
    291226
    292227   -- Instance port mappings.
     
    306241         board_id               => board_id,
    307242         crate_id               => crate_id,
     243         drs_refclk_in          => REFCLK,
     244         plllock_in             => D_PLLLCK,
    308245         trigger                => TRG,
    309246         wiz_int                => W_INT,
    310          CLK25_OUT              => CLK25_OUT,
    311          CLK25_PSOUT            => CLK25_PSOUT,
    312          CLK50_OUT              => CLK50_OUT,
    313247         CLK_25_PS              => CLK_25_PS1,
    314248         CLK_50                 => CLK_50,
    315          DCM_locked             => DCM_locked,
    316          LOCKED_extraOUT        => LOCKED_extraOUT,
    317          PSCLK_OUT              => PSCLK_OUT,
    318          PSDONE_extraOUT        => PSDONE_extraOUT,
    319          PSINCDEC_OUT           => PSINCDEC_OUT,
    320          PS_DIR_IN              => PS_DIR_IN,
    321249         RSRLOAD                => RSRLOAD,
    322250         SRCLK                  => SRCLK,
    323          SRIN_out               => SRIN_internal,
     251         SRIN_out               => SRIN,
    324252         adc_clk_en             => adc_clk_en,
    325253         adc_oeb                => OE_ADC,
    326254         additional_flasher_out => TRG_V,
     255         alarm_refclk_too_high  => alarm_refclk_too_high,
     256         alarm_refclk_too_low   => alarm_refclk_too_low,
    327257         amber                  => AMBER_LED,
    328          dac_cs                 => dummy,
     258         counter_result         => counter_result,
     259         dac_cs                 => DAC_CS,
    329260         denable                => DENABLE,
    330          drs_channel_id         => drs_channel_id,
     261         drs_channel_id         => D_A,
    331262         drs_dwrite             => DWRITE,
    332263         green                  => RED_LED,
    333264         led                    => led,
    334265         mosi                   => MOSI,
    335          offset                 => OPEN,
    336          ready                  => ready,
    337266         red                    => GREEN_LED,
    338267         sclk                   => S_CLK,
    339          sensor_cs              => sensor_cs,
    340          shifting               => shifting,
     268         sensor_cs              => TCS,
    341269         wiz_addr               => W_A,
    342270         wiz_cs                 => W_CS,
     
    348276      );
    349277
    350    -- Implicit buffered output assignments
    351    SRIN <= SRIN_internal;
    352 
    353278END struct;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10123 r10129  
    4747
    4848  constant FIRST_PORT : integer := 5000;
    49   constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0);
     49  constant CAM_IP_PREFIX : ip_type := (10, 0, 0, 0);
    5050  constant IP_offset : integer := 128;
    5151  constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000");
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak

    r10123 r10129  
    1717
    1818  type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
    19   type mac_list_type is array (0 to 3) of mac_type;
    2019  type ip_type is array (0 to 3) of integer;
    21   type ip_list_type is array (0 to 3) of ip_type;
     20 
     21  type mac_list_type is array (0 to 2) of mac_type;
     22  type ip_list_type is array (0 to 2) of ip_type;
    2223-- Network Settings
    2324
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10123 r10129  
    33-- Created:
    44--          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 17:58:58 27.01.2011
     5--          at - 15:27:49 04.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    2828      board_id               : IN     std_logic_vector (3 DOWNTO 0);
    2929      crate_id               : IN     std_logic_vector (1 DOWNTO 0);
     30      drs_refclk_in          : IN     std_logic;                                          -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
     31      plllock_in             : IN     std_logic_vector (3 DOWNTO 0);                      -- high level, if dominowave is running and DRS PLL locked
    3032      trigger                : IN     std_logic;
    3133      wiz_int                : IN     std_logic;
    32       CLK25_OUT              : OUT    std_logic;
    33       CLK25_PSOUT            : OUT    std_logic;
    34       CLK50_OUT              : OUT    std_logic;
    3534      CLK_25_PS              : OUT    std_logic;
    3635      CLK_50                 : OUT    std_logic;
    37       DCM_locked             : OUT    std_logic;
    38       LOCKED_extraOUT        : OUT    std_logic;
    39       PSCLK_OUT              : OUT    std_logic;
    40       PSDONE_extraOUT        : OUT    std_logic;
    41       PSINCDEC_OUT           : OUT    std_logic;
    42       PS_DIR_IN              : OUT    std_logic;
    43       RSRLOAD                : OUT    std_logic                     := '0';
    44       SRCLK                  : OUT    std_logic                     := '0';
    45       SRIN_out               : OUT    std_logic                     := '0';
    46       adc_clk_en             : OUT    std_logic                     := '0';
    47       adc_oeb                : OUT    std_logic                     := '1';
     36      RSRLOAD                : OUT    std_logic                      := '0';
     37      SRCLK                  : OUT    std_logic                      := '0';
     38      SRIN_out               : OUT    std_logic                      := '0';
     39      adc_clk_en             : OUT    std_logic                      := '0';
     40      adc_oeb                : OUT    std_logic                      := '1';
    4841      additional_flasher_out : OUT    std_logic;
     42      alarm_refclk_too_high  : OUT    std_logic                      := '0';              -- default domino wave off
     43      alarm_refclk_too_low   : OUT    std_logic                      := '0';              -- default domino wave off
    4944      amber                  : OUT    std_logic;
     45      counter_result         : OUT    std_logic_vector (11 DOWNTO 0) := (others => '0');
    5046      dac_cs                 : OUT    std_logic;
    51       denable                : OUT    std_logic                     := '0';              -- default domino wave off
    52       drs_channel_id         : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    53       drs_dwrite             : OUT    std_logic                     := '1';
     47      denable                : OUT    std_logic                      := '0';              -- default domino wave off
     48      drs_channel_id         : OUT    std_logic_vector (3 DOWNTO 0)  := (others => '0');
     49      drs_dwrite             : OUT    std_logic                      := '1';
    5450      green                  : OUT    std_logic;
    55       led                    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    56       mosi                   : OUT    std_logic                     := '0';
    57       offset                 : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    58       ready                  : OUT    std_logic                     := '0';
     51      led                    : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '0');
     52      mosi                   : OUT    std_logic                      := '0';
    5953      red                    : OUT    std_logic;
    6054      sclk                   : OUT    std_logic;
    6155      sensor_cs              : OUT    std_logic_vector (3 DOWNTO 0);
    62       -- status:
    63       shifting               : OUT    std_logic                     := '0';
    6456      wiz_addr               : OUT    std_logic_vector (9 DOWNTO 0);
    65       wiz_cs                 : OUT    std_logic                     := '1';
    66       wiz_rd                 : OUT    std_logic                     := '1';
    67       wiz_reset              : OUT    std_logic                     := '1';
    68       wiz_wr                 : OUT    std_logic                     := '1';
     57      wiz_cs                 : OUT    std_logic                      := '1';
     58      wiz_rd                 : OUT    std_logic                      := '1';
     59      wiz_reset              : OUT    std_logic                      := '1';
     60      wiz_wr                 : OUT    std_logic                      := '1';
    6961      sio                    : INOUT  std_logic;
    7062      wiz_data               : INOUT  std_logic_vector (15 DOWNTO 0)
     
    8072-- Created:
    8173--          by - dneise.UNKNOWN (E5B-LABOR6)
    82 --          at - 17:58:58 27.01.2011
     74--          at - 15:27:50 04.02.2011
    8375--
    8476-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     
    133125   SIGNAL dac_array              : dac_array_type;
    134126   SIGNAL data_out               : std_logic_vector(63 DOWNTO 0);
     127   SIGNAL denable_inhibit        : std_logic                                    := '0';                -- default domino wave off
     128   SIGNAL denable_prim           : std_logic                                    := '0';                -- default domino wave off
     129   SIGNAL din1                   : std_logic                                    := '0';                -- default domino wave off
    135130   SIGNAL dout                   : std_logic;
    136131   SIGNAL dout1                  : std_logic;
    137    SIGNAL drs_address            : std_logic_vector(3 DOWNTO 0)                 := (others => '0');
    138    SIGNAL drs_address_mode       : std_logic;
    139    SIGNAL drs_channel_internal   : std_logic_vector(3 DOWNTO 0)                 := (others => '0');
    140132   SIGNAL drs_clk_en             : std_logic                                    := '0';
    141133   SIGNAL drs_read_s_cell        : std_logic                                    := '0';
     
    191183
    192184   -- Implicit buffer signal declarations
    193    SIGNAL CLK_25_PS_internal : std_logic;
    194    SIGNAL CLK_50_internal    : std_logic;
     185   SIGNAL CLK_25_PS_internal             : std_logic;
     186   SIGNAL CLK_50_internal                : std_logic;
     187   SIGNAL alarm_refclk_too_high_internal : std_logic;
     188   SIGNAL alarm_refclk_too_low_internal  : std_logic;
    195189
    196190
    197191   -- Component Declarations
     192   COMPONENT REFCLK_counter
     193   PORT (
     194      clk                   : IN     std_logic;
     195      refclk_in             : IN     std_logic;
     196      alarm_refclk_too_high : OUT    std_logic                      := '0';
     197      alarm_refclk_too_low  : OUT    std_logic                      := '0';
     198      counter_result        : OUT    std_logic_vector (11 DOWNTO 0) := (others => '0')
     199   );
     200   END COMPONENT;
    198201   COMPONENT adc_buffer
    199202   PORT (
     
    207210   COMPONENT clock_generator_var_ps
    208211   PORT (
    209       CLK             : IN     std_logic ;
    210       RST_IN          : IN     std_logic ;
    211       direction       : IN     std_logic ;
    212       do_shift        : IN     std_logic ;
    213       CLK_25          : OUT    std_logic ;
    214       CLK_25_PS       : OUT    std_logic ;
    215       CLK_50          : OUT    std_logic ;
    216       DCM_locked      : OUT    std_logic ;
    217       LOCKED_extraOUT : OUT    std_logic ;
    218       PSCLK_OUT       : OUT    std_logic ;
    219       PSDONE_extraOUT : OUT    std_logic ;
    220       PSINCDEC_OUT    : OUT    std_logic ;
    221       offset          : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    222       ready           : OUT    std_logic                     := '0';
    223       -- status:
    224       shifting        : OUT    std_logic                     := '0'
     212      CLK       : IN     std_logic ;
     213      RST_IN    : IN     std_logic ;
     214      direction : IN     std_logic ;
     215      do_shift  : IN     std_logic ;
     216      CLK_25    : OUT    std_logic ;
     217      CLK_25_PS : OUT    std_logic ;
     218      CLK_50    : OUT    std_logic ;
     219      offset    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
    225220   );
    226221   END COMPONENT;
     
    487482   -- Optional embedded configurations
    488483   -- pragma synthesis_off
     484   FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
    489485   FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
    490486   FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
     
    514510   sclk <= sclk_enable AND sclk1;
    515511
     512   -- ModuleWare code(v1.9) for instance 'U_5' of 'and'
     513   denable <= denable_prim AND din1;
     514
    516515   -- ModuleWare code(v1.9) for instance 'U_11' of 'and'
    517516   dout1 <= dout AND trigger_enable;
    518517
    519    -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
    520    PS_DIR_IN <= ps_direction;
    521 
    522    -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
    523    CLK50_OUT <= CLK_50_internal;
    524 
    525    -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
    526    CLK25_OUT <= CLK_25;
    527 
    528    -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
    529    CLK25_PSOUT <= CLK_25_PS_internal;
    530 
    531    -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
    532    u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
    533                           drs_address_mode)
    534    BEGIN
    535       CASE drs_address_mode IS
    536       WHEN '0' => drs_channel_id <= drs_channel_internal;
    537       WHEN '1' => drs_channel_id <= drs_address;
    538       WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
    539       END CASE;
    540    END PROCESS u_0combo_proc;
     518   -- ModuleWare code(v1.9) for instance 'U_7' of 'inv'
     519   din1 <= NOT(denable_inhibit);
     520
     521   -- ModuleWare code(v1.9) for instance 'U_6' of 'or'
     522   denable_inhibit <= alarm_refclk_too_low_internal
     523                      OR alarm_refclk_too_high_internal;
    541524
    542525   -- ModuleWare code(v1.9) for instance 'U_9' of 'or'
     
    547530
    548531   -- Instance port mappings.
     532   REFCLK_counter_main : REFCLK_counter
     533      PORT MAP (
     534         clk                   => CLK_50_internal,
     535         refclk_in             => drs_refclk_in,
     536         counter_result        => counter_result,
     537         alarm_refclk_too_high => alarm_refclk_too_high_internal,
     538         alarm_refclk_too_low  => alarm_refclk_too_low_internal
     539      );
    549540   I_main_adc_buffer : adc_buffer
    550541      PORT MAP (
     
    557548   U_2 : clock_generator_var_ps
    558549      PORT MAP (
    559          CLK             => CLK,
    560          RST_IN          => ps_reset,
    561          direction       => ps_direction,
    562          do_shift        => ps_do_phase_shift,
    563          CLK_25          => CLK_25,
    564          CLK_25_PS       => CLK_25_PS_internal,
    565          CLK_50          => CLK_50_internal,
    566          DCM_locked      => DCM_locked,
    567          LOCKED_extraOUT => LOCKED_extraOUT,
    568          PSCLK_OUT       => PSCLK_OUT,
    569          PSDONE_extraOUT => PSDONE_extraOUT,
    570          PSINCDEC_OUT    => PSINCDEC_OUT,
    571          offset          => offset,
    572          ready           => ready,
    573          shifting        => shifting
     550         CLK       => CLK,
     551         RST_IN    => ps_reset,
     552         direction => ps_direction,
     553         do_shift  => ps_do_phase_shift,
     554         CLK_25    => CLK_25,
     555         CLK_25_PS => CLK_25_PS_internal,
     556         CLK_50    => CLK_50_internal,
     557         offset    => OPEN
    574558      );
    575559   U_3 : continous_pulser
     
    648632         adc_clk_en            => adc_clk_en,
    649633         adc_otr               => adc_otr,
    650          drs_channel_id        => drs_channel_internal,
     634         drs_channel_id        => drs_channel_id,
    651635         drs_readout_ready     => drs_readout_ready,
    652636         drs_readout_ready_ack => drs_readout_ready_ack,
     
    791775         BoardID           => board_id,
    792776         CrateID           => crate_id,
    793          denable           => denable,
     777         denable           => denable_prim,
    794778         dwrite_enable     => dwrite_enable,
    795779         sclk_enable       => sclk_enable,
     
    804788
    805789   -- Implicit buffered output assignments
    806    CLK_25_PS <= CLK_25_PS_internal;
    807    CLK_50    <= CLK_50_internal;
     790   CLK_25_PS             <= CLK_25_PS_internal;
     791   CLK_50                <= CLK_50_internal;
     792   alarm_refclk_too_high <= alarm_refclk_too_high_internal;
     793   alarm_refclk_too_low  <= alarm_refclk_too_low_internal;
    808794
    809795END struct;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd

    r9912 r10129  
    99library ieee;
    1010use ieee.std_logic_1164.all;
    11 use IEEE.STD_LOGIC_ARITH.all;
    12 use ieee.STD_LOGIC_UNSIGNED.all;
     11use IEEE.NUMERIC_STD.all;
    1312
    1413library FACT_FAD_lib;
     
    2019        PORT(
    2120                CLK : IN std_logic;
     21                rst : in std_logic; --asynch in of DCM
    2222               
    2323                -- interface to: clock_generator_variable_PS_struct.vhd
     
    7272
    7373architecture first_behave of phase_shifter is
    74 
     74  constant OFFS_MIN : integer := -128;
     75  constant OFFS_MAX : integer := 127;
     76   
    7577        type states is (INIT, READY_STATE, SHIFTING_STATE, WAITINGFORDONE);
    7678        signal state,next_state : states := INIT;
    7779       
    7880        signal local_direction : std_logic;
     81        signal offset_int : integer range OFFS_MIN to OFFS_MAX := 0;
     82       
     83       
    7984
    8085begin
    8186
    8287-- concurrent statements:
    83 
    8488DCM_locked <= LOCKED;
    8589PSCLK <= CLK;
     90offset <= std_logic_vector(to_signed(offset_int,8));
    8691
    8792  -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high.
    88   FSM_Registers: process(CLK, LOCKED)
     93  FSM_Registers: process(CLK, LOCKED, rst)
    8994  begin
    90     if LOCKED = '0' then
     95    if rst = '1' then
     96      state <= INIT;
     97    elsif LOCKED = '0' then
    9198      state <= INIT;
    9299    elsif Rising_edge(CLK) then
     
    96103
    97104  -- MAIN FSM
    98   FSM_logic: process(state, PSDONE, LOCKED, shift_phase)
     105  FSM_logic: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction)
    99106  begin
    100107    next_state <= state;
     
    103110        -- INIT state: here the FSM is idling, when LOCKED is not HIGH.
    104111    when INIT =>
    105         ready <= '0';
     112    ready <= '0';
     113    offset_int <= 0;
    106114                shifting <= '0';
    107115                PSEN <= '0';
     
    139147        if (PSDONE = '1') then
    140148                             next_state <= READY_STATE;
     149                             if (local_direction = '1') then
     150                               if (offset_int < OFFS_MAX) then
     151                                 offset_int <= offset_int + 1;
     152                               end if;
     153                             else
     154                               if (offset_int > OFFS_MIN) then
     155                                 offset_int <= offset_int - 1;
     156                               end if;
     157                             end if;
    141158        else
    142159                             next_state <= WAITINGFORDONE;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd.bak

    r10074 r10129  
    99library ieee;
    1010use ieee.std_logic_1164.all;
    11 use IEEE.STD_LOGIC_ARITH.all;
    12 use ieee.STD_LOGIC_UNSIGNED.all;
     11use IEEE.NUMERIC_STD.all;
    1312
    1413library FACT_FAD_lib;
     
    2019        PORT(
    2120                CLK : IN std_logic;
     21                rst : in std_logic; --asynch in of DCM
    2222               
    2323                -- interface to: clock_generator_variable_PS_struct.vhd
     
    7272
    7373architecture first_behave of phase_shifter is
    74 
     74  constant OFFS_MIN : integer := -128;
     75  constant OFFS_MAX : integer := 127;
     76   
    7577        type states is (INIT, READY_STATE, SHIFTING_STATE, WAITINGFORDONE);
    7678        signal state,next_state : states := INIT;
    7779       
    7880        signal local_direction : std_logic;
     81        signal offset_int : integer range OFFS_MIN to OFFS_MAX := 0;
     82       
     83       
    7984
    8085begin
    8186
    8287-- concurrent statements:
    83 
    8488DCM_locked <= LOCKED;
    8589PSCLK <= CLK;
     90offset <= std_logic_vector(to_signed(offset_int,8));
    8691
    8792  -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high.
    88   FSM_Registers: process(CLK, LOCKED)
     93  FSM_Registers: process(CLK, LOCKED, rst)
    8994  begin
    90     if LOCKED = '0' then
     95    if Rising_edge(rst) then
     96      state <= INIT;
     97    elsif LOCKED = '0' then
    9198      state <= INIT;
    9299    elsif Rising_edge(CLK) then
     
    96103
    97104  -- MAIN FSM
    98   FSM_logic: process(state, PSDONE, LOCKED, shift_phase)
     105  FSM_logic: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction)
    99106  begin
    100107    next_state <= state;
     
    103110        -- INIT state: here the FSM is idling, when LOCKED is not HIGH.
    104111    when INIT =>
    105         ready <= '0';
     112    ready <= '0';
     113    offset_int <= 0;
    106114                shifting <= '0';
    107115                PSEN <= '0';
     
    139147        if (PSDONE = '1') then
    140148                             next_state <= READY_STATE;
     149                             if (local_direction = '1') then
     150                               if (offset_int < OFFS_MAX) then
     151                                 offset_int <= offset_int + 1;
     152                               end if;
     153                             else
     154                               if (offset_int > OFFS_MIN) then
     155                                 offset_int <= offset_int - 1;
     156                               end if;
     157                             end if;
    141158        else
    142159                             next_state <= WAITINGFORDONE;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd

    r10121 r10129  
    22--
    33-- Created:
    4 --          by - daqct3.UNKNOWN (IHP110)
    5 --          at - 12:52:20 06.01.2011
     4--          by - dneise.UNKNOWN (E5B-LABOR6)
     5--          at - 16:13:08 03.02.2011
    66--
    7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    88--
    99LIBRARY ieee;
     
    3737--
    3838-- Created:
    39 --          by - daqct3.UNKNOWN (IHP110)
    40 --          at - 12:52:20 06.01.2011
     39--          by - dneise.UNKNOWN (E5B-LABOR6)
     40--          at - 16:13:08 03.02.2011
    4141--
    42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     42-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    4343--
    4444LIBRARY ieee;
     
    5757
    5858   -- Internal signal declarations
     59   SIGNAL T_sensor_start   : std_logic;
    5960   SIGNAL dac_config_ready : std_logic;
    6061   SIGNAL dac_config_start : std_logic;
     
    7071
    7172   -- Component Declarations
    72    COMPONENT spi_clock_generator
     73   COMPONENT clk_divider
    7374   GENERIC (
    74       CLK_DIVIDER : integer := 25      --2 MHz @ 50 MHz
     75      DIVIDER : integer := 25
    7576   );
    7677   PORT (
     
    119120   -- Optional embedded configurations
    120121   -- pragma synthesis_off
    121    FOR ALL : spi_clock_generator USE ENTITY FACT_FAD_lib.spi_clock_generator;
     122   FOR ALL : clk_divider USE ENTITY FACT_FAD_lib.clk_divider;
    122123   FOR ALL : spi_controller USE ENTITY FACT_FAD_lib.spi_controller;
    123124   FOR ALL : spi_distributor USE ENTITY FACT_FAD_lib.spi_distributor;
     
    128129
    129130   -- Instance port mappings.
    130    I_spi_clkgen : spi_clock_generator
     131   I1 : clk_divider
    131132      GENERIC MAP (
    132          CLK_DIVIDER => 25         --2 MHz @ 50 MHz
     133         DIVIDER => 25
    133134      )
    134135      PORT MAP (
    135136         clk  => clk_50MHz,
    136137         sclk => sclk_internal
     138      );
     139   Measure_Temperature_Timer : clk_divider
     140      GENERIC MAP (
     141         DIVIDER => 25
     142      )
     143      PORT MAP (
     144         clk  => sclk_internal,
     145         sclk => T_sensor_start
    137146      );
    138147   I_spi_controller : spi_controller
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10123 r10129  
    318318                ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) );
    319319              end if;
    320                                           else -- FAD is tested, eighther at ETHZ or at TUDO AND eighther with FMP or without.
     320                                          else -- FAD is tested, either at ETHZ or at TUDO AND either with FMP or without.
    321321                                            if ( FAD_at_ETHZ = '0' ) then
    322322                                             -- easy FAD is at TUDO -> only one choice.
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd.bak

    r10123 r10129  
    445445                                        -- Own IP-Address
    446446                                        when IP =>
    447                                           led(0) <= '1';
    448           led(1) <= '1';
    449           led(2) <= '1';
    450 
    451447                                                par_addr <= W5300_SIPR;
    452448                                                par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);
     
    474470                                        -- Socket Init
    475471                                        when SI =>
    476                                           led(3) <= '1';
    477472                                                par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
    478473                                                par_data <= X"0101"; -- ALIGN, TCP
     
    506501                                                end if;
    507502                                        when SI6 =>
    508                                           led(4) <= '1';
    509503                                                par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
    510504                                                par_data <= X"0002"; -- LISTEN
     
    520514                                               
    521515                                        when ESTABLISH =>
    522                                           led(5) <= '1';
    523516                                          socks_waiting <= '1';
    524517            socks_connected <= '0';
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf

    r10121 r10129  
    2828DESIGN clock_generator_var_ps
    2929VIEW symbol.sb
    30 GRAPHIC 481,0 21 0
    31 DESIGN clock_generator_var_ps
    32 VIEW symbol.sb
    33 GRAPHIC 544,0 22 0
    34 DESIGN clock_generator_var_ps
    35 VIEW symbol.sb
    36 GRAPHIC 524,0 23 0
    37 DESIGN clock_generator_var_ps
    38 VIEW symbol.sb
    39 GRAPHIC 539,0 24 0
    40 DESIGN clock_generator_var_ps
    41 VIEW symbol.sb
    42 GRAPHIC 534,0 25 0
    43 DESIGN clock_generator_var_ps
    44 VIEW symbol.sb
    45 GRAPHIC 475,0 26 0
    46 DESIGN clock_generator_var_ps
    47 VIEW symbol.sb
    48 GRAPHIC 463,0 27 0
    49 DESIGN clock_generator_var_ps
    50 VIEW symbol.sb
    51 GRAPHIC 469,0 29 0
    52 DESIGN clock_generator_var_ps
    53 VIEW symbol.sb
    54 GRAPHIC 1,0 32 0
    55 DESIGN clock_generator_var_ps
    56 VIEW symbol.sb
    57 GRAPHIC 1,0 33 0
    58 DESIGN clock_generator_var_ps
    59 VIEW struct.bd
    60 NO_GRAPHIC 36
    61 DESIGN clock_generator_var_ps
    62 VIEW struct.bd
    63 GRAPHIC 41,0 45 0
    64 DESIGN clock_generator_var_ps
    65 VIEW struct.bd
    66 NO_GRAPHIC 51
    67 DESIGN clock_generator_var_ps
    68 VIEW struct.bd
    69 GRAPHIC 0,0 54 2
    70 DESIGN clock_generator_var_ps
    71 VIEW struct.bd
    72 GRAPHIC 524,0 59 0
    73 DESIGN clock_generator_var_ps
    74 VIEW struct.bd
    75 GRAPHIC 600,0 60 0
    76 DESIGN clock_generator_var_ps
    77 VIEW struct.bd
    78 GRAPHIC 530,0 61 0
    79 DESIGN clock_generator_var_ps
    80 VIEW struct.bd
    81 GRAPHIC 586,0 62 0
    82 DESIGN clock_generator_var_ps
    83 VIEW struct.bd
    84 GRAPHIC 544,0 63 0
    85 DESIGN clock_generator_var_ps
    86 VIEW struct.bd
    87 GRAPHIC 558,0 64 0
    88 DESIGN clock_generator_var_ps
    89 VIEW struct.bd
    90 NO_GRAPHIC 65
    91 DESIGN clock_generator_var_ps
    92 VIEW struct.bd
    93 GRAPHIC 229,0 67 0
    94 DESIGN clock_generator_var_ps
    95 VIEW struct.bd
    96 NO_GRAPHIC 69
     30GRAPHIC 947,0 21 0
     31DESIGN clock_generator_var_ps
     32VIEW symbol.sb
     33GRAPHIC 1,0 24 0
     34DESIGN clock_generator_var_ps
     35VIEW symbol.sb
     36GRAPHIC 1,0 25 0
     37DESIGN clock_generator_var_ps
     38VIEW struct.bd
     39NO_GRAPHIC 28
     40DESIGN clock_generator_var_ps
     41VIEW struct.bd
     42GRAPHIC 41,0 37 0
     43DESIGN clock_generator_var_ps
     44VIEW struct.bd
     45NO_GRAPHIC 43
     46DESIGN clock_generator_var_ps
     47VIEW struct.bd
     48GRAPHIC 0,0 46 2
     49DESIGN clock_generator_var_ps
     50VIEW struct.bd
     51GRAPHIC 524,0 51 0
     52DESIGN clock_generator_var_ps
     53VIEW struct.bd
     54GRAPHIC 600,0 52 0
     55DESIGN clock_generator_var_ps
     56VIEW struct.bd
     57GRAPHIC 530,0 53 0
     58DESIGN clock_generator_var_ps
     59VIEW struct.bd
     60GRAPHIC 586,0 54 0
     61DESIGN clock_generator_var_ps
     62VIEW struct.bd
     63GRAPHIC 544,0 55 0
     64DESIGN clock_generator_var_ps
     65VIEW struct.bd
     66GRAPHIC 558,0 56 0
     67DESIGN clock_generator_var_ps
     68VIEW struct.bd
     69NO_GRAPHIC 57
     70DESIGN clock_generator_var_ps
     71VIEW struct.bd
     72GRAPHIC 229,0 59 0
     73DESIGN clock_generator_var_ps
     74VIEW struct.bd
     75NO_GRAPHIC 61
    9776LIBRARY FACT_FAD_lib
    9877DESIGN dcm_50_to_25
    9978VIEW @b@e@h@a@v@i@o@r@a@l
    100 GRAPHIC 403,0 71 0
    101 DESIGN clock_generator_var_ps
    102 VIEW struct.bd
    103 NO_GRAPHIC 77
    104 DESIGN clock_generator_var_ps
    105 VIEW struct.bd
    106 GRAPHIC 354,0 79 0
    107 DESIGN clock_generator_var_ps
    108 VIEW struct.bd
    109 NO_GRAPHIC 83
    110 DESIGN clock_generator_var_ps
    111 VIEW struct.bd
    112 GRAPHIC 514,0 85 0
    113 DESIGN clock_generator_var_ps
    114 VIEW struct.bd
    115 NO_GRAPHIC 95
    116 DESIGN clock_generator_var_ps
    117 VIEW struct.bd
    118 GRAPHIC 826,0 97 0
    119 DESIGN phase_shifter
    120 VIEW first_behave
    121 GRAPHIC 48,0 99 0
    122 DESIGN phase_shifter
    123 VIEW first_behave
    124 GRAPHIC 53,0 100 0
    125 DESIGN phase_shifter
    126 VIEW first_behave
    127 GRAPHIC 58,0 102 0
    128 DESIGN phase_shifter
    129 VIEW first_behave
    130 GRAPHIC 63,0 103 0
    131 DESIGN phase_shifter
    132 VIEW first_behave
    133 GRAPHIC 68,0 104 0
    134 DESIGN phase_shifter
    135 VIEW first_behave
    136 GRAPHIC 73,0 105 0
    137 DESIGN phase_shifter
    138 VIEW first_behave
    139 GRAPHIC 83,0 106 0
    140 DESIGN phase_shifter
    141 VIEW first_behave
    142 GRAPHIC 88,0 108 0
    143 DESIGN phase_shifter
    144 VIEW first_behave
    145 GRAPHIC 93,0 109 0
    146 DESIGN phase_shifter
    147 VIEW first_behave
    148 GRAPHIC 98,0 111 0
    149 DESIGN phase_shifter
    150 VIEW first_behave
    151 GRAPHIC 103,0 112 0
    152 DESIGN phase_shifter
    153 VIEW first_behave
    154 GRAPHIC 108,0 113 0
     79GRAPHIC 403,0 63 0
     80DESIGN clock_generator_var_ps
     81VIEW struct.bd
     82NO_GRAPHIC 69
     83DESIGN clock_generator_var_ps
     84VIEW struct.bd
     85GRAPHIC 354,0 71 0
     86DESIGN clock_generator_var_ps
     87VIEW struct.bd
     88NO_GRAPHIC 75
     89DESIGN clock_generator_var_ps
     90VIEW struct.bd
     91GRAPHIC 514,0 77 0
     92DESIGN clock_generator_var_ps
     93VIEW struct.bd
     94NO_GRAPHIC 87
     95DESIGN clock_generator_var_ps
     96VIEW struct.bd
     97GRAPHIC 826,0 89 0
     98DESIGN phase_shifter
     99VIEW first_behave
     100GRAPHIC 48,0 91 0
     101DESIGN phase_shifter
     102VIEW first_behave
     103GRAPHIC 281,0 92 0
     104DESIGN phase_shifter
     105VIEW first_behave
     106GRAPHIC 53,0 93 0
     107DESIGN phase_shifter
     108VIEW first_behave
     109GRAPHIC 58,0 95 0
     110DESIGN phase_shifter
     111VIEW first_behave
     112GRAPHIC 63,0 96 0
     113DESIGN phase_shifter
     114VIEW first_behave
     115GRAPHIC 68,0 97 0
     116DESIGN phase_shifter
     117VIEW first_behave
     118GRAPHIC 73,0 98 0
     119DESIGN phase_shifter
     120VIEW first_behave
     121GRAPHIC 83,0 99 0
     122DESIGN phase_shifter
     123VIEW first_behave
     124GRAPHIC 88,0 101 0
     125DESIGN phase_shifter
     126VIEW first_behave
     127GRAPHIC 93,0 102 0
     128DESIGN phase_shifter
     129VIEW first_behave
     130GRAPHIC 98,0 104 0
     131DESIGN phase_shifter
     132VIEW first_behave
     133GRAPHIC 103,0 105 0
     134DESIGN phase_shifter
     135VIEW first_behave
     136GRAPHIC 108,0 106 0
    155137LIBRARY FACT_FAD_lib
    156138DESIGN clock_generator_var_ps
    157139VIEW struct.bd
    158 NO_GRAPHIC 116
    159 DESIGN clock_generator_var_ps
    160 VIEW struct.bd
    161 GRAPHIC 403,0 119 0
    162 DESIGN clock_generator_var_ps
    163 VIEW struct.bd
    164 GRAPHIC 354,0 120 0
    165 DESIGN clock_generator_var_ps
    166 VIEW struct.bd
    167 GRAPHIC 514,0 121 0
    168 DESIGN clock_generator_var_ps
    169 VIEW struct.bd
    170 GRAPHIC 826,0 122 0
    171 DESIGN clock_generator_var_ps
    172 VIEW struct.bd
    173 NO_GRAPHIC 125
    174 DESIGN clock_generator_var_ps
    175 VIEW struct.bd
    176 GRAPHIC 1058,0 127 0
    177 DESIGN clock_generator_var_ps
    178 VIEW struct.bd
    179 GRAPHIC 1112,0 130 0
    180 DESIGN clock_generator_var_ps
    181 VIEW struct.bd
    182 GRAPHIC 1149,0 133 0
    183 DESIGN clock_generator_var_ps
    184 VIEW struct.bd
    185 GRAPHIC 1186,0 136 0
    186 DESIGN clock_generator_var_ps
    187 VIEW struct.bd
    188 NO_GRAPHIC 139
    189 DESIGN clock_generator_var_ps
    190 VIEW struct.bd
    191 GRAPHIC 403,0 141 0
    192 DESIGN clock_generator_var_ps
    193 VIEW struct.bd
    194 GRAPHIC 163,0 143 0
    195 DESIGN clock_generator_var_ps
    196 VIEW struct.bd
    197 GRAPHIC 209,0 144 0
    198 DESIGN clock_generator_var_ps
    199 VIEW struct.bd
    200 GRAPHIC 191,0 146 0
    201 DESIGN clock_generator_var_ps
    202 VIEW struct.bd
    203 GRAPHIC 354,0 148 0
    204 DESIGN clock_generator_var_ps
    205 VIEW struct.bd
    206 GRAPHIC 229,0 150 0
    207 DESIGN clock_generator_var_ps
    208 VIEW struct.bd
    209 GRAPHIC 526,0 151 0
    210 DESIGN clock_generator_var_ps
    211 VIEW struct.bd
    212 GRAPHIC 514,0 153 0
    213 DESIGN clock_generator_var_ps
    214 VIEW struct.bd
    215 GRAPHIC 526,0 155 0
    216 DESIGN clock_generator_var_ps
    217 VIEW struct.bd
    218 GRAPHIC 532,0 156 0
    219 DESIGN clock_generator_var_ps
    220 VIEW struct.bd
    221 GRAPHIC 546,0 157 0
    222 DESIGN clock_generator_var_ps
    223 VIEW struct.bd
    224 GRAPHIC 841,0 158 0
    225 DESIGN clock_generator_var_ps
    226 VIEW struct.bd
    227 GRAPHIC 1493,0 159 0
    228 DESIGN clock_generator_var_ps
    229 VIEW struct.bd
    230 GRAPHIC 1254,0 160 0
    231 DESIGN clock_generator_var_ps
    232 VIEW struct.bd
    233 GRAPHIC 602,0 161 0
    234 DESIGN clock_generator_var_ps
    235 VIEW struct.bd
    236 GRAPHIC 588,0 162 0
    237 DESIGN clock_generator_var_ps
    238 VIEW struct.bd
    239 GRAPHIC 826,0 164 0
    240 DESIGN clock_generator_var_ps
    241 VIEW struct.bd
    242 GRAPHIC 1458,0 166 0
    243 DESIGN clock_generator_var_ps
    244 VIEW struct.bd
    245 GRAPHIC 532,0 167 0
    246 DESIGN clock_generator_var_ps
    247 VIEW struct.bd
    248 GRAPHIC 546,0 168 0
    249 DESIGN clock_generator_var_ps
    250 VIEW struct.bd
    251 GRAPHIC 841,0 169 0
    252 DESIGN clock_generator_var_ps
    253 VIEW struct.bd
    254 GRAPHIC 588,0 170 0
    255 DESIGN clock_generator_var_ps
    256 VIEW struct.bd
    257 GRAPHIC 602,0 171 0
    258 DESIGN clock_generator_var_ps
    259 VIEW struct.bd
    260 GRAPHIC 1272,0 172 0
    261 DESIGN clock_generator_var_ps
    262 VIEW struct.bd
    263 GRAPHIC 1286,0 173 0
    264 DESIGN clock_generator_var_ps
    265 VIEW struct.bd
    266 GRAPHIC 869,0 174 0
    267 DESIGN clock_generator_var_ps
    268 VIEW struct.bd
    269 GRAPHIC 855,0 175 0
    270 DESIGN clock_generator_var_ps
    271 VIEW struct.bd
    272 GRAPHIC 883,0 176 0
    273 DESIGN clock_generator_var_ps
    274 VIEW struct.bd
    275 GRAPHIC 897,0 177 0
    276 DESIGN clock_generator_var_ps
    277 VIEW struct.bd
    278 GRAPHIC 229,0 181 0
    279 DESIGN clock_generator_var_ps
    280 VIEW struct.bd
    281 NO_GRAPHIC 183
     140NO_GRAPHIC 109
     141DESIGN clock_generator_var_ps
     142VIEW struct.bd
     143GRAPHIC 403,0 112 0
     144DESIGN clock_generator_var_ps
     145VIEW struct.bd
     146GRAPHIC 354,0 113 0
     147DESIGN clock_generator_var_ps
     148VIEW struct.bd
     149GRAPHIC 514,0 114 0
     150DESIGN clock_generator_var_ps
     151VIEW struct.bd
     152GRAPHIC 826,0 115 0
     153DESIGN clock_generator_var_ps
     154VIEW struct.bd
     155NO_GRAPHIC 118
     156DESIGN clock_generator_var_ps
     157VIEW struct.bd
     158NO_GRAPHIC 120
     159DESIGN clock_generator_var_ps
     160VIEW struct.bd
     161GRAPHIC 403,0 122 0
     162DESIGN clock_generator_var_ps
     163VIEW struct.bd
     164GRAPHIC 163,0 124 0
     165DESIGN clock_generator_var_ps
     166VIEW struct.bd
     167GRAPHIC 209,0 125 0
     168DESIGN clock_generator_var_ps
     169VIEW struct.bd
     170GRAPHIC 191,0 127 0
     171DESIGN clock_generator_var_ps
     172VIEW struct.bd
     173GRAPHIC 354,0 129 0
     174DESIGN clock_generator_var_ps
     175VIEW struct.bd
     176GRAPHIC 229,0 131 0
     177DESIGN clock_generator_var_ps
     178VIEW struct.bd
     179GRAPHIC 526,0 132 0
     180DESIGN clock_generator_var_ps
     181VIEW struct.bd
     182GRAPHIC 514,0 134 0
     183DESIGN clock_generator_var_ps
     184VIEW struct.bd
     185GRAPHIC 526,0 136 0
     186DESIGN clock_generator_var_ps
     187VIEW struct.bd
     188GRAPHIC 532,0 137 0
     189DESIGN clock_generator_var_ps
     190VIEW struct.bd
     191GRAPHIC 546,0 138 0
     192DESIGN clock_generator_var_ps
     193VIEW struct.bd
     194GRAPHIC 841,0 139 0
     195DESIGN clock_generator_var_ps
     196VIEW struct.bd
     197GRAPHIC 1493,0 140 0
     198DESIGN clock_generator_var_ps
     199VIEW struct.bd
     200GRAPHIC 1254,0 141 0
     201DESIGN clock_generator_var_ps
     202VIEW struct.bd
     203GRAPHIC 602,0 142 0
     204DESIGN clock_generator_var_ps
     205VIEW struct.bd
     206GRAPHIC 588,0 143 0
     207DESIGN clock_generator_var_ps
     208VIEW struct.bd
     209GRAPHIC 826,0 145 0
     210DESIGN clock_generator_var_ps
     211VIEW struct.bd
     212GRAPHIC 1458,0 147 0
     213DESIGN clock_generator_var_ps
     214VIEW struct.bd
     215GRAPHIC 1625,0 148 0
     216DESIGN clock_generator_var_ps
     217VIEW struct.bd
     218GRAPHIC 532,0 149 0
     219DESIGN clock_generator_var_ps
     220VIEW struct.bd
     221GRAPHIC 546,0 150 0
     222DESIGN clock_generator_var_ps
     223VIEW struct.bd
     224GRAPHIC 841,0 151 0
     225DESIGN clock_generator_var_ps
     226VIEW struct.bd
     227GRAPHIC 588,0 152 0
     228DESIGN clock_generator_var_ps
     229VIEW struct.bd
     230GRAPHIC 602,0 153 0
     231DESIGN clock_generator_var_ps
     232VIEW struct.bd
     233GRAPHIC 1272,0 154 0
     234DESIGN clock_generator_var_ps
     235VIEW struct.bd
     236GRAPHIC 1286,0 155 0
     237DESIGN clock_generator_var_ps
     238VIEW struct.bd
     239GRAPHIC 1609,0 158 0
     240DESIGN clock_generator_var_ps
     241VIEW struct.bd
     242GRAPHIC 229,0 163 0
     243DESIGN clock_generator_var_ps
     244VIEW struct.bd
     245NO_GRAPHIC 165
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r10123 r10129  
    5252DESIGN @f@a@d_@board
    5353VIEW symbol.sb
    54 GRAPHIC 3692,0 29 0
    55 DESIGN @f@a@d_@board
    56 VIEW symbol.sb
    57 GRAPHIC 1121,0 30 0
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    59 VIEW symbol.sb
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    485 DESIGN @f@a@d_main
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    488 DESIGN @f@a@d_main
    489 VIEW struct.bd
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    491 DESIGN @f@a@d_main
    492 VIEW struct.bd
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    494 DESIGN @f@a@d_main
    495 VIEW struct.bd
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     455DESIGN @f@a@d_main
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     458DESIGN @f@a@d_main
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     461DESIGN @f@a@d_main
     462VIEW struct.bd
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     464DESIGN @f@a@d_main
     465VIEW struct.bd
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    497467DESIGN control_unit
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    504474VIEW symbol.sb
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    524494DESIGN control_unit
    525495VIEW symbol.sb
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    530500DESIGN control_unit
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     502GRAPHIC 165,0 247 0
    533503DESIGN control_unit
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     505GRAPHIC 155,0 248 0
    536506DESIGN control_unit
    537507VIEW symbol.sb
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    539 DESIGN @f@a@d_main
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     509DESIGN @f@a@d_main
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    543513VIEW data@r@a@m_64b_16b_width14_5_a
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     514GRAPHIC 48,0 254 0
    545515DESIGN data@r@a@m_64b_16b_width14_5
    546516VIEW data@r@a@m_64b_16b_width14_5_a
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     517GRAPHIC 53,0 255 0
    548518DESIGN data@r@a@m_64b_16b_width14_5
    549519VIEW data@r@a@m_64b_16b_width14_5_a
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     520GRAPHIC 58,0 256 0
    551521DESIGN data@r@a@m_64b_16b_width14_5
    552522VIEW data@r@a@m_64b_16b_width14_5_a
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     523GRAPHIC 63,0 257 0
    554524DESIGN data@r@a@m_64b_16b_width14_5
    555525VIEW data@r@a@m_64b_16b_width14_5_a
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     526GRAPHIC 68,0 258 0
    557527DESIGN data@r@a@m_64b_16b_width14_5
    558528VIEW data@r@a@m_64b_16b_width14_5_a
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     529GRAPHIC 73,0 259 0
    560530DESIGN data@r@a@m_64b_16b_width14_5
    561531VIEW data@r@a@m_64b_16b_width14_5_a
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    563 DESIGN @f@a@d_main
    564 VIEW struct.bd
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    566 DESIGN data_generator
    567 VIEW symbol.sb
    568 GRAPHIC 14,0 269 1
    569 DESIGN data_generator
    570 VIEW @behavioral
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    572 DESIGN data_generator
    573 VIEW @behavioral
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    575 DESIGN data_generator
    576 VIEW @behavioral
    577 GRAPHIC 58,0 276 0
    578 DESIGN data_generator
    579 VIEW @behavioral
    580 GRAPHIC 73,0 277 0
    581 DESIGN data_generator
    582 VIEW @behavioral
    583 GRAPHIC 78,0 278 0
    584 DESIGN data_generator
    585 VIEW @behavioral
    586 GRAPHIC 402,0 279 0
    587 DESIGN data_generator
    588 VIEW @behavioral
    589 GRAPHIC 407,0 280 0
    590 DESIGN data_generator
    591 VIEW @behavioral
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    593 DESIGN data_generator
    594 VIEW @behavioral
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    596 DESIGN data_generator
    597 VIEW @behavioral
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    599 DESIGN data_generator
    600 VIEW @behavioral
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    602 DESIGN data_generator
    603 VIEW @behavioral
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    605 DESIGN data_generator
    606 VIEW @behavioral
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    608 DESIGN data_generator
    609 VIEW @behavioral
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    611 DESIGN data_generator
    612 VIEW @behavioral
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    614 DESIGN data_generator
    615 VIEW @behavioral
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    617 DESIGN data_generator
    618 VIEW @behavioral
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    620 DESIGN data_generator
    621 VIEW @behavioral
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    623 DESIGN data_generator
    624 VIEW @behavioral
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    626 DESIGN data_generator
    627 VIEW @behavioral
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    629 DESIGN data_generator
    630 VIEW @behavioral
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    632 DESIGN data_generator
    633 VIEW @behavioral
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    635 DESIGN data_generator
    636 VIEW @behavioral
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    638 DESIGN data_generator
    639 VIEW @behavioral
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    641 DESIGN data_generator
    642 VIEW @behavioral
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    644 DESIGN data_generator
    645 VIEW @behavioral
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    647 DESIGN data_generator
    648 VIEW @behavioral
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    650 DESIGN data_generator
    651 VIEW @behavioral
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    653 DESIGN data_generator
    654 VIEW @behavioral
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    656 DESIGN data_generator
    657 VIEW @behavioral
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    659 DESIGN data_generator
    660 VIEW @behavioral
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    662 DESIGN data_generator
    663 VIEW @behavioral
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    665 DESIGN data_generator
    666 VIEW @behavioral
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    668 DESIGN data_generator
    669 VIEW @behavioral
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    671 DESIGN data_generator
    672 VIEW @behavioral
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    674 DESIGN data_generator
    675 VIEW @behavioral
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    677 DESIGN data_generator
    678 VIEW @behavioral
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    680 DESIGN data_generator
    681 VIEW @behavioral
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    683 DESIGN data_generator
    684 VIEW @behavioral
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    686 DESIGN data_generator
    687 VIEW @behavioral
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    689 DESIGN data_generator
    690 VIEW @behavioral
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    692 DESIGN data_generator
    693 VIEW @behavioral
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    695 DESIGN data_generator
    696 VIEW @behavioral
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    698 DESIGN data_generator
    699 VIEW @behavioral
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    701 DESIGN data_generator
    702 VIEW @behavioral
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    704 DESIGN @f@a@d_main
    705 VIEW struct.bd
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    707 DESIGN @f@a@d_main
    708 VIEW struct.bd
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    710 DESIGN @f@a@d_main
    711 VIEW struct.bd
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    713 DESIGN @f@a@d_main
    714 VIEW struct.bd
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    716 DESIGN @f@a@d_main
    717 VIEW struct.bd
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    719 DESIGN @f@a@d_main
    720 VIEW struct.bd
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    722 DESIGN memory_manager
    723 VIEW symbol.sb
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    725 DESIGN memory_manager
    726 VIEW beha
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    728 DESIGN memory_manager
    729 VIEW beha
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    732 VIEW beha
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    734 DESIGN memory_manager
    735 VIEW beha
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    740 DESIGN memory_manager
    741 VIEW beha
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    743 DESIGN memory_manager
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    746 DESIGN memory_manager
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    749 DESIGN memory_manager
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    752 DESIGN memory_manager
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    755 DESIGN memory_manager
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    758 DESIGN memory_manager
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    761 DESIGN memory_manager
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    771 VIEW beha
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    776 DESIGN memory_manager
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    779 DESIGN memory_manager
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    783 VIEW struct.bd
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     533DESIGN @f@a@d_main
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     536DESIGN data_generator
     537VIEW symbol.sb
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     539DESIGN data_generator
     540VIEW @behavioral
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     542DESIGN data_generator
     543VIEW @behavioral
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     545DESIGN data_generator
     546VIEW @behavioral
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     548DESIGN data_generator
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     551DESIGN data_generator
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     554DESIGN data_generator
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     557DESIGN data_generator
     558VIEW @behavioral
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     560DESIGN data_generator
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     563DESIGN data_generator
     564VIEW @behavioral
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     566DESIGN data_generator
     567VIEW @behavioral
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     569DESIGN data_generator
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     572DESIGN data_generator
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     575DESIGN data_generator
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     578DESIGN data_generator
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     581DESIGN data_generator
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     584DESIGN data_generator
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     590DESIGN data_generator
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     593DESIGN data_generator
     594VIEW @behavioral
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     596DESIGN data_generator
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     599DESIGN data_generator
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     602DESIGN data_generator
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     605DESIGN data_generator
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     608DESIGN data_generator
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     611DESIGN data_generator
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     614DESIGN data_generator
     615VIEW @behavioral
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     617DESIGN data_generator
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     620DESIGN data_generator
     621VIEW @behavioral
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     623DESIGN data_generator
     624VIEW @behavioral
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     627VIEW @behavioral
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     629DESIGN data_generator
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     633VIEW @behavioral
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     635DESIGN data_generator
     636VIEW @behavioral
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     638DESIGN data_generator
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     641DESIGN data_generator
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     644DESIGN data_generator
     645VIEW @behavioral
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     647DESIGN data_generator
     648VIEW @behavioral
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     650DESIGN data_generator
     651VIEW @behavioral
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     653DESIGN data_generator
     654VIEW @behavioral
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     656DESIGN data_generator
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     659DESIGN data_generator
     660VIEW @behavioral
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     662DESIGN data_generator
     663VIEW @behavioral
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     665DESIGN data_generator
     666VIEW @behavioral
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     668DESIGN data_generator
     669VIEW @behavioral
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     671DESIGN data_generator
     672VIEW @behavioral
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     674DESIGN @f@a@d_main
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     677DESIGN @f@a@d_main
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     680DESIGN @f@a@d_main
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     683DESIGN @f@a@d_main
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     686DESIGN @f@a@d_main
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     689DESIGN @f@a@d_main
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     692DESIGN memory_manager
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     695DESIGN memory_manager
     696VIEW beha
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     698DESIGN memory_manager
     699VIEW beha
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     701DESIGN memory_manager
     702VIEW beha
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     704DESIGN memory_manager
     705VIEW beha
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     707DESIGN memory_manager
     708VIEW beha
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     710DESIGN memory_manager
     711VIEW beha
     712GRAPHIC 224,0 375 0
     713DESIGN memory_manager
     714VIEW beha
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     716DESIGN memory_manager
     717VIEW beha
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     719DESIGN memory_manager
     720VIEW beha
     721GRAPHIC 433,0 378 0
     722DESIGN memory_manager
     723VIEW beha
     724GRAPHIC 622,0 379 0
     725DESIGN memory_manager
     726VIEW beha
     727GRAPHIC 289,0 380 0
     728DESIGN memory_manager
     729VIEW beha
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     731DESIGN memory_manager
     732VIEW beha
     733GRAPHIC 284,0 382 0
     734DESIGN memory_manager
     735VIEW beha
     736GRAPHIC 294,0 383 0
     737DESIGN memory_manager
     738VIEW beha
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     740DESIGN memory_manager
     741VIEW beha
     742GRAPHIC 299,0 385 0
     743DESIGN memory_manager
     744VIEW beha
     745GRAPHIC 379,0 386 0
     746DESIGN memory_manager
     747VIEW beha
     748GRAPHIC 915,0 387 0
     749DESIGN memory_manager
     750VIEW beha
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     752DESIGN @f@a@d_main
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    788758DESIGN spi_interface
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    800770DESIGN spi_interface
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     796GRAPHIC 48,0 409 0
    827797DESIGN trigger_counter
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    839 DESIGN @f@a@d_main
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    842 DESIGN w5300_modul
    843 VIEW symbol.sb
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    845 DESIGN w5300_modul
    846 VIEW @behavioral
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    848 DESIGN w5300_modul
    849 VIEW @behavioral
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    852 VIEW @behavioral
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    854 DESIGN w5300_modul
    855 VIEW @behavioral
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    873 VIEW @behavioral
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    878 DESIGN w5300_modul
    879 VIEW @behavioral
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    894 VIEW @behavioral
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    897 VIEW @behavioral
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    900 VIEW @behavioral
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/spi_interface_struct.xrf

    r9912 r10129  
    6161DESIGN spi_interface
    6262VIEW struct.bd
    63 GRAPHIC 1243,0 58 0
    64 DESIGN spi_interface
    65 VIEW struct.bd
    66 GRAPHIC 1249,0 59 0
    67 DESIGN spi_interface
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    70 DESIGN spi_interface
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    76 DESIGN spi_interface
    77 VIEW struct.bd
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    79 DESIGN spi_interface
    80 VIEW struct.bd
    81 GRAPHIC 1350,0 64 0
    82 DESIGN spi_interface
    83 VIEW struct.bd
    84 NO_GRAPHIC 65
    85 DESIGN spi_interface
    86 VIEW struct.bd
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    88 DESIGN spi_interface
    89 VIEW struct.bd
    90 NO_GRAPHIC 69
     63GRAPHIC 2738,0 58 0
     64DESIGN spi_interface
     65VIEW struct.bd
     66GRAPHIC 1243,0 59 0
     67DESIGN spi_interface
     68VIEW struct.bd
     69GRAPHIC 1249,0 60 0
     70DESIGN spi_interface
     71VIEW struct.bd
     72GRAPHIC 1326,0 61 0
     73DESIGN spi_interface
     74VIEW struct.bd
     75GRAPHIC 449,0 62 0
     76DESIGN spi_interface
     77VIEW struct.bd
     78GRAPHIC 1334,0 63 0
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     80VIEW struct.bd
     81GRAPHIC 1342,0 64 0
     82DESIGN spi_interface
     83VIEW struct.bd
     84GRAPHIC 1350,0 65 0
     85DESIGN spi_interface
     86VIEW struct.bd
     87NO_GRAPHIC 66
     88DESIGN spi_interface
     89VIEW struct.bd
     90GRAPHIC 1469,0 68 0
     91DESIGN spi_interface
     92VIEW struct.bd
     93NO_GRAPHIC 70
    9194LIBRARY FACT_FAD_lib
    92 DESIGN spi_clock_generator
     95DESIGN clk_divider
    9396VIEW beha
    94 GRAPHIC 2267,0 71 0
    95 DESIGN spi_interface
    96 VIEW struct.bd
    97 GRAPHIC 2274,0 72 1
    98 DESIGN spi_interface
    99 VIEW struct.bd
    100 NO_GRAPHIC 78
    101 DESIGN spi_interface
    102 VIEW struct.bd
    103 GRAPHIC 2249,0 80 0
    104 DESIGN spi_interface
    105 VIEW struct.bd
    106 NO_GRAPHIC 94
    107 DESIGN spi_interface
    108 VIEW struct.bd
    109 GRAPHIC 2195,0 96 0
    110 DESIGN spi_interface
    111 VIEW struct.bd
    112 GRAPHIC 2202,0 97 1
    113 DESIGN spi_interface
    114 VIEW struct.bd
    115 NO_GRAPHIC 115
     97GRAPHIC 2645,0 72 0
     98DESIGN spi_interface
     99VIEW struct.bd
     100GRAPHIC 2652,0 73 1
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     102VIEW struct.bd
     103NO_GRAPHIC 79
     104DESIGN spi_interface
     105VIEW struct.bd
     106GRAPHIC 2249,0 81 0
     107DESIGN spi_interface
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     109NO_GRAPHIC 95
     110DESIGN spi_interface
     111VIEW struct.bd
     112GRAPHIC 2195,0 97 0
     113DESIGN spi_interface
     114VIEW struct.bd
     115GRAPHIC 2202,0 98 1
     116DESIGN spi_interface
     117VIEW struct.bd
     118NO_GRAPHIC 116
    116119LIBRARY FACT_FAD_lib
    117120DESIGN spi_interface
    118121VIEW struct.bd
    119 NO_GRAPHIC 117
    120 DESIGN spi_interface
    121 VIEW struct.bd
    122 GRAPHIC 2267,0 120 0
    123 DESIGN spi_interface
    124 VIEW struct.bd
    125 GRAPHIC 2249,0 121 0
    126 DESIGN spi_interface
    127 VIEW struct.bd
    128 GRAPHIC 2195,0 122 0
    129 DESIGN spi_interface
    130 VIEW struct.bd
    131 NO_GRAPHIC 125
    132 DESIGN spi_interface
    133 VIEW struct.bd
    134 NO_GRAPHIC 127
    135 DESIGN spi_interface
    136 VIEW struct.bd
    137 GRAPHIC 2267,0 129 0
    138 DESIGN spi_interface
    139 VIEW struct.bd
    140 GRAPHIC 2274,0 130 1
    141 DESIGN spi_interface
    142 VIEW struct.bd
    143 GRAPHIC 222,0 134 0
    144 DESIGN spi_interface
    145 VIEW struct.bd
    146 GRAPHIC 214,0 135 0
    147 DESIGN spi_interface
    148 VIEW struct.bd
    149 GRAPHIC 2249,0 137 0
    150 DESIGN spi_interface
    151 VIEW struct.bd
    152 GRAPHIC 2002,0 139 0
    153 DESIGN spi_interface
    154 VIEW struct.bd
    155 GRAPHIC 244,0 140 0
    156 DESIGN spi_interface
    157 VIEW struct.bd
    158 GRAPHIC 2357,0 141 0
    159 DESIGN spi_interface
    160 VIEW struct.bd
    161 GRAPHIC 1328,0 142 0
    162 DESIGN spi_interface
    163 VIEW struct.bd
    164 GRAPHIC 1336,0 143 0
    165 DESIGN spi_interface
    166 VIEW struct.bd
    167 GRAPHIC 451,0 144 0
    168 DESIGN spi_interface
    169 VIEW struct.bd
    170 GRAPHIC 252,0 145 0
    171 DESIGN spi_interface
    172 VIEW struct.bd
    173 GRAPHIC 260,0 146 0
    174 DESIGN spi_interface
    175 VIEW struct.bd
    176 GRAPHIC 1251,0 147 0
    177 DESIGN spi_interface
    178 VIEW struct.bd
    179 GRAPHIC 1245,0 148 0
    180 DESIGN spi_interface
    181 VIEW struct.bd
    182 GRAPHIC 1344,0 149 0
    183 DESIGN spi_interface
    184 VIEW struct.bd
    185 GRAPHIC 1352,0 150 0
    186 DESIGN spi_interface
    187 VIEW struct.bd
    188 GRAPHIC 2195,0 152 0
    189 DESIGN spi_interface
    190 VIEW struct.bd
    191 GRAPHIC 2202,0 153 1
    192 DESIGN spi_interface
    193 VIEW struct.bd
    194 GRAPHIC 1469,0 157 0
    195 DESIGN spi_interface
    196 VIEW struct.bd
    197 GRAPHIC 1227,0 158 0
    198 DESIGN spi_interface
    199 VIEW struct.bd
    200 GRAPHIC 1233,0 159 0
    201 DESIGN spi_interface
    202 VIEW struct.bd
    203 GRAPHIC 2310,0 160 0
    204 DESIGN spi_interface
    205 VIEW struct.bd
    206 GRAPHIC 1604,0 161 0
    207 DESIGN spi_interface
    208 VIEW struct.bd
    209 GRAPHIC 489,0 162 0
    210 DESIGN spi_interface
    211 VIEW struct.bd
    212 GRAPHIC 1598,0 163 0
    213 DESIGN spi_interface
    214 VIEW struct.bd
    215 GRAPHIC 1251,0 164 0
    216 DESIGN spi_interface
    217 VIEW struct.bd
    218 GRAPHIC 1245,0 165 0
    219 DESIGN spi_interface
    220 VIEW struct.bd
    221 GRAPHIC 1344,0 166 0
    222 DESIGN spi_interface
    223 VIEW struct.bd
    224 GRAPHIC 1352,0 167 0
    225 DESIGN spi_interface
    226 VIEW struct.bd
    227 GRAPHIC 1328,0 168 0
    228 DESIGN spi_interface
    229 VIEW struct.bd
    230 GRAPHIC 1336,0 169 0
    231 DESIGN spi_interface
    232 VIEW struct.bd
    233 GRAPHIC 451,0 170 0
    234 DESIGN spi_interface
    235 VIEW struct.bd
    236 GRAPHIC 1469,0 174 0
    237 DESIGN spi_interface
    238 VIEW struct.bd
    239 NO_GRAPHIC 176
     122NO_GRAPHIC 118
     123DESIGN spi_interface
     124VIEW struct.bd
     125GRAPHIC 2645,0 121 0
     126DESIGN spi_interface
     127VIEW struct.bd
     128GRAPHIC 2249,0 122 0
     129DESIGN spi_interface
     130VIEW struct.bd
     131GRAPHIC 2195,0 123 0
     132DESIGN spi_interface
     133VIEW struct.bd
     134NO_GRAPHIC 126
     135DESIGN spi_interface
     136VIEW struct.bd
     137NO_GRAPHIC 128
     138DESIGN spi_interface
     139VIEW struct.bd
     140GRAPHIC 2645,0 130 0
     141DESIGN spi_interface
     142VIEW struct.bd
     143GRAPHIC 2652,0 131 1
     144DESIGN spi_interface
     145VIEW struct.bd
     146GRAPHIC 222,0 135 0
     147DESIGN spi_interface
     148VIEW struct.bd
     149GRAPHIC 214,0 136 0
     150DESIGN spi_interface
     151VIEW struct.bd
     152GRAPHIC 2689,0 138 0
     153DESIGN spi_interface
     154VIEW struct.bd
     155GRAPHIC 2696,0 139 1
     156DESIGN spi_interface
     157VIEW struct.bd
     158GRAPHIC 2631,0 143 0
     159DESIGN spi_interface
     160VIEW struct.bd
     161GRAPHIC 2732,0 144 0
     162DESIGN spi_interface
     163VIEW struct.bd
     164GRAPHIC 2249,0 146 0
     165DESIGN spi_interface
     166VIEW struct.bd
     167GRAPHIC 2002,0 148 0
     168DESIGN spi_interface
     169VIEW struct.bd
     170GRAPHIC 244,0 149 0
     171DESIGN spi_interface
     172VIEW struct.bd
     173GRAPHIC 2357,0 150 0
     174DESIGN spi_interface
     175VIEW struct.bd
     176GRAPHIC 1328,0 151 0
     177DESIGN spi_interface
     178VIEW struct.bd
     179GRAPHIC 1336,0 152 0
     180DESIGN spi_interface
     181VIEW struct.bd
     182GRAPHIC 451,0 153 0
     183DESIGN spi_interface
     184VIEW struct.bd
     185GRAPHIC 252,0 154 0
     186DESIGN spi_interface
     187VIEW struct.bd
     188GRAPHIC 260,0 155 0
     189DESIGN spi_interface
     190VIEW struct.bd
     191GRAPHIC 1251,0 156 0
     192DESIGN spi_interface
     193VIEW struct.bd
     194GRAPHIC 1245,0 157 0
     195DESIGN spi_interface
     196VIEW struct.bd
     197GRAPHIC 1344,0 158 0
     198DESIGN spi_interface
     199VIEW struct.bd
     200GRAPHIC 1352,0 159 0
     201DESIGN spi_interface
     202VIEW struct.bd
     203GRAPHIC 2195,0 161 0
     204DESIGN spi_interface
     205VIEW struct.bd
     206GRAPHIC 2202,0 162 1
     207DESIGN spi_interface
     208VIEW struct.bd
     209GRAPHIC 1469,0 166 0
     210DESIGN spi_interface
     211VIEW struct.bd
     212GRAPHIC 1227,0 167 0
     213DESIGN spi_interface
     214VIEW struct.bd
     215GRAPHIC 1233,0 168 0
     216DESIGN spi_interface
     217VIEW struct.bd
     218GRAPHIC 2310,0 169 0
     219DESIGN spi_interface
     220VIEW struct.bd
     221GRAPHIC 1604,0 170 0
     222DESIGN spi_interface
     223VIEW struct.bd
     224GRAPHIC 489,0 171 0
     225DESIGN spi_interface
     226VIEW struct.bd
     227GRAPHIC 1598,0 172 0
     228DESIGN spi_interface
     229VIEW struct.bd
     230GRAPHIC 1251,0 173 0
     231DESIGN spi_interface
     232VIEW struct.bd
     233GRAPHIC 1245,0 174 0
     234DESIGN spi_interface
     235VIEW struct.bd
     236GRAPHIC 1344,0 175 0
     237DESIGN spi_interface
     238VIEW struct.bd
     239GRAPHIC 1352,0 176 0
     240DESIGN spi_interface
     241VIEW struct.bd
     242GRAPHIC 1328,0 177 0
     243DESIGN spi_interface
     244VIEW struct.bd
     245GRAPHIC 1336,0 178 0
     246DESIGN spi_interface
     247VIEW struct.bd
     248GRAPHIC 451,0 179 0
     249DESIGN spi_interface
     250VIEW struct.bd
     251GRAPHIC 1469,0 183 0
     252DESIGN spi_interface
     253VIEW struct.bd
     254NO_GRAPHIC 185
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r10123 r10129  
    4040)
    4141(Instance
    42 name "I3"
    43 duLibraryName "moduleware"
    44 duName "assignment"
    45 elements [
    46 ]
    47 mwi 1
    48 uid 7652,0
    49 )
    50 (Instance
    5142name "I0"
    5243duLibraryName "moduleware"
     
    6152(EmbeddedInstance
    6253name "eb_ID"
    63 number "1"
     54number "4"
    6455)
    6556(EmbeddedInstance
     
    7263)
    7364(EmbeddedInstance
    74 name "SRCLK"
    75 number "4"
    76 )
    77 (EmbeddedInstance
    78 name "T_CS"
    79 number "5"
    80 )
    81 (EmbeddedInstance
    82 name "MISC"
    83 number "6"
    84 )
    85 (EmbeddedInstance
    86 name "eb2"
    87 number "8"
    88 )
    89 (EmbeddedInstance
    9065name "eb3"
    9166number "9"
    9267)
    9368(EmbeddedInstance
    94 name "eb1"
    95 number "7"
     69name "SRCLK"
     70number "1"
    9671)
    9772]
     
    149124(vvPair
    150125variable "date"
    151 value "27.01.2011"
     126value "28.01.2011"
    152127)
    153128(vvPair
    154129variable "day"
    155 value "Do"
     130value "Fr"
    156131)
    157132(vvPair
    158133variable "day_long"
    159 value "Donnerstag"
     134value "Freitag"
    160135)
    161136(vvPair
    162137variable "dd"
    163 value "27"
     138value "28"
    164139)
    165140(vvPair
     
    265240(vvPair
    266241variable "task_ModelSimPath"
    267 value "<TBD>"
     242value "C:\\modeltech_6.6a\\win32"
    268243)
    269244(vvPair
     
    297272(vvPair
    298273variable "time"
    299 value "17:58:52"
     274value "16:12:10"
    300275)
    301276(vvPair
     
    688663n "wiz_reset"
    689664t "std_logic"
    690 o 47
     665o 40
    691666suid 2,0
    692667i "'1'"
     
    727702b "(7 DOWNTO 0)"
    728703posAdd 0
    729 o 36
     704o 32
    730705suid 7,0
    731706i "(OTHERS => '0')"
     
    764739preAdd 0
    765740posAdd 0
    766 o 11
     741o 13
    767742suid 18,0
    768743)
     
    799774n "adc_oeb"
    800775t "std_logic"
    801 o 28
     776o 21
    802777suid 21,0
    803778i "'1'"
     
    834809n "board_id"
    835810t "std_logic_vector"
    836 b "(3 downto 0)"
    837 preAdd 0
    838 posAdd 0
     811b "(3 DOWNTO 0)"
    839812o 9
    840813suid 24,0
     
    871844n "crate_id"
    872845t "std_logic_vector"
    873 b "(1 downto 0)"
     846b "(1 DOWNTO 0)"
    874847o 10
    875848suid 25,0
     
    909882t "std_logic_vector"
    910883b "(9 DOWNTO 0)"
    911 o 44
     884o 37
    912885suid 26,0
    913886)
     
    945918n "wiz_cs"
    946919t "std_logic"
    947 o 45
     920o 38
    948921suid 28,0
    949922i "'1'"
     
    983956t "std_logic_vector"
    984957b "(15 DOWNTO 0)"
    985 o 50
     958o 43
    986959suid 27,0
    987960)
     
    1018991n "wiz_int"
    1019992t "std_logic"
    1020 o 12
     993o 14
    1021994suid 31,0
    1022995)
     
    10541027n "wiz_rd"
    10551028t "std_logic"
    1056 o 46
     1029o 39
    10571030suid 30,0
    10581031i "'1'"
     
    10911064n "wiz_wr"
    10921065t "std_logic"
    1093 o 48
     1066o 41
    10941067suid 29,0
    10951068i "'1'"
     
    11271100n "CLK_25_PS"
    11281101t "std_logic"
    1129 o 16
     1102o 15
    11301103suid 35,0
    11311104)
     
    11371110shape (Triangle
    11381111uid 1370,0
    1139 ro 270
     1112ro 90
    11401113va (VaSet
    11411114vasetType 1
    11421115fg "0,65535,0"
    11431116)
    1144 xt "51250,68625,52000,69375"
     1117xt "80000,115625,80750,116375"
    11451118)
    11461119tg (CPTG
    11471120uid 1371,0
    11481121ps "CptPortTextPlaceStrategy"
    1149 stg "VerticalLayoutStrategy"
     1122stg "RightVerticalLayoutStrategy"
    11501123f (Text
    11511124uid 1372,0
    11521125va (VaSet
    11531126)
    1154 xt "53000,68500,56100,69500"
     1127xt "75900,115500,79000,116500"
    11551128st "CLK_50"
    1156 blo "53000,69300"
     1129ju 2
     1130blo "79000,116300"
    11571131)
    11581132)
     
    11621136n "CLK_50"
    11631137t "std_logic"
    1164 o 17
     1138o 16
    11651139suid 37,0
    11661140)
     
    13011275t "std_logic_vector"
    13021276b "(3 downto 0)"
    1303 o 33
     1277o 29
    13041278suid 48,0
    13051279i "(others => '0')"
     
    13371311n "drs_dwrite"
    13381312t "std_logic"
    1339 o 34
     1313o 30
    13401314suid 49,0
    13411315i "'1'"
     
    15091483n "RSRLOAD"
    15101484t "std_logic"
    1511 o 24
     1485o 17
    15121486suid 56,0
    15131487i "'0'"
     
    15451519n "SRCLK"
    15461520t "std_logic"
    1547 o 25
     1521o 18
    15481522suid 57,0
    15491523i "'0'"
     
    15821556n "dac_cs"
    15831557t "std_logic"
    1584 o 31
     1558o 27
    15851559suid 64,0
    15861560)
     
    16181592n "sclk"
    16191593t "std_logic"
    1620 o 41
     1594o 35
    16211595suid 62,0
    16221596)
     
    16551629t "std_logic_vector"
    16561630b "(3 DOWNTO 0)"
    1657 o 42
     1631o 36
    16581632suid 65,0
    16591633)
     
    16931667preAdd 0
    16941668posAdd 0
    1695 o 49
     1669o 42
    16961670suid 63,0
    16971671)
     
    17291703n "mosi"
    17301704t "std_logic"
    1731 o 37
     1705o 33
    17321706suid 66,0
    17331707i "'0'"
     
    17681742eolc "-- default domino wave off"
    17691743posAdd 0
    1770 o 32
     1744o 28
    17711745suid 67,0
    17721746i "'0'"
     
    18041778n "adc_clk_en"
    18051779t "std_logic"
    1806 o 27
     1780o 20
    18071781suid 69,0
    18081782i "'0'"
     
    18111785)
    18121786*45 (CptPort
    1813 uid 10246,0
    1814 ps "OnEdgeStrategy"
    1815 shape (Triangle
    1816 uid 10247,0
    1817 ro 90
    1818 va (VaSet
    1819 vasetType 1
    1820 fg "0,65535,0"
    1821 )
    1822 xt "80000,129625,80750,130375"
    1823 )
    1824 tg (CPTG
    1825 uid 10248,0
    1826 ps "CptPortTextPlaceStrategy"
    1827 stg "RightVerticalLayoutStrategy"
    1828 f (Text
    1829 uid 10249,0
    1830 va (VaSet
    1831 )
    1832 xt "73800,129500,79000,130500"
    1833 st "DCM_locked"
    1834 ju 2
    1835 blo "79000,130300"
    1836 )
    1837 )
    1838 thePort (LogicalPort
    1839 m 1
    1840 decl (Decl
    1841 n "DCM_locked"
    1842 t "std_logic"
    1843 preAdd 0
    1844 posAdd 0
    1845 o 18
    1846 suid 76,0
    1847 )
    1848 )
    1849 )
    1850 *46 (CptPort
    1851 uid 10254,0
    1852 ps "OnEdgeStrategy"
    1853 shape (Triangle
    1854 uid 10255,0
    1855 ro 90
    1856 va (VaSet
    1857 vasetType 1
    1858 fg "0,65535,0"
    1859 )
    1860 xt "80000,135625,80750,136375"
    1861 )
    1862 tg (CPTG
    1863 uid 10256,0
    1864 ps "CptPortTextPlaceStrategy"
    1865 stg "RightVerticalLayoutStrategy"
    1866 f (Text
    1867 uid 10257,0
    1868 va (VaSet
    1869 )
    1870 xt "71300,135500,79000,136500"
    1871 st "LOCKED_extraOUT"
    1872 ju 2
    1873 blo "79000,136300"
    1874 )
    1875 )
    1876 thePort (LogicalPort
    1877 m 1
    1878 decl (Decl
    1879 n "LOCKED_extraOUT"
    1880 t "std_logic"
    1881 o 19
    1882 suid 70,0
    1883 )
    1884 )
    1885 )
    1886 *47 (CptPort
    1887 uid 10258,0
    1888 ps "OnEdgeStrategy"
    1889 shape (Triangle
    1890 uid 10259,0
    1891 ro 90
    1892 va (VaSet
    1893 vasetType 1
    1894 fg "0,65535,0"
    1895 )
    1896 xt "80000,138625,80750,139375"
    1897 )
    1898 tg (CPTG
    1899 uid 10260,0
    1900 ps "CptPortTextPlaceStrategy"
    1901 stg "RightVerticalLayoutStrategy"
    1902 f (Text
    1903 uid 10261,0
    1904 va (VaSet
    1905 )
    1906 xt "74200,138500,79000,139500"
    1907 st "offset : (7:0)"
    1908 ju 2
    1909 blo "79000,139300"
    1910 )
    1911 )
    1912 thePort (LogicalPort
    1913 m 1
    1914 decl (Decl
    1915 n "offset"
    1916 t "std_logic_vector"
    1917 b "(7 downto 0)"
    1918 preAdd 0
    1919 posAdd 0
    1920 o 38
    1921 suid 77,0
    1922 i "(OTHERS => '0')"
    1923 )
    1924 )
    1925 )
    1926 *48 (CptPort
    1927 uid 10262,0
    1928 ps "OnEdgeStrategy"
    1929 shape (Triangle
    1930 uid 10263,0
    1931 ro 90
    1932 va (VaSet
    1933 vasetType 1
    1934 fg "0,65535,0"
    1935 )
    1936 xt "80000,125625,80750,126375"
    1937 )
    1938 tg (CPTG
    1939 uid 10264,0
    1940 ps "CptPortTextPlaceStrategy"
    1941 stg "RightVerticalLayoutStrategy"
    1942 f (Text
    1943 uid 10265,0
    1944 va (VaSet
    1945 )
    1946 xt "74600,125500,79000,126500"
    1947 st "PS_DIR_IN"
    1948 ju 2
    1949 blo "79000,126300"
    1950 )
    1951 )
    1952 thePort (LogicalPort
    1953 m 1
    1954 decl (Decl
    1955 n "PS_DIR_IN"
    1956 t "std_logic"
    1957 o 23
    1958 suid 80,0
    1959 )
    1960 )
    1961 )
    1962 *49 (CptPort
    1963 uid 10270,0
    1964 ps "OnEdgeStrategy"
    1965 shape (Triangle
    1966 uid 10271,0
    1967 ro 90
    1968 va (VaSet
    1969 vasetType 1
    1970 fg "0,65535,0"
    1971 )
    1972 xt "80000,134625,80750,135375"
    1973 )
    1974 tg (CPTG
    1975 uid 10272,0
    1976 ps "CptPortTextPlaceStrategy"
    1977 stg "RightVerticalLayoutStrategy"
    1978 f (Text
    1979 uid 10273,0
    1980 va (VaSet
    1981 )
    1982 xt "74000,134500,79000,135500"
    1983 st "PSCLK_OUT"
    1984 ju 2
    1985 blo "79000,135300"
    1986 )
    1987 )
    1988 thePort (LogicalPort
    1989 m 1
    1990 decl (Decl
    1991 n "PSCLK_OUT"
    1992 t "std_logic"
    1993 o 20
    1994 suid 74,0
    1995 )
    1996 )
    1997 )
    1998 *50 (CptPort
    1999 uid 10274,0
    2000 ps "OnEdgeStrategy"
    2001 shape (Triangle
    2002 uid 10275,0
    2003 ro 90
    2004 va (VaSet
    2005 vasetType 1
    2006 fg "0,65535,0"
    2007 )
    2008 xt "80000,133625,80750,134375"
    2009 )
    2010 tg (CPTG
    2011 uid 10276,0
    2012 ps "CptPortTextPlaceStrategy"
    2013 stg "RightVerticalLayoutStrategy"
    2014 f (Text
    2015 uid 10277,0
    2016 va (VaSet
    2017 )
    2018 xt "71200,133500,79000,134500"
    2019 st "PSDONE_extraOUT"
    2020 ju 2
    2021 blo "79000,134300"
    2022 )
    2023 )
    2024 thePort (LogicalPort
    2025 m 1
    2026 decl (Decl
    2027 n "PSDONE_extraOUT"
    2028 t "std_logic"
    2029 o 21
    2030 suid 71,0
    2031 )
    2032 )
    2033 )
    2034 *51 (CptPort
    2035 uid 10282,0
    2036 ps "OnEdgeStrategy"
    2037 shape (Triangle
    2038 uid 10283,0
    2039 ro 90
    2040 va (VaSet
    2041 vasetType 1
    2042 fg "0,65535,0"
    2043 )
    2044 xt "80000,127625,80750,128375"
    2045 )
    2046 tg (CPTG
    2047 uid 10284,0
    2048 ps "CptPortTextPlaceStrategy"
    2049 stg "RightVerticalLayoutStrategy"
    2050 f (Text
    2051 uid 10285,0
    2052 va (VaSet
    2053 )
    2054 xt "72000,127500,79000,128500"
    2055 st "PSINCDEC_OUT"
    2056 ju 2
    2057 blo "79000,128300"
    2058 )
    2059 )
    2060 thePort (LogicalPort
    2061 m 1
    2062 decl (Decl
    2063 n "PSINCDEC_OUT"
    2064 t "std_logic"
    2065 o 22
    2066 suid 72,0
    2067 )
    2068 )
    2069 )
    2070 *52 (CptPort
    2071 uid 10286,0
    2072 ps "OnEdgeStrategy"
    2073 shape (Triangle
    2074 uid 10287,0
    2075 ro 90
    2076 va (VaSet
    2077 vasetType 1
    2078 fg "0,65535,0"
    2079 )
    2080 xt "80000,131625,80750,132375"
    2081 )
    2082 tg (CPTG
    2083 uid 10288,0
    2084 ps "CptPortTextPlaceStrategy"
    2085 stg "RightVerticalLayoutStrategy"
    2086 f (Text
    2087 uid 10289,0
    2088 va (VaSet
    2089 )
    2090 xt "76800,131500,79000,132500"
    2091 st "ready"
    2092 ju 2
    2093 blo "79000,132300"
    2094 )
    2095 )
    2096 thePort (LogicalPort
    2097 m 1
    2098 decl (Decl
    2099 n "ready"
    2100 t "std_logic"
    2101 preAdd 0
    2102 posAdd 0
    2103 o 39
    2104 suid 79,0
    2105 i "'0'"
    2106 )
    2107 )
    2108 )
    2109 *53 (CptPort
    2110 uid 10290,0
    2111 ps "OnEdgeStrategy"
    2112 shape (Triangle
    2113 uid 10291,0
    2114 ro 90
    2115 va (VaSet
    2116 vasetType 1
    2117 fg "0,65535,0"
    2118 )
    2119 xt "80000,132625,80750,133375"
    2120 )
    2121 tg (CPTG
    2122 uid 10292,0
    2123 ps "CptPortTextPlaceStrategy"
    2124 stg "RightVerticalLayoutStrategy"
    2125 f (Text
    2126 uid 10293,0
    2127 va (VaSet
    2128 )
    2129 xt "76100,132500,79000,133500"
    2130 st "shifting"
    2131 ju 2
    2132 blo "79000,133300"
    2133 )
    2134 )
    2135 thePort (LogicalPort
    2136 m 1
    2137 decl (Decl
    2138 n "shifting"
    2139 t "std_logic"
    2140 prec "-- status:"
    2141 preAdd 0
    2142 posAdd 0
    2143 o 43
    2144 suid 78,0
    2145 i "'0'"
    2146 )
    2147 )
    2148 )
    2149 *54 (CptPort
    2150 uid 10320,0
    2151 ps "OnEdgeStrategy"
    2152 shape (Triangle
    2153 uid 10321,0
    2154 ro 90
    2155 va (VaSet
    2156 vasetType 1
    2157 fg "0,65535,0"
    2158 )
    2159 xt "80000,123625,80750,124375"
    2160 )
    2161 tg (CPTG
    2162 uid 10322,0
    2163 ps "CptPortTextPlaceStrategy"
    2164 stg "RightVerticalLayoutStrategy"
    2165 f (Text
    2166 uid 10323,0
    2167 va (VaSet
    2168 )
    2169 xt "74200,123500,79000,124500"
    2170 st "CLK25_OUT"
    2171 ju 2
    2172 blo "79000,124300"
    2173 )
    2174 )
    2175 thePort (LogicalPort
    2176 m 1
    2177 decl (Decl
    2178 n "CLK25_OUT"
    2179 t "std_logic"
    2180 o 13
    2181 suid 83,0
    2182 )
    2183 )
    2184 )
    2185 *55 (CptPort
    2186 uid 10324,0
    2187 ps "OnEdgeStrategy"
    2188 shape (Triangle
    2189 uid 10325,0
    2190 ro 90
    2191 va (VaSet
    2192 vasetType 1
    2193 fg "0,65535,0"
    2194 )
    2195 xt "80000,124625,80750,125375"
    2196 )
    2197 tg (CPTG
    2198 uid 10326,0
    2199 ps "CptPortTextPlaceStrategy"
    2200 stg "RightVerticalLayoutStrategy"
    2201 f (Text
    2202 uid 10327,0
    2203 va (VaSet
    2204 )
    2205 xt "72800,124500,79000,125500"
    2206 st "CLK25_PSOUT"
    2207 ju 2
    2208 blo "79000,125300"
    2209 )
    2210 )
    2211 thePort (LogicalPort
    2212 m 1
    2213 decl (Decl
    2214 n "CLK25_PSOUT"
    2215 t "std_logic"
    2216 o 14
    2217 suid 84,0
    2218 )
    2219 )
    2220 )
    2221 *56 (CptPort
    2222 uid 10328,0
    2223 ps "OnEdgeStrategy"
    2224 shape (Triangle
    2225 uid 10329,0
    2226 ro 90
    2227 va (VaSet
    2228 vasetType 1
    2229 fg "0,65535,0"
    2230 )
    2231 xt "80000,122625,80750,123375"
    2232 )
    2233 tg (CPTG
    2234 uid 10330,0
    2235 ps "CptPortTextPlaceStrategy"
    2236 stg "RightVerticalLayoutStrategy"
    2237 f (Text
    2238 uid 10331,0
    2239 va (VaSet
    2240 )
    2241 xt "74200,122500,79000,123500"
    2242 st "CLK50_OUT"
    2243 ju 2
    2244 blo "79000,123300"
    2245 )
    2246 )
    2247 thePort (LogicalPort
    2248 m 1
    2249 decl (Decl
    2250 n "CLK50_OUT"
    2251 t "std_logic"
    2252 o 15
    2253 suid 82,0
    2254 )
    2255 )
    2256 )
    2257 *57 (CptPort
    22581787uid 12314,0
    22591788ps "OnEdgeStrategy"
     
    22861815n "SRIN_out"
    22871816t "std_logic"
    2288 o 26
     1817o 19
    22891818suid 85,0
    22901819i "'0'"
     
    22921821)
    22931822)
    2294 *58 (CptPort
     1823*46 (CptPort
    22951824uid 12521,0
    22961825ps "OnEdgeStrategy"
     
    23231852n "amber"
    23241853t "std_logic"
    2325 o 30
     1854o 25
    23261855suid 87,0
    23271856)
    23281857)
    23291858)
    2330 *59 (CptPort
     1859*47 (CptPort
    23311860uid 12525,0
    23321861ps "OnEdgeStrategy"
     
    23591888n "green"
    23601889t "std_logic"
    2361 o 35
     1890o 31
    23621891suid 86,0
    23631892)
    23641893)
    23651894)
    2366 *60 (CptPort
     1895*48 (CptPort
    23671896uid 12529,0
    23681897ps "OnEdgeStrategy"
     
    23951924n "red"
    23961925t "std_logic"
    2397 o 40
     1926o 34
    23981927suid 88,0
    23991928)
    24001929)
    24011930)
    2402 *61 (CptPort
     1931*49 (CptPort
    24031932uid 13843,0
    24041933ps "OnEdgeStrategy"
     
    24311960n "additional_flasher_out"
    24321961t "std_logic"
    2433 o 29
     1962o 22
    24341963suid 90,0
    24351964)
    24361965)
    24371966)
    2438 *62 (CptPort
     1967*50 (CptPort
    24391968uid 14682,0
    24401969ps "OnEdgeStrategy"
     
    24461975fg "0,65535,0"
    24471976)
    2448 xt "51250,138625,52000,139375"
     1977xt "51250,131625,52000,132375"
    24491978)
    24501979tg (CPTG
     
    24561985va (VaSet
    24571986)
    2458 xt "53000,138500,58500,139500"
     1987xt "53000,131500,58500,132500"
    24591988st "D_T_in : (1:0)"
    2460 blo "53000,139