Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd.bak (revision 10132) +++ (revision ) @@ -1,357 +1,0 @@ --- --- VHDL Architecture FACT_FAD_lib.data_generator.beha --- --- Created: --- by - FPGA_Developer.UNKNOWN (EEPC8) --- at - 14:36:14 10.02.2010 --- --- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library fact_fad_lib; -use fact_fad_lib.fad_definitions.all; - --- -- Uncomment the following library declaration if instantiating --- -- any Xilinx primitives in this code. --- library UNISIM; --- use UNISIM.VComponents.all; - -entity data_generator is - generic( - RAM_ADDR_WIDTH : integer := 12 - ); - port( --- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - - clk : in std_logic; - data_out : out std_logic_vector (63 downto 0); - addr_out : out std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); - write_ea : out std_logic_vector (0 downto 0) := "0"; - ram_start_addr : in std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); - ram_write_ea : in std_logic; - ram_write_ready : out std_logic := '0'; - -- -- - ram_write_ready_ack : IN std_logic; - -- -- - config_start_mm, config_start_cm, config_start_spi : out std_logic := '0'; - config_ready_mm, config_ready_cm, config_ready_spi : in std_logic; - config_started_mm, config_started_cm, config_started_spi : in std_logic; - roi_array : in roi_array_type; - roi_max : in roi_max_type; - sensor_array : in sensor_array_type; - sensor_ready : in std_logic; - dac_array : in dac_array_type; - package_length : in std_logic_vector (15 downto 0); - board_id : in std_logic_vector (3 downto 0); - crate_id : in std_logic_vector (1 downto 0); - trigger_id : in std_logic_vector (47 downto 0); - trigger : in std_logic; --- s_trigger : in std_logic; - new_config : in std_logic; - config_started : out std_logic := '0'; - adc_data_array : in adc_data_array_type; - adc_oeb : out std_logic := '1'; - adc_clk_en : out std_logic := '0'; - adc_otr : in std_logic_vector (3 downto 0); - drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0'); - -- -- --- drs_dwrite : out std_logic := '1'; - drs_readout_ready : out std_logic := '0'; - -- -- - drs_clk_en, drs_read_s_cell : out std_logic := '0'; - - drs_srin_write_8b : out std_logic := '0'; - drs_srin_write_ack : in std_logic; - drs_srin_data : out std_logic_vector (7 downto 0) := (others => '0'); - drs_srin_write_ready : in std_logic; - - drs_read_s_cell_ready : in std_logic; - drs_s_cell_array : in drs_s_cell_array_type; - - drs_readout_started : out std_logic := '0' - ); -end data_generator ; - -architecture Behavioral of data_generator is - -type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, - WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, - WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1, - WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); - -signal state_generate : state_generate_type := INIT; -signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - -signal data_cntr : integer range 0 to 1024 := 0; -signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0'); -signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words -signal channel_id : integer range 0 to 9 := 0; -signal adc_wait_cnt : integer range 0 to 7 := 0; - -signal trigger_flag :std_logic := '0'; -signal ram_write_ea_flag : std_logic := '0'; -signal new_config_int : std_logic := '0'; - -signal roi_max_int : roi_max_type; - -signal sig_drs_readout_started : std_logic := '0'; - -begin - - drs_readout_started <= sig_drs_readout_started; - - generate_data : process (clk) - begin - if rising_edge (clk) then - trigger_flag <= trigger; - - addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); - - case state_generate is - when INIT => - state_generate <= CONFIG; - - when CONFIG => - config_started <= '1'; - if (new_config = '0') then - config_started <= '0'; - -- config config manager - config_start_cm <= '1'; - if (config_started_cm = '1') then - config_start_cm <= '0'; - state_generate <= CONFIG1; - end if; - end if; - when CONFIG1 => - if (config_ready_cm = '1') then - config_start_mm <= '1'; - end if; - if (config_started_mm = '1') then - config_start_mm <= '0'; - state_generate <= CONFIG2; - end if; - when CONFIG2 => - if (config_ready_mm = '1') then - config_start_spi <= '1'; - end if; - if (config_started_spi = '1') then - config_start_spi <= '0'; - state_generate <= CONFIG3; - end if; - when CONFIG3 => - if (config_ready_spi = '1') then - state_generate <= CONFIG4; --- state_generate <= WRITE_DATA_IDLE; - end if; - -- configure DRS - when CONFIG4 => - drs_channel_id <= DRS_WRITE_SHIFT_REG; - drs_srin_data <= "11111111"; - drs_srin_write_8b <= '1'; - if (drs_srin_write_ack = '1') then - drs_srin_write_8b <= '0'; - state_generate <= CONFIG5; - end if; - when CONFIG5 => - if (drs_srin_write_ready = '1') then - roi_max_int <= roi_max; - state_generate <= CONFIG6; - end if; - when CONFIG6 => - drs_channel_id <= DRS_WRITE_CONFIG_REG; - drs_srin_data <= "11111111"; - drs_srin_write_8b <= '1'; - if (drs_srin_write_ack = '1') then - drs_srin_write_8b <= '0'; - state_generate <= CONFIG7; - end if; - when CONFIG7 => - if (drs_srin_write_ready = '1') then - roi_max_int <= roi_max; - state_generate <= WRITE_DATA_IDLE; - end if; - -- end configure DRS - - when WRITE_DATA_IDLE => - if (new_config = '1') then - state_generate <= CONFIG; - end if; --- if (ram_write_ea = '1' and (trigger_flag = '1' or s_trigger = '1')) then - if (ram_write_ea = '1' and trigger_flag = '1') then - sig_drs_readout_started <= '1'; -- is set to '0' in state WRITE_DAC1 - -- stop drs, dwrite low - -- drs_dwrite <= '0'; - -- start reading of drs stop cell - drs_read_s_cell <= '1'; - -- enable adc output - adc_oeb <= '0'; - -- switch on ADC_CLK - adc_clk_en <= '1'; - start_addr <= ram_start_addr; - state_generate <= WRITE_HEADER; - evnt_cntr <= evnt_cntr + 1; - end if; - when WRITE_HEADER => - write_ea <= "1"; - data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; - addr_cntr <= addr_cntr + 3; - state_generate <= WRITE_BOARD_ID; - when WRITE_BOARD_ID => -- crate ID & board ID - data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_TEMPERATURES; - when WRITE_TEMPERATURES => -- temperatures - if (sensor_ready = '1') then - data_out <= conv_std_logic_vector (sensor_array (3), 16) - & conv_std_logic_vector (sensor_array (2), 16) - & conv_std_logic_vector (sensor_array (1), 16) - & conv_std_logic_vector (sensor_array (0), 16); - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_DAC1; - end if; - - when WRITE_DAC1 => - sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE - data_out <= conv_std_logic_vector (dac_array (3), 16) - & conv_std_logic_vector (dac_array (2), 16) - & conv_std_logic_vector (dac_array (1), 16) - & conv_std_logic_vector (dac_array (0), 16); - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_DAC2; - when WRITE_DAC2 => - data_out <= conv_std_logic_vector (dac_array (7), 16) - & conv_std_logic_vector (dac_array (6), 16) - & conv_std_logic_vector (dac_array (5), 16) - & conv_std_logic_vector (dac_array (4), 16); - addr_cntr <= addr_cntr + 1; - state_generate <= WAIT_FOR_STOP_CELL; - - when WAIT_FOR_STOP_CELL => - drs_read_s_cell <= '0'; - if (drs_read_s_cell_ready = '1') then - state_generate <= START_DRS_READING; - end if; - - when START_DRS_READING => - --drs channel number - drs_channel_id <= conv_std_logic_vector (channel_id, 4); - --starte drs-clocking - --adc_oeb <= '0'; -- nur für Emulator - drs_clk_en <= '1'; - adc_wait_cnt <= 0; - state_generate <= WRITE_CHANNEL_ID; - - when WRITE_CHANNEL_ID => -- write DRS and Channel IDs - data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4) - & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4) - & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4) - & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4); - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_START_CELL; - when WRITE_START_CELL => -- write start cells - data_out <= "000000" & drs_s_cell_array (3) - & "000000" & drs_s_cell_array (2) - & "000000" & drs_s_cell_array (1) - & "000000" & drs_s_cell_array (0); - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_ROI; - when WRITE_ROI => -- write ROI - data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11) - & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11) - & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11) - & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); - addr_cntr <= addr_cntr + 1; - state_generate <= WAIT_FOR_ADC; - when WAIT_FOR_ADC => - -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA??? - adc_wait_cnt <= adc_wait_cnt + 1; - else - state_generate <= WRITE_ADC_DATA; - end if; - when WRITE_ADC_DATA => - if (data_cntr < roi_max (channel_id)) then - data_out <= "000" & adc_otr(3) & adc_data_array(3) - & "000" & adc_otr(2) & adc_data_array(2) - & "000" & adc_otr(1) & adc_data_array(1) - & "000" & adc_otr(0) & adc_data_array(0); - -- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) --- & "00010" & conv_std_logic_vector (data_cntr, 11) --- & "00100" & conv_std_logic_vector (data_cntr, 11) --- & "00110" & conv_std_logic_vector (data_cntr, 11) ; - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_ADC_DATA; - data_cntr <= data_cntr + 1; - else - drs_clk_en <= '0'; - --adc_oeb <= '1'; -- nur für Emulator - if (channel_id = 8) then - state_generate <= WRITE_EXTERNAL_TRIGGER; - adc_oeb <= '1'; - -- switch off ADC_CLK - adc_clk_en <= '0'; - else - channel_id <= channel_id + 1; -- increment channel_id - state_generate <= START_DRS_READING; - data_cntr <= 0; - end if; - end if; - - - when WRITE_EXTERNAL_TRIGGER => -- external trigger ID - addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); --- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); - data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); - state_generate <= WRITE_INTERNAL_TRIGGER; - when WRITE_INTERNAL_TRIGGER => -- internal trigger ID - addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); - data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); - state_generate <= WRITE_END_FLAG; - when WRITE_END_FLAG => - data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_DATA_END; - when WRITE_DATA_END => - write_ea <= "0"; - ram_write_ready <= '1'; - state_generate <= WRITE_DATA_END_WAIT; - when WRITE_DATA_END_WAIT => - -- -- - if (ram_write_ready_ack = '1') then - state_generate <= WRITE_DATA_STOP; - -- -- - ram_write_ready <= '0'; - -- -- - end if; - -- -- - when WRITE_DATA_STOP => - -- -- - if (ram_write_ready_ack = '0') then - -- -- --- drs_dwrite <= '1'; - drs_readout_ready <= '1'; - data_cntr <= 0; - addr_cntr <= 0; - channel_id <= 0; - state_generate <= WRITE_DATA_STOP1; - -- -- - end if; - -- -- - when WRITE_DATA_STOP1 => - if (drs_readout_ready_ack = '1') then - drs_readout_ready <= '0'; - state_generate <= WRITE_DATA_IDLE; - end if; - when others => - null; - - end case; -- state_generate - end if; -- rising_edge (clk) - end process generate_data; - -end Behavioral; - - Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf.bak (revision 10132) +++ (revision ) @@ -1,261 +1,0 @@ -########################################################### -# Pin location constraints -########################################################### - -#CLOCK -NET X_50M LOC = AF13 | IOSTANDARD=LVCMOS33; #ok - -## single ended trigger input -NET TRG LOC = AC8 | IOSTANDARD=LVCMOS33; #ok - -#Test Trigger input on 'Testpoint near W5300' -#NET _TW<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok -#NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33 ; - - - -## trigger veto: xilinx output -NET TRG_V LOC = AC9 | IOSTANDARD=LVCMOS33; #ok -## NET INIT_B LOC = AA15 | IOSTANDARD=LVCMOS33; #ok - - - -# RS485 Driver - -NET RS485_C_DE LOC = C5 | IOSTANDARD=LVCMOS33; #ok -NET RS485_C_RE LOC = C6 | IOSTANDARD=LVCMOS33; #ok -NET RS485_C_DO LOC = C7 | IOSTANDARD=LVCMOS33; #ok -NET RS485_C_DI LOC = C8 | IOSTANDARD=LVCMOS33; #ok - -NET RS485_E_DE LOC = D20 | IOSTANDARD=LVCMOS33; #ok -NET RS485_E_RE LOC = D21 | IOSTANDARD=LVCMOS33; #ok -NET RS485_E_DO LOC = D22 | IOSTANDARD=LVCMOS33; #ok -NET RS485_E_DI LOC = D23 | IOSTANDARD=LVCMOS33; #ok - - -# BOARD ID - inputs -NET LINE<0> LOC = Y1 | IOSTANDARD=LVCMOS33; #ok -NET LINE<1> LOC = Y2 | IOSTANDARD=LVCMOS33; #ok -NET LINE<2> LOC = AB1 | IOSTANDARD=LVCMOS33; #ok -NET LINE<3> LOC = AC1 | IOSTANDARD=LVCMOS33; #ok -NET LINE<4> LOC = AD1 | IOSTANDARD=LVCMOS33; #ok -NET LINE<5> LOC = AD2 | IOSTANDARD=LVCMOS33; #ok - -# W5300 -####################################################### -NET W_D<15> LOC = D24 | IOSTANDARD=LVCMOS33; #ok -NET W_D<14> LOC = D25 | IOSTANDARD=LVCMOS33; #ok -NET W_D<13> LOC = D26 | IOSTANDARD=LVCMOS33; #ok -NET W_D<12> LOC = E24 | IOSTANDARD=LVCMOS33; #ok -NET W_D<11> LOC = E26 | IOSTANDARD=LVCMOS33; #ok -NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; #ok -NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; #ok -NET W_D<8> LOC = G23 | IOSTANDARD=LVCMOS33; #ok -NET W_D<7> LOC = G24 | IOSTANDARD=LVCMOS33; #ok -NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; #ok -NET W_D<5> LOC = K25 | IOSTANDARD=LVCMOS33; #ok -NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; #ok -NET W_D<3> LOC = J22 | IOSTANDARD=LVCMOS33; #ok -NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; #ok -NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; #ok -NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; #ok - -NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; #ok -NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; #ok -NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; #ok -NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; #ok -NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; #ok -NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; #ok -NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; #ok -NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; #ok -NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; #ok -NET W_A<0> LOC = Y22 | IOSTANDARD=LVCMOS33; #ok DUMMY - -NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; #ok -NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; #ok -NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; #ok -NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; #ok -NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; #ok - -#NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #ok -#NET W_BRDY<2> LOC = AC26 | IOSTANDARD=LVCMOS33; #ok -#NET W_BRDY<1> LOC = AC25 | IOSTANDARD=LVCMOS33; #ok -#NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #ok -# Testpoint near W5300 -#NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok -#NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok -#NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok -#NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok - -# Platform Flash - serial connection -####################################################### -##NET FL_CLK LOC = AE24 | IOSTANDARD=LVCMOS33; #ok -##NET FL_D0 LOC = AF24 | IOSTANDARD=LVCMOS33; #ok - -# DRS Signals -####################################################### -NET DENABLE LOC = B1 | IOSTANDARD=LVCMOS25; #ok -NET DWRITE LOC = R2 | IOSTANDARD=LVCMOS25; #ok - -NET SRIN LOC = E1 | IOSTANDARD=LVCMOS25; #ok -- nur fuer vollauslese noetig; auf Z legen. -NET REFCLK LOC = AC11 | IOSTANDARD=LVCMOS25; #ok -- listen to REFCLK possible - - -NET D_A<3> LOC = N1 | IOSTANDARD=LVCMOS25; #ok -NET D_A<2> LOC = M2 | IOSTANDARD=LVCMOS25; #ok -NET D_A<1> LOC = K2 | IOSTANDARD=LVCMOS25; #ok -NET D_A<0> LOC = H2 | IOSTANDARD=LVCMOS25; #ok - - -# PLL-Lock input: high active -NET D_PLLLCK<0> LOC = L3 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok -NET D_PLLLCK<1> LOC = N2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok -NET D_PLLLCK<2> LOC = AA2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok -NET D_PLLLCK<3> LOC = AC2 | IOSTANDARD=LVCMOS25 | PULLDOWN ; #ok - -# SROUT input: read stop position here -# bus?? -NET D0_SROUT LOC = B2 | IOSTANDARD=LVCMOS25; #ok -NET D1_SROUT LOC = E3 | IOSTANDARD=LVCMOS25; #ok -NET D2_SROUT LOC = N4 | IOSTANDARD=LVCMOS25; #ok -NET D3_SROUT LOC = U1 | IOSTANDARD=LVCMOS25; #ok - -# RSRLOAD & SRCLK output: clock out analog samples here -# SRCLK bus?? -NET RSRLOAD LOC = H1 | IOSTANDARD=LVCMOS25; #ok -# -NET D0_SRCLK LOC = F2 | IOSTANDARD=LVCMOS25; #ok -NET D1_SRCLK LOC = F3 | IOSTANDARD=LVCMOS25; #ok -NET D2_SRCLK LOC = R3 | IOSTANDARD=LVCMOS25; #ok -NET D3_SRCLK LOC = V1 | IOSTANDARD=LVCMOS25; #ok - -# Testpoints near DRS Chips -# oganized in 3 times 4x2 pins -NET D_T<0> LOC = D3 | IOSTANDARD=LVCMOS25; #ok -NET D_T<1> LOC = G3 | IOSTANDARD=LVCMOS25; #ok -NET D_T<2> LOC = G4 | IOSTANDARD=LVCMOS25; #ok -NET D_T<3> LOC = J4 | IOSTANDARD=LVCMOS25; #ok -NET D_T<4> LOC = K5 | IOSTANDARD=LVCMOS25; #ok -NET D_T<5> LOC = L4 | IOSTANDARD=LVCMOS25; #ok -#NET D_T_in<0> LOC = M3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<6> LOC = M3 -#NET D_T_in<1> LOC = T3 | IOSTANDARD=LVCMOS25 | pullup; #ok was: NET D_T<7> LOC = T3 -NET D_T<6> LOC = M3 | IOSTANDARD=LVCMOS25; #ok -NET D_T<7> LOC = T3 | IOSTANDARD=LVCMOS25; #ok -NET D_T2<0> LOC = U2 | IOSTANDARD=LVCMOS25; #ok was D_T<8> -NET D_T2<1> LOC = V2 | IOSTANDARD=LVCMOS25; #ok was D_T<9> -#NET D_T2<2> LOC = W3 | IOSTANDARD=LVCMOS25; #ok aka D_TA was D_T<10> -#NET D_T2<3> LOC = AA3 | IOSTANDARD=LVCMOS25; #ok aka D_TB was D_T<11> -NET D_T_in<0> LOC = W3 | IOSTANDARD=LVCMOS25 | pullup; #ok aka D_TA was D_T<10> -NET D_T_in<1> LOC = AA3 | IOSTANDARD=LVCMOS25 | pullup; #ok aka D_TB was D_T<11> - -# ADC Signals -####################################################### -NET OE_ADC LOC = D6 | IOSTANDARD=LVCMOS33; #ok FIXME was A-OEB - -NET A_CLK<0> LOC = B23 | IOSTANDARD=LVCMOS33; #ok aka A0_CLK -NET A_CLK<1> LOC = A3 | IOSTANDARD=LVCMOS33; #ok aka A1_CLK -NET A_CLK<2> LOC = AE3 | IOSTANDARD=LVCMOS33; #ok aka A2_CLK -NET A_CLK<3> LOC = AE25 | IOSTANDARD=LVCMOS33; #ok aka A3_CLK - -NET A_OTR<0> LOC = A22 | IOSTANDARD=LVCMOS33; #ok aka A0_OTR -NET A_OTR<1> LOC = B12 | IOSTANDARD=LVCMOS33; #ok aka A1_OTR -NET A_OTR<2> LOC = AF3 | IOSTANDARD=LVCMOS33; #ok aka A2_OTR -NET A_OTR<3> LOC = AE17 | IOSTANDARD=LVCMOS33; #ok aka A3_OTR - -# ADC data -NET A0_D<0> LOC = D13 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<1> LOC = A15 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<2> LOC = B15 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<3> LOC = B17 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<4> LOC = D16 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<5> LOC = A18 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<6> LOC = B18 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<7> LOC = A19 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<8> LOC = B19 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<9> LOC = A20 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<10> LOC = B21 | IOSTANDARD=LVCMOS33; #ok -NET A0_D<11> LOC = C22 | IOSTANDARD=LVCMOS33; #ok - -NET A1_D<0> LOC = B3 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<1> LOC = A4 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<2> LOC = B4 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<3> LOC = B6 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<4> LOC = B7 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<5> LOC = A8 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<6> LOC = B8 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<7> LOC = A9 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<8> LOC = B9 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<9> LOC = A10 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<10> LOC = B10 | IOSTANDARD=LVCMOS33; #ok -NET A1_D<11> LOC = A12 | IOSTANDARD=LVCMOS33; #ok - -NET A2_D<0> LOC = AD14 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<1> LOC = AD11 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<2> LOC = AD7 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<3> LOC = AE8 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<4> LOC = AF8 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<5> LOC = AE7 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<6> LOC = AC6 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<7> LOC = AE6 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<8> LOC = AF5 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<9> LOC = AD6 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<10> LOC = AF4 | IOSTANDARD=LVCMOS33; #ok -NET A2_D<11> LOC = AE4 | IOSTANDARD=LVCMOS33; #ok - -NET A3_D<0> LOC = AF25 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<1> LOC = AE23 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<2> LOC = AF23 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<3> LOC = AD22 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<4> LOC = AE21 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<5> LOC = AD21 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<6> LOC = AF20 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<7> LOC = AE20 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<8> LOC = AF19 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<9> LOC = AC22 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<10> LOC = AE19 | IOSTANDARD=LVCMOS33; #ok -NET A3_D<11> LOC = AD19 | IOSTANDARD=LVCMOS33; #ok - -# testpoints near ADC - -NET A0_T<0> LOC = D8 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<1> LOC = D9 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<2> LOC = D10 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<3> LOC = E10 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<4> LOC = E12 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<5> LOC = E14 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<6> LOC = D17 | IOSTANDARD=LVCMOS33; #ok -NET A0_T<7> LOC = D18 | IOSTANDARD=LVCMOS33; #ok - -NET A1_T<0> LOC = AB9 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<1> LOC = AB12 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<2> LOC = AC12 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok -NET A1_T<7> LOC = AB18 | IOSTANDARD=LVCMOS33; #ok - - - -# SPI bus -####################################################### -NET S_CLK LOC = C10 | IOSTANDARD=LVCMOS33; #ok -NET MOSI LOC = C11 | IOSTANDARD=LVCMOS33; #ok -NET MISO LOC = C12 | IOSTANDARD=LVCMOS33; #ok - -NET TCS<0> LOC = C15 | IOSTANDARD=LVCMOS33; #ok -NET TCS<1> LOC = C16 | IOSTANDARD=LVCMOS33; #ok -NET TCS<2> LOC = C17 | IOSTANDARD=LVCMOS33; #ok -NET TCS<3> LOC = C18 | IOSTANDARD=LVCMOS33; #ok -NET DAC_CS LOC = C20 | IOSTANDARD=LVCMOS33; #ok -NET EE_CS LOC = C21 | IOSTANDARD=LVCMOS33; #ok - - - -# LEDs -####################################################### -NET AMBER_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; #schematic: LED_3 D3 AMBER -NET GREEN_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; #schematic: LED_0 D1 GREEN -NET RED_LED LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2 RED - - Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd.bak (revision 10132) +++ (revision ) @@ -1,175 +1,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; --- use IEEE.NUMERIC_STD.ALL; - -package fad_definitions is - - --- Declare constants - - type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); - type ip_type is array (0 to 3) of integer; - - type mac_list_type is array (0 to 2) of mac_type; - type ip_list_type is array (0 to 2) of ip_type; --- Network Settings - - constant ETHZ_GATEWAY : ip_type := (192, 33, 96, 1); - constant CAM_GATEWAY : ip_type := (192, 33, 96, 1); --??????????????? - constant TUDO_GATEWAY : ip_type := (129, 217, 160, 1); - - constant ETHZ_NETMASK : ip_type := (255, 255, 248, 0); - constant CAM_NETMASK : ip_type := (255, 255, 248, 0); --??????????????? - constant TUDO_NETMASK : ip_type := (255, 255, 255, 0); - - --constant MAC_ZERO : mac_type := (X"0000", X"0000", X"0000"); - constant MAC_FAD0 : mac_type := (X"0011", X"9561", X"97B4"); - constant MAC_FAD1 : mac_type := (X"FAC7", X"0FAD", X"0001"); - constant MAC_FAD2 : mac_type := (X"FAC7", X"0FAD", X"0002"); - - --constant IP_ZERO : ip_type := (0,0,0,0); - constant IP_TUDO : ip_type := (129, 217, 160, 119); - constant IP_ETHZ_FAD0 : ip_type := (192, 33, 99, 225); - constant IP_ETHZ_FAD1 : ip_type := (192, 33, 99, 226); - constant IP_ETHZ_FAD2 : ip_type := (192, 33, 99, 237); - - -- IP lookup table used to convert CID,BID into IP, if not in camera. - constant IP_LIST : ip_list_type := (IP_ETHZ_FAD0, IP_ETHZ_FAD1, IP_ETHZ_FAD2); - constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2); - - constant FIRST_PORT : integer := 5000; - constant CAM_IP_PREFIX : ip_type := (192, 168, 0, 0); - constant IP_offset : integer := 128; - constant CAM_MAC_prefix : mac_type := (X"FAC7", X"0FAD", X"0000"); --- Network Settings End - - constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; - constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; - constant PACKAGE_HEADER_LENGTH : integer := 22; - constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag - - constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset - --- W5300 Registers - constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); - constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; - constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; - constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; - constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; - constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; - constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; - constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; - constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; - constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; - constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; - constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; - constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; - constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; - constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; - constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; - constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; - constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; - constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; - - constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; - constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; - constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; - constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; - constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; - constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; - constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; - constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; - constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; - constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; - constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; - constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; - constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; --- End W5300 registers - --- - constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes - constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words - - constant LOG2_OF_RAM_SIZE_64B : integer := 15; - --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; - constant RAM_SIZE_64B : integer := 24576; - constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; - --- TYPE definitions - type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0); - type roi_array_type is array (0 to 35) of integer range 0 to 1024; - type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0); - type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0); - - type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1; - type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; - --- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106, --- 181, 121, 189, 101, 101, 187, 56, 187, 101, --- 2, 141, 101, 100, 10, 100, 178, 101, 174, --- 12, 181, 100, 102, 101, 102, 0, 101, 108); --- constant DEFAULT_ROI : roi_array_type := (others => 100); - constant DEFAULT_ROI : roi_array_type := (others => 210); - - constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); - --constant DEFAULT_DAC : dac_array_type := (others => 0); - - constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; - constant DEFAULT_DRSADDR_MODE : std_logic := '0'; - - - --- Commands - constant CMD_START : std_logic_vector := X"C0"; - constant CMD_STOP : std_logic_vector := X"30"; - constant CMD_TRIGGER : std_logic_vector := X"A0"; - - constant CMD_TRIGGER_C : std_logic_vector := X"B0"; - constant CMD_TRIGGER_S : std_logic_vector := X"20"; - constant CMD_READ : std_logic_vector := X"0A"; - constant CMD_WRITE : std_logic_vector := X"05"; --- Config-RAM - constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values - constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values - - constant CMD_DENABLE : std_logic_vector := X"06"; - constant CMD_DDISABLE : std_logic_vector := X"07"; - constant CMD_DWRITE_RUN : std_logic_vector := X"08"; - constant CMD_DWRITE_STOP : std_logic_vector := X"09"; - constant CMD_SCLK_ON : std_logic_vector := X"10"; - constant CMD_SCLK_OFF : std_logic_vector := X"11"; - - constant CMD_PS_DIRINC : std_logic_vector := X"12"; - constant CMD_PS_DIRDEC : std_logic_vector := X"13"; - constant CMD_PS_DO : std_logic_vector := X"14"; - -constant CMD_SRCLK_ON : std_logic_vector := X"15"; -constant CMD_SRCLK_OFF : std_logic_vector := X"16"; - -constant CMD_TRIGGERS_ON : std_logic_vector := X"18"; -constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; - -constant CMD_PS_RESET : std_logic_vector := X"17"; - -constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; - --- DRS Registers - constant DRS_CONFIG_REG : std_logic_vector := "1100"; - constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; - constant DRS_WRITE_CONFIG_REG : std_logic_vector := "1110"; - constant DRS_DISABLE_ALL_OUTS : std_logic_vector := "1111"; - --- Declare functions and procedure - - -end fad_definitions; - - Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd.bak (revision 10132) +++ (revision ) @@ -1,281 +1,0 @@ --- --- VHDL Architecture FACT_FAD_lib.memory_manager.beha --- --- Created: --- by - kai.UNKNOWN (E5PCXX) --- at - 14:33:25 02.03.2010 --- --- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) --- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; - -library FACT_FAD_lib; -use FACT_FAD_lib.fad_definitions.all; - --- library UNISIM; --- use UNISIM.VComponents.all; --- USE IEEE.NUMERIC_STD.all; - --- RAM_ADDR_WIDTH_64B is used for --- output ram_start_addr - --- RAM_ADDR_WIDTH_16B is used for --- output wiz_ram_start_addr - - -ENTITY memory_manager IS - generic( - RAM_ADDR_WIDTH_64B : integer := 12; - RAM_ADDR_WIDTH_16B : integer := 14 - ); - PORT( - clk : IN std_logic; - config_start : IN std_logic; - ram_write_ready : IN std_logic; - roi_array : IN roi_array_type; - ram_write_ea : OUT std_logic := '0'; - config_ready, config_started : OUT std_logic := '0'; - roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); - package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); - wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); - wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); - wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); - wiz_write_ea : OUT std_logic := '0'; - wiz_write_header : OUT std_logic := '0'; - wiz_write_end : OUT std_logic := '0'; - wiz_busy : IN std_logic; - ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') - ); - --- Declarations - -END memory_manager ; - --- -ARCHITECTURE beha OF memory_manager IS - -type state_mm_type is (MM_CONFIG, MAX_ROI, MAX_ROI1, MAX_ROI2, FIFO_CALC, RAM_CALC, RAM_CALC1, RAM_CALC2, MM_MAIN, MM_MAIN1); -signal state_mm : state_mm_type := MM_CONFIG; - ---type roi_array_type is array (0 to 35) of integer range 0 to 1024; -type roi_max_array_type is array (0 to 8) of integer range 0 to 1024; -type channel_size_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; -type fifo_write_length_type is array (0 to 8) of integer range 0 to W5300_TX_FIFO_SIZE; -type fifo_channels_array_type is array (0 to 8) of integer range 0 to 9; -type fifo_package_size_ram_type is array (0 to 8) of integer range 0 to RAM_SIZE_16B; - -signal roi_max_array : roi_max_array_type := (others => 0); - --- size of channel groups (16 bit) -signal channel_size : channel_size_type := (others => 0); --- write length of packages (16 bit) -signal fifo_write_length : fifo_write_length_type := (others => 0); --- number of channels per package -signal fifo_channels_array : fifo_channels_array_type := (others => 0); --- size of packages in ram (16 bit) -signal fifo_package_size_ram : fifo_package_size_ram_type := (others => 0); --- -signal event_size_ram : integer range 0 to RAM_SIZE_16B := 0; -signal event_size_ram_64b : integer range 0 to RAM_SIZE_64B := 0; -signal event_size : integer range 0 to RAM_SIZE_16B := 0; - -signal drs_id : integer range 0 to 4 := 0; -signal channel_id : integer range 0 to 9 := 0; -signal channel_index : integer range 0 to 9 := 0; -signal package_index : integer range 0 to 9 := 0; -signal number_of_packages : integer range 0 to 9 := 0; -signal max_events_ram, events_in_ram : integer range 0 to 2048; -signal event_start_addr : integer range 0 to (RAM_SIZE_64B - 1); -signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1); -signal event_ready_flag : std_logic := '0'; - -signal roi_index : integer range 0 to 45 := 0; -signal temp_roi : integer range 0 to 1024 := 0; - -BEGIN - - mm : process (clk) - begin - if rising_edge (clk) then - case state_mm is - - when MM_CONFIG => - if (config_start = '1') then - config_started <= '1'; - roi_max_array <= (others => 0); - channel_size <= (others => 0); - fifo_write_length <= (others => 0); - fifo_channels_array <= (others => 0); - event_size <= 0; - ram_write_ea <= '0'; - state_mm <= MAX_ROI; - end if; - - -- calculate max ROIs and channel sizes - when MAX_ROI => - roi_index <= (drs_id * 9) + channel_id; - state_mm <= MAX_ROI1; - when MAX_ROI1 => - temp_roi <= roi_array (roi_index); - state_mm <= MAX_ROI2; - when MAX_ROI2 => - if (channel_id < 9) then - if ( temp_roi > roi_max_array (channel_id)) then - roi_max_array (channel_id) <= temp_roi; - end if; - channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3; - drs_id <= drs_id + 1; - state_mm <= MAX_ROI; - if (drs_id = 3) then - drs_id <= 0; - channel_id <= channel_id + 1; - end if; - else - drs_id <= 0; - channel_id <= 0; - channel_size (0) <= channel_size (0) + PACKAGE_HEADER_LENGTH; - channel_size (8) <= channel_size (8) + PACKAGE_END_LENGTH; - state_mm <= FIFO_CALC; - end if; - - -- calculate number of channels that fit in FIFO - when FIFO_CALC => - if (channel_id < 9) then - if ((fifo_write_length (package_index) + channel_size (channel_id)) <= W5300_TX_FIFO_SIZE) then - fifo_write_length (package_index) <= fifo_write_length (package_index) + channel_size (channel_id); - fifo_channels_array (package_index) <= fifo_channels_array (package_index) + 1; - channel_id <= channel_id + 1; - event_size <= event_size + channel_size (channel_id); - else - package_index <= package_index + 1; - end if; - else - number_of_packages <= package_index + 1; - package_index <= 0; - channel_index <= 0; - channel_id <= 0; - fifo_package_size_ram <= (others => 0); - fifo_package_size_ram (0) <= PACKAGE_HEADER_LENGTH + 6; - event_size_ram <= 0; - event_size_ram_64b <= 0; - max_events_ram <= 0; - state_mm <= RAM_CALC; - end if; - - when RAM_CALC => - if (package_index < number_of_packages) then - if (channel_index < fifo_channels_array (package_index)) then - fifo_package_size_ram (package_index) <= fifo_package_size_ram (package_index) + ((roi_max_array (channel_id) + 3) * 4); - channel_index <= channel_index + 1; - channel_id <= channel_id + 1; - else - package_index <= package_index + 1; - event_size_ram <= event_size_ram + fifo_package_size_ram (package_index); - channel_index <= 0; - end if; - else - fifo_package_size_ram (package_index - 1) <= fifo_package_size_ram (package_index - 1) + 4; - event_size_ram <= event_size_ram + 4; -- Size of Event in RAM (16 Bit), + CRC + Endflag + 2 Spare - state_mm <= RAM_CALC1; - end if; - when RAM_CALC1 => - max_events_ram <= max_events_ram + 1; - if ((max_events_ram * event_size_ram) <= RAM_SIZE_16B) then - state_mm <= RAM_CALC1; - else - max_events_ram <= max_events_ram - 1; - state_mm <= RAM_CALC2; - end if; - when RAM_CALC2 => - event_size_ram_64b <= (event_size_ram / 4); - events_in_ram <= 0; - event_start_addr <= 0; - write_start_addr <= 0; - package_index <= 0; - channel_id <= 0; - ram_start_addr <= (others => '0'); - ram_write_ea <= '1'; - config_started <= '0'; - config_ready <= '1'; - package_length <= conv_std_logic_vector (event_size, 16); - for i in 0 to 8 loop - roi_max(i) <= conv_std_logic_vector(roi_max_array(i), 11); - end loop; - state_mm <= MM_MAIN; - - when MM_MAIN => - state_mm <= MM_MAIN1; - if ((ram_write_ready = '1') and (event_ready_flag = '0')) then - ram_write_ea <= '0'; - events_in_ram <= events_in_ram + 1; - if ((event_start_addr + event_size_ram_64b) < (RAM_SIZE_64B - event_size_ram_64b)) then - event_start_addr <= event_start_addr + event_size_ram_64b; - else - event_start_addr <= 0; - end if; - event_ready_flag <= '1'; - end if; - wiz_write_ea <= '0'; -- ????? - - when MM_MAIN1 => - state_mm <= MM_MAIN; - if (config_start = '1') then - config_ready <= '0'; - if (events_in_ram = 0) then - state_mm <= MM_CONFIG; - end if; - end if; - if (event_ready_flag = '1') then - if (events_in_ram < max_events_ram) then - ram_write_ea <= '1'; - -- ram_start_addr <= conv_std_logic_vector(event_start_addr, 12); - ram_start_addr <= conv_std_logic_vector(event_start_addr, RAM_ADDR_WIDTH_64B); - event_ready_flag <= '0'; - end if; - end if; - if ((events_in_ram > 0) and (wiz_busy = '0')) then - if (package_index < number_of_packages) then - -- wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, 14); - wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B); - wiz_write_length <= conv_std_logic_vector(fifo_write_length (package_index), 17); - wiz_number_of_channels <= conv_std_logic_vector(fifo_channels_array (package_index), 4); - wiz_write_ea <= '1'; - package_index <= package_index + 1; - if (package_index = 0) then - -- first package -> write header - wiz_write_header <= '1'; - else - wiz_write_header <= '0'; - end if; - if (package_index = (number_of_packages - 1)) then - -- last package -> write end-flag - wiz_write_end <= '1'; - -- next address - if ((write_start_addr + event_size_ram + fifo_package_size_ram (package_index) ) < (RAM_SIZE_16B - event_size_ram)) then - --write_start_addr <= write_start_addr + event_size_ram; - write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); - else - write_start_addr <= 0; - end if; - else - write_start_addr <= write_start_addr + fifo_package_size_ram (package_index); - wiz_write_end <= '0'; - end if; - else - events_in_ram <= events_in_ram - 1; - package_index <= 0; - end if; - end if; - - - end case; -- state_mm - end if; - end process mm; - - - -END ARCHITECTURE beha; - Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd.bak =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd.bak (revision 10132) +++ (revision ) @@ -1,167 +1,0 @@ --- --- phase_shifter.vhd --- --- implements interface between w5300_modul.vhd --- and clock_generator_variable_PS_struct.vhd --- --- --- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -library FACT_FAD_lib; -use FACT_FAD_lib.fad_definitions.all; - - -ENTITY phase_shifter IS - - PORT( - CLK : IN std_logic; - rst : in std_logic; --asynch in of DCM - - -- interface to: clock_generator_variable_PS_struct.vhd - PSCLK : OUT std_logic; - PSEN : OUT std_logic := '0'; - PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' - PSDONE : IN std_logic; -- will pulse once, if phase shifting was done. - LOCKED : IN std_logic; - - - -- interface to: w5300_modul.vhd - shift_phase : IN std_logic; - direction : IN std_logic; -- corresponds to 'PSINCDEC' - - -- status: - shifting : OUT std_logic := '0'; - ready : OUT std_logic := '0'; - offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - DCM_locked : OUT std_logic - - ); -END phase_shifter; - --- usage: --- w5300_modul will set 'direction' to desired direction and pulse 'shift_phase' once --- to initiate a phase shifting process. --- while phase shifting, 'shifting' will show '1' and further pulses will be discarded. --- 'offset' shows the number of phase_shift steps that have been performed. --- ready is high, when DCM is LOCKED and not phase_shifting. --- DCM_status is a copy, of the STATUS input. --- DCM_locked is a copy of LOCKED --- --- how it works internally: --- PSCLK is connected to clk, always. --- --- main FSM goes from init to ready, when LOCKED is high. --- main FSM goes from ready to shifting, when shift_phase goes high. --- when in shifting: --- PSINCDEC is set to 'direction' --- PSEN is set high --- shifting is set high --- next state waiting-for-done is entered --- --- when in waiting-for-done: --- PSEN is set low --- if PSDONE is found to be high. --- shifting is set low and state ready is entered. --- --- whenever LOCKED goes low FSM enters 'init' state --- when in init state: --- 'ready' is set low - -architecture first_behave of phase_shifter is - constant OFFS_MIN : integer := -128; - constant OFFS_MAX : integer := 127; - - type states is (INIT, READY_STATE, SHIFTING_STATE, WAITINGFORDONE); - signal state,next_state : states := INIT; - - signal local_direction : std_logic; - signal offset_int : integer range OFFS_MIN to OFFS_MAX := 0; - - - -begin - --- concurrent statements: -DCM_locked <= LOCKED; -PSCLK <= CLK; -offset <= std_logic_vector(to_signed(offset_int,8)); - - -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high. - FSM_Registers: process(CLK, LOCKED, rst) - begin - if Rising_edge(rst) then - state <= INIT; - elsif LOCKED = '0' then - state <= INIT; - elsif Rising_edge(CLK) then - state <= next_state; - end if; - end process; - - -- MAIN FSM - FSM_logic: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction) - begin - next_state <= state; - case state is - - -- INIT state: here the FSM is idling, when LOCKED is not HIGH. - when INIT => - ready <= '0'; - offset_int <= 0; - shifting <= '0'; - PSEN <= '0'; - if (LOCKED = '1') then - next_state <= READY_STATE; - else - next_state <= INIT; - end if; - - -- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high - when READY_STATE => - ready <= '1'; - shifting <= '0'; - PSEN <= '0'; - if (shift_phase = '1') then - next_state <= SHIFTING_STATE; - local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high - else - next_state <= READY_STATE; - end if; - - -- SHIFTING_STATE state: PSENC is set HIGH here and set low in the next state. - when SHIFTING_STATE => - ready <= '1'; - shifting <= '1'; - PSEN <= '1'; - PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up. - next_state <= WAITINGFORDONE; - - -- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle. - when WAITINGFORDONE => - ready <= '1'; - shifting <= '1'; - PSEN <= '0'; - if (PSDONE = '1') then - next_state <= READY_STATE; - if (local_direction = '1') then - if (offset_int < OFFS_MAX) then - offset_int <= offset_int + 1; - end if; - else - if (offset_int > OFFS_MIN) then - offset_int <= offset_int - 1; - end if; - end if; - else - next_state <= WAITINGFORDONE; - end if; - - end case; - end process; - - - -end first_behave;