Index: rmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/adc_emulator_beha.vhd.bak (revision 10134) +++ (revision ) @@ -1,106 +1,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10:44:52 01/07/2010 --- Design Name: --- Module Name: adc_emulator - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- --- hds interface_start -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_unsigned.all; -USE ieee.std_logic_textio.all; -LIBRARY std; -USE std.textio.all; - -ENTITY adc_emulator IS - GENERIC( - INPUT_FILE : string := "filename" - ); - PORT( - clk : IN STD_LOGIC; - data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); - otr : OUT STD_LOGIC; - oeb : IN STD_LOGIC - ); - --- Declarations - -END adc_emulator ; - -architecture Behavioral of adc_emulator is - - -- type_rom_type has to be a multiple of 4 bit because HREAD is used - type type_shift_reg is array (0 to 7) of std_logic_vector(12 downto 0); - type type_rom_array is array (0 to 1024) of std_logic_vector(15 downto 0); - - -- 'InitRomFromFile' reads one column of 'rom_filename' and puts the returned value to 'rom(i)' - impure function InitRomFromFile (rom_filename : in string) return type_rom_array is - file rom_file : text open read_mode is rom_filename; - variable rom_file_line: line; - variable rom : type_rom_array; - begin - for i in 0 to 1023 loop - readline(rom_file, rom_file_line); - hread(rom_file_line, rom(i)); - end loop; - return rom; - end function InitRomFromFile; - - signal rom : type_rom_array := InitRomFromFile(INPUT_FILE); - signal rom_reg : type_shift_reg; - signal rom_addr : std_logic_vector(9 downto 0) := (others => '0'); - signal rom_data : std_logic_vector(12 downto 0); - -begin - - rom_data <= rom(conv_integer(rom_addr))(12 downto 0); - data <= rom_reg(7)(11 downto 0) when oeb = '0' else (others => 'Z'); - otr <= rom_reg(7)(12); - - fetch_data_proc: process(clk) - begin - if rising_edge(clk) then - if (oeb = '0') then - rom_addr <= rom_addr + 1; - else - rom_addr <= (others => '0'); - end if; - end if; - end process fetch_data_proc; - - - ad_conv_proc: process(clk) - begin - if rising_edge(clk) then - if (oeb = '0') then - if (conv_integer(rom_data) > 2**12-1) then - rom_reg(0) <= '1' & X"FFF"; -- set OTR flag when rom_data is too high and set adc value to max - else - rom_reg(0) <= rom_data; -- shifting input cause output is shifted 7 cycles - end if; - rom_reg(1) <= rom_reg(0); - rom_reg(2) <= rom_reg(1); - rom_reg(3) <= rom_reg(2); - rom_reg(4) <= rom_reg(3); - rom_reg(5) <= rom_reg(4); - rom_reg(6) <= rom_reg(5); - rom_reg(7) <= rom_reg(6); - end if; - end if; - end process ad_conv_proc; - -end Behavioral; - Index: rmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd.bak (revision 10134) +++ (revision ) @@ -1,64 +1,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 13:40:20 01/07/2010 --- Design Name: --- Module Name: clock_generator - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- --- hds interface_start -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - --- synthesis translate_off --- -ENTITY clock_generator IS - GENERIC( - clock_period : time := 20 ns; - reset_time : time := 50 ns - ); - PORT( - clk : OUT STD_LOGIC := '0'; - rst : OUT STD_LOGIC := '0' - ); - --- Declarations - -END clock_generator ; --- hds interface_end - -architecture Behavioral of clock_generator is - -begin - - clock_gen_proc: process - begin - clk <= '0'; - wait for clock_period / 2; - clk <= '1'; - wait for clock_period / 2; - end process clock_gen_proc; - - reset_gen_proc: process - begin - rst <= '1'; - wait for reset_time; - rst <= '0'; - wait; - end process reset_gen_proc; - - -end Behavioral; ---synthesis translate_on Index: rmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/max6662_emulator_beha.vhd.bak (revision 10134) +++ (revision ) @@ -1,65 +1,0 @@ --- --- VHDL Architecture FACT_FAD_TB_lib.spi_devices_emulator.beha --- --- Created: --- by - Benjamin Krumm.UNKNOWN (EEPC8) --- at - 09:26:11 28.04.2010 --- --- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; -USE ieee.std_logic_unsigned.all; -LIBRARY FACT_FAD_lib; -USE FACT_FAD_lib.fad_definitions.all; - -ENTITY max6662_emulator IS - GENERIC( - DRS_TEMPERATURE : integer := 51 - ); - PORT( - sclk : in std_logic; - sio : inout std_logic; - sensor_cs : in std_logic_vector (3 DOWNTO 0) - ); - --- Declarations - -END max6662_emulator ; - -ARCHITECTURE beha OF max6662_emulator IS - - signal data : std_logic_vector(15 downto 0) := (others => '0'); - signal spi_cycle_cnt : integer := 0; - signal temperature : integer range -55 to 150 := DRS_TEMPERATURE; - -BEGIN - sio <= 'Z'; - spi_cnt_proc: process (sclk) - begin - if rising_edge(sclk) then - if (sensor_cs /= "1111") then - spi_cycle_cnt <= spi_cycle_cnt + 1; - else - spi_cycle_cnt <= 0; - end if; - end if; - end process spi_cnt_proc; - - sensor_data_proc: process (spi_cycle_cnt, sclk) - begin - if falling_edge(sclk) then - sio <= 'Z'; - if (spi_cycle_cnt = 1) then - data <= '0' & conv_std_logic_vector(temperature + conv_integer(sensor_cs), 12) & "000"; - end if; - if (spi_cycle_cnt > 7) then - sio <= data(15); - data(15 downto 1) <= data(14 downto 0); - end if; - end if; - end process sensor_data_proc; - -END ARCHITECTURE beha; - Index: rmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd.bak (revision 10134) +++ (revision ) @@ -1,42 +1,0 @@ --- --- VHDL Architecture FACT_FAD_TB_lib.simple_trigger.beha --- --- Created: --- by - FPGA_Developer.UNKNOWN (EEPC8) --- at - 14:01:15 10.02.2010 --- --- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; ---USE ieee.NUMERIC_STD.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library FACT_FAD_lib; -use FACT_FAD_lib.fad_definitions.all; - -entity trigger_generator is - generic( - TRIGGER_RATE : time := 1 ms; - PULSE_WIDTH : time := 20 ns - ); - port( - trigger : out std_logic - ); -end trigger_generator ; - -architecture beha of trigger_generator is -begin - - trigger_proc: process - begin - trigger <= '0'; - wait for TRIGGER_RATE; - trigger <= '1'; - wait for PULSE_WIDTH; - trigger <= '0'; - --wait; - end process trigger_proc; -end architecture beha; - Index: rmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd.bak (revision 10134) +++ (revision ) @@ -1,89 +1,0 @@ --- --- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha --- --- Created: --- by - FPGA_Developer.UNKNOWN (EEPC8) --- at - 07:51:36 04.02.2010 --- --- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; -USE ieee.std_logic_unsigned.all; -LIBRARY FACT_FAD_lib; -USE FACT_FAD_lib.fad_definitions.all; - -ENTITY w5300_emulator IS - PORT( - addr : in std_logic_vector (9 DOWNTO 0); - data : inout std_logic_vector (15 DOWNTO 0); - rd : in std_logic; - wr : in std_logic - ); - --- Declarations - -END w5300_emulator ; - -architecture beha of w5300_emulator is - - signal open_done : std_logic_vector(7 downto 0) := (others => '0'); - signal data_temp : std_logic_vector(15 downto 0); - - signal RSR_0, RSR_1 : std_logic_vector (15 downto 0); - signal FIFOR_CNT : integer := 0; - -begin - - data <= data_temp when (rd = '0') else (others => 'Z'); - data_temp <= data when (wr = '0') else (others => 'Z'); - - set_proc : process - begin - RSR_0 <= X"0000"; - RSR_1 <= X"0000"; - wait for 250 us; - RSR_1 <= X"0001"; - wait for 200 us; - RSR_1 <= X"0002"; - wait; - end process set_proc; - - w5300_proc : process (addr) - begin - for i in 0 to 7 loop - if (addr = conv_integer(W5300_S0_SSR) + i * 64) then - if (open_done(i) = '0') then - data_temp <= X"0013"; - open_done(i) <= '1'; - else - data_temp <= X"0017"; - end if; - elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then - data_temp <= X"0000"; - elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then - data_temp <= X"3C00"; - elsif (addr = conv_integer(W5300_S0_RX_RSR)) then - data_temp <= RSR_0; - elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then - data_temp <= RSR_1; - elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then - if (FIFOR_CNT = 0) then - data_temp <= X"A000"; --- FIFOR_CNT <= 1; - elsif (FIFOR_CNT = 1) then - data_temp <= X"0500"; - FIFOR_CNT <= 2; - elsif (FIFOR_CNT = 2) then - data_temp <= X"0000"; - end if; - else - null; - end if; - end loop; - end process w5300_proc; - - -end architecture beha; -