Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd	(revision 10138)
@@ -172,4 +172,5 @@
           when CONFIG7 =>
             if (drs_srin_write_ready = '1') then
+              drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers
               roi_max_int <= roi_max;
               state_generate <= WRITE_DATA_IDLE;
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd	(revision 10138)
@@ -85,5 +85,5 @@
         when SRIN_WRITE_END =>
           SRCLK_EN <= '0';
-          srin_out <= '1';
+          srin_out <= '0';
           srin_write_ready <= '1';
           srin_write_ack <= '0';
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd	(revision 10138)
@@ -163,4 +163,5 @@
 
 -- DRS Registers
+  constant DRS_ADDR_IDLE : std_logic_vector := "1001";
   constant DRS_CONFIG_REG : std_logic_vector := "1100";  
   constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101";  
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 10138)
@@ -144,5 +144,5 @@
 signal local_fifo_channels : std_logic_vector (3 downto 0);
 
-signal data_valid_int : std_logic := '0';
+
 
 
@@ -162,5 +162,9 @@
 	-- signals for synching in asynchronous input signals
 	------------------------------------------------------------------------------
-	signal w5300_interrupt_sr : std_logic_vector(1 downto 0); 
+	signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11";
+	 --?? not sure if this init value is good
+	 -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles.
+	 -- I hope!
+	signal data_valid_sr : std_logic_vector(1 downto 0) := "00"; 
 	------------------------------------------------------------------------------
 
@@ -187,8 +191,10 @@
 		-- synch asynchronous input in:
 		w5300_interrupt_sr <= w5300_interrupt_sr(1) & int;
+		data_valid_sr <= data_valid_sr(1) & data_valid;
 		
 			-- interrupt is handled synchronously
 			-- W5300 pulls low its interrpt line in case of:
-			--	??? I don't know ... connection loss ???
+			--	When Sockets time out and 
+			-- When sockets receive disconnection request.
 			
 			if (w5300_interrupt_sr = "01") and (interrupt_ignore = '0') then
@@ -560,6 +566,8 @@
 					    state_init <= MAIN;
 					  end if;
-					
-          -- main "loop"
+					-----------------------------------------
+          -- MAIN "loop" --------------------------
+          -----------------------------------------
+          
 					when MAIN =>
 					  socks_waiting <= '0';
@@ -573,5 +581,5 @@
             data_valid_ack <= '0';
             state_init <= MAIN1;
-            data_valid_int <= data_valid;
+            --data_valid_int <= data_valid;
 					when MAIN1 =>
             if (chk_recv_cntr = 1000) then
@@ -586,6 +594,7 @@
           when MAIN2 =>
             busy <= '0';
-					  if (data_valid = '1') then
-					    data_valid_int <= '0';
+					  --if (data_valid = '1') then
+					  if (data_valid_sr = "01" or data_valid_sr = "11") then
+					    --data_valid_int <= '0';
 					    busy <= '1';
               local_write_length <= write_length;
@@ -607,4 +616,9 @@
             next_state <= MAIN;
             state_init <= WRITE_DATA;
+
+            -----------------------------------------
+            -- END OF MAIN         ------------------
+            -----------------------------------------
+
 					  
 
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd	(revision 10138)
@@ -333,17 +333,17 @@
 (vvPair
 variable "date"
-value "04.02.2011"
+value "08.02.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "04"
+value "08"
 )
 (vvPair
@@ -485,5 +485,5 @@
 (vvPair
 variable "time"
-value "12:56:44"
+value "11:06:22"
 )
 (vvPair
@@ -577,5 +577,6 @@
 )
 xt "-172000,106800,-128500,107600"
-st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
+st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
+"
 )
 )
@@ -595,5 +596,6 @@
 )
 xt "-172000,42800,-132000,43600"
-st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
+"
 )
 )
@@ -613,5 +615,6 @@
 )
 xt "-172000,62000,-139500,62800"
-st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
+st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
+"
 )
 )
@@ -631,5 +634,6 @@
 )
 xt "-172000,80400,-132000,81200"
-st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
+st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
+"
 )
 )
@@ -649,5 +653,6 @@
 )
 xt "-172000,81200,-139500,82000"
-st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
+st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
+"
 )
 )
@@ -667,5 +672,6 @@
 )
 xt "-172000,34400,-132000,35200"
-st "wiz_reset              : std_logic                                    := '1'"
+st "wiz_reset              : std_logic                                    := '1'
+"
 )
 )
@@ -685,5 +691,6 @@
 )
 xt "-172000,32000,-143500,32800"
-st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
+st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
+"
 )
 )
@@ -703,5 +710,6 @@
 )
 xt "-172000,36800,-143000,37600"
-st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
+st "wiz_data               : std_logic_vector(15 DOWNTO 0)
+"
 )
 )
@@ -721,5 +729,6 @@
 )
 xt "-172000,32800,-132000,33600"
-st "wiz_cs                 : std_logic                                    := '1'"
+st "wiz_cs                 : std_logic                                    := '1'
+"
 )
 )
@@ -739,5 +748,6 @@
 )
 xt "-172000,35200,-132000,36000"
-st "wiz_wr                 : std_logic                                    := '1'"
+st "wiz_wr                 : std_logic                                    := '1'
+"
 )
 )
@@ -757,5 +767,6 @@
 )
 xt "-172000,33600,-132000,34400"
-st "wiz_rd                 : std_logic                                    := '1'"
+st "wiz_rd                 : std_logic                                    := '1'
+"
 )
 )
@@ -774,5 +785,6 @@
 )
 xt "-172000,13600,-153500,14400"
-st "wiz_int                : std_logic"
+st "wiz_int                : std_logic
+"
 )
 )
@@ -1291,5 +1303,5 @@
 fg "0,65535,0"
 )
-xt "0,65625,750,66375"
+xt "0,70625,750,71375"
 )
 tg (CPTG
@@ -1301,8 +1313,8 @@
 va (VaSet
 )
-xt "-17300,65500,-1000,66500"
+xt "-17300,70500,-1000,71500"
 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
 ju 2
-blo "-1000,66300"
+blo "-1000,71300"
 )
 )
@@ -1366,5 +1378,5 @@
 fg "0,65535,0"
 )
-xt "-21750,70625,-21000,71375"
+xt "-21750,69625,-21000,70375"
 )
 tg (CPTG
@@ -1376,7 +1388,7 @@
 va (VaSet
 )
-xt "-20000,70500,-13200,71500"
+xt "-20000,69500,-13200,70500"
 st "trigger_id : (47:0)"
-blo "-20000,71300"
+blo "-20000,70300"
 )
 )
@@ -1474,5 +1486,5 @@
 fg "0,65535,0"
 )
-xt "0,66625,750,67375"
+xt "0,71625,750,72375"
 )
 tg (CPTG
@@ -1484,8 +1496,8 @@
 va (VaSet
 )
-xt "-6300,66500,-1000,67500"
+xt "-6300,71500,-1000,72500"
 st "ram_write_ea"
 ju 2
-blo "-1000,67300"
+blo "-1000,72300"
 )
 )
@@ -1509,5 +1521,5 @@
 fg "0,65535,0"
 )
-xt "0,67625,750,68375"
+xt "0,72625,750,73375"
 )
 tg (CPTG
@@ -1519,8 +1531,8 @@
 va (VaSet
 )
-xt "-7300,67500,-1000,68500"
+xt "-7300,72500,-1000,73500"
 st "ram_write_ready"
 ju 2
-blo "-1000,68300"
+blo "-1000,73300"
 )
 )
@@ -1547,5 +1559,5 @@
 fg "0,65535,0"
 )
-xt "0,76625,750,77375"
+xt "0,78625,750,79375"
 )
 tg (CPTG
@@ -1557,8 +1569,8 @@
 va (VaSet
 )
-xt "-4000,76500,-1000,77500"
+xt "-4000,78500,-1000,79500"
 st "roi_max"
 ju 2
-blo "-1000,77300"
+blo "-1000,79300"
 )
 )
@@ -1617,5 +1629,5 @@
 fg "0,65535,0"
 )
-xt "0,77625,750,78375"
+xt "0,79625,750,80375"
 )
 tg (CPTG
@@ -1627,8 +1639,8 @@
 va (VaSet
 )
-xt "-10100,77500,-1000,78500"
+xt "-10100,79500,-1000,80500"
 st "package_length : (15:0)"
 ju 2
-blo "-1000,78300"
+blo "-1000,80300"
 )
 )
@@ -2016,5 +2028,5 @@
 fg "0,65535,0"
 )
-xt "0,74625,750,75375"
+xt "0,77625,750,78375"
 )
 tg (CPTG
@@ -2026,8 +2038,8 @@
 va (VaSet
 )
-xt "-7700,74500,-1000,75500"
+xt "-7700,77500,-1000,78500"
 st "config_ready_mm"
 ju 2
-blo "-1000,75300"
+blo "-1000,78300"
 )
 )
@@ -2156,5 +2168,5 @@
 fg "0,65535,0"
 )
-xt "0,72625,750,73375"
+xt "0,75625,750,76375"
 )
 tg (CPTG
@@ -2166,8 +2178,8 @@
 va (VaSet
 )
-xt "-7400,72500,-1000,73500"
+xt "-7400,75500,-1000,76500"
 st "config_start_mm"
 ju 2
-blo "-1000,73300"
+blo "-1000,76300"
 )
 )
@@ -2344,5 +2356,5 @@
 fg "0,65535,0"
 )
-xt "0,73625,750,74375"
+xt "0,76625,750,77375"
 )
 tg (CPTG
@@ -2354,8 +2366,8 @@
 va (VaSet
 )
-xt "-8200,73500,-1000,74500"
+xt "-8200,76500,-1000,77500"
 st "config_started_mm"
 ju 2
-blo "-1000,74300"
+blo "-1000,77300"
 )
 )
@@ -2626,5 +2638,5 @@
 fg "0,65535,0"
 )
-xt "0,68625,750,69375"
+xt "0,73625,750,74375"
 )
 tg (CPTG
@@ -2636,8 +2648,8 @@
 va (VaSet
 )
-xt "-8800,68500,-1000,69500"
+xt "-8800,73500,-1000,74500"
 st "ram_write_ready_ack"
 ju 2
-blo "-1000,69300"
+blo "-1000,74300"
 )
 )
@@ -2870,5 +2882,6 @@
 )
 xt "-172000,9600,-143500,10400"
-st "board_id               : std_logic_vector(3 DOWNTO 0)"
+st "board_id               : std_logic_vector(3 DOWNTO 0)
+"
 )
 )
@@ -2889,5 +2902,6 @@
 )
 xt "-172000,12800,-153500,13600"
-st "trigger                : std_logic"
+st "trigger                : std_logic
+"
 )
 )
@@ -3257,5 +3271,5 @@
 fg "0,65535,0"
 )
-xt "87250,71625,88000,72375"
+xt "87250,72625,88000,73375"
 )
 tg (CPTG
@@ -3267,7 +3281,7 @@
 va (VaSet
 )
-xt "89000,71500,96900,72500"
+xt "89000,72500,96900,73500"
 st "write_length : (16:0)"
-blo "89000,72300"
+blo "89000,73300"
 )
 )
@@ -3294,5 +3308,5 @@
 fg "0,65535,0"
 )
-xt "87250,72625,88000,73375"
+xt "87250,73625,88000,74375"
 )
 tg (CPTG
@@ -3304,7 +3318,7 @@
 va (VaSet
 )
-xt "89000,72500,105300,73500"
+xt "89000,73500,105300,74500"
 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
-blo "89000,73300"
+blo "89000,74300"
 )
 )
@@ -3406,5 +3420,5 @@
 fg "0,65535,0"
 )
-xt "87250,70625,88000,71375"
+xt "87250,71625,88000,72375"
 )
 tg (CPTG
@@ -3416,7 +3430,7 @@
 va (VaSet
 )
-xt "89000,70500,93100,71500"
+xt "89000,71500,93100,72500"
 st "data_valid"
-blo "89000,71300"
+blo "89000,72300"
 )
 )
@@ -3442,5 +3456,5 @@
 fg "0,65535,0"
 )
-xt "87250,69625,88000,70375"
+xt "87250,70625,88000,71375"
 )
 tg (CPTG
@@ -3452,7 +3466,7 @@
 va (VaSet
 )
-xt "89000,69500,90900,70500"
+xt "89000,70500,90900,71500"
 st "busy"
-blo "89000,70300"
+blo "89000,71300"
 )
 )
@@ -3480,5 +3494,5 @@
 fg "0,65535,0"
 )
-xt "87250,73625,88000,74375"
+xt "87250,74625,88000,75375"
 )
 tg (CPTG
@@ -3490,7 +3504,7 @@
 va (VaSet
 )
-xt "89000,73500,96800,74500"
+xt "89000,74500,96800,75500"
 st "fifo_channels : (3:0)"
-blo "89000,74300"
+blo "89000,75300"
 )
 )
@@ -3516,5 +3530,5 @@
 fg "0,65535,0"
 )
-xt "87250,74625,88000,75375"
+xt "87250,75625,88000,76375"
 )
 tg (CPTG
@@ -3526,7 +3540,7 @@
 va (VaSet
 )
-xt "89000,74500,94700,75500"
+xt "89000,75500,94700,76500"
 st "write_end_flag"
-blo "89000,75300"
+blo "89000,76300"
 )
 )
@@ -3550,5 +3564,5 @@
 fg "0,65535,0"
 )
-xt "87250,75625,88000,76375"
+xt "87250,76625,88000,77375"
 )
 tg (CPTG
@@ -3560,7 +3574,7 @@
 va (VaSet
 )
-xt "89000,75500,95800,76500"
+xt "89000,76500,95800,77500"
 st "write_header_flag"
-blo "89000,76300"
+blo "89000,77300"
 )
 )
@@ -3994,5 +4008,5 @@
 fg "0,65535,0"
 )
-xt "87250,76625,88000,77375"
+xt "87250,77625,88000,78375"
 )
 tg (CPTG
@@ -4004,7 +4018,7 @@
 va (VaSet
 )
-xt "89000,76500,94600,77500"
+xt "89000,77500,94600,78500"
 st "data_valid_ack"
-blo "89000,77300"
+blo "89000,78300"
 )
 )
@@ -4687,5 +4701,6 @@
 )
 xt "-172000,10400,-143500,11200"
-st "crate_id               : std_logic_vector(1 DOWNTO 0)"
+st "crate_id               : std_logic_vector(1 DOWNTO 0)
+"
 )
 )
@@ -4703,5 +4718,5 @@
 fg "0,65535,0"
 )
-xt "-41000,67625,-40250,68375"
+xt "-41000,68625,-40250,69375"
 )
 tg (CPTG
@@ -4713,8 +4728,8 @@
 va (VaSet
 )
-xt "-48800,67500,-42000,68500"
+xt "-48800,68500,-42000,69500"
 st "trigger_id : (47:0)"
 ju 2
-blo "-42000,68300"
+blo "-42000,69300"
 )
 )
@@ -4743,5 +4758,5 @@
 fg "0,65535,0"
 )
-xt "-52750,67625,-52000,68375"
+xt "-52750,68625,-52000,69375"
 )
 tg (CPTG
@@ -4753,7 +4768,7 @@
 va (VaSet
 )
-xt "-51000,67500,-48200,68500"
+xt "-51000,68500,-48200,69500"
 st "trigger"
-blo "-51000,68300"
+blo "-51000,69300"
 )
 )
@@ -4780,5 +4795,5 @@
 fg "0,65535,0"
 )
-xt "-52750,66625,-52000,67375"
+xt "-52750,67625,-52000,68375"
 )
 tg (CPTG
@@ -4790,7 +4805,7 @@
 va (VaSet
 )
-xt "-51000,66500,-49700,67500"
+xt "-51000,67500,-49700,68500"
 st "clk"
-blo "-51000,67300"
+blo "-51000,68300"
 )
 )
@@ -4814,5 +4829,5 @@
 lineWidth 2
 )
-xt "-52000,66000,-41000,70000"
+xt "-52000,67000,-41000,71000"
 )
 oxt "32000,2000,43000,12000"
@@ -4828,7 +4843,7 @@
 font "Arial,8,1"
 )
-xt "-50300,70000,-43700,71000"
+xt "-50300,71000,-43700,72000"
 st "FACT_FAD_LIB"
-blo "-50300,70800"
+blo "-50300,71800"
 tm "BdLibraryNameMgr"
 )
@@ -4839,7 +4854,7 @@
 font "Arial,8,1"
 )
-xt "-50300,71000,-43700,72000"
+xt "-50300,72000,-43700,73000"
 st "trigger_counter"
-blo "-50300,71800"
+blo "-50300,72800"
 tm "CptNameMgr"
 )
@@ -4850,7 +4865,7 @@
 font "Arial,8,1"
 )
-xt "-50300,71000,-42700,72000"
+xt "-50300,72000,-42700,73000"
 st "I_main_ext_trigger"
-blo "-50300,71800"
+blo "-50300,72800"
 tm "InstanceNameMgr"
 )
@@ -4867,5 +4882,5 @@
 font "Courier New,8,0"
 )
-xt "-52000,65000,-52000,65000"
+xt "-52000,66000,-52000,66000"
 )
 header ""
@@ -4881,5 +4896,5 @@
 fg "49152,49152,49152"
 )
-xt "-51750,68250,-50250,69750"
+xt "-51750,69250,-50250,70750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -4911,5 +4926,6 @@
 )
 xt "-172000,98800,-139500,99600"
-st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
+st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
+"
 )
 )
@@ -4931,5 +4947,6 @@
 )
 xt "-172000,82000,-132000,82800"
-st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
+"
 )
 )
@@ -4947,5 +4964,5 @@
 fg "0,65535,0"
 )
-xt "31250,72625,32000,73375"
+xt "27250,70625,28000,71375"
 )
 tg (CPTG
@@ -4958,7 +4975,7 @@
 font "arial,8,0"
 )
-xt "33000,72500,51400,73500"
+xt "29000,70500,47400,71500"
 st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
-blo "33000,73300"
+blo "29000,71300"
 )
 )
@@ -4983,23 +5000,25 @@
 shape (Triangle
 uid 2352,0
-ro 90
+ro 180
 va (VaSet
 vasetType 1
 fg "0,65535,0"
 )
-xt "31250,70625,32000,71375"
+xt "28625,67250,29375,68000"
 )
 tg (CPTG
 uid 2353,0
 ps "CptPortTextPlaceStrategy"
-stg "VerticalLayoutStrategy"
+stg "RightVerticalLayoutStrategy"
 f (Text
 uid 2354,0
+ro 270
 va (VaSet
 font "arial,8,0"
 )
-xt "33000,70500,34300,71500"
+xt "28500,69000,29500,70300"
 st "clk"
-blo "33000,71300"
+ju 2
+blo "29300,69000"
 )
 )
@@ -5024,5 +5043,5 @@
 fg "0,65535,0"
 )
-xt "31250,79625,32000,80375"
+xt "27250,77625,28000,78375"
 )
 tg (CPTG
@@ -5035,7 +5054,7 @@
 font "arial,8,0"
 )
-xt "33000,79500,38100,80500"
+xt "29000,77500,34100,78500"
 st "config_ready"
-blo "33000,80300"
+blo "29000,78300"
 )
 )
@@ -5062,5 +5081,5 @@
 fg "0,65535,0"
 )
-xt "31250,77625,32000,78375"
+xt "27250,75625,28000,76375"
 )
 tg (CPTG
@@ -5073,7 +5092,7 @@
 font "arial,8,0"
 )
-xt "33000,77500,37800,78500"
+xt "29000,75500,33800,76500"
 st "config_start"
-blo "33000,78300"
+blo "29000,76300"
 )
 )
@@ -5098,5 +5117,5 @@
 fg "0,65535,0"
 )
-xt "31250,73625,32000,74375"
+xt "27250,71625,28000,72375"
 )
 tg (CPTG
@@ -5109,7 +5128,7 @@
 font "arial,8,0"
 )
-xt "33000,73500,38300,74500"
+xt "29000,71500,34300,72500"
 st "ram_write_ea"
-blo "33000,74300"
+blo "29000,72300"
 )
 )
@@ -5136,5 +5155,5 @@
 fg "0,65535,0"
 )
-xt "31250,74625,32000,75375"
+xt "27250,72625,28000,73375"
 )
 tg (CPTG
@@ -5147,7 +5166,7 @@
 font "arial,8,0"
 )
-xt "33000,74500,39300,75500"
+xt "29000,72500,35300,73500"
 st "ram_write_ready"
-blo "33000,75300"
+blo "29000,73300"
 )
 )
@@ -5173,5 +5192,5 @@
 fg "0,65535,0"
 )
-xt "31250,80625,32000,81375"
+xt "27250,78625,28000,79375"
 )
 tg (CPTG
@@ -5184,7 +5203,7 @@
 font "arial,8,0"
 )
-xt "33000,80500,36000,81500"
+xt "29000,78500,32000,79500"
 st "roi_max"
-blo "33000,81300"
+blo "29000,79300"
 )
 )
@@ -5212,5 +5231,5 @@
 fg "0,65535,0"
 )
-xt "63000,70625,63750,71375"
+xt "59000,70625,59750,71375"
 )
 tg (CPTG
@@ -5223,8 +5242,8 @@
 font "arial,8,0"
 )
-xt "58600,70500,62000,71500"
+xt "54600,70500,58000,71500"
 st "wiz_busy"
 ju 2
-blo "62000,71300"
+blo "58000,71300"
 )
 )
@@ -5249,5 +5268,5 @@
 fg "0,65535,0"
 )
-xt "63000,74625,63750,75375"
+xt "59000,74625,59750,75375"
 )
 tg (CPTG
@@ -5260,8 +5279,8 @@
 font "arial,8,0"
 )
-xt "50200,74500,62000,75500"
+xt "46200,74500,58000,75500"
 st "wiz_number_of_channels : (3:0)"
 ju 2
-blo "62000,75300"
+blo "58000,75300"
 )
 )
@@ -5289,5 +5308,5 @@
 fg "0,65535,0"
 )
-xt "63000,73625,63750,74375"
+xt "59000,73625,59750,74375"
 )
 tg (CPTG
@@ -5300,8 +5319,8 @@
 font "arial,8,0"
 )
-xt "42100,73500,62000,74500"
+xt "38100,73500,58000,74500"
 st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
 ju 2
-blo "62000,74300"
+blo "58000,74300"
 )
 )
@@ -5330,5 +5349,5 @@
 fg "0,65535,0"
 )
-xt "63000,71625,63750,72375"
+xt "59000,71625,59750,72375"
 )
 tg (CPTG
@@ -5341,8 +5360,8 @@
 font "arial,8,0"
 )
-xt "56900,71500,62000,72500"
+xt "52900,71500,58000,72500"
 st "wiz_write_ea"
 ju 2
-blo "62000,72300"
+blo "58000,72300"
 )
 )
@@ -5369,5 +5388,5 @@
 fg "0,65535,0"
 )
-xt "63000,75625,63750,76375"
+xt "59000,75625,59750,76375"
 )
 tg (CPTG
@@ -5380,8 +5399,8 @@
 font "arial,8,0"
 )
-xt "56500,75500,62000,76500"
+xt "52500,75500,58000,76500"
 st "wiz_write_end"
 ju 2
-blo "62000,76300"
+blo "58000,76300"
 )
 )
@@ -5408,5 +5427,5 @@
 fg "0,65535,0"
 )
-xt "63000,76625,63750,77375"
+xt "59000,76625,59750,77375"
 )
 tg (CPTG
@@ -5419,8 +5438,8 @@
 font "arial,8,0"
 )
-xt "55400,76500,62000,77500"
+xt "51400,76500,58000,77500"
 st "wiz_write_header"
 ju 2
-blo "62000,77300"
+blo "58000,77300"
 )
 )
@@ -5447,5 +5466,5 @@
 fg "0,65535,0"
 )
-xt "63000,72625,63750,73375"
+xt "59000,72625,59750,73375"
 )
 tg (CPTG
@@ -5458,8 +5477,8 @@
 font "arial,8,0"
 )
-xt "52600,72500,62000,73500"
+xt "48600,72500,58000,73500"
 st "wiz_write_length : (16:0)"
 ju 2
-blo "62000,73300"
+blo "58000,73300"
 )
 )
@@ -5487,5 +5506,5 @@
 fg "0,65535,0"
 )
-xt "31250,87625,32000,88375"
+xt "27250,85625,28000,86375"
 )
 tg (CPTG
@@ -5498,7 +5517,7 @@
 font "arial,8,0"
 )
-xt "33000,87500,36400,88500"
+xt "29000,85500,32400,86500"
 st "roi_array"
-blo "33000,88300"
+blo "29000,86300"
 )
 )
@@ -5525,5 +5544,5 @@
 fg "0,65535,0"
 )
-xt "31250,81625,32000,82375"
+xt "27250,79625,28000,80375"
 )
 tg (CPTG
@@ -5536,7 +5555,7 @@
 font "arial,8,0"
 )
-xt "33000,81500,42100,82500"
+xt "29000,79500,38100,80500"
 st "package_length : (15:0)"
-blo "33000,82300"
+blo "29000,80300"
 )
 )
@@ -5564,5 +5583,5 @@
 fg "0,65535,0"
 )
-xt "31250,78625,32000,79375"
+xt "27250,76625,28000,77375"
 )
 tg (CPTG
@@ -5575,7 +5594,7 @@
 font "arial,8,0"
 )
-xt "33000,78500,38600,79500"
+xt "29000,76500,34600,77500"
 st "config_started"
-blo "33000,79300"
+blo "29000,77300"
 )
 )
@@ -5602,5 +5621,5 @@
 fg "0,65535,0"
 )
-xt "63000,77625,63750,78375"
+xt "59000,77625,59750,78375"
 )
 tg (CPTG
@@ -5613,8 +5632,8 @@
 font "arial,8,0"
 )
-xt "59000,77500,62000,78500"
+xt "55000,77500,58000,78500"
 st "wiz_ack"
 ju 2
-blo "62000,78300"
+blo "58000,78300"
 )
 )
@@ -5639,5 +5658,5 @@
 fg "0,65535,0"
 )
-xt "31250,75625,32000,76375"
+xt "27250,73625,28000,74375"
 )
 tg (CPTG
@@ -5650,7 +5669,7 @@
 font "arial,8,0"
 )
-xt "33000,75500,40800,76500"
+xt "29000,73500,36800,74500"
 st "ram_write_ready_ack"
-blo "33000,76300"
+blo "29000,74300"
 )
 )
@@ -5679,5 +5698,5 @@
 lineWidth 2
 )
-xt "32000,70000,63000,90000"
+xt "28000,68000,59000,88000"
 )
 oxt "15000,6000,23000,16000"
@@ -5692,7 +5711,7 @@
 font "arial,8,1"
 )
-xt "32350,90000,38550,91000"
+xt "28350,88000,34550,89000"
 st "FACT_FAD_lib"
-blo "32350,90800"
+blo "28350,88800"
 tm "BdLibraryNameMgr"
 )
@@ -5702,7 +5721,7 @@
 font "arial,8,1"
 )
-xt "32350,91000,39650,92000"
+xt "28350,89000,35650,90000"
 st "memory_manager"
-blo "32350,91800"
+blo "28350,89800"
 tm "CptNameMgr"
 )
@@ -5712,7 +5731,7 @@
 font "arial,8,1"
 )
-xt "32350,92000,42850,93000"
+xt "28350,90000,38850,91000"
 st "I_main_memory_manager"
-blo "32350,92800"
+blo "28350,90800"
 tm "InstanceNameMgr"
 )
@@ -5729,5 +5748,5 @@
 font "Courier New,8,0"
 )
-xt "32000,68400,61500,70000"
+xt "31000,66400,60500,68000"
 st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer )  
 RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
@@ -5755,5 +5774,5 @@
 fg "49152,49152,49152"
 )
-xt "32250,88250,33750,89750"
+xt "28250,86250,29750,87750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -5781,5 +5800,6 @@
 )
 xt "-172000,101200,-149500,102000"
-st "SIGNAL wiz_busy               : std_logic"
+st "SIGNAL wiz_busy               : std_logic
+"
 )
 )
@@ -5800,5 +5820,6 @@
 )
 xt "-172000,103600,-128500,104400"
-st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
+st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
+"
 )
 )
@@ -5820,5 +5841,6 @@
 )
 xt "-172000,106000,-122500,106800"
-st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
+st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
+"
 )
 )
@@ -5841,5 +5863,6 @@
 )
 xt "-172000,102800,-122500,103600"
-st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
+st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
+"
 )
 )
@@ -5861,5 +5884,6 @@
 )
 xt "-172000,102000,-122500,102800"
-st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
+st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
+"
 )
 )
@@ -5880,5 +5904,6 @@
 )
 xt "-172000,104400,-128500,105200"
-st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
+st "SIGNAL wiz_write_end          : std_logic                                    := '0'
+"
 )
 )
@@ -5899,5 +5924,6 @@
 )
 xt "-172000,105200,-128500,106000"
-st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
+st "SIGNAL wiz_write_header       : std_logic                                    := '0'
+"
 )
 )
@@ -5916,5 +5942,6 @@
 )
 xt "-172000,82800,-149500,83600"
-st "SIGNAL ram_write_ea           : std_logic"
+st "SIGNAL ram_write_ea           : std_logic
+"
 )
 )
@@ -5934,5 +5961,6 @@
 )
 xt "-172000,83600,-128500,84400"
-st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
+st "SIGNAL ram_write_ready        : std_logic                                    := '0'
+"
 )
 )
@@ -5952,5 +5980,6 @@
 )
 xt "-172000,54800,-128500,55600"
-st "SIGNAL config_start           : std_logic                                    := '0'"
+st "SIGNAL config_start           : std_logic                                    := '0'
+"
 )
 )
@@ -5969,5 +5998,6 @@
 )
 xt "-172000,49200,-149500,50000"
-st "SIGNAL config_ready           : std_logic"
+st "SIGNAL config_ready           : std_logic
+"
 )
 )
@@ -5986,5 +6016,6 @@
 )
 xt "-172000,86800,-148000,87600"
-st "SIGNAL roi_max                : roi_max_type"
+st "SIGNAL roi_max                : roi_max_type
+"
 )
 )
@@ -6004,5 +6035,6 @@
 )
 xt "-172000,77200,-139500,78000"
-st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
+st "SIGNAL package_length         : std_logic_vector(15 downto 0)
+"
 )
 )
@@ -6022,5 +6054,6 @@
 )
 xt "-172000,19200,-132000,20000"
-st "adc_oeb                : std_logic                                    := '1'"
+st "adc_oeb                : std_logic                                    := '1'
+"
 )
 )
@@ -6129,5 +6162,6 @@
 )
 xt "-172000,86000,-147000,86800"
-st "SIGNAL roi_array              : roi_array_type"
+st "SIGNAL roi_array              : roi_array_type
+"
 )
 )
@@ -6562,5 +6596,6 @@
 )
 xt "-172000,14400,-153500,15200"
-st "CLK_25_PS              : std_logic"
+st "CLK_25_PS              : std_logic
+"
 )
 )
@@ -6624,5 +6659,6 @@
 )
 xt "-172000,15200,-153500,16000"
-st "CLK_50                 : std_logic"
+st "CLK_50                 : std_logic
+"
 )
 )
@@ -6641,5 +6677,6 @@
 )
 xt "-172000,39600,-149500,40400"
-st "SIGNAL CLK_25                 : std_logic"
+st "SIGNAL CLK_25                 : std_logic
+"
 )
 )
@@ -6703,5 +6740,6 @@
 )
 xt "-172000,3200,-153500,4000"
-st "CLK                    : std_logic"
+st "CLK                    : std_logic
+"
 )
 )
@@ -6721,5 +6759,6 @@
 )
 xt "-172000,8800,-143500,9600"
-st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
+st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
+"
 )
 )
@@ -6738,5 +6777,6 @@
 )
 xt "-172000,8000,-148000,8800"
-st "adc_data_array         : adc_data_array_type"
+st "adc_data_array         : adc_data_array_type
+"
 )
 )
@@ -6801,5 +6841,6 @@
 )
 xt "-172000,66800,-128500,67600"
-st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
+st "SIGNAL drs_clk_en             : std_logic                                    := '0'
+"
 )
 )
@@ -6818,5 +6859,6 @@
 )
 xt "-172000,73200,-143500,74000"
-st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
+st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
+"
 )
 )
@@ -6836,5 +6878,6 @@
 )
 xt "-172000,67600,-128500,68400"
-st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
+st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
+"
 )
 )
@@ -6855,5 +6898,6 @@
 )
 xt "-172000,25600,-126000,26400"
-st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
+st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
+"
 )
 )
@@ -6873,5 +6917,6 @@
 )
 xt "-172000,26400,-132000,27200"
-st "drs_dwrite             : std_logic                                    := '1'"
+st "drs_dwrite             : std_logic                                    := '1'
+"
 )
 )
@@ -6980,5 +7025,6 @@
 )
 xt "-172000,4800,-153500,5600"
-st "SROUT_in_0             : std_logic"
+st "SROUT_in_0             : std_logic
+"
 )
 )
@@ -6997,5 +7043,6 @@
 )
 xt "-172000,5600,-153500,6400"
-st "SROUT_in_1             : std_logic"
+st "SROUT_in_1             : std_logic
+"
 )
 )
@@ -7014,5 +7061,6 @@
 )
 xt "-172000,6400,-153500,7200"
-st "SROUT_in_2             : std_logic"
+st "SROUT_in_2             : std_logic
+"
 )
 )
@@ -7031,5 +7079,6 @@
 )
 xt "-172000,7200,-153500,8000"
-st "SROUT_in_3             : std_logic"
+st "SROUT_in_3             : std_logic
+"
 )
 )
@@ -7228,5 +7277,6 @@
 )
 xt "-172000,68400,-149500,69200"
-st "SIGNAL drs_read_s_cell_ready  : std_logic"
+st "SIGNAL drs_read_s_cell_ready  : std_logic
+"
 )
 )
@@ -7883,5 +7933,6 @@
 )
 xt "-172000,16000,-132000,16800"
-st "RSRLOAD                : std_logic                                    := '0'"
+st "RSRLOAD                : std_logic                                    := '0'
+"
 )
 )
@@ -7946,5 +7997,6 @@
 )
 xt "-172000,16800,-132000,17600"
-st "SRCLK                  : std_logic                                    := '0'"
+st "SRCLK                  : std_logic                                    := '0'
+"
 )
 )
@@ -8599,5 +8651,6 @@
 )
 xt "-172000,45200,-140000,46000"
-st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
+st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
+"
 )
 )
@@ -8616,5 +8669,6 @@
 )
 xt "-172000,47600,-149500,48400"
-st "SIGNAL config_data_valid      : std_logic"
+st "SIGNAL config_data_valid      : std_logic
+"
 )
 )
@@ -8633,5 +8687,6 @@
 )
 xt "-172000,46000,-149500,46800"
-st "SIGNAL config_busy            : std_logic"
+st "SIGNAL config_busy            : std_logic
+"
 )
 )
@@ -8651,5 +8706,6 @@
 )
 xt "-172000,46800,-139500,47600"
-st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
+st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
+"
 )
 )
@@ -8668,5 +8724,6 @@
 )
 xt "-172000,60400,-149500,61200"
-st "SIGNAL config_wr_en           : std_logic"
+st "SIGNAL config_wr_en           : std_logic
+"
 )
 )
@@ -8685,5 +8742,6 @@
 )
 xt "-172000,48400,-149500,49200"
-st "SIGNAL config_rd_en           : std_logic"
+st "SIGNAL config_rd_en           : std_logic
+"
 )
 )
@@ -8702,5 +8760,6 @@
 )
 xt "-172000,61200,-147000,62000"
-st "SIGNAL dac_array              : dac_array_type"
+st "SIGNAL dac_array              : dac_array_type
+"
 )
 )
@@ -8719,5 +8778,6 @@
 )
 xt "-172000,55600,-149500,56400"
-st "SIGNAL config_start_cm        : std_logic"
+st "SIGNAL config_start_cm        : std_logic
+"
 )
 )
@@ -8736,5 +8796,6 @@
 )
 xt "-172000,50000,-149500,50800"
-st "SIGNAL config_ready_cm        : std_logic"
+st "SIGNAL config_ready_cm        : std_logic
+"
 )
 )
@@ -8756,5 +8817,6 @@
 )
 xt "-172000,28000,-126000,28800"
-st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
+st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
+"
 )
 )
@@ -8773,5 +8835,6 @@
 )
 xt "-172000,91600,-149500,92400"
-st "SIGNAL sensor_ready           : std_logic"
+st "SIGNAL sensor_ready           : std_logic
+"
 )
 )
@@ -8790,5 +8853,6 @@
 )
 xt "-172000,90800,-145500,91600"
-st "SIGNAL sensor_array           : sensor_array_type"
+st "SIGNAL sensor_array           : sensor_array_type
+"
 )
 )
@@ -8807,5 +8871,6 @@
 )
 xt "-172000,50800,-149500,51600"
-st "SIGNAL config_ready_spi       : std_logic"
+st "SIGNAL config_ready_spi       : std_logic
+"
 )
 )
@@ -8826,5 +8891,6 @@
 )
 xt "-172000,42000,-140000,42800"
-st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
+st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
+"
 )
 )
@@ -8843,5 +8909,6 @@
 )
 xt "-172000,41200,-144500,42000"
-st "SIGNAL adc_data_array_int     : adc_data_array_type"
+st "SIGNAL adc_data_array_int     : adc_data_array_type
+"
 )
 )
@@ -9133,5 +9200,6 @@
 )
 xt "-172000,56400,-128500,57200"
-st "SIGNAL config_start_spi       : std_logic                                    := '0'"
+st "SIGNAL config_start_spi       : std_logic                                    := '0'
+"
 )
 )
@@ -9666,5 +9734,6 @@
 )
 xt "-172000,30400,-153500,31200"
-st "sclk                   : std_logic"
+st "sclk                   : std_logic
+"
 )
 )
@@ -9685,5 +9754,6 @@
 )
 xt "-172000,36000,-153500,36800"
-st "sio                    : std_logic"
+st "sio                    : std_logic
+"
 )
 )
@@ -9702,5 +9772,6 @@
 )
 xt "-172000,24000,-153500,24800"
-st "dac_cs                 : std_logic"
+st "dac_cs                 : std_logic
+"
 )
 )
@@ -9720,5 +9791,6 @@
 )
 xt "-172000,31200,-143500,32000"
-st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
+st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
+"
 )
 )
@@ -9918,5 +9990,6 @@
 )
 xt "-172000,76400,-128500,77200"
-st "SIGNAL new_config             : std_logic                                    := '0'"
+st "SIGNAL new_config             : std_logic                                    := '0'
+"
 )
 )
@@ -9935,5 +10008,6 @@
 )
 xt "-172000,57200,-149500,58000"
-st "SIGNAL config_started         : std_logic"
+st "SIGNAL config_started         : std_logic
+"
 )
 )
@@ -9953,5 +10027,6 @@
 )
 xt "-172000,59600,-128500,60400"
-st "SIGNAL config_started_spi     : std_logic                                    := '0'"
+st "SIGNAL config_started_spi     : std_logic                                    := '0'
+"
 )
 )
@@ -9971,5 +10046,6 @@
 )
 xt "-172000,58000,-128500,58800"
-st "SIGNAL config_started_cu      : std_logic                                    := '0'"
+st "SIGNAL config_started_cu      : std_logic                                    := '0'
+"
 )
 )
@@ -9988,5 +10064,6 @@
 )
 xt "-172000,58800,-149500,59600"
-st "SIGNAL config_started_mm      : std_logic"
+st "SIGNAL config_started_mm      : std_logic
+"
 )
 )
@@ -10006,5 +10083,6 @@
 )
 xt "-172000,28800,-132000,29600"
-st "mosi                   : std_logic                                    := '0'"
+st "mosi                   : std_logic                                    := '0'
+"
 )
 )
@@ -10071,5 +10149,6 @@
 )
 xt "-172000,24800,-118500,25600"
-st "denable                : std_logic                                    := '0' -- default domino wave off"
+st "denable                : std_logic                                    := '0' -- default domino wave off
+"
 )
 )
@@ -10133,5 +10212,6 @@
 )
 xt "-172000,75600,-128500,76400"
-st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
+st "SIGNAL dwrite_enable          : std_logic                                    := '1'
+"
 )
 )
@@ -10520,5 +10600,6 @@
 )
 xt "-172000,74800,-128500,75600"
-st "SIGNAL dwrite                 : std_logic                                    := '1'"
+st "SIGNAL dwrite                 : std_logic                                    := '1'
+"
 )
 )
@@ -10894,5 +10975,6 @@
 )
 xt "-172000,100400,-149500,101200"
-st "SIGNAL wiz_ack                : std_logic"
+st "SIGNAL wiz_ack                : std_logic
+"
 )
 )
@@ -11277,5 +11359,6 @@
 )
 xt "-172000,89200,-149500,90000"
-st "SIGNAL sclk1                  : std_logic"
+st "SIGNAL sclk1                  : std_logic
+"
 )
 )
@@ -11294,5 +11377,6 @@
 )
 xt "-172000,90000,-149500,90800"
-st "SIGNAL sclk_enable            : std_logic"
+st "SIGNAL sclk_enable            : std_logic
+"
 )
 )
@@ -11312,5 +11396,6 @@
 )
 xt "-172000,18400,-132000,19200"
-st "adc_clk_en             : std_logic                                    := '0'"
+st "adc_clk_en             : std_logic                                    := '0'
+"
 )
 )
@@ -11766,5 +11851,6 @@
 )
 xt "-172000,78000,-113000,78800"
-st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards"
+st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards
+"
 )
 )
@@ -11787,5 +11873,6 @@
 )
 xt "-172000,78800,-112000,79600"
-st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once"
+st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once
+"
 )
 )
@@ -11807,5 +11894,6 @@
 )
 xt "-172000,79600,-104500,80400"
-st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift"
+st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift
+"
 )
 )
@@ -11825,5 +11913,6 @@
 )
 xt "-172000,94000,-128500,94800"
-st "SIGNAL srclk_enable           : std_logic                                    := '0'"
+st "SIGNAL srclk_enable           : std_logic                                    := '0'
+"
 )
 )
@@ -12209,5 +12298,6 @@
 )
 xt "-172000,40400,-128500,41200"
-st "SIGNAL SRCLK1                 : std_logic                                    := '0'"
+st "SIGNAL SRCLK1                 : std_logic                                    := '0'
+"
 )
 )
@@ -12231,5 +12321,6 @@
 xt "-172000,51600,-128500,53200"
 st "-- --
-SIGNAL config_rw_ack          : std_logic                                    := '0'"
+SIGNAL config_rw_ack          : std_logic                                    := '0'
+"
 )
 )
@@ -12253,5 +12344,6 @@
 xt "-172000,53200,-128500,54800"
 st "-- --
-SIGNAL config_rw_ready        : std_logic                                    := '0'"
+SIGNAL config_rw_ready        : std_logic                                    := '0'
+"
 )
 )
@@ -12270,5 +12362,6 @@
 )
 xt "-172000,87600,-149500,88400"
-st "SIGNAL s_trigger              : std_logic"
+st "SIGNAL s_trigger              : std_logic
+"
 )
 )
@@ -12287,5 +12380,6 @@
 )
 xt "-172000,96400,-149500,97200"
-st "SIGNAL start_srin_write_8b    : std_logic"
+st "SIGNAL start_srin_write_8b    : std_logic
+"
 )
 )
@@ -12305,5 +12399,6 @@
 )
 xt "-172000,94800,-128500,95600"
-st "SIGNAL srin_write_ack         : std_logic                                    := '0'"
+st "SIGNAL srin_write_ack         : std_logic                                    := '0'
+"
 )
 )
@@ -12323,5 +12418,6 @@
 )
 xt "-172000,95600,-128500,96400"
-st "SIGNAL srin_write_ready       : std_logic                                    := '0'"
+st "SIGNAL srin_write_ready       : std_logic                                    := '0'
+"
 )
 )
@@ -12342,5 +12438,6 @@
 )
 xt "-172000,74000,-122500,74800"
-st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')"
+st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')
+"
 )
 )
@@ -12360,5 +12457,6 @@
 )
 xt "-172000,17600,-132000,18400"
-st "SRIN_out               : std_logic                                    := '0'"
+st "SRIN_out               : std_logic                                    := '0'
+"
 )
 )
@@ -12863,23 +12961,4 @@
 )
 *431 (Net
-uid 10449,0
-decl (Decl
-n "trigger_out"
-t "std_logic"
-preAdd 0
-posAdd 0
-o 120
-suid 240,0
-)
-declText (MLText
-uid 10450,0
-va (VaSet
-font "Courier New,8,0"
-)
-xt "-172000,99600,-149500,100400"
-st "SIGNAL trigger_out            : std_logic"
-)
-)
-*432 (Net
 uid 10465,0
 lang 2
@@ -12901,8 +12980,9 @@
 xt "-172000,84400,-128500,86000"
 st "-- --
-SIGNAL ram_write_ready_ack    : std_logic                                    := '0'"
-)
-)
-*433 (Net
+SIGNAL ram_write_ready_ack    : std_logic                                    := '0'
+"
+)
+)
+*432 (Net
 uid 10627,0
 decl (Decl
@@ -12918,8 +12998,9 @@
 )
 xt "-172000,92400,-149500,93200"
-st "SIGNAL socks_connected        : std_logic"
-)
-)
-*434 (Net
+st "SIGNAL socks_connected        : std_logic
+"
+)
+)
+*433 (Net
 uid 10635,0
 decl (Decl
@@ -12935,8 +13016,9 @@
 )
 xt "-172000,93200,-149500,94000"
-st "SIGNAL socks_waiting          : std_logic"
-)
-)
-*435 (Net
+st "SIGNAL socks_waiting          : std_logic
+"
+)
+)
+*434 (Net
 uid 10721,0
 decl (Decl
@@ -12952,8 +13034,9 @@
 )
 xt "-172000,27200,-153500,28000"
-st "green                  : std_logic"
-)
-)
-*436 (PortIoOut
+st "green                  : std_logic
+"
+)
+)
+*435 (PortIoOut
 uid 10729,0
 shape (CompositeShape
@@ -12999,5 +13082,5 @@
 )
 )
-*437 (Net
+*436 (Net
 uid 10735,0
 decl (Decl
@@ -13013,8 +13096,9 @@
 )
 xt "-172000,22400,-153500,23200"
-st "amber                  : std_logic"
-)
-)
-*438 (PortIoOut
+st "amber                  : std_logic
+"
+)
+)
+*437 (PortIoOut
 uid 10743,0
 shape (CompositeShape
@@ -13060,5 +13144,5 @@
 )
 )
-*439 (Net
+*438 (Net
 uid 10749,0
 decl (Decl
@@ -13074,8 +13158,9 @@
 )
 xt "-172000,29600,-153500,30400"
-st "red                    : std_logic"
-)
-)
-*440 (PortIoOut
+st "red                    : std_logic
+"
+)
+)
+*439 (PortIoOut
 uid 10757,0
 shape (CompositeShape
@@ -13121,8 +13206,8 @@
 )
 )
-*441 (SaComponent
+*440 (SaComponent
 uid 11209,0
 optionalChildren [
-*442 (CptPort
+*441 (CptPort
 uid 11181,0
 ps "OnEdgeStrategy"
@@ -13157,5 +13242,5 @@
 )
 )
-*443 (CptPort
+*442 (CptPort
 uid 11185,0
 ps "OnEdgeStrategy"
@@ -13192,5 +13277,5 @@
 )
 )
-*444 (CptPort
+*443 (CptPort
 uid 11189,0
 ps "OnEdgeStrategy"
@@ -13227,5 +13312,5 @@
 )
 )
-*445 (CptPort
+*444 (CptPort
 uid 11193,0
 ps "OnEdgeStrategy"
@@ -13262,5 +13347,5 @@
 )
 )
-*446 (CptPort
+*445 (CptPort
 uid 11197,0
 ps "OnEdgeStrategy"
@@ -13295,5 +13380,5 @@
 )
 )
-*447 (CptPort
+*446 (CptPort
 uid 11201,0
 ps "OnEdgeStrategy"
@@ -13328,5 +13413,5 @@
 )
 )
-*448 (CptPort
+*447 (CptPort
 uid 11205,0
 ps "OnEdgeStrategy"
@@ -13361,5 +13446,5 @@
 )
 )
-*449 (CptPort
+*448 (CptPort
 uid 12693,0
 ps "OnEdgeStrategy"
@@ -13413,5 +13498,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*450 (Text
+*449 (Text
 uid 11212,0
 va (VaSet
@@ -13423,5 +13508,5 @@
 tm "BdLibraryNameMgr"
 )
-*451 (Text
+*450 (Text
 uid 11213,0
 va (VaSet
@@ -13433,5 +13518,5 @@
 tm "CptNameMgr"
 )
-*452 (Text
+*451 (Text
 uid 11214,0
 va (VaSet
@@ -13500,5 +13585,5 @@
 archFileType "UNKNOWN"
 )
-*453 (Net
+*452 (Net
 uid 11403,0
 decl (Decl
@@ -13514,8 +13599,9 @@
 )
 xt "-172000,72400,-149500,73200"
-st "SIGNAL drs_readout_started    : std_logic"
-)
-)
-*454 (Net
+st "SIGNAL drs_readout_started    : std_logic
+"
+)
+)
+*453 (Net
 uid 11856,0
 decl (Decl
@@ -13531,14 +13617,15 @@
 )
 xt "-172000,98000,-149500,98800"
-st "SIGNAL trigger_enable         : std_logic"
-)
-)
-*455 (MWC
+st "SIGNAL trigger_enable         : std_logic
+"
+)
+)
+*454 (MWC
 uid 12295,0
 optionalChildren [
-*456 (CptPort
+*455 (CptPort
 uid 12267,0
 optionalChildren [
-*457 (Line
+*456 (Line
 uid 12271,0
 layer 5
@@ -13553,5 +13640,5 @@
 ]
 )
-*458 (Property
+*457 (Property
 uid 12272,0
 pclass "_MW_GEOM_"
@@ -13600,8 +13687,8 @@
 )
 )
-*459 (CptPort
+*458 (CptPort
 uid 12273,0
 optionalChildren [
-*460 (Line
+*459 (Line
 uid 12277,0
 layer 5
@@ -13655,8 +13742,8 @@
 )
 )
-*461 (CptPort
+*460 (CptPort
 uid 12278,0
 optionalChildren [
-*462 (Line
+*461 (Line
 uid 12282,0
 layer 5
@@ -13708,8 +13795,8 @@
 )
 )
-*463 (CommentGraphic
+*462 (CommentGraphic
 uid 12283,0
 optionalChildren [
-*464 (Property
+*463 (Property
 uid 12285,0
 pclass "_MW_GEOM_"
@@ -13735,8 +13822,8 @@
 oxt "7000,10000,7000,10000"
 )
-*465 (CommentGraphic
+*464 (CommentGraphic
 uid 12286,0
 optionalChildren [
-*466 (Property
+*465 (Property
 uid 12288,0
 pclass "_MW_GEOM_"
@@ -13762,8 +13849,8 @@
 oxt "7000,6000,7000,6000"
 )
-*467 (Grouping
+*466 (Grouping
 uid 12289,0
 optionalChildren [
-*468 (CommentGraphic
+*467 (CommentGraphic
 uid 12291,0
 shape (PolyLine2D
@@ -13786,5 +13873,5 @@
 oxt "7000,6000,9000,10000"
 )
-*469 (CommentGraphic
+*468 (CommentGraphic
 uid 12293,0
 shape (Arc2D
@@ -13839,5 +13926,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*470 (Text
+*469 (Text
 uid 12298,0
 va (VaSet
@@ -13849,5 +13936,5 @@
 blo "-80500,73300"
 )
-*471 (Text
+*470 (Text
 uid 12299,0
 va (VaSet
@@ -13858,5 +13945,5 @@
 blo "-80500,74300"
 )
-*472 (Text
+*471 (Text
 uid 12300,0
 va (VaSet
@@ -13903,5 +13990,5 @@
 )
 )
-*473 (Net
+*472 (Net
 uid 12304,0
 decl (Decl
@@ -13919,11 +14006,12 @@
 )
 xt "-172000,65200,-149500,66000"
-st "SIGNAL dout                   : std_logic"
-)
-)
-*474 (SaComponent
+st "SIGNAL dout                   : std_logic
+"
+)
+)
+*473 (SaComponent
 uid 12625,0
 optionalChildren [
-*475 (CptPort
+*474 (CptPort
 uid 12605,0
 ps "OnEdgeStrategy"
@@ -13958,5 +14046,5 @@
 )
 )
-*476 (CptPort
+*475 (CptPort
 uid 12609,0
 ps "OnEdgeStrategy"
@@ -13994,5 +14082,5 @@
 )
 )
-*477 (CptPort
+*476 (CptPort
 uid 12613,0
 ps "OnEdgeStrategy"
@@ -14029,5 +14117,5 @@
 )
 )
-*478 (CptPort
+*477 (CptPort
 uid 12617,0
 ps "OnEdgeStrategy"
@@ -14063,5 +14151,5 @@
 )
 )
-*479 (CptPort
+*478 (CptPort
 uid 12621,0
 ps "OnEdgeStrategy"
@@ -14099,5 +14187,5 @@
 )
 )
-*480 (CptPort
+*479 (CptPort
 uid 12673,0
 ps "OnEdgeStrategy"
@@ -14149,5 +14237,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*481 (Text
+*480 (Text
 uid 12628,0
 va (VaSet
@@ -14159,5 +14247,5 @@
 tm "BdLibraryNameMgr"
 )
-*482 (Text
+*481 (Text
 uid 12629,0
 va (VaSet
@@ -14169,5 +14257,5 @@
 tm "CptNameMgr"
 )
-*483 (Text
+*482 (Text
 uid 12630,0
 va (VaSet
@@ -14216,5 +14304,5 @@
 archFileType "UNKNOWN"
 )
-*484 (Net
+*483 (Net
 uid 12641,0
 decl (Decl
@@ -14232,8 +14320,9 @@
 )
 xt "-172000,66000,-149500,66800"
-st "SIGNAL dout1                  : std_logic"
-)
-)
-*485 (Net
+st "SIGNAL dout1                  : std_logic
+"
+)
+)
+*484 (Net
 uid 12647,0
 decl (Decl
@@ -14256,8 +14345,9 @@
 st "-- --
 --      drs_dwrite : out std_logic := '1';
-SIGNAL drs_readout_ready      : std_logic                                    := '0'"
-)
-)
-*486 (Net
+SIGNAL drs_readout_ready      : std_logic                                    := '0'
+"
+)
+)
+*485 (Net
 uid 12653,0
 decl (Decl
@@ -14273,8 +14363,9 @@
 )
 xt "-172000,71600,-149500,72400"
-st "SIGNAL drs_readout_ready_ack  : std_logic"
-)
-)
-*487 (Net
+st "SIGNAL drs_readout_ready_ack  : std_logic
+"
+)
+)
+*486 (Net
 uid 12705,0
 decl (Decl
@@ -14290,8 +14381,9 @@
 )
 xt "-172000,20000,-153500,20800"
-st "additional_flasher_out : std_logic"
-)
-)
-*488 (PortIoOut
+st "additional_flasher_out : std_logic
+"
+)
+)
+*487 (PortIoOut
 uid 12713,0
 shape (CompositeShape
@@ -14337,8 +14429,8 @@
 )
 )
-*489 (SaComponent
+*488 (SaComponent
 uid 13117,0
 optionalChildren [
-*490 (CptPort
+*489 (CptPort
 uid 13101,0
 ps "OnEdgeStrategy"
@@ -14350,5 +14442,5 @@
 fg "0,65535,0"
 )
-xt "63000,61625,63750,62375"
+xt "72000,61625,72750,62375"
 )
 tg (CPTG
@@ -14360,8 +14452,8 @@
 va (VaSet
 )
-xt "60100,61500,62000,62500"
+xt "69100,61500,71000,62500"
 st "CLK"
 ju 2
-blo "62000,62300"
+blo "71000,62300"
 )
 )
@@ -14374,5 +14466,5 @@
 )
 )
-*491 (CptPort
+*490 (CptPort
 uid 13105,0
 ps "OnEdgeStrategy"
@@ -14384,5 +14476,5 @@
 fg "0,65535,0"
 )
-xt "63000,62625,63750,63375"
+xt "72000,62625,72750,63375"
 )
 tg (CPTG
@@ -14394,8 +14486,8 @@
 va (VaSet
 )
-xt "59400,62500,62000,63500"
+xt "68400,62500,71000,63500"
 st "enable"
 ju 2
-blo "62000,63300"
+blo "71000,63300"
 )
 )
@@ -14408,5 +14500,5 @@
 )
 )
-*492 (CptPort
+*491 (CptPort
 uid 13109,0
 ps "OnEdgeStrategy"
@@ -14418,5 +14510,5 @@
 fg "0,65535,0"
 )
-xt "63000,63625,63750,64375"
+xt "72000,63625,72750,64375"
 )
 tg (CPTG
@@ -14428,8 +14520,8 @@
 va (VaSet
 )
-xt "55900,63500,62000,64500"
+xt "64900,63500,71000,64500"
 st "multiplier : (7:0)"
 ju 2
-blo "62000,64300"
+blo "71000,64300"
 )
 )
@@ -14443,5 +14535,5 @@
 )
 )
-*493 (CptPort
+*492 (CptPort
 uid 13113,0
 ps "OnEdgeStrategy"
@@ -14453,5 +14545,5 @@
 fg "0,65535,0"
 )
-xt "50250,61625,51000,62375"
+xt "59250,61625,60000,62375"
 )
 tg (CPTG
@@ -14463,7 +14555,7 @@
 va (VaSet
 )
-xt "52000,61500,54800,62500"
+xt "61000,61500,63800,62500"
 st "trigger"
-blo "52000,62300"
+blo "61000,62300"
 )
 )
@@ -14486,5 +14578,5 @@
 lineWidth 2
 )
-xt "51000,61000,63000,65000"
+xt "60000,61000,72000,65000"
 )
 oxt "0,0,8000,10000"
@@ -14494,32 +14586,32 @@
 stg "VerticalLayoutStrategy"
 textVec [
+*493 (Text
+uid 13120,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "62350,65000,68550,66000"
+st "FACT_FAD_lib"
+blo "62350,65800"
+tm "BdLibraryNameMgr"
+)
 *494 (Text
-uid 13120,0
+uid 13121,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "53350,65000,59550,66000"
-st "FACT_FAD_lib"
-blo "53350,65800"
-tm "BdLibraryNameMgr"
+xt "62350,66000,69650,67000"
+st "continous_pulser"
+blo "62350,66800"
+tm "CptNameMgr"
 )
 *495 (Text
-uid 13121,0
+uid 13122,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "53350,66000,60650,67000"
-st "continous_pulser"
-blo "53350,66800"
-tm "CptNameMgr"
-)
-*496 (Text
-uid 13122,0
-va (VaSet
-font "Arial,8,1"
-)
-xt "53350,67000,55150,68000"
+xt "62350,67000,64150,68000"
 st "U_3"
-blo "53350,67800"
+blo "62350,67800"
 tm "InstanceNameMgr"
 )
@@ -14536,5 +14628,5 @@
 font "Courier New,8,0"
 )
-xt "44000,60200,71500,61000"
+xt "53000,60200,80500,61000"
 st "MINIMAL_TRIGGER_WAIT_TIME = 250000    ( integer )  "
 )
@@ -14556,5 +14648,5 @@
 fg "49152,49152,49152"
 )
-xt "51250,63250,52750,64750"
+xt "60250,63250,61750,64750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -14567,5 +14659,5 @@
 archFileType "UNKNOWN"
 )
-*497 (Net
+*496 (Net
 uid 13157,0
 decl (Decl
@@ -14582,8 +14674,9 @@
 )
 xt "-172000,43600,-128500,44400"
-st "SIGNAL c_trigger_enable       : std_logic                                    := '0'"
-)
-)
-*498 (Net
+st "SIGNAL c_trigger_enable       : std_logic                                    := '0'
+"
+)
+)
+*497 (Net
 uid 13163,0
 decl (Decl
@@ -14603,8 +14696,9 @@
 )
 xt "-172000,44400,-112000,45200"
-st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes"
-)
-)
-*499 (Net
+st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes
+"
+)
+)
+*498 (Net
 uid 13206,0
 decl (Decl
@@ -14620,8 +14714,9 @@
 )
 xt "-172000,88400,-149500,89200"
-st "SIGNAL s_trigger_0            : std_logic"
-)
-)
-*500 (Net
+st "SIGNAL s_trigger_0            : std_logic
+"
+)
+)
+*499 (Net
 uid 13208,0
 decl (Decl
@@ -14637,14 +14732,15 @@
 )
 xt "-172000,97200,-149500,98000"
-st "SIGNAL trigger1               : std_logic"
-)
-)
-*501 (MWC
+st "SIGNAL trigger1               : std_logic
+"
+)
+)
+*500 (MWC
 uid 13266,0
 optionalChildren [
-*502 (CptPort
+*501 (CptPort
 uid 13230,0
 optionalChildren [
-*503 (Line
+*502 (Line
 uid 13234,0
 layer 5
@@ -14653,8 +14749,8 @@
 vasetType 3
 )
-xt "40408,62000,42000,62000"
-pts [
-"42000,62000"
-"40408,62000"
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 font "arial,8,0"
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 ju 2
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 font "arial,8,0"
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 st "dout"
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 shape (CustomPolygon
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 shape (PolyLine2D
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+xt "49500,61500,54300,62500"
 st "moduleware"
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-)
-)
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-)
-)
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-st "plllock_in             : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
-)
-)
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-)
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-)
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-)
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 blo "148500,89300"
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 blo "155350,77900"
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 blo "155350,78900"
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 )
 xt "-172000,63600,-115000,64400"
-st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off"
-)
-)
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+st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off
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+)
+)
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 decl (Decl
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 )
 xt "-172000,64400,-115000,65200"
-st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off"
-)
-)
-*598 (Net
+st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off
+"
+)
+)
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 decl (Decl
@@ -16884,5 +16988,25 @@
 )
 xt "-172000,62800,-115000,63600"
-st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off"
+st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off
+"
+)
+)
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+decl (Decl
+n "trigger_out"
+t "std_logic"
+o 123
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+i "'0'"
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+declText (MLText
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+va (VaSet
+font "Courier New,8,0"
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+xt "-172000,99600,-128500,100400"
+st "SIGNAL trigger_out            : std_logic                                    := '0'
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 lineWidth 2
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-xt "-40250,68000,-21750,71000"
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-"-36000,68000"
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-"-21750,71000"
+xt "-40250,69000,-21750,70000"
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-xt "750,66000,31250,73000"
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+xt "750,71000,27250,71000"
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@@ -17542,7 +17664,7 @@
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-xt "2000,65000,18700,66000"
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-blo "2000,65800"
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+xt "59750,71000,87250,71000"
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 )
-xt "64000,70000,67400,71000"
+xt "60000,70000,63400,71000"
 st "wiz_busy"
-blo "64000,70800"
+blo "60000,70800"
 tm "WireNameMgr"
 )
@@ -17595,10 +17715,8 @@
 vasetType 3
 )
-xt "63750,71000,87250,72000"
-pts [
-"63750,72000"
-"84000,72000"
-"84000,71000"
-"87250,71000"
+xt "59750,72000,87250,72000"
+pts [
+"59750,72000"
+"87250,72000"
 ]
 )
@@ -17618,7 +17736,7 @@
 va (VaSet
 )
-xt "64000,71000,69100,72000"
+xt "60000,71000,65100,72000"
 st "wiz_write_ea"
-blo "64000,71800"
+blo "60000,71800"
 tm "WireNameMgr"
 )
@@ -17634,12 +17752,8 @@
 lineWidth 2
 )
-xt "63750,72000,87250,79000"
-pts [
-"63750,73000"
-"67000,73000"
-"67000,79000"
-"85000,79000"
-"85000,72000"
-"87250,72000"
+xt "59750,73000,87250,73000"
+pts [
+"59750,73000"
+"87250,73000"
 ]
 )
@@ -17660,7 +17774,7 @@
 va (VaSet
 )
-xt "64000,72000,73400,73000"
+xt "60000,72000,69400,73000"
 st "wiz_write_length : (16:0)"
-blo "64000,72800"
+blo "60000,72800"
 tm "WireNameMgr"
 )
@@ -17676,10 +17790,8 @@
 lineWidth 2
 )
-xt "63750,73000,87250,74000"
-pts [
-"63750,74000"
-"84000,74000"
-"84000,73000"
-"87250,73000"
+xt "59750,74000,87250,74000"
+pts [
+"59750,74000"
+"87250,74000"
 ]
 )
@@ -17700,7 +17812,7 @@
 va (VaSet
 )
-xt "64000,73000,82800,74000"
+xt "60000,73000,78800,74000"
 st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
-blo "64000,73800"
+blo "60000,73800"
 tm "WireNameMgr"
 )
@@ -17716,12 +17828,8 @@
 lineWidth 2
 )
-xt "63750,74000,87250,80000"
-pts [
-"63750,75000"
-"66000,75000"
-"66000,80000"
-"86000,80000"
-"86000,74000"
-"87250,74000"
+xt "59750,75000,87250,75000"
+pts [
+"59750,75000"
+"87250,75000"
 ]
 )
@@ -17742,7 +17850,7 @@
 va (VaSet
 )
-xt "64000,74000,75800,75000"
+xt "60000,74000,71800,75000"
 st "wiz_number_of_channels : (3:0)"
-blo "64000,74800"
+blo "60000,74800"
 tm "WireNameMgr"
 )
@@ -17757,10 +17865,8 @@
 vasetType 3
 )
-xt "63750,75000,87250,76000"
-pts [
-"63750,76000"
-"84000,76000"
-"84000,75000"
-"87250,75000"
+xt "59750,76000,87250,76000"
+pts [
+"59750,76000"
+"87250,76000"
 ]
 )
@@ -17780,7 +17886,7 @@
 va (VaSet
 )
-xt "64000,75000,69500,76000"
+xt "60000,75000,65500,76000"
 st "wiz_write_end"
-blo "64000,75800"
+blo "60000,75800"
 tm "WireNameMgr"
 )
@@ -17795,10 +17901,8 @@
 vasetType 3
 )
-xt "63750,76000,87250,77000"
-pts [
-"63750,77000"
-"71000,77000"
-"71000,76000"
-"87250,76000"
+xt "59750,77000,87250,77000"
+pts [
+"59750,77000"
+"87250,77000"
 ]
 )
@@ -17818,7 +17922,7 @@
 va (VaSet
 )
-xt "64000,76000,70600,77000"
+xt "60000,76000,66600,77000"
 st "wiz_write_header"
-blo "64000,76800"
+blo "60000,76800"
 tm "WireNameMgr"
 )
@@ -17833,10 +17937,8 @@
 vasetType 3
 )
-xt "750,67000,31250,74000"
-pts [
-"750,67000"
-"26000,67000"
-"26000,74000"
-"31250,74000"
+xt "750,72000,27250,72000"
+pts [
+"750,72000"
+"27250,72000"
 ]
 )
@@ -17856,7 +17958,7 @@
 va (VaSet
 )
-xt "2000,66000,7300,67000"
+xt "1000,71000,6300,72000"
 st "ram_write_ea"
-blo "2000,66800"
+blo "1000,71800"
 tm "WireNameMgr"
 )
@@ -17871,10 +17973,8 @@
 vasetType 3
 )
-xt "750,68000,31250,75000"
-pts [
-"750,68000"
-"25000,68000"
-"25000,75000"
-"31250,75000"
+xt "750,73000,27250,73000"
+pts [
+"750,73000"
+"27250,73000"
 ]
 )
@@ -17894,7 +17994,7 @@
 va (VaSet
 )
-xt "2000,67000,8300,68000"
+xt "1000,72000,7300,73000"
 st "ram_write_ready"
-blo "2000,67800"
+blo "1000,72800"
 tm "WireNameMgr"
 )
@@ -17909,10 +18009,8 @@
 vasetType 3
 )
-xt "750,73000,31250,78000"
-pts [
-"750,73000"
-"23000,73000"
-"23000,78000"
-"31250,78000"
+xt "750,76000,27250,76000"
+pts [
+"750,76000"
+"27250,76000"
 ]
 )
@@ -17933,7 +18031,7 @@
 va (VaSet
 )
-xt "1000,72000,5800,73000"
+xt "1000,75000,5800,76000"
 st "config_start"
-blo "1000,72800"
+blo "1000,75800"
 tm "WireNameMgr"
 )
@@ -17948,10 +18046,8 @@
 vasetType 3
 )
-xt "750,75000,31250,80000"
-pts [
-"750,75000"
-"21000,75000"
-"21000,80000"
-"31250,80000"
+xt "750,78000,27250,78000"
+pts [
+"750,78000"
+"27250,78000"
 ]
 )
@@ -17971,7 +18067,7 @@
 va (VaSet
 )
-xt "1000,74000,6100,75000"
+xt "1000,77000,6100,78000"
 st "config_ready"
-blo "1000,74800"
+blo "1000,77800"
 tm "WireNameMgr"
 )
@@ -17986,10 +18082,8 @@
 vasetType 3
 )
-xt "750,77000,31250,81000"
-pts [
-"750,77000"
-"20000,77000"
-"20000,81000"
-"31250,81000"
+xt "750,79000,27250,79000"
+pts [
+"750,79000"
+"27250,79000"
 ]
 )
@@ -18009,7 +18103,7 @@
 va (VaSet
 )
-xt "1000,76000,4000,77000"
+xt "1000,78000,4000,79000"
 st "roi_max"
-blo "1000,76800"
+blo "1000,78800"
 tm "WireNameMgr"
 )
@@ -18025,10 +18119,8 @@
 lineWidth 2
 )
-xt "750,78000,31250,82000"
-pts [
-"750,78000"
-"19000,78000"
-"19000,82000"
-"31250,82000"
+xt "750,80000,27250,80000"
+pts [
+"750,80000"
+"27250,80000"
 ]
 )
@@ -18049,7 +18141,7 @@
 va (VaSet
 )
-xt "1000,77000,10100,78000"
+xt "1000,79000,10100,80000"
 st "package_length : (15:0)"
-blo "1000,77800"
+blo "1000,79800"
 tm "WireNameMgr"
 )
@@ -19238,8 +19330,10 @@
 vasetType 3
 )
-xt "18000,88000,31250,88000"
+xt "18000,86000,27250,88000"
 pts [
 "18000,88000"
-"31250,88000"
+"24000,88000"
+"24000,86000"
+"27250,86000"
 ]
 )
@@ -19259,7 +19353,7 @@
 va (VaSet
 )
-xt "28000,87000,31400,88000"
+xt "24000,85000,27400,86000"
 st "roi_array"
-blo "28000,87800"
+blo "24000,85800"
 tm "WireNameMgr"
 )
@@ -19531,16 +19625,4 @@
 optionalChildren [
 &651
-*672 (BdJunction
-uid 6086,0
-ps "OnConnectorStrategy"
-shape (Circle
-uid 6087,0
-va (VaSet
-vasetType 1
-)
-xt "27600,46600,28400,47400"
-radius 400
-)
-)
 ]
 shape (OrthoPolyLine
@@ -19584,5 +19666,5 @@
 on &188
 )
-*673 (Wire
+*672 (Wire
 uid 5626,0
 shape (OrthoPolyLine
@@ -19620,5 +19702,5 @@
 on &266
 )
-*674 (Wire
+*673 (Wire
 uid 5634,0
 shape (OrthoPolyLine
@@ -19658,5 +19740,5 @@
 on &265
 )
-*675 (Wire
+*674 (Wire
 uid 5646,0
 shape (OrthoPolyLine
@@ -19694,5 +19776,5 @@
 on &185
 )
-*676 (Wire
+*675 (Wire
 uid 5745,0
 shape (OrthoPolyLine
@@ -19732,5 +19814,5 @@
 on &276
 )
-*677 (Wire
+*676 (Wire
 uid 5805,0
 shape (OrthoPolyLine
@@ -19766,5 +19848,5 @@
 on &187
 )
-*678 (Wire
+*677 (Wire
 uid 5813,0
 shape (OrthoPolyLine
@@ -19804,5 +19886,5 @@
 on &293
 )
-*679 (Wire
+*678 (Wire
 uid 5821,0
 shape (OrthoPolyLine
@@ -19842,5 +19924,5 @@
 on &294
 )
-*680 (Wire
+*679 (Wire
 uid 5829,0
 shape (OrthoPolyLine
@@ -19880,5 +19962,5 @@
 on &295
 )
-*681 (Wire
+*680 (Wire
 uid 5837,0
 shape (OrthoPolyLine
@@ -19920,5 +20002,5 @@
 on &296
 )
-*682 (Wire
+*681 (Wire
 uid 5950,0
 shape (OrthoPolyLine
@@ -19958,5 +20040,5 @@
 on &301
 )
-*683 (Wire
+*682 (Wire
 uid 5962,0
 shape (OrthoPolyLine
@@ -19996,5 +20078,5 @@
 on &302
 )
-*684 (Wire
+*683 (Wire
 uid 6002,0
 shape (OrthoPolyLine
@@ -20034,5 +20116,5 @@
 on &304
 )
-*685 (Wire
+*684 (Wire
 uid 6008,0
 shape (OrthoPolyLine
@@ -20072,5 +20154,5 @@
 on &303
 )
-*686 (Wire
+*685 (Wire
 uid 6018,0
 shape (OrthoPolyLine
@@ -20079,10 +20161,8 @@
 vasetType 3
 )
-xt "750,74000,31250,79000"
-pts [
-"750,74000"
-"22000,74000"
-"22000,79000"
-"31250,79000"
+xt "750,77000,27250,77000"
+pts [
+"750,77000"
+"27250,77000"
 ]
 )
@@ -20102,7 +20182,7 @@
 va (VaSet
 )
-xt "1000,73000,8200,74000"
+xt "1000,76000,8200,77000"
 st "config_started_mm"
-blo "1000,73800"
+blo "1000,76800"
 tm "WireNameMgr"
 )
@@ -20110,5 +20190,5 @@
 on &305
 )
-*687 (Wire
+*686 (Wire
 uid 6064,0
 shape (OrthoPolyLine
@@ -20145,5 +20225,5 @@
 on &258
 )
-*688 (Wire
+*687 (Wire
 uid 6072,0
 shape (OrthoPolyLine
@@ -20184,44 +20264,5 @@
 on &188
 )
-*689 (Wire
-uid 6082,0
-shape (OrthoPolyLine
-uid 6083,0
-va (VaSet
-vasetType 3
-lineColor "0,32896,0"
-)
-xt "28000,47000,31250,71000"
-pts [
-"31250,71000"
-"28000,71000"
-"28000,47000"
-]
-)
-start &134
-end &672
-sat 32
-eat 32
-stc 0
-st 0
-sf 1
-si 0
-tg (WTG
-uid 6084,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 6085,0
-va (VaSet
-)
-xt "28000,70000,31100,71000"
-st "CLK_25"
-blo "28000,70800"
-tm "WireNameMgr"
-)
-)
-on &188
-)
-*690 (Wire
+*688 (Wire
 uid 6160,0
 shape (OrthoPolyLine
@@ -20261,5 +20302,5 @@
 on &306
 )
-*691 (Wire
+*689 (Wire
 uid 6276,0
 shape (OrthoPolyLine
@@ -20268,8 +20309,8 @@
 vasetType 3
 )
-xt "-61000,67000,-52750,67000"
-pts [
-"-61000,67000"
-"-52750,67000"
+xt "-61000,68000,-52750,68000"
+pts [
+"-61000,68000"
+"-52750,68000"
 ]
 )
@@ -20287,7 +20328,7 @@
 va (VaSet
 )
-xt "-58000,66000,-53500,67000"
+xt "-58000,67000,-53500,68000"
 st "CLK_25_PS"
-blo "-58000,66800"
+blo "-58000,67800"
 tm "WireNameMgr"
 )
@@ -20295,5 +20336,5 @@
 on &185
 )
-*692 (Wire
+*690 (Wire
 uid 6362,0
 shape (OrthoPolyLine
@@ -20308,5 +20349,5 @@
 ]
 )
-start &546
+start &545
 end &309
 ss 0
@@ -20334,5 +20375,5 @@
 on &308
 )
-*693 (Wire
+*691 (Wire
 uid 6452,0
 shape (OrthoPolyLine
@@ -20370,5 +20411,5 @@
 on &310
 )
-*694 (Wire
+*692 (Wire
 uid 6540,0
 shape (OrthoPolyLine
@@ -20384,5 +20425,5 @@
 )
 start &315
-end &477
+end &476
 sat 32
 eat 32
@@ -20407,5 +20448,5 @@
 on &329
 )
-*695 (Wire
+*693 (Wire
 uid 6548,0
 shape (OrthoPolyLine
@@ -20444,5 +20485,5 @@
 on &310
 )
-*696 (Wire
+*694 (Wire
 uid 8416,0
 shape (OrthoPolyLine
@@ -20451,10 +20492,8 @@
 vasetType 3
 )
-xt "63750,77000,87250,78000"
-pts [
-"63750,78000"
-"84000,78000"
-"84000,77000"
-"87250,77000"
+xt "59750,78000,87250,78000"
+pts [
+"59750,78000"
+"87250,78000"
 ]
 )
@@ -20474,7 +20513,7 @@
 va (VaSet
 )
-xt "64000,77000,67000,78000"
+xt "60000,77000,63000,78000"
 st "wiz_ack"
-blo "64000,77800"
+blo "60000,77800"
 tm "WireNameMgr"
 )
@@ -20482,5 +20521,5 @@
 on &341
 )
-*697 (Wire
+*695 (Wire
 uid 8732,0
 shape (OrthoPolyLine
@@ -20520,5 +20559,5 @@
 on &360
 )
-*698 (Wire
+*696 (Wire
 uid 8738,0
 shape (OrthoPolyLine
@@ -20556,5 +20595,5 @@
 on &361
 )
-*699 (Wire
+*697 (Wire
 uid 8752,0
 shape (OrthoPolyLine
@@ -20591,5 +20630,5 @@
 on &361
 )
-*700 (Wire
+*698 (Wire
 uid 9006,0
 shape (OrthoPolyLine
@@ -20629,5 +20668,5 @@
 on &362
 )
-*701 (Wire
+*699 (Wire
 uid 9233,0
 shape (OrthoPolyLine
@@ -20664,5 +20703,5 @@
 on &376
 )
-*702 (Wire
+*700 (Wire
 uid 9241,0
 shape (OrthoPolyLine
@@ -20699,5 +20738,5 @@
 on &377
 )
-*703 (Wire
+*701 (Wire
 uid 9253,0
 shape (OrthoPolyLine
@@ -20733,5 +20772,5 @@
 on &376
 )
-*704 (Wire
+*702 (Wire
 uid 9261,0
 shape (OrthoPolyLine
@@ -20767,5 +20806,5 @@
 on &377
 )
-*705 (Wire
+*703 (Wire
 uid 9943,0
 shape (OrthoPolyLine
@@ -20802,5 +20841,5 @@
 on &378
 )
-*706 (Wire
+*704 (Wire
 uid 9951,0
 shape (OrthoPolyLine
@@ -20837,5 +20876,5 @@
 on &379
 )
-*707 (Wire
+*705 (Wire
 uid 10010,0
 shape (OrthoPolyLine
@@ -20875,5 +20914,5 @@
 on &398
 )
-*708 (Wire
+*706 (Wire
 uid 10018,0
 shape (OrthoPolyLine
@@ -20911,5 +20950,5 @@
 on &379
 )
-*709 (Wire
+*707 (Wire
 uid 10036,0
 shape (OrthoPolyLine
@@ -20945,5 +20984,5 @@
 on &378
 )
-*710 (Wire
+*708 (Wire
 uid 10194,0
 shape (OrthoPolyLine
@@ -20985,5 +21024,5 @@
 on &399
 )
-*711 (Wire
+*709 (Wire
 uid 10202,0
 shape (OrthoPolyLine
@@ -21023,5 +21062,5 @@
 on &400
 )
-*712 (Wire
+*710 (Wire
 uid 10266,0
 shape (OrthoPolyLine
@@ -21056,7 +21095,7 @@
 )
 )
-on &499
-)
-*713 (Wire
+on &498
+)
+*711 (Wire
 uid 10298,0
 shape (OrthoPolyLine
@@ -21094,5 +21133,5 @@
 on &402
 )
-*714 (Wire
+*712 (Wire
 uid 10304,0
 shape (OrthoPolyLine
@@ -21130,5 +21169,5 @@
 on &403
 )
-*715 (Wire
+*713 (Wire
 uid 10310,0
 shape (OrthoPolyLine
@@ -21166,5 +21205,5 @@
 on &404
 )
-*716 (Wire
+*714 (Wire
 uid 10316,0
 shape (OrthoPolyLine
@@ -21204,5 +21243,5 @@
 on &405
 )
-*717 (Wire
+*715 (Wire
 uid 10322,0
 shape (OrthoPolyLine
@@ -21242,5 +21281,5 @@
 on &406
 )
-*718 (Wire
+*716 (Wire
 uid 10431,0
 shape (OrthoPolyLine
@@ -21279,57 +21318,5 @@
 on &401
 )
-*719 (Wire
-uid 10439,0
-optionalChildren [
-*720 (BdJunction
-uid 12639,0
-ps "OnConnectorStrategy"
-shape (Circle
-uid 12640,0
-va (VaSet
-vasetType 1
-)
-xt "-54400,71600,-53600,72400"
-radius 400
-)
-)
-]
-shape (OrthoPolyLine
-uid 10440,0
-va (VaSet
-vasetType 3
-)
-xt "-54000,68000,-21750,72000"
-pts [
-"-21750,72000"
-"-54000,72000"
-"-54000,68000"
-"-52750,68000"
-]
-)
-start &30
-end &125
-sat 32
-eat 32
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10441,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10442,0
-va (VaSet
-)
-xt "-25750,71000,-21150,72000"
-st "trigger_out"
-blo "-25750,71800"
-tm "WireNameMgr"
-)
-)
-on &431
-)
-*721 (Wire
+*717 (Wire
 uid 10467,0
 shape (OrthoPolyLine
@@ -21338,10 +21325,8 @@
 vasetType 3
 )
-xt "750,69000,31250,76000"
-pts [
-"31250,76000"
-"24000,76000"
-"24000,69000"
-"750,69000"
+xt "750,74000,27250,74000"
+pts [
+"27250,74000"
+"750,74000"
 ]
 )
@@ -21362,13 +21347,13 @@
 va (VaSet
 )
-xt "2000,68000,9800,69000"
+xt "1000,73000,8800,74000"
 st "ram_write_ready_ack"
-blo "2000,68800"
+blo "1000,73800"
 tm "WireNameMgr"
 )
 )
-on &432
-)
-*722 (Wire
+on &431
+)
+*718 (Wire
 uid 10629,0
 shape (OrthoPolyLine
@@ -21403,7 +21388,7 @@
 )
 )
-on &433
-)
-*723 (Wire
+on &432
+)
+*719 (Wire
 uid 10637,0
 shape (OrthoPolyLine
@@ -21438,7 +21423,7 @@
 )
 )
-on &434
-)
-*724 (Wire
+on &433
+)
+*720 (Wire
 uid 10685,0
 shape (OrthoPolyLine
@@ -21453,5 +21438,5 @@
 ]
 )
-end &447
+end &446
 sat 16
 eat 32
@@ -21473,7 +21458,7 @@
 )
 )
-on &434
-)
-*725 (Wire
+on &433
+)
+*721 (Wire
 uid 10691,0
 shape (OrthoPolyLine
@@ -21488,5 +21473,5 @@
 ]
 )
-end &448
+end &447
 sat 16
 eat 32
@@ -21508,7 +21493,7 @@
 )
 )
-on &433
-)
-*726 (Wire
+on &432
+)
+*722 (Wire
 uid 10699,0
 shape (OrthoPolyLine
@@ -21524,5 +21509,5 @@
 ]
 )
-end &442
+end &441
 sat 16
 eat 32
@@ -21546,5 +21531,5 @@
 on &187
 )
-*727 (Wire
+*723 (Wire
 uid 10707,0
 shape (OrthoPolyLine
@@ -21559,5 +21544,5 @@
 ]
 )
-end &446
+end &445
 sat 16
 eat 32
@@ -21579,7 +21564,7 @@
 )
 )
-on &453
-)
-*728 (Wire
+on &452
+)
+*724 (Wire
 uid 10723,0
 shape (OrthoPolyLine
@@ -21594,6 +21579,6 @@
 ]
 )
-start &443
-end &436
+start &442
+end &435
 sat 32
 eat 32
@@ -21617,7 +21602,7 @@
 )
 )
-on &435
-)
-*729 (Wire
+on &434
+)
+*725 (Wire
 uid 10737,0
 shape (OrthoPolyLine
@@ -21632,6 +21617,6 @@
 ]
 )
-start &444
-end &438
+start &443
+end &437
 sat 32
 eat 32
@@ -21655,7 +21640,7 @@
 )
 )
-on &437
-)
-*730 (Wire
+on &436
+)
+*726 (Wire
 uid 10751,0
 shape (OrthoPolyLine
@@ -21670,6 +21655,6 @@
 ]
 )
-start &445
-end &440
+start &444
+end &439
 sat 32
 eat 32
@@ -21693,7 +21678,7 @@
 )
 )
-on &439
-)
-*731 (Wire
+on &438
+)
+*727 (Wire
 uid 11405,0
 shape (OrthoPolyLine
@@ -21729,7 +21714,7 @@
 )
 )
-on &453
-)
-*732 (Wire
+on &452
+)
+*728 (Wire
 uid 11858,0
 shape (OrthoPolyLine
@@ -21764,7 +21749,7 @@
 )
 )
-on &454
-)
-*733 (Wire
+on &453
+)
+*729 (Wire
 uid 11952,0
 shape (OrthoPolyLine
@@ -21779,5 +21764,5 @@
 ]
 )
-end &461
+end &460
 sat 16
 eat 32
@@ -21800,7 +21785,7 @@
 )
 )
-on &454
-)
-*734 (Wire
+on &453
+)
+*730 (Wire
 uid 12306,0
 shape (OrthoPolyLine
@@ -21816,5 +21801,5 @@
 )
 start &411
-end &459
+end &458
 sat 32
 eat 32
@@ -21838,44 +21823,7 @@
 )
 )
-on &473
-)
-*735 (Wire
-uid 12635,0
-shape (OrthoPolyLine
-uid 12636,0
-va (VaSet
-vasetType 3
-)
-xt "-55250,72000,-54000,72000"
-pts [
-"-54000,72000"
-"-55250,72000"
-]
-)
-start &720
-end &476
-sat 32
-eat 32
-stc 0
-st 0
-sf 1
-si 0
-tg (WTG
-uid 12637,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 12638,0
-va (VaSet
-)
-xt "-54000,71000,-49400,72000"
-st "trigger_out"
-blo "-54000,71800"
-tm "WireNameMgr"
-)
-)
-on &431
-)
-*736 (Wire
+on &472
+)
+*731 (Wire
 uid 12643,0
 shape (OrthoPolyLine
@@ -21892,6 +21840,6 @@
 ]
 )
-start &456
-end &475
+start &455
+end &474
 sat 32
 eat 32
@@ -21915,7 +21863,7 @@
 )
 )
-on &484
-)
-*737 (Wire
+on &483
+)
+*732 (Wire
 uid 12649,0
 shape (OrthoPolyLine
@@ -21927,10 +21875,9 @@
 pts [
 "-21750,74000"
-"-38000,74000"
 "-55250,74000"
 ]
 )
 start &66
-end &478
+end &477
 sat 32
 eat 32
@@ -21952,7 +21899,7 @@
 )
 )
-on &485
-)
-*738 (Wire
+on &484
+)
+*733 (Wire
 uid 12655,0
 shape (OrthoPolyLine
@@ -21969,5 +21916,5 @@
 )
 start &67
-end &479
+end &478
 sat 32
 eat 32
@@ -21989,7 +21936,7 @@
 )
 )
-on &486
-)
-*739 (Wire
+on &485
+)
+*734 (Wire
 uid 12687,0
 shape (OrthoPolyLine
@@ -22007,5 +21954,5 @@
 ]
 )
-end &480
+end &479
 sat 16
 eat 32
@@ -22029,5 +21976,5 @@
 on &188
 )
-*740 (Wire
+*735 (Wire
 uid 12707,0
 shape (OrthoPolyLine
@@ -22042,6 +21989,6 @@
 ]
 )
-start &449
-end &488
+start &448
+end &487
 sat 32
 eat 32
@@ -22065,7 +22012,7 @@
 )
 )
-on &487
-)
-*741 (Wire
+on &486
+)
+*736 (Wire
 uid 13143,0
 shape (OrthoPolyLine
@@ -22074,11 +22021,11 @@
 vasetType 3
 )
-xt "63750,62000,69000,62000"
-pts [
-"69000,62000"
-"63750,62000"
-]
-)
-end &490
+xt "72750,62000,78000,62000"
+pts [
+"78000,62000"
+"72750,62000"
+]
+)
+end &489
 sat 16
 eat 32
@@ -22094,7 +22041,7 @@
 va (VaSet
 )
-xt "65000,61000,68100,62000"
+xt "74000,61000,77100,62000"
 st "CLK_25"
-blo "65000,61800"
+blo "74000,61800"
 tm "WireNameMgr"
 )
@@ -22102,5 +22049,5 @@
 on &188
 )
-*742 (Wire
+*737 (Wire
 uid 13159,0
 shape (OrthoPolyLine
@@ -22109,14 +22056,14 @@
 vasetType 3
 )
-xt "63750,63000,87250,67000"
+xt "72750,63000,87250,67000"
 pts [
 "87250,67000"
-"79000,67000"
-"79000,63000"
-"63750,63000"
+"77000,67000"
+"77000,63000"
+"72750,63000"
 ]
 )
 start &114
-end &491
+end &490
 sat 32
 eat 32
@@ -22138,7 +22085,7 @@
 )
 )
-on &497
-)
-*743 (Wire
+on &496
+)
+*738 (Wire
 uid 13165,0
 shape (OrthoPolyLine
@@ -22148,14 +22095,14 @@
 lineWidth 2
 )
-xt "63750,64000,87250,68000"
+xt "72750,64000,87250,68000"
 pts [
 "87250,68000"
-"78000,68000"
-"78000,64000"
-"63750,64000"
+"76000,68000"
+"76000,64000"
+"72750,64000"
 ]
 )
 start &115
-end &492
+end &491
 sat 32
 eat 32
@@ -22178,7 +22125,7 @@
 )
 )
-on &498
-)
-*744 (Wire
+on &497
+)
+*739 (Wire
 uid 13210,0
 shape (OrthoPolyLine
@@ -22187,12 +22134,12 @@
 vasetType 3
 )
-xt "42000,62000,50250,62000"
-pts [
-"50250,62000"
-"42000,62000"
-]
-)
-start &493
-end &502
+xt "54000,62000,59250,62000"
+pts [
+"59250,62000"
+"54000,62000"
+]
+)
+start &492
+end &501
 sat 32
 eat 32
@@ -22208,13 +22155,13 @@
 va (VaSet
 )
-xt "46250,61000,49450,62000"
+xt "53250,61000,56450,62000"
 st "trigger1"
-blo "46250,61800"
+blo "53250,61800"
 tm "WireNameMgr"
 )
 )
-on &500
-)
-*745 (Wire
+on &499
+)
+*740 (Wire
 uid 13216,0
 shape (OrthoPolyLine
@@ -22223,11 +22170,11 @@
 vasetType 3
 )
-xt "42000,60000,45000,60000"
-pts [
-"45000,60000"
-"42000,60000"
-]
-)
-end &507
+xt "54000,60000,59000,60000"
+pts [
+"59000,60000"
+"54000,60000"
+]
+)
+end &506
 sat 16
 eat 32
@@ -22243,15 +22190,14 @@
 uid 13221,0
 va (VaSet
-isHidden 1
-)
-xt "43000,59000,47800,60000"
+)
+xt "54000,59000,58800,60000"
 st "s_trigger_0"
-blo "43000,59800"
+blo "54000,59800"
 tm "WireNameMgr"
 )
 )
-on &499
-)
-*746 (Wire
+on &498
+)
+*741 (Wire
 uid 13224,0
 shape (OrthoPolyLine
@@ -22260,11 +22206,11 @@
 vasetType 3
 )
-xt "33000,61000,36000,61000"
-pts [
-"36000,61000"
-"33000,61000"
-]
-)
-start &504
+xt "45000,61000,48000,61000"
+pts [
+"48000,61000"
+"45000,61000"
+]
+)
+start &503
 sat 32
 eat 16
@@ -22280,9 +22226,8 @@
 uid 13229,0
 va (VaSet
-isHidden 1
-)
-xt "34000,60000,37600,61000"
+)
+xt "45000,60000,48600,61000"
 st "s_trigger"
-blo "34000,60800"
+blo "45000,60800"
 tm "WireNameMgr"
 )
@@ -22290,5 +22235,5 @@
 on &401
 )
-*747 (Wire
+*742 (Wire
 uid 13695,0
 shape (OrthoPolyLine
@@ -22304,5 +22249,5 @@
 ]
 )
-start &524
+start &523
 end &116
 sat 32
@@ -22327,7 +22272,7 @@
 )
 )
-on &525
-)
-*748 (Wire
+on &524
+)
+*743 (Wire
 uid 13921,0
 shape (OrthoPolyLine
@@ -22366,5 +22311,5 @@
 on &71
 )
-*749 (Wire
+*744 (Wire
 uid 13929,0
 shape (OrthoPolyLine
@@ -22403,5 +22348,5 @@
 on &122
 )
-*750 (Wire
+*745 (Wire
 uid 14048,0
 shape (OrthoPolyLine
@@ -22416,6 +22361,6 @@
 ]
 )
-start &526
-end &532
+start &525
+end &531
 sat 32
 eat 32
@@ -22438,7 +22383,7 @@
 )
 )
-on &527
-)
-*751 (Wire
+on &526
+)
+*746 (Wire
 uid 14171,0
 shape (OrthoPolyLine
@@ -22454,5 +22399,5 @@
 ]
 )
-start &528
+start &527
 sat 32
 eat 16
@@ -22476,7 +22421,7 @@
 )
 )
-on &529
-)
-*752 (Wire
+on &528
+)
+*747 (Wire
 uid 14427,0
 shape (OrthoPolyLine
@@ -22491,5 +22436,5 @@
 ]
 )
-end &531
+end &530
 sat 16
 eat 32
@@ -22513,5 +22458,5 @@
 on &187
 )
-*753 (Wire
+*748 (Wire
 uid 14479,0
 shape (OrthoPolyLine
@@ -22526,6 +22471,6 @@
 ]
 )
-start &534
-end &540
+start &533
+end &539
 sat 32
 eat 32
@@ -22549,7 +22494,7 @@
 )
 )
-on &539
-)
-*754 (Wire
+on &538
+)
+*749 (Wire
 uid 14493,0
 shape (OrthoPolyLine
@@ -22564,6 +22509,6 @@
 ]
 )
-start &535
-end &542
+start &534
+end &541
 sat 32
 eat 32
@@ -22587,7 +22532,7 @@
 )
 )
-on &541
-)
-*755 (Wire
+on &540
+)
+*750 (Wire
 uid 14622,0
 shape (OrthoPolyLine
@@ -22603,6 +22548,6 @@
 ]
 )
-start &533
-end &544
+start &532
+end &543
 sat 32
 eat 32
@@ -22627,7 +22572,7 @@
 )
 )
-on &543
-)
-*756 (Wire
+on &542
+)
+*751 (Wire
 uid 15071,0
 shape (OrthoPolyLine
@@ -22643,5 +22588,5 @@
 )
 start &101
-end &549
+end &548
 sat 32
 eat 32
@@ -22663,7 +22608,7 @@
 )
 )
-on &596
-)
-*757 (Wire
+on &595
+)
+*752 (Wire
 uid 15081,0
 shape (OrthoPolyLine
@@ -22678,6 +22623,6 @@
 ]
 )
-start &551
-end &589
+start &550
+end &588
 sat 32
 eat 32
@@ -22701,7 +22646,7 @@
 )
 )
-on &597
-)
-*758 (Wire
+on &596
+)
+*753 (Wire
 uid 15122,0
 shape (OrthoPolyLine
@@ -22717,6 +22662,6 @@
 ]
 )
-start &587
-end &564
+start &586
+end &563
 sat 32
 eat 32
@@ -22739,7 +22684,7 @@
 )
 )
-on &598
-)
-*759 (Wire
+on &597
+)
+*754 (Wire
 uid 15130,0
 shape (OrthoPolyLine
@@ -22754,5 +22699,5 @@
 ]
 )
-end &579
+end &578
 es 0
 sat 16
@@ -22777,7 +22722,7 @@
 )
 )
-on &541
-)
-*760 (Wire
+on &540
+)
+*755 (Wire
 uid 15138,0
 shape (OrthoPolyLine
@@ -22792,5 +22737,5 @@
 ]
 )
-end &581
+end &580
 es 0
 sat 16
@@ -22815,5 +22760,128 @@
 )
 )
-on &539
+on &538
+)
+*756 (Wire
+uid 15379,0
+shape (OrthoPolyLine
+uid 15380,0
+va (VaSet
+vasetType 3
+)
+xt "29000,64000,29000,67250"
+pts [
+"29000,64000"
+"29000,67250"
+]
+)
+end &134
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 15383,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 15384,0
+va (VaSet
+)
+xt "29000,64000,32100,65000"
+st "CLK_25"
+blo "29000,64800"
+tm "WireNameMgr"
+)
+)
+on &188
+)
+*757 (Wire
+uid 15494,0
+optionalChildren [
+*758 (BdJunction
+uid 15502,0
+ps "OnConnectorStrategy"
+shape (Circle
+uid 15503,0
+va (VaSet
+vasetType 1
+)
+xt "-54400,71600,-53600,72400"
+radius 400
+)
+)
+]
+shape (OrthoPolyLine
+uid 15495,0
+va (VaSet
+vasetType 3
+)
+xt "-55250,72000,-21750,72000"
+pts [
+"-55250,72000"
+"-21750,72000"
+]
+)
+start &475
+end &30
+sat 32
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 15496,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 15497,0
+va (VaSet
+)
+xt "-53250,71000,-48650,72000"
+st "trigger_out"
+blo "-53250,71800"
+tm "WireNameMgr"
+)
+)
+on &598
+)
+*759 (Wire
+uid 15498,0
+shape (OrthoPolyLine
+uid 15499,0
+va (VaSet
+vasetType 3
+)
+xt "-54000,69000,-52750,72000"
+pts [
+"-52750,69000"
+"-54000,69000"
+"-54000,72000"
+]
+)
+start &125
+end &758
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 15500,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 15501,0
+va (VaSet
+)
+xt "-58000,69000,-53400,70000"
+st "trigger_out"
+blo "-58000,69800"
+tm "WireNameMgr"
+)
+)
+on &598
 )
 ]
@@ -22829,9 +22897,9 @@
 color "26368,26368,26368"
 )
-packageList *761 (PackageList
+packageList *760 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*762 (Text
+*761 (Text
 uid 42,0
 va (VaSet
@@ -22842,5 +22910,5 @@
 blo "-163000,-15200"
 )
-*763 (MLText
+*762 (MLText
 uid 43,0
 va (VaSet
@@ -22867,5 +22935,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*764 (Text
+*763 (Text
 uid 45,0
 va (VaSet
@@ -22877,5 +22945,5 @@
 blo "20000,800"
 )
-*765 (Text
+*764 (Text
 uid 46,0
 va (VaSet
@@ -22887,5 +22955,5 @@
 blo "20000,1800"
 )
-*766 (MLText
+*765 (MLText
 uid 47,0
 va (VaSet
@@ -22897,5 +22965,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*767 (Text
+*766 (Text
 uid 48,0
 va (VaSet
@@ -22907,5 +22975,5 @@
 blo "20000,4800"
 )
-*768 (MLText
+*767 (MLText
 uid 49,0
 va (VaSet
@@ -22915,5 +22983,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*769 (Text
+*768 (Text
 uid 50,0
 va (VaSet
@@ -22925,5 +22993,5 @@
 blo "20000,5800"
 )
-*770 (MLText
+*769 (MLText
 uid 51,0
 va (VaSet
@@ -22937,5 +23005,5 @@
 )
 windowSize "0,0,1281,1024"
-viewArea "-25598,42048,41245,97173"
+viewArea "-65700,47500,1143,102625"
 cachedDiagramExtent "-174000,-25425,428157,346294"
 pageSetupInfo (PageSetupInfo
@@ -22963,5 +23031,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
-lastUid 15275,0
+lastUid 15505,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -23025,5 +23093,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*771 (Text
+*770 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23034,5 +23102,5 @@
 tm "BdLibraryNameMgr"
 )
-*772 (Text
+*771 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23043,5 +23111,5 @@
 tm "BlkNameMgr"
 )
-*773 (Text
+*772 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23094,5 +23162,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*774 (Text
+*773 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23102,5 +23170,5 @@
 blo "550,4300"
 )
-*775 (Text
+*774 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23110,5 +23178,5 @@
 blo "550,5300"
 )
-*776 (Text
+*775 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23159,5 +23227,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*777 (Text
+*776 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23168,5 +23236,5 @@
 tm "BdLibraryNameMgr"
 )
-*778 (Text
+*777 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23177,5 +23245,5 @@
 tm "CptNameMgr"
 )
-*779 (Text
+*778 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23231,5 +23299,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*780 (Text
+*779 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23239,5 +23307,5 @@
 blo "500,4300"
 )
-*781 (Text
+*780 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23247,5 +23315,5 @@
 blo "500,5300"
 )
-*782 (Text
+*781 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23292,5 +23360,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*783 (Text
+*782 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23300,5 +23368,5 @@
 blo "50,4300"
 )
-*784 (Text
+*783 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23308,5 +23376,5 @@
 blo "50,5300"
 )
-*785 (Text
+*784 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23349,5 +23417,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*786 (Text
+*785 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23358,5 +23426,5 @@
 tm "HdlTextNameMgr"
 )
-*787 (Text
+*786 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23761,5 +23829,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*788 (Text
+*787 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23769,5 +23837,5 @@
 blo "14100,20800"
 )
-*789 (MLText
+*788 (MLText
 va (VaSet
 )
@@ -23821,5 +23889,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*790 (Text
+*789 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23829,5 +23897,5 @@
 blo "14100,20800"
 )
-*791 (MLText
+*790 (MLText
 va (VaSet
 )
@@ -23969,44 +24037,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 299,0
+suid 301,0
 usingSuid 1
-emptyRow *792 (LEmptyRow
+emptyRow *791 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*793 (RefLabelRowHdr
-)
-*794 (TitleRowHdr
-)
-*795 (FilterRowHdr
-)
-*796 (RefLabelColHdr
+*792 (RefLabelRowHdr
+)
+*793 (TitleRowHdr
+)
+*794 (FilterRowHdr
+)
+*795 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*797 (RowExpandColHdr
+*796 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*798 (GroupColHdr
+*797 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*799 (NameColHdr
+*798 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*800 (ModeColHdr
+*799 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*801 (TypeColHdr
+*800 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*802 (BoundsColHdr
+*801 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*803 (InitColHdr
+*802 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*804 (EolColHdr
+*803 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*805 (LeafLogPort
+*804 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24022,5 +24090,5 @@
 uid 516,0
 )
-*806 (LeafLogPort
+*805 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24035,5 +24103,5 @@
 uid 518,0
 )
-*807 (LeafLogPort
+*806 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24048,5 +24116,5 @@
 uid 520,0
 )
-*808 (LeafLogPort
+*807 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24061,5 +24129,5 @@
 uid 530,0
 )
-*809 (LeafLogPort
+*808 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24074,5 +24142,5 @@
 uid 532,0
 )
-*810 (LeafLogPort
+*809 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24087,5 +24155,5 @@
 uid 534,0
 )
-*811 (LeafLogPort
+*810 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24100,5 +24168,5 @@
 uid 536,0
 )
-*812 (LeafLogPort
+*811 (LeafLogPort
 port (LogicalPort
 m 2
@@ -24113,16 +24181,29 @@
 uid 538,0
 )
+*812 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "wiz_cs"
+t "std_logic"
+o 44
+suid 14,0
+i "'1'"
+)
+)
+uid 540,0
+)
 *813 (LeafLogPort
 port (LogicalPort
 m 1
 decl (Decl
-n "wiz_cs"
-t "std_logic"
-o 44
-suid 14,0
+n "wiz_wr"
+t "std_logic"
+o 47
+suid 15,0
 i "'1'"
 )
 )
-uid 540,0
+uid 542,0
 )
 *814 (LeafLogPort
@@ -24130,17 +24211,4 @@
 m 1
 decl (Decl
-n "wiz_wr"
-t "std_logic"
-o 47
-suid 15,0
-i "'1'"
-)
-)
-uid 542,0
-)
-*815 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
 n "wiz_rd"
 t "std_logic"
@@ -24152,5 +24220,5 @@
 uid 546,0
 )
-*816 (LeafLogPort
+*815 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24163,5 +24231,5 @@
 uid 548,0
 )
-*817 (LeafLogPort
+*816 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24175,5 +24243,5 @@
 uid 1455,0
 )
-*818 (LeafLogPort
+*817 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24188,5 +24256,5 @@
 uid 1457,0
 )
-*819 (LeafLogPort
+*818 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24200,5 +24268,5 @@
 uid 1694,0
 )
-*820 (LeafLogPort
+*819 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24216,5 +24284,5 @@
 uid 1993,0
 )
-*821 (LeafLogPort
+*820 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24231,4 +24299,17 @@
 uid 2305,0
 )
+*821 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "wiz_busy"
+t "std_logic"
+o 122
+suid 38,0
+)
+)
+uid 2510,0
+)
 *822 (LeafLogPort
 port (LogicalPort
@@ -24236,17 +24317,4 @@
 m 4
 decl (Decl
-n "wiz_busy"
-t "std_logic"
-o 122
-suid 38,0
-)
-)
-uid 2510,0
-)
-*823 (LeafLogPort
-port (LogicalPort
-lang 2
-m 4
-decl (Decl
 n "wiz_write_ea"
 t "std_logic"
@@ -24258,5 +24326,5 @@
 uid 2512,0
 )
-*824 (LeafLogPort
+*823 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24273,5 +24341,5 @@
 uid 2514,0
 )
-*825 (LeafLogPort
+*824 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24289,5 +24357,5 @@
 uid 2516,0
 )
-*826 (LeafLogPort
+*825 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24304,4 +24372,18 @@
 uid 2518,0
 )
+*826 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "wiz_write_end"
+t "std_logic"
+o 126
+suid 43,0
+i "'0'"
+)
+)
+uid 2520,0
+)
 *827 (LeafLogPort
 port (LogicalPort
@@ -24309,18 +24391,4 @@
 m 4
 decl (Decl
-n "wiz_write_end"
-t "std_logic"
-o 126
-suid 43,0
-i "'0'"
-)
-)
-uid 2520,0
-)
-*828 (LeafLogPort
-port (LogicalPort
-lang 2
-m 4
-decl (Decl
 n "wiz_write_header"
 t "std_logic"
@@ -24332,15 +24400,28 @@
 uid 2522,0
 )
+*828 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ram_write_ea"
+t "std_logic"
+o 100
+suid 48,0
+)
+)
+uid 2604,0
+)
 *829 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "ram_write_ea"
-t "std_logic"
-o 100
-suid 48,0
-)
-)
-uid 2604,0
+n "ram_write_ready"
+t "std_logic"
+o 101
+suid 49,0
+i "'0'"
+)
+)
+uid 2606,0
 )
 *830 (LeafLogPort
@@ -24348,12 +24429,12 @@
 m 4
 decl (Decl
-n "ram_write_ready"
-t "std_logic"
-o 101
-suid 49,0
+n "config_start"
+t "std_logic"
+o 67
+suid 50,0
 i "'0'"
 )
 )
-uid 2606,0
+uid 2608,0
 )
 *831 (LeafLogPort
@@ -24361,17 +24442,4 @@
 m 4
 decl (Decl
-n "config_start"
-t "std_logic"
-o 67
-suid 50,0
-i "'0'"
-)
-)
-uid 2608,0
-)
-*832 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "config_ready"
 t "std_logic"
@@ -24382,5 +24450,5 @@
 uid 2610,0
 )
-*833 (LeafLogPort
+*832 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24394,5 +24462,5 @@
 uid 2612,0
 )
-*834 (LeafLogPort
+*833 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24407,5 +24475,5 @@
 uid 2646,0
 )
-*835 (LeafLogPort
+*834 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24420,5 +24488,5 @@
 uid 2812,0
 )
-*836 (LeafLogPort
+*835 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24432,42 +24500,42 @@
 uid 2962,0
 )
+*836 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "CLK_25_PS"
+t "std_logic"
+o 15
+suid 81,0
+)
+)
+uid 3902,0
+)
 *837 (LeafLogPort
 port (LogicalPort
 m 1
 decl (Decl
-n "CLK_25_PS"
-t "std_logic"
-o 15
-suid 81,0
-)
-)
-uid 3902,0
+n "CLK_50"
+t "std_logic"
+o 16
+suid 90,0
+)
+)
+uid 4070,0
 )
 *838 (LeafLogPort
 port (LogicalPort
-m 1
-decl (Decl
-n "CLK_50"
-t "std_logic"
-o 16
-suid 90,0
-)
-)
-uid 4070,0
+m 4
+decl (Decl
+n "CLK_25"
+t "std_logic"
+o 50
+suid 91,0
+)
+)
+uid 4212,0
 )
 *839 (LeafLogPort
 port (LogicalPort
-m 4
-decl (Decl
-n "CLK_25"
-t "std_logic"
-o 50
-suid 91,0
-)
-)
-uid 4212,0
-)
-*840 (LeafLogPort
-port (LogicalPort
 decl (Decl
 n "CLK"
@@ -24479,5 +24547,5 @@
 uid 4234,0
 )
-*841 (LeafLogPort
+*840 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24491,5 +24559,5 @@
 uid 4262,0
 )
-*842 (LeafLogPort
+*841 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24502,5 +24570,5 @@
 uid 4276,0
 )
-*843 (LeafLogPort
+*842 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24515,5 +24583,5 @@
 uid 4563,0
 )
-*844 (LeafLogPort
+*843 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24527,5 +24595,5 @@
 uid 4565,0
 )
-*845 (LeafLogPort
+*844 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24540,5 +24608,5 @@
 uid 4569,0
 )
-*846 (LeafLogPort
+*845 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24554,5 +24622,5 @@
 uid 4585,0
 )
-*847 (LeafLogPort
+*846 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24567,59 +24635,72 @@
 uid 4587,0
 )
+*847 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "SROUT_in_0"
+t "std_logic"
+o 2
+suid 112,0
+)
+)
+uid 4733,0
+)
 *848 (LeafLogPort
 port (LogicalPort
 decl (Decl
-n "SROUT_in_0"
-t "std_logic"
-o 2
-suid 112,0
-)
-)
-uid 4733,0
+n "SROUT_in_1"
+t "std_logic"
+o 3
+suid 113,0
+)
+)
+uid 4735,0
 )
 *849 (LeafLogPort
 port (LogicalPort
 decl (Decl
-n "SROUT_in_1"
-t "std_logic"
-o 3
-suid 113,0
-)
-)
-uid 4735,0
+n "SROUT_in_2"
+t "std_logic"
+o 4
+suid 114,0
+)
+)
+uid 4737,0
 )
 *850 (LeafLogPort
 port (LogicalPort
 decl (Decl
-n "SROUT_in_2"
-t "std_logic"
-o 4
-suid 114,0
-)
-)
-uid 4737,0
+n "SROUT_in_3"
+t "std_logic"
+o 5
+suid 115,0
+)
+)
+uid 4739,0
 )
 *851 (LeafLogPort
 port (LogicalPort
-decl (Decl
-n "SROUT_in_3"
-t "std_logic"
-o 5
-suid 115,0
-)
-)
-uid 4739,0
+m 4
+decl (Decl
+n "drs_read_s_cell_ready"
+t "std_logic"
+o 84
+suid 116,0
+)
+)
+uid 4749,0
 )
 *852 (LeafLogPort
 port (LogicalPort
-m 4
-decl (Decl
-n "drs_read_s_cell_ready"
-t "std_logic"
-o 84
-suid 116,0
-)
-)
-uid 4749,0
+m 1
+decl (Decl
+n "RSRLOAD"
+t "std_logic"
+o 23
+suid 117,0
+i "'0'"
+)
+)
+uid 4974,0
 )
 *853 (LeafLogPort
@@ -24627,17 +24708,4 @@
 m 1
 decl (Decl
-n "RSRLOAD"
-t "std_logic"
-o 23
-suid 117,0
-i "'0'"
-)
-)
-uid 4974,0
-)
-*854 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
 n "SRCLK"
 t "std_logic"
@@ -24649,5 +24717,5 @@
 uid 4976,0
 )
-*855 (LeafLogPort
+*854 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24662,20 +24730,20 @@
 uid 5198,0
 )
+*855 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "config_data_valid"
+t "std_logic"
+o 60
+suid 120,0
+)
+)
+uid 5200,0
+)
 *856 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "config_data_valid"
-t "std_logic"
-o 60
-suid 120,0
-)
-)
-uid 5200,0
-)
-*857 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "config_busy"
 t "std_logic"
@@ -24686,5 +24754,5 @@
 uid 5202,0
 )
-*858 (LeafLogPort
+*857 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24699,20 +24767,20 @@
 uid 5204,0
 )
+*858 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "config_wr_en"
+t "std_logic"
+o 74
+suid 123,0
+)
+)
+uid 5206,0
+)
 *859 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "config_wr_en"
-t "std_logic"
-o 74
-suid 123,0
-)
-)
-uid 5206,0
-)
-*860 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "config_rd_en"
 t "std_logic"
@@ -24723,5 +24791,5 @@
 uid 5208,0
 )
-*861 (LeafLogPort
+*860 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24735,20 +24803,20 @@
 uid 5210,0
 )
+*861 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "config_start_cm"
+t "std_logic"
+o 68
+suid 131,0
+)
+)
+uid 5212,0
+)
 *862 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "config_start_cm"
-t "std_logic"
-o 68
-suid 131,0
-)
-)
-uid 5212,0
-)
-*863 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "config_ready_cm"
 t "std_logic"
@@ -24759,5 +24827,5 @@
 uid 5214,0
 )
-*864 (LeafLogPort
+*863 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24774,5 +24842,5 @@
 uid 5226,0
 )
-*865 (LeafLogPort
+*864 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24786,5 +24854,5 @@
 uid 5502,0
 )
-*866 (LeafLogPort
+*865 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24798,5 +24866,5 @@
 uid 5504,0
 )
-*867 (LeafLogPort
+*866 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24810,5 +24878,5 @@
 uid 5600,0
 )
-*868 (LeafLogPort
+*867 (LeafLogPort
 port (LogicalPort
 lang 10
@@ -24824,5 +24892,5 @@
 uid 5642,0
 )
-*869 (LeafLogPort
+*868 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24836,5 +24904,5 @@
 uid 5644,0
 )
-*870 (LeafLogPort
+*869 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24849,5 +24917,5 @@
 uid 5751,0
 )
-*871 (LeafLogPort
+*870 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24861,5 +24929,5 @@
 uid 5867,0
 )
-*872 (LeafLogPort
+*871 (LeafLogPort
 port (LogicalPort
 m 2
@@ -24875,5 +24943,5 @@
 uid 5869,0
 )
-*873 (LeafLogPort
+*872 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24887,5 +24955,5 @@
 uid 5871,0
 )
-*874 (LeafLogPort
+*873 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24900,16 +24968,28 @@
 uid 5873,0
 )
+*874 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "new_config"
+t "std_logic"
+o 92
+suid 155,0
+i "'0'"
+)
+)
+uid 5966,0
+)
 *875 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "new_config"
-t "std_logic"
-o 92
-suid 155,0
-i "'0'"
-)
-)
-uid 5966,0
+n "config_started"
+t "std_logic"
+o 70
+suid 156,0
+)
+)
+uid 5968,0
 )
 *876 (LeafLogPort
@@ -24917,11 +24997,12 @@
 m 4
 decl (Decl
-n "config_started"
-t "std_logic"
-o 70
-suid 156,0
-)
-)
-uid 5968,0
+n "config_started_spi"
+t "std_logic"
+o 73
+suid 159,0
+i "'0'"
+)
+)
+uid 6022,0
 )
 *877 (LeafLogPort
@@ -24929,12 +25010,12 @@
 m 4
 decl (Decl
-n "config_started_spi"
-t "std_logic"
-o 73
-suid 159,0
+n "config_started_cu"
+t "std_logic"
+o 71
+suid 160,0
 i "'0'"
 )
 )
-uid 6022,0
+uid 6024,0
 )
 *878 (LeafLogPort
@@ -24942,17 +25023,4 @@
 m 4
 decl (Decl
-n "config_started_cu"
-t "std_logic"
-o 71
-suid 160,0
-i "'0'"
-)
-)
-uid 6024,0
-)
-*879 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "config_started_mm"
 t "std_logic"
@@ -24963,5 +25031,5 @@
 uid 6026,0
 )
-*880 (LeafLogPort
+*879 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24976,5 +25044,5 @@
 uid 6172,0
 )
-*881 (LeafLogPort
+*880 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24991,21 +25059,21 @@
 uid 6374,0
 )
+*881 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "dwrite_enable"
+t "std_logic"
+o 91
+suid 167,0
+i "'1'"
+)
+)
+uid 6464,0
+)
 *882 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "dwrite_enable"
-t "std_logic"
-o 91
-suid 167,0
-i "'1'"
-)
-)
-uid 6464,0
-)
-*883 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "dwrite"
 t "std_logic"
@@ -25017,5 +25085,5 @@
 uid 6554,0
 )
-*884 (LeafLogPort
+*883 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -25030,20 +25098,20 @@
 uid 8420,0
 )
+*884 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "sclk1"
+t "std_logic"
+o 107
+suid 191,0
+)
+)
+uid 8758,0
+)
 *885 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "sclk1"
-t "std_logic"
-o 107
-suid 191,0
-)
-)
-uid 8758,0
-)
-*886 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "sclk_enable"
 t "std_logic"
@@ -25054,5 +25122,5 @@
 uid 8760,0
 )
-*887 (LeafLogPort
+*886 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25067,5 +25135,5 @@
 uid 9018,0
 )
-*888 (LeafLogPort
+*887 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25082,5 +25150,5 @@
 uid 9247,0
 )
-*889 (LeafLogPort
+*888 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25098,5 +25166,5 @@
 uid 9249,0
 )
-*890 (LeafLogPort
+*889 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25113,21 +25181,21 @@
 uid 10024,0
 )
+*890 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "srclk_enable"
+t "std_logic"
+o 113
+suid 222,0
+i "'0'"
+)
+)
+uid 10026,0
+)
 *891 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "srclk_enable"
-t "std_logic"
-o 113
-suid 222,0
-i "'0'"
-)
-)
-uid 10026,0
-)
-*892 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "SRCLK1"
 t "std_logic"
@@ -25139,5 +25207,5 @@
 uid 10028,0
 )
-*893 (LeafLogPort
+*892 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25155,5 +25223,5 @@
 uid 10208,0
 )
-*894 (LeafLogPort
+*893 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25171,15 +25239,27 @@
 uid 10210,0
 )
+*894 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "s_trigger"
+t "std_logic"
+o 105
+suid 230,0
+)
+)
+uid 10294,0
+)
 *895 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "s_trigger"
-t "std_logic"
-o 105
-suid 230,0
-)
-)
-uid 10294,0
+n "start_srin_write_8b"
+t "std_logic"
+o 116
+suid 231,0
+)
+)
+uid 10334,0
 )
 *896 (LeafLogPort
@@ -25187,11 +25267,12 @@
 m 4
 decl (Decl
-n "start_srin_write_8b"
-t "std_logic"
-o 116
-suid 231,0
-)
-)
-uid 10334,0
+n "srin_write_ack"
+t "std_logic"
+o 114
+suid 232,0
+i "'0'"
+)
+)
+uid 10336,0
 )
 *897 (LeafLogPort
@@ -25199,17 +25280,4 @@
 m 4
 decl (Decl
-n "srin_write_ack"
-t "std_logic"
-o 114
-suid 232,0
-i "'0'"
-)
-)
-uid 10336,0
-)
-*898 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
 n "srin_write_ready"
 t "std_logic"
@@ -25221,5 +25289,5 @@
 uid 10338,0
 )
-*899 (LeafLogPort
+*898 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25235,5 +25303,5 @@
 uid 10340,0
 )
-*900 (LeafLogPort
+*899 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25248,19 +25316,5 @@
 uid 10342,0
 )
-*901 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
-n "trigger_out"
-t "std_logic"
-preAdd 0
-posAdd 0
-o 120
-suid 240,0
-)
-)
-uid 10473,0
-)
-*902 (LeafLogPort
+*900 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -25279,27 +25333,51 @@
 uid 10475,0
 )
+*901 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "socks_connected"
+t "std_logic"
+o 111
+suid 243,0
+)
+)
+uid 10763,0
+)
+*902 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "socks_waiting"
+t "std_logic"
+o 112
+suid 244,0
+)
+)
+uid 10765,0
+)
 *903 (LeafLogPort
 port (LogicalPort
-m 4
-decl (Decl
-n "socks_connected"
-t "std_logic"
-o 111
-suid 243,0
-)
-)
-uid 10763,0
+m 1
+decl (Decl
+n "green"
+t "std_logic"
+o 34
+suid 248,0
+)
+)
+uid 10767,0
 )
 *904 (LeafLogPort
 port (LogicalPort
-m 4
-decl (Decl
-n "socks_waiting"
-t "std_logic"
-o 112
-suid 244,0
-)
-)
-uid 10765,0
+m 1
+decl (Decl
+n "amber"
+t "std_logic"
+o 29
+suid 249,0
+)
+)
+uid 10769,0
 )
 *905 (LeafLogPort
@@ -25307,50 +25385,26 @@
 m 1
 decl (Decl
-n "green"
-t "std_logic"
-o 34
-suid 248,0
-)
-)
-uid 10767,0
+n "red"
+t "std_logic"
+o 39
+suid 250,0
+)
+)
+uid 10771,0
 )
 *906 (LeafLogPort
 port (LogicalPort
-m 1
-decl (Decl
-n "amber"
-t "std_logic"
-o 29
-suid 249,0
-)
-)
-uid 10769,0
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-litem &796
+*1055 (MRCItem
+litem &795
 pos 0
 dimension 20
 uid 74,0
 )
-*1057 (MRCItem
-litem &798
+*1056 (MRCItem
+litem &797
 pos 1
 dimension 50
 uid 75,0
 )
-*1058 (MRCItem
-litem &799
+*1057 (MRCItem
+litem &798
 pos 2
 dimension 100
 uid 76,0
 )
-*1059 (MRCItem
-litem &800
+*1058 (MRCItem
+litem &799
 pos 3
 dimension 50
 uid 77,0
 )
-*1060 (MRCItem
-litem &801
+*1059 (MRCItem
+litem &800
 pos 4
 dimension 100
 uid 78,0
 )
-*1061 (MRCItem
-litem &802
+*1060 (MRCItem
+litem &801
 pos 5
 dimension 100
 uid 79,0
 )
-*1062 (MRCItem
-litem &803
+*1061 (MRCItem
+litem &802
 pos 6
 dimension 50
 uid 80,0
 )
-*1063 (MRCItem
-litem &804
+*1062 (MRCItem
+litem &803
 pos 7
 dimension 290
@@ -26476,39 +26543,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *1064 (LEmptyRow
+emptyRow *1063 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*1065 (RefLabelRowHdr
-)
-*1066 (TitleRowHdr
-)
-*1067 (FilterRowHdr
-)
-*1068 (RefLabelColHdr
+*1064 (RefLabelRowHdr
+)
+*1065 (TitleRowHdr
+)
+*1066 (FilterRowHdr
+)
+*1067 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*1069 (RowExpandColHdr
+*1068 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*1070 (GroupColHdr
+*1069 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*1071 (NameColHdr
+*1070 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*1072 (TypeColHdr
+*1071 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*1073 (InitColHdr
+*1072 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*1074 (PragmaColHdr
+*1073 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*1075 (EolColHdr
+*1074 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*1076 (LogGeneric
+*1075 (LogGeneric
 generic (GiElement
 name "RAMADDRWIDTH64b"
@@ -26525,5 +26592,5 @@
 uid 95,0
 optionalChildren [
-*1077 (Sheet
+*1076 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -26542,6 +26609,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *1078 (MRCItem
-litem &1064
+emptyMRCItem *1077 (MRCItem
+litem &1063
 pos 1
 dimension 20
@@ -26549,18 +26616,18 @@
 uid 97,0
 optionalChildren [
-*1079 (MRCItem
-litem &1065
+*1078 (MRCItem
+litem &1064
 pos 0
 dimension 20
 uid 98,0
 )
-*1080 (MRCItem
-litem &1066
+*1079 (MRCItem
+litem &1065
 pos 1
 dimension 23
 uid 99,0
 )
-*1081 (MRCItem
-litem &1067
+*1080 (MRCItem
+litem &1066
 pos 2
 hidden 1
@@ -26568,6 +26635,6 @@
 uid 100,0
 )
-*1082 (MRCItem
-litem &1076
+*1081 (MRCItem
+litem &1075
 pos 0
 dimension 20
@@ -26585,42 +26652,42 @@
 uid 101,0
 optionalChildren [
-*1083 (MRCItem
-litem &1068
+*1082 (MRCItem
+litem &1067
 pos 0
 dimension 20
 uid 102,0
 )
-*1084 (MRCItem
-litem &1070
+*1083 (MRCItem
+litem &1069
 pos 1
 dimension 50
 uid 103,0
 )
-*1085 (MRCItem
-litem &1071
+*1084 (MRCItem
+litem &1070
 pos 2
 dimension 186
 uid 104,0
 )
-*1086 (MRCItem
-litem &1072
+*1085 (MRCItem
+litem &1071
 pos 3
 dimension 96
 uid 105,0
 )
-*1087 (MRCItem
-litem &1073
+*1086 (MRCItem
+litem &1072
 pos 4
 dimension 50
 uid 106,0
 )
-*1088 (MRCItem
-litem &1074
+*1087 (MRCItem
+litem &1073
 pos 5
 dimension 50
 uid 107,0
 )
-*1089 (MRCItem
-litem &1075
+*1088 (MRCItem
+litem &1074
 pos 6
 dimension 80
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak	(revision 10138)
@@ -333,17 +333,17 @@
 (vvPair
 variable "date"
-value "04.02.2011"
+value "08.02.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "04"
+value "08"
 )
 (vvPair
@@ -485,5 +485,5 @@
 (vvPair
 variable "time"
-value "11:32:44"
+value "11:05:26"
 )
 (vvPair
@@ -576,5 +576,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,106800,-128500,107600"
+xt "-172000,106000,-128500,106800"
 st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
 "
@@ -1303,5 +1303,5 @@
 fg "0,65535,0"
 )
-xt "0,65625,750,66375"
+xt "0,70625,750,71375"
 )
 tg (CPTG
@@ -1313,8 +1313,8 @@
 va (VaSet
 )
-xt "-17300,65500,-1000,66500"
+xt "-17300,70500,-1000,71500"
 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
 ju 2
-blo "-1000,66300"
+blo "-1000,71300"
 )
 )
@@ -1378,5 +1378,5 @@
 fg "0,65535,0"
 )
-xt "-21750,70625,-21000,71375"
+xt "-21750,69625,-21000,70375"
 )
 tg (CPTG
@@ -1388,7 +1388,7 @@
 va (VaSet
 )
-xt "-20000,70500,-13200,71500"
+xt "-20000,69500,-13200,70500"
 st "trigger_id : (47:0)"
-blo "-20000,71300"
+blo "-20000,70300"
 )
 )
@@ -1486,5 +1486,5 @@
 fg "0,65535,0"
 )
-xt "0,66625,750,67375"
+xt "0,71625,750,72375"
 )
 tg (CPTG
@@ -1496,8 +1496,8 @@
 va (VaSet
 )
-xt "-6300,66500,-1000,67500"
+xt "-6300,71500,-1000,72500"
 st "ram_write_ea"
 ju 2
-blo "-1000,67300"
+blo "-1000,72300"
 )
 )
@@ -1521,5 +1521,5 @@
 fg "0,65535,0"
 )
-xt "0,67625,750,68375"
+xt "0,72625,750,73375"
 )
 tg (CPTG
@@ -1531,8 +1531,8 @@
 va (VaSet
 )
-xt "-7300,67500,-1000,68500"
+xt "-7300,72500,-1000,73500"
 st "ram_write_ready"
 ju 2
-blo "-1000,68300"
+blo "-1000,73300"
 )
 )
@@ -1559,5 +1559,5 @@
 fg "0,65535,0"
 )
-xt "0,76625,750,77375"
+xt "0,78625,750,79375"
 )
 tg (CPTG
@@ -1569,8 +1569,8 @@
 va (VaSet
 )
-xt "-4000,76500,-1000,77500"
+xt "-4000,78500,-1000,79500"
 st "roi_max"
 ju 2
-blo "-1000,77300"
+blo "-1000,79300"
 )
 )
@@ -1629,5 +1629,5 @@
 fg "0,65535,0"
 )
-xt "0,77625,750,78375"
+xt "0,79625,750,80375"
 )
 tg (CPTG
@@ -1639,8 +1639,8 @@
 va (VaSet
 )
-xt "-10100,77500,-1000,78500"
+xt "-10100,79500,-1000,80500"
 st "package_length : (15:0)"
 ju 2
-blo "-1000,78300"
+blo "-1000,80300"
 )
 )
@@ -2028,5 +2028,5 @@
 fg "0,65535,0"
 )
-xt "0,74625,750,75375"
+xt "0,77625,750,78375"
 )
 tg (CPTG
@@ -2038,8 +2038,8 @@
 va (VaSet
 )
-xt "-7700,74500,-1000,75500"
+xt "-7700,77500,-1000,78500"
 st "config_ready_mm"
 ju 2
-blo "-1000,75300"
+blo "-1000,78300"
 )
 )
@@ -2168,5 +2168,5 @@
 fg "0,65535,0"
 )
-xt "0,72625,750,73375"
+xt "0,75625,750,76375"
 )
 tg (CPTG
@@ -2178,8 +2178,8 @@
 va (VaSet
 )
-xt "-7400,72500,-1000,73500"
+xt "-7400,75500,-1000,76500"
 st "config_start_mm"
 ju 2
-blo "-1000,73300"
+blo "-1000,76300"
 )
 )
@@ -2356,5 +2356,5 @@
 fg "0,65535,0"
 )
-xt "0,73625,750,74375"
+xt "0,76625,750,77375"
 )
 tg (CPTG
@@ -2366,8 +2366,8 @@
 va (VaSet
 )
-xt "-8200,73500,-1000,74500"
+xt "-8200,76500,-1000,77500"
 st "config_started_mm"
 ju 2
-blo "-1000,74300"
+blo "-1000,77300"
 )
 )
@@ -2638,5 +2638,5 @@
 fg "0,65535,0"
 )
-xt "0,68625,750,69375"
+xt "0,73625,750,74375"
 )
 tg (CPTG
@@ -2648,8 +2648,8 @@
 va (VaSet
 )
-xt "-8800,68500,-1000,69500"
+xt "-8800,73500,-1000,74500"
 st "ram_write_ready_ack"
 ju 2
-blo "-1000,69300"
+blo "-1000,74300"
 )
 )
@@ -2799,7 +2799,7 @@
 font "Arial,8,1"
 )
-xt "-20700,97000,-14500,98000"
+xt "-20700,98000,-14500,99000"
 st "FACT_FAD_lib"
-blo "-20700,97800"
+blo "-20700,98800"
 tm "BdLibraryNameMgr"
 )
@@ -2809,7 +2809,7 @@
 font "Arial,8,1"
 )
-xt "-20700,98000,-14300,99000"
+xt "-20700,99000,-14300,100000"
 st "data_generator"
-blo "-20700,98800"
+blo "-20700,99800"
 tm "CptNameMgr"
 )
@@ -2819,7 +2819,7 @@
 font "Arial,8,1"
 )
-xt "-20700,99000,-11100,100000"
+xt "-20700,100000,-11100,101000"
 st "I_main_data_generator"
-blo "-20700,99800"
+blo "-20700,100800"
 tm "InstanceNameMgr"
 )
@@ -3271,5 +3271,5 @@
 fg "0,65535,0"
 )
-xt "87250,71625,88000,72375"
+xt "87250,72625,88000,73375"
 )
 tg (CPTG
@@ -3281,7 +3281,7 @@
 va (VaSet
 )
-xt "89000,71500,96900,72500"
+xt "89000,72500,96900,73500"
 st "write_length : (16:0)"
-blo "89000,72300"
+blo "89000,73300"
 )
 )
@@ -3308,5 +3308,5 @@
 fg "0,65535,0"
 )
-xt "87250,72625,88000,73375"
+xt "87250,73625,88000,74375"
 )
 tg (CPTG
@@ -3318,7 +3318,7 @@
 va (VaSet
 )
-xt "89000,72500,105300,73500"
+xt "89000,73500,105300,74500"
 st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
-blo "89000,73300"
+blo "89000,74300"
 )
 )
@@ -3420,5 +3420,5 @@
 fg "0,65535,0"
 )
-xt "87250,70625,88000,71375"
+xt "87250,71625,88000,72375"
 )
 tg (CPTG
@@ -3430,7 +3430,7 @@
 va (VaSet
 )
-xt "89000,70500,93100,71500"
+xt "89000,71500,93100,72500"
 st "data_valid"
-blo "89000,71300"
+blo "89000,72300"
 )
 )
@@ -3456,5 +3456,5 @@
 fg "0,65535,0"
 )
-xt "87250,69625,88000,70375"
+xt "87250,70625,88000,71375"
 )
 tg (CPTG
@@ -3466,7 +3466,7 @@
 va (VaSet
 )
-xt "89000,69500,90900,70500"
+xt "89000,70500,90900,71500"
 st "busy"
-blo "89000,70300"
+blo "89000,71300"
 )
 )
@@ -3494,5 +3494,5 @@
 fg "0,65535,0"
 )
-xt "87250,73625,88000,74375"
+xt "87250,74625,88000,75375"
 )
 tg (CPTG
@@ -3504,7 +3504,7 @@
 va (VaSet
 )
-xt "89000,73500,96800,74500"
+xt "89000,74500,96800,75500"
 st "fifo_channels : (3:0)"
-blo "89000,74300"
+blo "89000,75300"
 )
 )
@@ -3530,5 +3530,5 @@
 fg "0,65535,0"
 )
-xt "87250,74625,88000,75375"
+xt "87250,75625,88000,76375"
 )
 tg (CPTG
@@ -3540,7 +3540,7 @@
 va (VaSet
 )
-xt "89000,74500,94700,75500"
+xt "89000,75500,94700,76500"
 st "write_end_flag"
-blo "89000,75300"
+blo "89000,76300"
 )
 )
@@ -3564,5 +3564,5 @@
 fg "0,65535,0"
 )
-xt "87250,75625,88000,76375"
+xt "87250,76625,88000,77375"
 )
 tg (CPTG
@@ -3574,7 +3574,7 @@
 va (VaSet
 )
-xt "89000,75500,95800,76500"
+xt "89000,76500,95800,77500"
 st "write_header_flag"
-blo "89000,76300"
+blo "89000,77300"
 )
 )
@@ -4008,5 +4008,5 @@
 fg "0,65535,0"
 )
-xt "87250,76625,88000,77375"
+xt "87250,77625,88000,78375"
 )
 tg (CPTG
@@ -4018,7 +4018,7 @@
 va (VaSet
 )
-xt "89000,76500,94600,77500"
+xt "89000,77500,94600,78500"
 st "data_valid_ack"
-blo "89000,77300"
+blo "89000,78300"
 )
 )
@@ -4718,5 +4718,5 @@
 fg "0,65535,0"
 )
-xt "-41000,67625,-40250,68375"
+xt "-41000,68625,-40250,69375"
 )
 tg (CPTG
@@ -4728,8 +4728,8 @@
 va (VaSet
 )
-xt "-48800,67500,-42000,68500"
+xt "-48800,68500,-42000,69500"
 st "trigger_id : (47:0)"
 ju 2
-blo "-42000,68300"
+blo "-42000,69300"
 )
 )
@@ -4758,5 +4758,5 @@
 fg "0,65535,0"
 )
-xt "-52750,67625,-52000,68375"
+xt "-52750,68625,-52000,69375"
 )
 tg (CPTG
@@ -4768,7 +4768,7 @@
 va (VaSet
 )
-xt "-51000,67500,-48200,68500"
+xt "-51000,68500,-48200,69500"
 st "trigger"
-blo "-51000,68300"
+blo "-51000,69300"
 )
 )
@@ -4795,5 +4795,5 @@
 fg "0,65535,0"
 )
-xt "-52750,66625,-52000,67375"
+xt "-52750,67625,-52000,68375"
 )
 tg (CPTG
@@ -4805,7 +4805,7 @@
 va (VaSet
 )
-xt "-51000,66500,-49700,67500"
+xt "-51000,67500,-49700,68500"
 st "clk"
-blo "-51000,67300"
+blo "-51000,68300"
 )
 )
@@ -4829,5 +4829,5 @@
 lineWidth 2
 )
-xt "-52000,66000,-41000,70000"
+xt "-52000,67000,-41000,71000"
 )
 oxt "32000,2000,43000,12000"
@@ -4843,7 +4843,7 @@
 font "Arial,8,1"
 )
-xt "-50300,70000,-43700,71000"
+xt "-50300,71000,-43700,72000"
 st "FACT_FAD_LIB"
-blo "-50300,70800"
+blo "-50300,71800"
 tm "BdLibraryNameMgr"
 )
@@ -4854,7 +4854,7 @@
 font "Arial,8,1"
 )
-xt "-50300,71000,-43700,72000"
+xt "-50300,72000,-43700,73000"
 st "trigger_counter"
-blo "-50300,71800"
+blo "-50300,72800"
 tm "CptNameMgr"
 )
@@ -4865,7 +4865,7 @@
 font "Arial,8,1"
 )
-xt "-50300,71000,-42700,72000"
+xt "-50300,72000,-42700,73000"
 st "I_main_ext_trigger"
-blo "-50300,71800"
+blo "-50300,72800"
 tm "InstanceNameMgr"
 )
@@ -4882,5 +4882,5 @@
 font "Courier New,8,0"
 )
-xt "-52000,65000,-52000,65000"
+xt "-52000,66000,-52000,66000"
 )
 header ""
@@ -4896,5 +4896,5 @@
 fg "49152,49152,49152"
 )
-xt "-51750,68250,-50250,69750"
+xt "-51750,69250,-50250,70750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -4964,5 +4964,5 @@
 fg "0,65535,0"
 )
-xt "31250,72625,32000,73375"
+xt "27250,70625,28000,71375"
 )
 tg (CPTG
@@ -4975,7 +4975,7 @@
 font "arial,8,0"
 )
-xt "33000,72500,51400,73500"
+xt "29000,70500,47400,71500"
 st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
-blo "33000,73300"
+blo "29000,71300"
 )
 )
@@ -5000,23 +5000,25 @@
 shape (Triangle
 uid 2352,0
-ro 90
+ro 180
 va (VaSet
 vasetType 1
 fg "0,65535,0"
 )
-xt "31250,70625,32000,71375"
+xt "28625,67250,29375,68000"
 )
 tg (CPTG
 uid 2353,0
 ps "CptPortTextPlaceStrategy"
-stg "VerticalLayoutStrategy"
+stg "RightVerticalLayoutStrategy"
 f (Text
 uid 2354,0
+ro 270
 va (VaSet
 font "arial,8,0"
 )
-xt "33000,70500,34300,71500"
+xt "28500,69000,29500,70300"
 st "clk"
-blo "33000,71300"
+ju 2
+blo "29300,69000"
 )
 )
@@ -5041,5 +5043,5 @@
 fg "0,65535,0"
 )
-xt "31250,79625,32000,80375"
+xt "27250,77625,28000,78375"
 )
 tg (CPTG
@@ -5052,7 +5054,7 @@
 font "arial,8,0"
 )
-xt "33000,79500,38100,80500"
+xt "29000,77500,34100,78500"
 st "config_ready"
-blo "33000,80300"
+blo "29000,78300"
 )
 )
@@ -5079,5 +5081,5 @@
 fg "0,65535,0"
 )
-xt "31250,77625,32000,78375"
+xt "27250,75625,28000,76375"
 )
 tg (CPTG
@@ -5090,7 +5092,7 @@
 font "arial,8,0"
 )
-xt "33000,77500,37800,78500"
+xt "29000,75500,33800,76500"
 st "config_start"
-blo "33000,78300"
+blo "29000,76300"
 )
 )
@@ -5115,5 +5117,5 @@
 fg "0,65535,0"
 )
-xt "31250,73625,32000,74375"
+xt "27250,71625,28000,72375"
 )
 tg (CPTG
@@ -5126,7 +5128,7 @@
 font "arial,8,0"
 )
-xt "33000,73500,38300,74500"
+xt "29000,71500,34300,72500"
 st "ram_write_ea"
-blo "33000,74300"
+blo "29000,72300"
 )
 )
@@ -5153,5 +5155,5 @@
 fg "0,65535,0"
 )
-xt "31250,74625,32000,75375"
+xt "27250,72625,28000,73375"
 )
 tg (CPTG
@@ -5164,7 +5166,7 @@
 font "arial,8,0"
 )
-xt "33000,74500,39300,75500"
+xt "29000,72500,35300,73500"
 st "ram_write_ready"
-blo "33000,75300"
+blo "29000,73300"
 )
 )
@@ -5190,5 +5192,5 @@
 fg "0,65535,0"
 )
-xt "31250,80625,32000,81375"
+xt "27250,78625,28000,79375"
 )
 tg (CPTG
@@ -5201,7 +5203,7 @@
 font "arial,8,0"
 )
-xt "33000,80500,36000,81500"
+xt "29000,78500,32000,79500"
 st "roi_max"
-blo "33000,81300"
+blo "29000,79300"
 )
 )
@@ -5229,5 +5231,5 @@
 fg "0,65535,0"
 )
-xt "63000,70625,63750,71375"
+xt "59000,70625,59750,71375"
 )
 tg (CPTG
@@ -5240,8 +5242,8 @@
 font "arial,8,0"
 )
-xt "58600,70500,62000,71500"
+xt "54600,70500,58000,71500"
 st "wiz_busy"
 ju 2
-blo "62000,71300"
+blo "58000,71300"
 )
 )
@@ -5266,5 +5268,5 @@
 fg "0,65535,0"
 )
-xt "63000,74625,63750,75375"
+xt "59000,74625,59750,75375"
 )
 tg (CPTG
@@ -5277,8 +5279,8 @@
 font "arial,8,0"
 )
-xt "50200,74500,62000,75500"
+xt "46200,74500,58000,75500"
 st "wiz_number_of_channels : (3:0)"
 ju 2
-blo "62000,75300"
+blo "58000,75300"
 )
 )
@@ -5306,5 +5308,5 @@
 fg "0,65535,0"
 )
-xt "63000,73625,63750,74375"
+xt "59000,73625,59750,74375"
 )
 tg (CPTG
@@ -5317,8 +5319,8 @@
 font "arial,8,0"
 )
-xt "42100,73500,62000,74500"
+xt "38100,73500,58000,74500"
 st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
 ju 2
-blo "62000,74300"
+blo "58000,74300"
 )
 )
@@ -5347,5 +5349,5 @@
 fg "0,65535,0"
 )
-xt "63000,71625,63750,72375"
+xt "59000,71625,59750,72375"
 )
 tg (CPTG
@@ -5358,8 +5360,8 @@
 font "arial,8,0"
 )
-xt "56900,71500,62000,72500"
+xt "52900,71500,58000,72500"
 st "wiz_write_ea"
 ju 2
-blo "62000,72300"
+blo "58000,72300"
 )
 )
@@ -5386,5 +5388,5 @@
 fg "0,65535,0"
 )
-xt "63000,75625,63750,76375"
+xt "59000,75625,59750,76375"
 )
 tg (CPTG
@@ -5397,8 +5399,8 @@
 font "arial,8,0"
 )
-xt "56500,75500,62000,76500"
+xt "52500,75500,58000,76500"
 st "wiz_write_end"
 ju 2
-blo "62000,76300"
+blo "58000,76300"
 )
 )
@@ -5425,5 +5427,5 @@
 fg "0,65535,0"
 )
-xt "63000,76625,63750,77375"
+xt "59000,76625,59750,77375"
 )
 tg (CPTG
@@ -5436,8 +5438,8 @@
 font "arial,8,0"
 )
-xt "55400,76500,62000,77500"
+xt "51400,76500,58000,77500"
 st "wiz_write_header"
 ju 2
-blo "62000,77300"
+blo "58000,77300"
 )
 )
@@ -5464,5 +5466,5 @@
 fg "0,65535,0"
 )
-xt "63000,72625,63750,73375"
+xt "59000,72625,59750,73375"
 )
 tg (CPTG
@@ -5475,8 +5477,8 @@
 font "arial,8,0"
 )
-xt "52600,72500,62000,73500"
+xt "48600,72500,58000,73500"
 st "wiz_write_length : (16:0)"
 ju 2
-blo "62000,73300"
+blo "58000,73300"
 )
 )
@@ -5504,5 +5506,5 @@
 fg "0,65535,0"
 )
-xt "31250,87625,32000,88375"
+xt "27250,85625,28000,86375"
 )
 tg (CPTG
@@ -5515,7 +5517,7 @@
 font "arial,8,0"
 )
-xt "33000,87500,36400,88500"
+xt "29000,85500,32400,86500"
 st "roi_array"
-blo "33000,88300"
+blo "29000,86300"
 )
 )
@@ -5542,5 +5544,5 @@
 fg "0,65535,0"
 )
-xt "31250,81625,32000,82375"
+xt "27250,79625,28000,80375"
 )
 tg (CPTG
@@ -5553,7 +5555,7 @@
 font "arial,8,0"
 )
-xt "33000,81500,42100,82500"
+xt "29000,79500,38100,80500"
 st "package_length : (15:0)"
-blo "33000,82300"
+blo "29000,80300"
 )
 )
@@ -5581,5 +5583,5 @@
 fg "0,65535,0"
 )
-xt "31250,78625,32000,79375"
+xt "27250,76625,28000,77375"
 )
 tg (CPTG
@@ -5592,7 +5594,7 @@
 font "arial,8,0"
 )
-xt "33000,78500,38600,79500"
+xt "29000,76500,34600,77500"
 st "config_started"
-blo "33000,79300"
+blo "29000,77300"
 )
 )
@@ -5619,5 +5621,5 @@
 fg "0,65535,0"
 )
-xt "63000,77625,63750,78375"
+xt "59000,77625,59750,78375"
 )
 tg (CPTG
@@ -5630,8 +5632,8 @@
 font "arial,8,0"
 )
-xt "59000,77500,62000,78500"
+xt "55000,77500,58000,78500"
 st "wiz_ack"
 ju 2
-blo "62000,78300"
+blo "58000,78300"
 )
 )
@@ -5656,5 +5658,5 @@
 fg "0,65535,0"
 )
-xt "31250,75625,32000,76375"
+xt "27250,73625,28000,74375"
 )
 tg (CPTG
@@ -5667,7 +5669,7 @@
 font "arial,8,0"
 )
-xt "33000,75500,40800,76500"
+xt "29000,73500,36800,74500"
 st "ram_write_ready_ack"
-blo "33000,76300"
+blo "29000,74300"
 )
 )
@@ -5696,5 +5698,5 @@
 lineWidth 2
 )
-xt "32000,70000,63000,90000"
+xt "28000,68000,59000,88000"
 )
 oxt "15000,6000,23000,16000"
@@ -5709,7 +5711,7 @@
 font "arial,8,1"
 )
-xt "32350,90000,38550,91000"
+xt "28350,88000,34550,89000"
 st "FACT_FAD_lib"
-blo "32350,90800"
+blo "28350,88800"
 tm "BdLibraryNameMgr"
 )
@@ -5719,7 +5721,7 @@
 font "arial,8,1"
 )
-xt "32350,91000,39650,92000"
+xt "28350,89000,35650,90000"
 st "memory_manager"
-blo "32350,91800"
+blo "28350,89800"
 tm "CptNameMgr"
 )
@@ -5729,7 +5731,7 @@
 font "arial,8,1"
 )
-xt "32350,92000,42850,93000"
+xt "28350,90000,38850,91000"
 st "I_main_memory_manager"
-blo "32350,92800"
+blo "28350,90800"
 tm "InstanceNameMgr"
 )
@@ -5746,5 +5748,5 @@
 font "Courier New,8,0"
 )
-xt "32000,68400,61500,70000"
+xt "31000,66400,60500,68000"
 st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer )  
 RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
@@ -5772,5 +5774,5 @@
 fg "49152,49152,49152"
 )
-xt "32250,88250,33750,89750"
+xt "28250,86250,29750,87750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -5797,5 +5799,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,101200,-149500,102000"
+xt "-172000,100400,-149500,101200"
 st "SIGNAL wiz_busy               : std_logic
 "
@@ -5817,5 +5819,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,103600,-128500,104400"
+xt "-172000,102800,-128500,103600"
 st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
 "
@@ -5838,5 +5840,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,106000,-122500,106800"
+xt "-172000,105200,-122500,106000"
 st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
 "
@@ -5860,5 +5862,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,102800,-122500,103600"
+xt "-172000,102000,-122500,102800"
 st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
 "
@@ -5881,5 +5883,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,102000,-122500,102800"
+xt "-172000,101200,-122500,102000"
 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
 "
@@ -5901,5 +5903,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,104400,-128500,105200"
+xt "-172000,103600,-128500,104400"
 st "SIGNAL wiz_write_end          : std_logic                                    := '0'
 "
@@ -5921,5 +5923,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,105200,-128500,106000"
+xt "-172000,104400,-128500,105200"
 st "SIGNAL wiz_write_header       : std_logic                                    := '0'
 "
@@ -6932,5 +6934,5 @@
 sl 0
 ro 90
-xt "-29000,65625,-27500,66375"
+xt "-28000,66625,-26500,67375"
 )
 (Line
@@ -6938,8 +6940,8 @@
 sl 0
 ro 90
-xt "-27500,66000,-27000,66000"
-pts [
-"-27000,66000"
-"-27500,66000"
+xt "-26500,67000,-26000,67000"
+pts [
+"-26000,67000"
+"-26500,67000"
 ]
 )
@@ -6956,8 +6958,8 @@
 va (VaSet
 )
-xt "-35900,65500,-30000,66500"
+xt "-34900,66500,-29000,67500"
 st "drs_channel_id"
 ju 2
-blo "-30000,66300"
+blo "-29000,67300"
 tm "WireNameMgr"
 )
@@ -10972,5 +10974,5 @@
 font "Courier New,8,0"
 )
-xt "-172000,100400,-149500,101200"
+xt "-172000,99600,-149500,100400"
 st "SIGNAL wiz_ack                : std_logic
 "
@@ -12959,24 +12961,4 @@
 )
 *431 (Net
-uid 10449,0
-decl (Decl
-n "trigger_out"
-t "std_logic"
-preAdd 0
-posAdd 0
-o 120
-suid 240,0
-)
-declText (MLText
-uid 10450,0
-va (VaSet
-font "Courier New,8,0"
-)
-xt "-172000,99600,-149500,100400"
-st "SIGNAL trigger_out            : std_logic
-"
-)
-)
-*432 (Net
 uid 10465,0
 lang 2
@@ -13002,5 +12984,5 @@
 )
 )
-*433 (Net
+*432 (Net
 uid 10627,0
 decl (Decl
@@ -13020,5 +13002,5 @@
 )
 )
-*434 (Net
+*433 (Net
 uid 10635,0
 decl (Decl
@@ -13038,5 +13020,5 @@
 )
 )
-*435 (Net
+*434 (Net
 uid 10721,0
 decl (Decl
@@ -13056,5 +13038,5 @@
 )
 )
-*436 (PortIoOut
+*435 (PortIoOut
 uid 10729,0
 shape (CompositeShape
@@ -13100,5 +13082,5 @@
 )
 )
-*437 (Net
+*436 (Net
 uid 10735,0
 decl (Decl
@@ -13118,5 +13100,5 @@
 )
 )
-*438 (PortIoOut
+*437 (PortIoOut
 uid 10743,0
 shape (CompositeShape
@@ -13162,5 +13144,5 @@
 )
 )
-*439 (Net
+*438 (Net
 uid 10749,0
 decl (Decl
@@ -13180,5 +13162,5 @@
 )
 )
-*440 (PortIoOut
+*439 (PortIoOut
 uid 10757,0
 shape (CompositeShape
@@ -13224,8 +13206,8 @@
 )
 )
-*441 (SaComponent
+*440 (SaComponent
 uid 11209,0
 optionalChildren [
-*442 (CptPort
+*441 (CptPort
 uid 11181,0
 ps "OnEdgeStrategy"
@@ -13260,5 +13242,5 @@
 )
 )
-*443 (CptPort
+*442 (CptPort
 uid 11185,0
 ps "OnEdgeStrategy"
@@ -13295,5 +13277,5 @@
 )
 )
-*444 (CptPort
+*443 (CptPort
 uid 11189,0
 ps "OnEdgeStrategy"
@@ -13330,5 +13312,5 @@
 )
 )
-*445 (CptPort
+*444 (CptPort
 uid 11193,0
 ps "OnEdgeStrategy"
@@ -13365,5 +13347,5 @@
 )
 )
-*446 (CptPort
+*445 (CptPort
 uid 11197,0
 ps "OnEdgeStrategy"
@@ -13398,5 +13380,5 @@
 )
 )
-*447 (CptPort
+*446 (CptPort
 uid 11201,0
 ps "OnEdgeStrategy"
@@ -13431,5 +13413,5 @@
 )
 )
-*448 (CptPort
+*447 (CptPort
 uid 11205,0
 ps "OnEdgeStrategy"
@@ -13464,5 +13446,5 @@
 )
 )
-*449 (CptPort
+*448 (CptPort
 uid 12693,0
 ps "OnEdgeStrategy"
@@ -13516,5 +13498,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*450 (Text
+*449 (Text
 uid 11212,0
 va (VaSet
@@ -13526,5 +13508,5 @@
 tm "BdLibraryNameMgr"
 )
-*451 (Text
+*450 (Text
 uid 11213,0
 va (VaSet
@@ -13536,5 +13518,5 @@
 tm "CptNameMgr"
 )
-*452 (Text
+*451 (Text
 uid 11214,0
 va (VaSet
@@ -13603,5 +13585,5 @@
 archFileType "UNKNOWN"
 )
-*453 (Net
+*452 (Net
 uid 11403,0
 decl (Decl
@@ -13621,5 +13603,5 @@
 )
 )
-*454 (Net
+*453 (Net
 uid 11856,0
 decl (Decl
@@ -13639,11 +13621,11 @@
 )
 )
-*455 (MWC
+*454 (MWC
 uid 12295,0
 optionalChildren [
-*456 (CptPort
+*455 (CptPort
 uid 12267,0
 optionalChildren [
-*457 (Line
+*456 (Line
 uid 12271,0
 layer 5
@@ -13658,5 +13640,5 @@
 ]
 )
-*458 (Property
+*457 (Property
 uid 12272,0
 pclass "_MW_GEOM_"
@@ -13705,8 +13687,8 @@
 )
 )
-*459 (CptPort
+*458 (CptPort
 uid 12273,0
 optionalChildren [
-*460 (Line
+*459 (Line
 uid 12277,0
 layer 5
@@ -13760,8 +13742,8 @@
 )
 )
-*461 (CptPort
+*460 (CptPort
 uid 12278,0
 optionalChildren [
-*462 (Line
+*461 (Line
 uid 12282,0
 layer 5
@@ -13813,8 +13795,8 @@
 )
 )
-*463 (CommentGraphic
+*462 (CommentGraphic
 uid 12283,0
 optionalChildren [
-*464 (Property
+*463 (Property
 uid 12285,0
 pclass "_MW_GEOM_"
@@ -13840,8 +13822,8 @@
 oxt "7000,10000,7000,10000"
 )
-*465 (CommentGraphic
+*464 (CommentGraphic
 uid 12286,0
 optionalChildren [
-*466 (Property
+*465 (Property
 uid 12288,0
 pclass "_MW_GEOM_"
@@ -13867,8 +13849,8 @@
 oxt "7000,6000,7000,6000"
 )
-*467 (Grouping
+*466 (Grouping
 uid 12289,0
 optionalChildren [
-*468 (CommentGraphic
+*467 (CommentGraphic
 uid 12291,0
 shape (PolyLine2D
@@ -13891,5 +13873,5 @@
 oxt "7000,6000,9000,10000"
 )
-*469 (CommentGraphic
+*468 (CommentGraphic
 uid 12293,0
 shape (Arc2D
@@ -13944,5 +13926,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*470 (Text
+*469 (Text
 uid 12298,0
 va (VaSet
@@ -13954,5 +13936,5 @@
 blo "-80500,73300"
 )
-*471 (Text
+*470 (Text
 uid 12299,0
 va (VaSet
@@ -13963,5 +13945,5 @@
 blo "-80500,74300"
 )
-*472 (Text
+*471 (Text
 uid 12300,0
 va (VaSet
@@ -14008,5 +13990,5 @@
 )
 )
-*473 (Net
+*472 (Net
 uid 12304,0
 decl (Decl
@@ -14028,8 +14010,8 @@
 )
 )
-*474 (SaComponent
+*473 (SaComponent
 uid 12625,0
 optionalChildren [
-*475 (CptPort
+*474 (CptPort
 uid 12605,0
 ps "OnEdgeStrategy"
@@ -14064,5 +14046,5 @@
 )
 )
-*476 (CptPort
+*475 (CptPort
 uid 12609,0
 ps "OnEdgeStrategy"
@@ -14100,5 +14082,5 @@
 )
 )
-*477 (CptPort
+*476 (CptPort
 uid 12613,0
 ps "OnEdgeStrategy"
@@ -14135,5 +14117,5 @@
 )
 )
-*478 (CptPort
+*477 (CptPort
 uid 12617,0
 ps "OnEdgeStrategy"
@@ -14169,5 +14151,5 @@
 )
 )
-*479 (CptPort
+*478 (CptPort
 uid 12621,0
 ps "OnEdgeStrategy"
@@ -14205,5 +14187,5 @@
 )
 )
-*480 (CptPort
+*479 (CptPort
 uid 12673,0
 ps "OnEdgeStrategy"
@@ -14255,5 +14237,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*481 (Text
+*480 (Text
 uid 12628,0
 va (VaSet
@@ -14265,5 +14247,5 @@
 tm "BdLibraryNameMgr"
 )
-*482 (Text
+*481 (Text
 uid 12629,0
 va (VaSet
@@ -14275,5 +14257,5 @@
 tm "CptNameMgr"
 )
-*483 (Text
+*482 (Text
 uid 12630,0
 va (VaSet
@@ -14322,5 +14304,5 @@
 archFileType "UNKNOWN"
 )
-*484 (Net
+*483 (Net
 uid 12641,0
 decl (Decl
@@ -14342,5 +14324,5 @@
 )
 )
-*485 (Net
+*484 (Net
 uid 12647,0
 decl (Decl
@@ -14367,5 +14349,5 @@
 )
 )
-*486 (Net
+*485 (Net
 uid 12653,0
 decl (Decl
@@ -14385,5 +14367,5 @@
 )
 )
-*487 (Net
+*486 (Net
 uid 12705,0
 decl (Decl
@@ -14403,5 +14385,5 @@
 )
 )
-*488 (PortIoOut
+*487 (PortIoOut
 uid 12713,0
 shape (CompositeShape
@@ -14447,8 +14429,8 @@
 )
 )
-*489 (SaComponent
+*488 (SaComponent
 uid 13117,0
 optionalChildren [
-*490 (CptPort
+*489 (CptPort
 uid 13101,0
 ps "OnEdgeStrategy"
@@ -14460,5 +14442,5 @@
 fg "0,65535,0"
 )
-xt "63000,61625,63750,62375"
+xt "72000,61625,72750,62375"
 )
 tg (CPTG
@@ -14470,8 +14452,8 @@
 va (VaSet
 )
-xt "60100,61500,62000,62500"
+xt "69100,61500,71000,62500"
 st "CLK"
 ju 2
-blo "62000,62300"
+blo "71000,62300"
 )
 )
@@ -14484,5 +14466,5 @@
 )
 )
-*491 (CptPort
+*490 (CptPort
 uid 13105,0
 ps "OnEdgeStrategy"
@@ -14494,5 +14476,5 @@
 fg "0,65535,0"
 )
-xt "63000,62625,63750,63375"
+xt "72000,62625,72750,63375"
 )
 tg (CPTG
@@ -14504,8 +14486,8 @@
 va (VaSet
 )
-xt "59400,62500,62000,63500"
+xt "68400,62500,71000,63500"
 st "enable"
 ju 2
-blo "62000,63300"
+blo "71000,63300"
 )
 )
@@ -14518,5 +14500,5 @@
 )
 )
-*492 (CptPort
+*491 (CptPort
 uid 13109,0
 ps "OnEdgeStrategy"
@@ -14528,5 +14510,5 @@
 fg "0,65535,0"
 )
-xt "63000,63625,63750,64375"
+xt "72000,63625,72750,64375"
 )
 tg (CPTG
@@ -14538,8 +14520,8 @@
 va (VaSet
 )
-xt "55900,63500,62000,64500"
+xt "64900,63500,71000,64500"
 st "multiplier : (7:0)"
 ju 2
-blo "62000,64300"
+blo "71000,64300"
 )
 )
@@ -14553,5 +14535,5 @@
 )
 )
-*493 (CptPort
+*492 (CptPort
 uid 13113,0
 ps "OnEdgeStrategy"
@@ -14563,5 +14545,5 @@
 fg "0,65535,0"
 )
-xt "50250,61625,51000,62375"
+xt "59250,61625,60000,62375"
 )
 tg (CPTG
@@ -14573,7 +14555,7 @@
 va (VaSet
 )
-xt "52000,61500,54800,62500"
+xt "61000,61500,63800,62500"
 st "trigger"
-blo "52000,62300"
+blo "61000,62300"
 )
 )
@@ -14596,5 +14578,5 @@
 lineWidth 2
 )
-xt "51000,61000,63000,65000"
+xt "60000,61000,72000,65000"
 )
 oxt "0,0,8000,10000"
@@ -14604,32 +14586,32 @@
 stg "VerticalLayoutStrategy"
 textVec [
+*493 (Text
+uid 13120,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "62350,65000,68550,66000"
+st "FACT_FAD_lib"
+blo "62350,65800"
+tm "BdLibraryNameMgr"
+)
 *494 (Text
-uid 13120,0
+uid 13121,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "53350,65000,59550,66000"
-st "FACT_FAD_lib"
-blo "53350,65800"
-tm "BdLibraryNameMgr"
+xt "62350,66000,69650,67000"
+st "continous_pulser"
+blo "62350,66800"
+tm "CptNameMgr"
 )
 *495 (Text
-uid 13121,0
+uid 13122,0
 va (VaSet
 font "Arial,8,1"
 )
-xt "53350,66000,60650,67000"
-st "continous_pulser"
-blo "53350,66800"
-tm "CptNameMgr"
-)
-*496 (Text
-uid 13122,0
-va (VaSet
-font "Arial,8,1"
-)
-xt "53350,67000,55150,68000"
+xt "62350,67000,64150,68000"
 st "U_3"
-blo "53350,67800"
+blo "62350,67800"
 tm "InstanceNameMgr"
 )
@@ -14646,5 +14628,5 @@
 font "Courier New,8,0"
 )
-xt "44000,60200,71500,61000"
+xt "53000,60200,80500,61000"
 st "MINIMAL_TRIGGER_WAIT_TIME = 250000    ( integer )  "
 )
@@ -14666,5 +14648,5 @@
 fg "49152,49152,49152"
 )
-xt "51250,63250,52750,64750"
+xt "60250,63250,61750,64750"
 iconName "VhdlFileViewIcon.png"
 iconMaskName "VhdlFileViewIcon.msk"
@@ -14677,5 +14659,5 @@
 archFileType "UNKNOWN"
 )
-*497 (Net
+*496 (Net
 uid 13157,0
 decl (Decl
@@ -14696,5 +14678,5 @@
 )
 )
-*498 (Net
+*497 (Net
 uid 13163,0
 decl (Decl
@@ -14718,5 +14700,5 @@
 )
 )
-*499 (Net
+*498 (Net
 uid 13206,0
 decl (Decl
@@ -14736,5 +14718,5 @@
 )
 )
-*500 (Net
+*499 (Net
 uid 13208,0
 decl (Decl
@@ -14754,11 +14736,11 @@
 )
 )
-*501 (MWC
+*500 (MWC
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 optionalChildren [
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 va (VaSet
 )
-xt "64000,70000,67400,71000"
+xt "60000,70000,63400,71000"
 st "wiz_busy"
-blo "64000,70800"
+blo "60000,70800"
 tm "WireNameMgr"
 )
@@ -17711,5 +17689,5 @@
 on &155
 )
-*617 (Wire
+*616 (Wire
 uid 2476,0
 shape (OrthoPolyLine
@@ -17718,10 +17696,8 @@
 vasetType 3
 )
-xt "63750,71000,87250,72000"
-pts [
-"63750,72000"
-"84000,72000"
-"84000,71000"
-"87250,71000"
+xt "59750,72000,87250,72000"
+pts [
+"59750,72000"
+"87250,72000"
 ]
 )
@@ -17741,7 +17717,7 @@
 va (VaSet
 )
-xt "64000,71000,69100,72000"
+xt "60000,71000,65100,72000"
 st "wiz_write_ea"
-blo "64000,71800"
+blo "60000,71800"
 tm "WireNameMgr"
 )
@@ -17749,5 +17725,5 @@
 on &156
 )
-*618 (Wire
+*617 (Wire
 uid 2482,0
 shape (OrthoPolyLine
@@ -17757,12 +17733,8 @@
 lineWidth 2
 )
-xt "63750,72000,87250,79000"
-pts [
-"63750,73000"
-"67000,73000"
-"67000,79000"
-"85000,79000"
-"85000,72000"
-"87250,72000"
+xt "59750,73000,87250,73000"
+pts [
+"59750,73000"
+"87250,73000"
 ]
 )
@@ -17783,7 +17755,7 @@
 va (VaSet
 )
-xt "64000,72000,73400,73000"
+xt "60000,72000,69400,73000"
 st "wiz_write_length : (16:0)"
-blo "64000,72800"
+blo "60000,72800"
 tm "WireNameMgr"
 )
@@ -17791,5 +17763,5 @@
 on &157
 )
-*619 (Wire
+*618 (Wire
 uid 2488,0
 shape (OrthoPolyLine
@@ -17799,10 +17771,8 @@
 lineWidth 2
 )
-xt "63750,73000,87250,74000"
-pts [
-"63750,74000"
-"84000,74000"
-"84000,73000"
-"87250,73000"
+xt "59750,74000,87250,74000"
+pts [
+"59750,74000"
+"87250,74000"
 ]
 )
@@ -17823,7 +17793,7 @@
 va (VaSet
 )
-xt "64000,73000,82800,74000"
+xt "60000,73000,78800,74000"
 st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
-blo "64000,73800"
+blo "60000,73800"
 tm "WireNameMgr"
 )
@@ -17831,5 +17801,5 @@
 on &158
 )
-*620 (Wire
+*619 (Wire
 uid 2494,0
 shape (OrthoPolyLine
@@ -17839,12 +17809,8 @@
 lineWidth 2
 )
-xt "63750,74000,87250,80000"
-pts [
-"63750,75000"
-"66000,75000"
-"66000,80000"
-"86000,80000"
-"86000,74000"
-"87250,74000"
+xt "59750,75000,87250,75000"
+pts [
+"59750,75000"
+"87250,75000"
 ]
 )
@@ -17865,7 +17831,7 @@
 va (VaSet
 )
-xt "64000,74000,75800,75000"
+xt "60000,74000,71800,75000"
 st "wiz_number_of_channels : (3:0)"
-blo "64000,74800"
+blo "60000,74800"
 tm "WireNameMgr"
 )
@@ -17873,5 +17839,5 @@
 on &159
 )
-*621 (Wire
+*620 (Wire
 uid 2500,0
 shape (OrthoPolyLine
@@ -17880,10 +17846,8 @@
 vasetType 3
 )
-xt "63750,75000,87250,76000"
-pts [
-"63750,76000"
-"84000,76000"
-"84000,75000"
-"87250,75000"
+xt "59750,76000,87250,76000"
+pts [
+"59750,76000"
+"87250,76000"
 ]
 )
@@ -17903,7 +17867,7 @@
 va (VaSet
 )
-xt "64000,75000,69500,76000"
+xt "60000,75000,65500,76000"
 st "wiz_write_end"
-blo "64000,75800"
+blo "60000,75800"
 tm "WireNameMgr"
 )
@@ -17911,5 +17875,5 @@
 on &160
 )
-*622 (Wire
+*621 (Wire
 uid 2506,0
 shape (OrthoPolyLine
@@ -17918,10 +17882,8 @@
 vasetType 3
 )
-xt "63750,76000,87250,77000"
-pts [
-"63750,77000"
-"71000,77000"
-"71000,76000"
-"87250,76000"
+xt "59750,77000,87250,77000"
+pts [
+"59750,77000"
+"87250,77000"
 ]
 )
@@ -17941,7 +17903,7 @@
 va (VaSet
 )
-xt "64000,76000,70600,77000"
+xt "60000,76000,66600,77000"
 st "wiz_write_header"
-blo "64000,76800"
+blo "60000,76800"
 tm "WireNameMgr"
 )
@@ -17949,5 +17911,5 @@
 on &161
 )
-*623 (Wire
+*622 (Wire
 uid 2576,0
 shape (OrthoPolyLine
@@ -17956,10 +17918,8 @@
 vasetType 3
 )
-xt "750,67000,31250,74000"
-pts [
-"750,67000"
-"26000,67000"
-"26000,74000"
-"31250,74000"
+xt "750,72000,27250,72000"
+pts [
+"750,72000"
+"27250,72000"
 ]
 )
@@ -17979,7 +17939,7 @@
 va (VaSet
 )
-xt "2000,66000,7300,67000"
+xt "1000,71000,6300,72000"
 st "ram_write_ea"
-blo "2000,66800"
+blo "1000,71800"
 tm "WireNameMgr"
 )
@@ -17987,5 +17947,5 @@
 on &162
 )
-*624 (Wire
+*623 (Wire
 uid 2582,0
 shape (OrthoPolyLine
@@ -17994,10 +17954,8 @@
 vasetType 3
 )
-xt "750,68000,31250,75000"
-pts [
-"750,68000"
-"25000,68000"
-"25000,75000"
-"31250,75000"
+xt "750,73000,27250,73000"
+pts [
+"750,73000"
+"27250,73000"
 ]
 )
@@ -18017,7 +17975,7 @@
 va (VaSet
 )
-xt "2000,67000,8300,68000"
+xt "1000,72000,7300,73000"
 st "ram_write_ready"
-blo "2000,67800"
+blo "1000,72800"
 tm "WireNameMgr"
 )
@@ -18025,5 +17983,5 @@
 on &163
 )
-*625 (Wire
+*624 (Wire
 uid 2588,0
 shape (OrthoPolyLine
@@ -18032,10 +17990,8 @@
 vasetType 3
 )
-xt "750,73000,31250,78000"
-pts [
-"750,73000"
-"23000,73000"
-"23000,78000"
-"31250,78000"
+xt "750,76000,27250,76000"
+pts [
+"750,76000"
+"27250,76000"
 ]
 )
@@ -18056,7 +18012,7 @@
 va (VaSet
 )
-xt "1000,72000,5800,73000"
+xt "1000,75000,5800,76000"
 st "config_start"
-blo "1000,72800"
+blo "1000,75800"
 tm "WireNameMgr"
 )
@@ -18064,5 +18020,5 @@
 on &164
 )
-*626 (Wire
+*625 (Wire
 uid 2594,0
 shape (OrthoPolyLine
@@ -18071,10 +18027,8 @@
 vasetType 3
 )
-xt "750,75000,31250,80000"
-pts [
-"750,75000"
-"21000,75000"
-"21000,80000"
-"31250,80000"
+xt "750,78000,27250,78000"
+pts [
+"750,78000"
+"27250,78000"
 ]
 )
@@ -18094,7 +18048,7 @@
 va (VaSet
 )
-xt "1000,74000,6100,75000"
+xt "1000,77000,6100,78000"
 st "config_ready"
-blo "1000,74800"
+blo "1000,77800"
 tm "WireNameMgr"
 )
@@ -18102,5 +18056,5 @@
 on &165
 )
-*627 (Wire
+*626 (Wire
 uid 2600,0
 shape (OrthoPolyLine
@@ -18109,10 +18063,8 @@
 vasetType 3
 )
-xt "750,77000,31250,81000"
-pts [
-"750,77000"
-"20000,77000"
-"20000,81000"
-"31250,81000"
+xt "750,79000,27250,79000"
+pts [
+"750,79000"
+"27250,79000"
 ]
 )
@@ -18132,7 +18084,7 @@
 va (VaSet
 )
-xt "1000,76000,4000,77000"
+xt "1000,78000,4000,79000"
 st "roi_max"
-blo "1000,76800"
+blo "1000,78800"
 tm "WireNameMgr"
 )
@@ -18140,5 +18092,5 @@
 on &166
 )
-*628 (Wire
+*627 (Wire
 uid 2642,0
 shape (OrthoPolyLine
@@ -18148,10 +18100,8 @@
 lineWidth 2
 )
-xt "750,78000,31250,82000"
-pts [
-"750,78000"
-"19000,78000"
-"19000,82000"
-"31250,82000"
+xt "750,80000,27250,80000"
+pts [
+"750,80000"
+"27250,80000"
 ]
 )
@@ -18172,7 +18122,7 @@
 va (VaSet
 )
-xt "1000,77000,10100,78000"
+xt "1000,79000,10100,80000"
 st "package_length : (15:0)"
-blo "1000,77800"
+blo "1000,79800"
 tm "WireNameMgr"
 )
@@ -18180,5 +18130,5 @@
 on &167
 )
-*629 (Wire
+*628 (Wire
 uid 2778,0
 shape (OrthoPolyLine
@@ -18218,5 +18168,5 @@
 on &168
 )
-*630 (Wire
+*629 (Wire
 uid 2786,0
 shape (OrthoPolyLine
@@ -18258,8 +18208,8 @@
 on &191
 )
-*631 (Wire
+*630 (Wire
 uid 3888,0
 optionalChildren [
-*632 (BdJunction
+*631 (BdJunction
 uid 4230,0
 ps "OnConnectorStrategy"
@@ -18273,5 +18223,5 @@
 )
 )
-*633 (BdJunction
+*632 (BdJunction
 uid 4244,0
 ps "OnConnectorStrategy"
@@ -18324,5 +18274,5 @@
 on &187
 )
-*634 (Wire
+*633 (Wire
 uid 3984,0
 shape (OrthoPolyLine
@@ -18365,5 +18315,5 @@
 on &185
 )
-*635 (Wire
+*634 (Wire
 uid 4042,0
 shape (OrthoPolyLine
@@ -18403,5 +18353,5 @@
 on &190
 )
-*636 (Wire
+*635 (Wire
 uid 4226,0
 shape (OrthoPolyLine
@@ -18419,5 +18369,5 @@
 )
 start &189
-end &632
+end &631
 sat 32
 eat 32
@@ -18443,5 +18393,5 @@
 on &187
 )
-*637 (Wire
+*636 (Wire
 uid 4240,0
 shape (OrthoPolyLine
@@ -18459,5 +18409,5 @@
 )
 start &335
-end &633
+end &632
 sat 32
 eat 32
@@ -18482,5 +18432,5 @@
 on &187
 )
-*638 (Wire
+*637 (Wire
 uid 4272,0
 shape (OrthoPolyLine
@@ -18520,5 +18470,5 @@
 on &192
 )
-*639 (Wire
+*638 (Wire
 uid 4401,0
 shape (OrthoPolyLine
@@ -18558,5 +18508,5 @@
 on &194
 )
-*640 (Wire
+*639 (Wire
 uid 4407,0
 shape (OrthoPolyLine
@@ -18596,5 +18546,5 @@
 on &195
 )
-*641 (Wire
+*640 (Wire
 uid 4419,0
 shape (OrthoPolyLine
@@ -18634,5 +18584,5 @@
 on &196
 )
-*642 (Wire
+*641 (Wire
 uid 4537,0
 shape (OrthoPolyLine
@@ -18642,10 +18592,8 @@
 lineWidth 2
 )
-xt "-27000,66000,-21750,67000"
+xt "-26000,67000,-21750,67000"
 pts [
 "-21750,67000"
-"-25000,67000"
-"-25000,66000"
-"-27000,66000"
+"-26000,67000"
 ]
 )
@@ -18676,5 +18624,5 @@
 on &197
 )
-*643 (Wire
+*642 (Wire
 uid 4545,0
 shape (OrthoPolyLine
@@ -18713,5 +18661,5 @@
 on &198
 )
-*644 (Wire
+*643 (Wire
 uid 4671,0
 shape (OrthoPolyLine
@@ -18751,5 +18699,5 @@
 on &201
 )
-*645 (Wire
+*644 (Wire
 uid 4679,0
 shape (OrthoPolyLine
@@ -18789,5 +18737,5 @@
 on &202
 )
-*646 (Wire
+*645 (Wire
 uid 4687,0
 shape (OrthoPolyLine
@@ -18827,5 +18775,5 @@
 on &203
 )
-*647 (Wire
+*646 (Wire
 uid 4695,0
 shape (OrthoPolyLine
@@ -18865,5 +18813,5 @@
 on &204
 )
-*648 (Wire
+*647 (Wire
 uid 4743,0
 shape (OrthoPolyLine
@@ -18903,8 +18851,8 @@
 on &209
 )
-*649 (Wire
+*648 (Wire
 uid 4757,0
 optionalChildren [
-*650 (BdJunction
+*649 (BdJunction
 uid 6076,0
 ps "OnConnectorStrategy"
@@ -18934,5 +18882,5 @@
 )
 start &211
-end *651 (BdJunction
+end *650 (BdJunction
 uid 6080,0
 ps "OnConnectorStrategy"
@@ -18968,5 +18916,5 @@
 on &188
 )
-*652 (Wire
+*651 (Wire
 uid 4948,0
 shape (OrthoPolyLine
@@ -19006,5 +18954,5 @@
 on &230
 )
-*653 (Wire
+*652 (Wire
 uid 4962,0
 shape (OrthoPolyLine
@@ -19044,5 +18992,5 @@
 on &232
 )
-*654 (Wire
+*653 (Wire
 uid 5090,0
 shape (OrthoPolyLine
@@ -19083,5 +19031,5 @@
 on &252
 )
-*655 (Wire
+*654 (Wire
 uid 5098,0
 shape (OrthoPolyLine
@@ -19117,5 +19065,5 @@
 on &253
 )
-*656 (Wire
+*655 (Wire
 uid 5106,0
 shape (OrthoPolyLine
@@ -19154,5 +19102,5 @@
 on &254
 )
-*657 (Wire
+*656 (Wire
 uid 5114,0
 shape (OrthoPolyLine
@@ -19193,5 +19141,5 @@
 on &255
 )
-*658 (Wire
+*657 (Wire
 uid 5122,0
 shape (OrthoPolyLine
@@ -19230,5 +19178,5 @@
 on &256
 )
-*659 (Wire
+*658 (Wire
 uid 5130,0
 shape (OrthoPolyLine
@@ -19267,8 +19215,8 @@
 on &257
 )
-*660 (Wire
+*659 (Wire
 uid 5138,0
 optionalChildren [
-*661 (BdJunction
+*660 (BdJunction
 uid 5400,0
 ps "OnConnectorStrategy"
@@ -19320,5 +19268,5 @@
 on &171
 )
-*662 (Wire
+*661 (Wire
 uid 5146,0
 shape (OrthoPolyLine
@@ -19356,5 +19304,5 @@
 on &258
 )
-*663 (Wire
+*662 (Wire
 uid 5168,0
 shape (OrthoPolyLine
@@ -19363,11 +19311,13 @@
 vasetType 3
 )
-xt "18000,88000,31250,88000"
+xt "18000,86000,27250,88000"
 pts [
 "18000,88000"
-"31250,88000"
-]
-)
-start &661
+"24000,88000"
+"24000,86000"
+"27250,86000"
+]
+)
+start &660
 end &147
 sat 32
@@ -19384,7 +19334,7 @@
 va (VaSet
 )
-xt "28000,87000,31400,88000"
+xt "24000,85000,27400,86000"
 st "roi_array"
-blo "28000,87800"
+blo "24000,85800"
 tm "WireNameMgr"
 )
@@ -19392,5 +19342,5 @@
 on &171
 )
-*664 (Wire
+*663 (Wire
 uid 5184,0
 shape (OrthoPolyLine
@@ -19429,5 +19379,5 @@
 on &259
 )
-*665 (Wire
+*664 (Wire
 uid 5190,0
 shape (OrthoPolyLine
@@ -19466,5 +19416,5 @@
 on &260
 )
-*666 (Wire
+*665 (Wire
 uid 5222,0
 shape (OrthoPolyLine
@@ -19506,5 +19456,5 @@
 on &261
 )
-*667 (Wire
+*666 (Wire
 uid 5404,0
 shape (OrthoPolyLine
@@ -19543,5 +19493,5 @@
 on &264
 )
-*668 (Wire
+*667 (Wire
 uid 5474,0
 shape (OrthoPolyLine
@@ -19580,5 +19530,5 @@
 on &262
 )
-*669 (Wire
+*668 (Wire
 uid 5480,0
 shape (OrthoPolyLine
@@ -19617,5 +19567,5 @@
 on &263
 )
-*670 (Wire
+*669 (Wire
 uid 5582,0
 shape (OrthoPolyLine
@@ -19652,20 +19602,8 @@
 on &187
 )
-*671 (Wire
+*670 (Wire
 uid 5602,0
 optionalChildren [
-&651
-*672 (BdJunction
-uid 6086,0
-ps "OnConnectorStrategy"
-shape (Circle
-uid 6087,0
-va (VaSet
-vasetType 1
-)
-xt "27600,46600,28400,47400"
-radius 400
-)
-)
+&650
 ]
 shape (OrthoPolyLine
@@ -19709,5 +19647,5 @@
 on &188
 )
-*673 (Wire
+*671 (Wire
 uid 5626,0
 shape (OrthoPolyLine
@@ -19745,5 +19683,5 @@
 on &266
 )
-*674 (Wire
+*672 (Wire
 uid 5634,0
 shape (OrthoPolyLine
@@ -19783,5 +19721,5 @@
 on &265
 )
-*675 (Wire
+*673 (Wire
 uid 5646,0
 shape (OrthoPolyLine
@@ -19819,5 +19757,5 @@
 on &185
 )
-*676 (Wire
+*674 (Wire
 uid 5745,0
 shape (OrthoPolyLine
@@ -19857,5 +19795,5 @@
 on &276
 )
-*677 (Wire
+*675 (Wire
 uid 5805,0
 shape (OrthoPolyLine
@@ -19891,5 +19829,5 @@
 on &187
 )
-*678 (Wire
+*676 (Wire
 uid 5813,0
 shape (OrthoPolyLine
@@ -19929,5 +19867,5 @@
 on &293
 )
-*679 (Wire
+*677 (Wire
 uid 5821,0
 shape (OrthoPolyLine
@@ -19967,5 +19905,5 @@
 on &294
 )
-*680 (Wire
+*678 (Wire
 uid 5829,0
 shape (OrthoPolyLine
@@ -20005,5 +19943,5 @@
 on &295
 )
-*681 (Wire
+*679 (Wire
 uid 5837,0
 shape (OrthoPolyLine
@@ -20045,5 +19983,5 @@
 on &296
 )
-*682 (Wire
+*680 (Wire
 uid 5950,0
 shape (OrthoPolyLine
@@ -20083,5 +20021,5 @@
 on &301
 )
-*683 (Wire
+*681 (Wire
 uid 5962,0
 shape (OrthoPolyLine
@@ -20121,5 +20059,5 @@
 on &302
 )
-*684 (Wire
+*682 (Wire
 uid 6002,0
 shape (OrthoPolyLine
@@ -20159,5 +20097,5 @@
 on &304
 )
-*685 (Wire
+*683 (Wire
 uid 6008,0
 shape (OrthoPolyLine
@@ -20197,5 +20135,5 @@
 on &303
 )
-*686 (Wire
+*684 (Wire
 uid 6018,0
 shape (OrthoPolyLine
@@ -20204,10 +20142,8 @@
 vasetType 3
 )
-xt "750,74000,31250,79000"
-pts [
-"750,74000"
-"22000,74000"
-"22000,79000"
-"31250,79000"
+xt "750,77000,27250,77000"
+pts [
+"750,77000"
+"27250,77000"
 ]
 )
@@ -20227,7 +20163,7 @@
 va (VaSet
 )
-xt "1000,73000,8200,74000"
+xt "1000,76000,8200,77000"
 st "config_started_mm"
-blo "1000,73800"
+blo "1000,76800"
 tm "WireNameMgr"
 )
@@ -20235,5 +20171,5 @@
 on &305
 )
-*687 (Wire
+*685 (Wire
 uid 6064,0
 shape (OrthoPolyLine
@@ -20270,5 +20206,5 @@
 on &258
 )
-*688 (Wire
+*686 (Wire
 uid 6072,0
 shape (OrthoPolyLine
@@ -20286,5 +20222,5 @@
 )
 start &366
-end &650
+end &649
 sat 32
 eat 32
@@ -20309,44 +20245,5 @@
 on &188
 )
-*689 (Wire
-uid 6082,0
-shape (OrthoPolyLine
-uid 6083,0
-va (VaSet
-vasetType 3
-lineColor "0,32896,0"
-)
-xt "28000,47000,31250,71000"
-pts [
-"31250,71000"
-"28000,71000"
-"28000,47000"
-]
-)
-start &134
-end &672
-sat 32
-eat 32
-stc 0
-st 0
-sf 1
-si 0
-tg (WTG
-uid 6084,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 6085,0
-va (VaSet
-)
-xt "28000,70000,31100,71000"
-st "CLK_25"
-blo "28000,70800"
-tm "WireNameMgr"
-)
-)
-on &188
-)
-*690 (Wire
+*687 (Wire
 uid 6160,0
 shape (OrthoPolyLine
@@ -20386,5 +20283,5 @@
 on &306
 )
-*691 (Wire
+*688 (Wire
 uid 6276,0
 shape (OrthoPolyLine
@@ -20393,8 +20290,8 @@
 vasetType 3
 )
-xt "-61000,67000,-52750,67000"
-pts [
-"-61000,67000"
-"-52750,67000"
+xt "-61000,68000,-52750,68000"
+pts [
+"-61000,68000"
+"-52750,68000"
 ]
 )
@@ -20412,7 +20309,7 @@
 va (VaSet
 )
-xt "-58000,66000,-53500,67000"
+xt "-58000,67000,-53500,68000"
 st "CLK_25_PS"
-blo "-58000,66800"
+blo "-58000,67800"
 tm "WireNameMgr"
 )
@@ -20420,5 +20317,5 @@
 on &185
 )
-*692 (Wire
+*689 (Wire
 uid 6362,0
 shape (OrthoPolyLine
@@ -20433,5 +20330,5 @@
 ]
 )
-start &546
+start &545
 end &309
 ss 0
@@ -20459,5 +20356,5 @@
 on &308
 )
-*693 (Wire
+*690 (Wire
 uid 6452,0
 shape (OrthoPolyLine
@@ -20495,5 +20392,5 @@
 on &310
 )
-*694 (Wire
+*691 (Wire
 uid 6540,0
 shape (OrthoPolyLine
@@ -20509,5 +20406,5 @@
 )
 start &315
-end &477
+end &476
 sat 32
 eat 32
@@ -20532,5 +20429,5 @@
 on &329
 )
-*695 (Wire
+*692 (Wire
 uid 6548,0
 shape (OrthoPolyLine
@@ -20569,5 +20466,5 @@
 on &310
 )
-*696 (Wire
+*693 (Wire
 uid 8416,0
 shape (OrthoPolyLine
@@ -20576,10 +20473,8 @@
 vasetType 3
 )
-xt "63750,77000,87250,78000"
-pts [
-"63750,78000"
-"84000,78000"
-"84000,77000"
-"87250,77000"
+xt "59750,78000,87250,78000"
+pts [
+"59750,78000"
+"87250,78000"
 ]
 )
@@ -20599,7 +20494,7 @@
 va (VaSet
 )
-xt "64000,77000,67000,78000"
+xt "60000,77000,63000,78000"
 st "wiz_ack"
-blo "64000,77800"
+blo "60000,77800"
 tm "WireNameMgr"
 )
@@ -20607,5 +20502,5 @@
 on &341
 )
-*697 (Wire
+*694 (Wire
 uid 8732,0
 shape (OrthoPolyLine
@@ -20645,5 +20540,5 @@
 on &360
 )
-*698 (Wire
+*695 (Wire
 uid 8738,0
 shape (OrthoPolyLine
@@ -20681,5 +20576,5 @@
 on &361
 )
-*699 (Wire
+*696 (Wire
 uid 8752,0
 shape (OrthoPolyLine
@@ -20716,5 +20611,5 @@
 on &361
 )
-*700 (Wire
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 shape (OrthoPolyLine
@@ -20754,5 +20649,5 @@
 on &362
 )
-*701 (Wire
+*698 (Wire
 uid 9233,0
 shape (OrthoPolyLine
@@ -20789,5 +20684,5 @@
 on &376
 )
-*702 (Wire
+*699 (Wire
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 shape (OrthoPolyLine
@@ -20824,5 +20719,5 @@
 on &377
 )
-*703 (Wire
+*700 (Wire
 uid 9253,0
 shape (OrthoPolyLine
@@ -20858,5 +20753,5 @@
 on &376
 )
-*704 (Wire
+*701 (Wire
 uid 9261,0
 shape (OrthoPolyLine
@@ -20892,5 +20787,5 @@
 on &377
 )
-*705 (Wire
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 uid 9943,0
 shape (OrthoPolyLine
@@ -20927,5 +20822,5 @@
 on &378
 )
-*706 (Wire
+*703 (Wire
 uid 9951,0
 shape (OrthoPolyLine
@@ -20962,5 +20857,5 @@
 on &379
 )
-*707 (Wire
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 uid 10010,0
 shape (OrthoPolyLine
@@ -21000,5 +20895,5 @@
 on &398
 )
-*708 (Wire
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 uid 10018,0
 shape (OrthoPolyLine
@@ -21036,5 +20931,5 @@
 on &379
 )
-*709 (Wire
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 uid 10036,0
 shape (OrthoPolyLine
@@ -21070,5 +20965,5 @@
 on &378
 )
-*710 (Wire
+*707 (Wire
 uid 10194,0
 shape (OrthoPolyLine
@@ -21110,5 +21005,5 @@
 on &399
 )
-*711 (Wire
+*708 (Wire
 uid 10202,0
 shape (OrthoPolyLine
@@ -21148,5 +21043,5 @@
 on &400
 )
-*712 (Wire
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 shape (OrthoPolyLine
@@ -21181,7 +21076,7 @@
 )
 )
-on &499
-)
-*713 (Wire
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+)
+*710 (Wire
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 shape (OrthoPolyLine
@@ -21219,5 +21114,5 @@
 on &402
 )
-*714 (Wire
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 uid 10304,0
 shape (OrthoPolyLine
@@ -21255,5 +21150,5 @@
 on &403
 )
-*715 (Wire
+*712 (Wire
 uid 10310,0
 shape (OrthoPolyLine
@@ -21291,5 +21186,5 @@
 on &404
 )
-*716 (Wire
+*713 (Wire
 uid 10316,0
 shape (OrthoPolyLine
@@ -21329,5 +21224,5 @@
 on &405
 )
-*717 (Wire
+*714 (Wire
 uid 10322,0
 shape (OrthoPolyLine
@@ -21367,5 +21262,5 @@
 on &406
 )
-*718 (Wire
+*715 (Wire
 uid 10431,0
 shape (OrthoPolyLine
@@ -21404,57 +21299,5 @@
 on &401
 )
-*719 (Wire
-uid 10439,0
-optionalChildren [
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-uid 12639,0
-ps "OnConnectorStrategy"
-shape (Circle
-uid 12640,0
-va (VaSet
-vasetType 1
-)
-xt "-54400,71600,-53600,72400"
-radius 400
-)
-)
-]
-shape (OrthoPolyLine
-uid 10440,0
-va (VaSet
-vasetType 3
-)
-xt "-54000,68000,-21750,72000"
-pts [
-"-21750,72000"
-"-54000,72000"
-"-54000,68000"
-"-52750,68000"
-]
-)
-start &30
-end &125
-sat 32
-eat 32
-st 0
-sf 1
-si 0
-tg (WTG
-uid 10441,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 10442,0
-va (VaSet
-)
-xt "-25750,71000,-21150,72000"
-st "trigger_out"
-blo "-25750,71800"
-tm "WireNameMgr"
-)
-)
-on &431
-)
-*721 (Wire
+*716 (Wire
 uid 10467,0
 shape (OrthoPolyLine
@@ -21463,10 +21306,8 @@
 vasetType 3
 )
-xt "750,69000,31250,76000"
-pts [
-"31250,76000"
-"24000,76000"
-"24000,69000"
-"750,69000"
+xt "750,74000,27250,74000"
+pts [
+"27250,74000"
+"750,74000"
 ]
 )
@@ -21487,13 +21328,13 @@
 va (VaSet
 )
-xt "2000,68000,9800,69000"
+xt "1000,73000,8800,74000"
 st "ram_write_ready_ack"
-blo "2000,68800"
+blo "1000,73800"
 tm "WireNameMgr"
 )
 )
-on &432
-)
-*722 (Wire
+on &431
+)
+*717 (Wire
 uid 10629,0
 shape (OrthoPolyLine
@@ -21528,7 +21369,7 @@
 )
 )
-on &433
-)
-*723 (Wire
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+)
+*718 (Wire
 uid 10637,0
 shape (OrthoPolyLine
@@ -21563,7 +21404,7 @@
 )
 )
-on &434
-)
-*724 (Wire
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+)
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 uid 10685,0
 shape (OrthoPolyLine
@@ -21578,5 +21419,5 @@
 ]
 )
-end &447
+end &446
 sat 16
 eat 32
@@ -21598,7 +21439,7 @@
 )
 )
-on &434
-)
-*725 (Wire
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+)
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 shape (OrthoPolyLine
@@ -21613,5 +21454,5 @@
 ]
 )
-end &448
+end &447
 sat 16
 eat 32
@@ -21633,7 +21474,7 @@
 )
 )
-on &433
-)
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+)
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 shape (OrthoPolyLine
@@ -21649,5 +21490,5 @@
 ]
 )
-end &442
+end &441
 sat 16
 eat 32
@@ -21671,5 +21512,5 @@
 on &187
 )
-*727 (Wire
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 uid 10707,0
 shape (OrthoPolyLine
@@ -21684,5 +21525,5 @@
 ]
 )
-end &446
+end &445
 sat 16
 eat 32
@@ -21704,7 +21545,7 @@
 )
 )
-on &453
-)
-*728 (Wire
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+)
+*723 (Wire
 uid 10723,0
 shape (OrthoPolyLine
@@ -21719,6 +21560,6 @@
 ]
 )
-start &443
-end &436
+start &442
+end &435
 sat 32
 eat 32
@@ -21742,7 +21583,7 @@
 )
 )
-on &435
-)
-*729 (Wire
+on &434
+)
+*724 (Wire
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 shape (OrthoPolyLine
@@ -21757,6 +21598,6 @@
 ]
 )
-start &444
-end &438
+start &443
+end &437
 sat 32
 eat 32
@@ -21780,7 +21621,7 @@
 )
 )
-on &437
-)
-*730 (Wire
+on &436
+)
+*725 (Wire
 uid 10751,0
 shape (OrthoPolyLine
@@ -21795,6 +21636,6 @@
 ]
 )
-start &445
-end &440
+start &444
+end &439
 sat 32
 eat 32
@@ -21818,7 +21659,7 @@
 )
 )
-on &439
-)
-*731 (Wire
+on &438
+)
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 uid 11405,0
 shape (OrthoPolyLine
@@ -21854,7 +21695,7 @@
 )
 )
-on &453
-)
-*732 (Wire
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+)
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 shape (OrthoPolyLine
@@ -21889,7 +21730,7 @@
 )
 )
-on &454
-)
-*733 (Wire
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+)
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 shape (OrthoPolyLine
@@ -21904,5 +21745,5 @@
 ]
 )
-end &461
+end &460
 sat 16
 eat 32
@@ -21925,7 +21766,7 @@
 )
 )
-on &454
-)
-*734 (Wire
+on &453
+)
+*729 (Wire
 uid 12306,0
 shape (OrthoPolyLine
@@ -21941,5 +21782,5 @@
 )
 start &411
-end &459
+end &458
 sat 32
 eat 32
@@ -21963,44 +21804,7 @@
 )
 )
-on &473
-)
-*735 (Wire
-uid 12635,0
-shape (OrthoPolyLine
-uid 12636,0
-va (VaSet
-vasetType 3
-)
-xt "-55250,72000,-54000,72000"
-pts [
-"-54000,72000"
-"-55250,72000"
-]
-)
-start &720
-end &476
-sat 32
-eat 32
-stc 0
-st 0
-sf 1
-si 0
-tg (WTG
-uid 12637,0
-ps "ConnStartEndStrategy"
-stg "STSignalDisplayStrategy"
-f (Text
-uid 12638,0
-va (VaSet
-)
-xt "-54000,71000,-49400,72000"
-st "trigger_out"
-blo "-54000,71800"
-tm "WireNameMgr"
-)
-)
-on &431
-)
-*736 (Wire
+on &472
+)
+*730 (Wire
 uid 12643,0
 shape (OrthoPolyLine
@@ -22017,6 +21821,6 @@
 ]
 )
-start &456
-end &475
+start &455
+end &474
 sat 32
 eat 32
@@ -22040,7 +21844,7 @@
 )
 )
-on &484
-)
-*737 (Wire
+on &483
+)
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 uid 12649,0
 shape (OrthoPolyLine
@@ -22052,10 +21856,9 @@
 pts [
 "-21750,74000"
-"-38000,74000"
 "-55250,74000"
 ]
 )
 start &66
-end &478
+end &477
 sat 32
 eat 32
@@ -22077,7 +21880,7 @@
 )
 )
-on &485
-)
-*738 (Wire
+on &484
+)
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 shape (OrthoPolyLine
@@ -22094,5 +21897,5 @@
 )
 start &67
-end &479
+end &478
 sat 32
 eat 32
@@ -22114,7 +21917,7 @@
 )
 )
-on &486
-)
-*739 (Wire
+on &485
+)
+*733 (Wire
 uid 12687,0
 shape (OrthoPolyLine
@@ -22132,5 +21935,5 @@
 ]
 )
-end &480
+end &479
 sat 16
 eat 32
@@ -22154,5 +21957,5 @@
 on &188
 )
-*740 (Wire
+*734 (Wire
 uid 12707,0
 shape (OrthoPolyLine
@@ -22167,6 +21970,6 @@
 ]
 )
-start &449
-end &488
+start &448
+end &487
 sat 32
 eat 32
@@ -22190,7 +21993,7 @@
 )
 )
-on &487
-)
-*741 (Wire
+on &486
+)
+*735 (Wire
 uid 13143,0
 shape (OrthoPolyLine
@@ -22199,11 +22002,11 @@
 vasetType 3
 )
-xt "63750,62000,69000,62000"
-pts [
-"69000,62000"
-"63750,62000"
-]
-)
-end &490
+xt "72750,62000,78000,62000"
+pts [
+"78000,62000"
+"72750,62000"
+]
+)
+end &489
 sat 16
 eat 32
@@ -22219,7 +22022,7 @@
 va (VaSet
 )
-xt "65000,61000,68100,62000"
+xt "74000,61000,77100,62000"
 st "CLK_25"
-blo "65000,61800"
+blo "74000,61800"
 tm "WireNameMgr"
 )
@@ -22227,5 +22030,5 @@
 on &188
 )
-*742 (Wire
+*736 (Wire
 uid 13159,0
 shape (OrthoPolyLine
@@ -22234,14 +22037,14 @@
 vasetType 3
 )
-xt "63750,63000,87250,67000"
+xt "72750,63000,87250,67000"
 pts [
 "87250,67000"
-"79000,67000"
-"79000,63000"
-"63750,63000"
+"77000,67000"
+"77000,63000"
+"72750,63000"
 ]
 )
 start &114
-end &491
+end &490
 sat 32
 eat 32
@@ -22263,7 +22066,7 @@
 )
 )
-on &497
-)
-*743 (Wire
+on &496
+)
+*737 (Wire
 uid 13165,0
 shape (OrthoPolyLine
@@ -22273,14 +22076,14 @@
 lineWidth 2
 )
-xt "63750,64000,87250,68000"
+xt "72750,64000,87250,68000"
 pts [
 "87250,68000"
-"78000,68000"
-"78000,64000"
-"63750,64000"
+"76000,68000"
+"76000,64000"
+"72750,64000"
 ]
 )
 start &115
-end &492
+end &491
 sat 32
 eat 32
@@ -22303,7 +22106,7 @@
 )
 )
-on &498
-)
-*744 (Wire
+on &497
+)
+*738 (Wire
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 shape (OrthoPolyLine
@@ -22312,12 +22115,12 @@
 vasetType 3
 )
-xt "42000,62000,50250,62000"
-pts [
-"50250,62000"
-"42000,62000"
-]
-)
-start &493
-end &502
+xt "54000,62000,59250,62000"
+pts [
+"59250,62000"
+"54000,62000"
+]
+)
+start &492
+end &501
 sat 32
 eat 32
@@ -22333,13 +22136,13 @@
 va (VaSet
 )
-xt "46250,61000,49450,62000"
+xt "53250,61000,56450,62000"
 st "trigger1"
-blo "46250,61800"
+blo "53250,61800"
 tm "WireNameMgr"
 )
 )
-on &500
-)
-*745 (Wire
+on &499
+)
+*739 (Wire
 uid 13216,0
 shape (OrthoPolyLine
@@ -22348,11 +22151,11 @@
 vasetType 3
 )
-xt "42000,60000,45000,60000"
-pts [
-"45000,60000"
-"42000,60000"
-]
-)
-end &507
+xt "54000,60000,59000,60000"
+pts [
+"59000,60000"
+"54000,60000"
+]
+)
+end &506
 sat 16
 eat 32
@@ -22368,15 +22171,14 @@
 uid 13221,0
 va (VaSet
-isHidden 1
-)
-xt "43000,59000,47800,60000"
+)
+xt "54000,59000,58800,60000"
 st "s_trigger_0"
-blo "43000,59800"
+blo "54000,59800"
 tm "WireNameMgr"
 )
 )
-on &499
-)
-*746 (Wire
+on &498
+)
+*740 (Wire
 uid 13224,0
 shape (OrthoPolyLine
@@ -22385,11 +22187,11 @@
 vasetType 3
 )
-xt "33000,61000,36000,61000"
-pts [
-"36000,61000"
-"33000,61000"
-]
-)
-start &504
+xt "45000,61000,48000,61000"
+pts [
+"48000,61000"
+"45000,61000"
+]
+)
+start &503
 sat 32
 eat 16
@@ -22405,9 +22207,8 @@
 uid 13229,0
 va (VaSet
-isHidden 1
-)
-xt "34000,60000,37600,61000"
+)
+xt "45000,60000,48600,61000"
 st "s_trigger"
-blo "34000,60800"
+blo "45000,60800"
 tm "WireNameMgr"
 )
@@ -22415,5 +22216,5 @@
 on &401
 )
-*747 (Wire
+*741 (Wire
 uid 13695,0
 shape (OrthoPolyLine
@@ -22429,5 +22230,5 @@
 ]
 )
-start &524
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 sat 32
@@ -22452,7 +22253,7 @@
 )
 )
-on &525
-)
-*748 (Wire
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+)
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 uid 13921,0
 shape (OrthoPolyLine
@@ -22491,5 +22292,5 @@
 on &71
 )
-*749 (Wire
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 shape (OrthoPolyLine
@@ -22528,5 +22329,5 @@
 on &122
 )
-*750 (Wire
+*744 (Wire
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 shape (OrthoPolyLine
@@ -22541,6 +22342,6 @@
 ]
 )
-start &526
-end &532
+start &525
+end &531
 sat 32
 eat 32
@@ -22563,7 +22364,7 @@
 )
 )
-on &527
-)
-*751 (Wire
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+)
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 shape (OrthoPolyLine
@@ -22579,5 +22380,5 @@
 ]
 )
-start &528
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 sat 32
 eat 16
@@ -22601,7 +22402,7 @@
 )
 )
-on &529
-)
-*752 (Wire
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+)
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 uid 14427,0
 shape (OrthoPolyLine
@@ -22616,5 +22417,5 @@
 ]
 )
-end &531
+end &530
 sat 16
 eat 32
@@ -22638,5 +22439,5 @@
 on &187
 )
-*753 (Wire
+*747 (Wire
 uid 14479,0
 shape (OrthoPolyLine
@@ -22651,6 +22452,6 @@
 ]
 )
-start &534
-end &540
+start &533
+end &539
 sat 32
 eat 32
@@ -22674,7 +22475,7 @@
 )
 )
-on &539
-)
-*754 (Wire
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+)
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 uid 14493,0
 shape (OrthoPolyLine
@@ -22689,6 +22490,6 @@
 ]
 )
-start &535
-end &542
+start &534
+end &541
 sat 32
 eat 32
@@ -22712,7 +22513,7 @@
 )
 )
-on &541
-)
-*755 (Wire
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+)
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 shape (OrthoPolyLine
@@ -22728,6 +22529,6 @@
 ]
 )
-start &533
-end &544
+start &532
+end &543
 sat 32
 eat 32
@@ -22752,7 +22553,7 @@
 )
 )
-on &543
-)
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+)
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@@ -22768,5 +22569,5 @@
 )
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-end &549
+end &548
 sat 32
 eat 32
@@ -22788,7 +22589,7 @@
 )
 )
-on &596
-)
-*757 (Wire
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+)
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 shape (OrthoPolyLine
@@ -22803,6 +22604,6 @@
 ]
 )
-start &551
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+end &588
 sat 32
 eat 32
@@ -22826,7 +22627,7 @@
 )
 )
-on &597
-)
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+)
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@@ -22842,6 +22643,6 @@
 ]
 )
-start &587
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+start &586
+end &563
 sat 32
 eat 32
@@ -22864,7 +22665,7 @@
 )
 )
-on &598
-)
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+)
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@@ -22879,5 +22680,5 @@
 ]
 )
-end &579
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 es 0
 sat 16
@@ -22902,7 +22703,7 @@
 )
 )
-on &541
-)
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+)
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@@ -22917,5 +22718,5 @@
 ]
 )
-end &581
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 es 0
 sat 16
@@ -22940,5 +22741,40 @@
 )
 )
-on &539
+on &538
+)
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+va (VaSet
+vasetType 3
+)
+xt "29000,64000,29000,67250"
+pts [
+"29000,64000"
+"29000,67250"
+]
+)
+end &134
+sat 16
+eat 32
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+si 0
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+stg "STSignalDisplayStrategy"
+f (Text
+uid 15384,0
+va (VaSet
+)
+xt "29000,64000,32100,65000"
+st "CLK_25"
+blo "29000,64800"
+tm "WireNameMgr"
+)
+)
+on &188
 )
 ]
@@ -22954,9 +22790,9 @@
 color "26368,26368,26368"
 )
-packageList *761 (PackageList
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 stg "VerticalLayoutStrategy"
 textVec [
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 va (VaSet
@@ -22967,5 +22803,5 @@
 blo "-163000,-15200"
 )
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 va (VaSet
@@ -22992,5 +22828,5 @@
 stg "VerticalLayoutStrategy"
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 va (VaSet
@@ -23002,5 +22838,5 @@
 blo "20000,800"
 )
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 va (VaSet
@@ -23012,5 +22848,5 @@
 blo "20000,1800"
 )
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 va (VaSet
@@ -23022,5 +22858,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
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 va (VaSet
@@ -23032,5 +22868,5 @@
 blo "20000,4800"
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 va (VaSet
@@ -23040,5 +22876,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
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 va (VaSet
@@ -23050,5 +22886,5 @@
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 )
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 va (VaSet
@@ -23062,5 +22898,5 @@
 )
 windowSize "0,0,1281,1024"
-viewArea "-85665,-1810,-19291,52928"
+viewArea "-65668,47481,1175,102606"
 cachedDiagramExtent "-174000,-25425,428157,346294"
 pageSetupInfo (PageSetupInfo
@@ -23088,5 +22924,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
-lastUid 15174,0
+lastUid 15388,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -23150,5 +22986,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*771 (Text
+*766 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23159,5 +22995,5 @@
 tm "BdLibraryNameMgr"
 )
-*772 (Text
+*767 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23168,5 +23004,5 @@
 tm "BlkNameMgr"
 )
-*773 (Text
+*768 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23219,5 +23055,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*774 (Text
+*769 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23227,5 +23063,5 @@
 blo "550,4300"
 )
-*775 (Text
+*770 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23235,5 +23071,5 @@
 blo "550,5300"
 )
-*776 (Text
+*771 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23284,5 +23120,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*777 (Text
+*772 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23293,5 +23129,5 @@
 tm "BdLibraryNameMgr"
 )
-*778 (Text
+*773 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23302,5 +23138,5 @@
 tm "CptNameMgr"
 )
-*779 (Text
+*774 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23356,5 +23192,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*780 (Text
+*775 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23364,5 +23200,5 @@
 blo "500,4300"
 )
-*781 (Text
+*776 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23372,5 +23208,5 @@
 blo "500,5300"
 )
-*782 (Text
+*777 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23417,5 +23253,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*783 (Text
+*778 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23425,5 +23261,5 @@
 blo "50,4300"
 )
-*784 (Text
+*779 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23433,5 +23269,5 @@
 blo "50,5300"
 )
-*785 (Text
+*780 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23474,5 +23310,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*786 (Text
+*781 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23483,5 +23319,5 @@
 tm "HdlTextNameMgr"
 )
-*787 (Text
+*782 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23886,5 +23722,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*788 (Text
+*783 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23894,5 +23730,5 @@
 blo "14100,20800"
 )
-*789 (MLText
+*784 (MLText
 va (VaSet
 )
@@ -23946,5 +23782,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*790 (Text
+*785 (Text
 va (VaSet
 font "Arial,8,1"
@@ -23954,5 +23790,5 @@
 blo "14100,20800"
 )
-*791 (MLText
+*786 (MLText
 va (VaSet
 )
@@ -24079,7 +23915,7 @@
 font "Arial,8,1"
 )
-xt "-174000,107600,-169300,108600"
+xt "-174000,106800,-169300,107800"
 st "Post User:"
-blo "-174000,108400"
+blo "-174000,107600"
 )
 postUserText (MLText
@@ -24094,44 +23930,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 299,0
+suid 300,0
 usingSuid 1
-emptyRow *792 (LEmptyRow
+emptyRow *787 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*793 (RefLabelRowHdr
-)
-*794 (TitleRowHdr
-)
-*795 (FilterRowHdr
-)
-*796 (RefLabelColHdr
+*788 (RefLabelRowHdr
+)
+*789 (TitleRowHdr
+)
+*790 (FilterRowHdr
+)
+*791 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*797 (RowExpandColHdr
+*792 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*798 (GroupColHdr
+*793 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*799 (NameColHdr
+*794 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*800 (ModeColHdr
+*795 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*801 (TypeColHdr
+*796 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*802 (BoundsColHdr
+*797 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*803 (InitColHdr
+*798 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*804 (EolColHdr
+*799 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*805 (LeafLogPort
+*800 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24147,5 +23983,5 @@
 uid 516,0
 )
-*806 (LeafLogPort
+*801 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24160,5 +23996,5 @@
 uid 518,0
 )
-*807 (LeafLogPort
+*802 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24173,5 +24009,5 @@
 uid 520,0
 )
-*808 (LeafLogPort
+*803 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24186,5 +24022,5 @@
 uid 530,0
 )
-*809 (LeafLogPort
+*804 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24199,5 +24035,5 @@
 uid 532,0
 )
-*810 (LeafLogPort
+*805 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24212,5 +24048,5 @@
 uid 534,0
 )
-*811 (LeafLogPort
+*806 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24225,5 +24061,5 @@
 uid 536,0
 )
-*812 (LeafLogPort
+*807 (LeafLogPort
 port (LogicalPort
 m 2
@@ -24238,5 +24074,5 @@
 uid 538,0
 )
-*813 (LeafLogPort
+*808 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24251,5 +24087,5 @@
 uid 540,0
 )
-*814 (LeafLogPort
+*809 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24264,5 +24100,5 @@
 uid 542,0
 )
-*815 (LeafLogPort
+*810 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24277,5 +24113,5 @@
 uid 546,0
 )
-*816 (LeafLogPort
+*811 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24288,5 +24124,5 @@
 uid 548,0
 )
-*817 (LeafLogPort
+*812 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24300,5 +24136,5 @@
 uid 1455,0
 )
-*818 (LeafLogPort
+*813 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24313,5 +24149,5 @@
 uid 1457,0
 )
-*819 (LeafLogPort
+*814 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24325,5 +24161,5 @@
 uid 1694,0
 )
-*820 (LeafLogPort
+*815 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24341,5 +24177,5 @@
 uid 1993,0
 )
-*821 (LeafLogPort
+*816 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24356,5 +24192,5 @@
 uid 2305,0
 )
-*822 (LeafLogPort
+*817 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24369,5 +24205,5 @@
 uid 2510,0
 )
-*823 (LeafLogPort
+*818 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24383,5 +24219,5 @@
 uid 2512,0
 )
-*824 (LeafLogPort
+*819 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24398,5 +24234,5 @@
 uid 2514,0
 )
-*825 (LeafLogPort
+*820 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24414,5 +24250,5 @@
 uid 2516,0
 )
-*826 (LeafLogPort
+*821 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24429,5 +24265,5 @@
 uid 2518,0
 )
-*827 (LeafLogPort
+*822 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24443,5 +24279,5 @@
 uid 2520,0
 )
-*828 (LeafLogPort
+*823 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -24457,5 +24293,5 @@
 uid 2522,0
 )
-*829 (LeafLogPort
+*824 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24469,5 +24305,5 @@
 uid 2604,0
 )
-*830 (LeafLogPort
+*825 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24482,5 +24318,5 @@
 uid 2606,0
 )
-*831 (LeafLogPort
+*826 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24495,5 +24331,5 @@
 uid 2608,0
 )
-*832 (LeafLogPort
+*827 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24507,5 +24343,5 @@
 uid 2610,0
 )
-*833 (LeafLogPort
+*828 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24519,5 +24355,5 @@
 uid 2612,0
 )
-*834 (LeafLogPort
+*829 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24532,5 +24368,5 @@
 uid 2646,0
 )
-*835 (LeafLogPort
+*830 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24545,5 +24381,5 @@
 uid 2812,0
 )
-*836 (LeafLogPort
+*831 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24557,5 +24393,5 @@
 uid 2962,0
 )
-*837 (LeafLogPort
+*832 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24569,5 +24405,5 @@
 uid 3902,0
 )
-*838 (LeafLogPort
+*833 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24581,5 +24417,5 @@
 uid 4070,0
 )
-*839 (LeafLogPort
+*834 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24593,5 +24429,5 @@
 uid 4212,0
 )
-*840 (LeafLogPort
+*835 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24604,5 +24440,5 @@
 uid 4234,0
 )
-*841 (LeafLogPort
+*836 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24616,5 +24452,5 @@
 uid 4262,0
 )
-*842 (LeafLogPort
+*837 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24627,5 +24463,5 @@
 uid 4276,0
 )
-*843 (LeafLogPort
+*838 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24640,5 +24476,5 @@
 uid 4563,0
 )
-*844 (LeafLogPort
+*839 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24652,5 +24488,5 @@
 uid 4565,0
 )
-*845 (LeafLogPort
+*840 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24665,5 +24501,5 @@
 uid 4569,0
 )
-*846 (LeafLogPort
+*841 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24679,5 +24515,5 @@
 uid 4585,0
 )
-*847 (LeafLogPort
+*842 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24692,5 +24528,5 @@
 uid 4587,0
 )
-*848 (LeafLogPort
+*843 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24703,5 +24539,5 @@
 uid 4733,0
 )
-*849 (LeafLogPort
+*844 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24714,5 +24550,5 @@
 uid 4735,0
 )
-*850 (LeafLogPort
+*845 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24725,5 +24561,5 @@
 uid 4737,0
 )
-*851 (LeafLogPort
+*846 (LeafLogPort
 port (LogicalPort
 decl (Decl
@@ -24736,5 +24572,5 @@
 uid 4739,0
 )
-*852 (LeafLogPort
+*847 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24748,5 +24584,5 @@
 uid 4749,0
 )
-*853 (LeafLogPort
+*848 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24761,5 +24597,5 @@
 uid 4974,0
 )
-*854 (LeafLogPort
+*849 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24774,5 +24610,5 @@
 uid 4976,0
 )
-*855 (LeafLogPort
+*850 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24787,5 +24623,5 @@
 uid 5198,0
 )
-*856 (LeafLogPort
+*851 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24799,5 +24635,5 @@
 uid 5200,0
 )
-*857 (LeafLogPort
+*852 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24811,5 +24647,5 @@
 uid 5202,0
 )
-*858 (LeafLogPort
+*853 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24824,5 +24660,5 @@
 uid 5204,0
 )
-*859 (LeafLogPort
+*854 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24836,5 +24672,5 @@
 uid 5206,0
 )
-*860 (LeafLogPort
+*855 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24848,5 +24684,5 @@
 uid 5208,0
 )
-*861 (LeafLogPort
+*856 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24860,5 +24696,5 @@
 uid 5210,0
 )
-*862 (LeafLogPort
+*857 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24872,5 +24708,5 @@
 uid 5212,0
 )
-*863 (LeafLogPort
+*858 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24884,5 +24720,5 @@
 uid 5214,0
 )
-*864 (LeafLogPort
+*859 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24899,5 +24735,5 @@
 uid 5226,0
 )
-*865 (LeafLogPort
+*860 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24911,5 +24747,5 @@
 uid 5502,0
 )
-*866 (LeafLogPort
+*861 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24923,5 +24759,5 @@
 uid 5504,0
 )
-*867 (LeafLogPort
+*862 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24935,5 +24771,5 @@
 uid 5600,0
 )
-*868 (LeafLogPort
+*863 (LeafLogPort
 port (LogicalPort
 lang 10
@@ -24949,5 +24785,5 @@
 uid 5642,0
 )
-*869 (LeafLogPort
+*864 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24961,5 +24797,5 @@
 uid 5644,0
 )
-*870 (LeafLogPort
+*865 (LeafLogPort
 port (LogicalPort
 m 4
@@ -24974,5 +24810,5 @@
 uid 5751,0
 )
-*871 (LeafLogPort
+*866 (LeafLogPort
 port (LogicalPort
 m 1
@@ -24986,5 +24822,5 @@
 uid 5867,0
 )
-*872 (LeafLogPort
+*867 (LeafLogPort
 port (LogicalPort
 m 2
@@ -25000,5 +24836,5 @@
 uid 5869,0
 )
-*873 (LeafLogPort
+*868 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25012,5 +24848,5 @@
 uid 5871,0
 )
-*874 (LeafLogPort
+*869 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25025,5 +24861,5 @@
 uid 5873,0
 )
-*875 (LeafLogPort
+*870 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25038,5 +24874,5 @@
 uid 5966,0
 )
-*876 (LeafLogPort
+*871 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25050,5 +24886,5 @@
 uid 5968,0
 )
-*877 (LeafLogPort
+*872 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25063,5 +24899,5 @@
 uid 6022,0
 )
-*878 (LeafLogPort
+*873 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25076,5 +24912,5 @@
 uid 6024,0
 )
-*879 (LeafLogPort
+*874 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25088,5 +24924,5 @@
 uid 6026,0
 )
-*880 (LeafLogPort
+*875 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25101,5 +24937,5 @@
 uid 6172,0
 )
-*881 (LeafLogPort
+*876 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25116,5 +24952,5 @@
 uid 6374,0
 )
-*882 (LeafLogPort
+*877 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25129,5 +24965,5 @@
 uid 6464,0
 )
-*883 (LeafLogPort
+*878 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25142,5 +24978,5 @@
 uid 6554,0
 )
-*884 (LeafLogPort
+*879 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -25155,5 +24991,5 @@
 uid 8420,0
 )
-*885 (LeafLogPort
+*880 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25167,5 +25003,5 @@
 uid 8758,0
 )
-*886 (LeafLogPort
+*881 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25179,5 +25015,5 @@
 uid 8760,0
 )
-*887 (LeafLogPort
+*882 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25192,5 +25028,5 @@
 uid 9018,0
 )
-*888 (LeafLogPort
+*883 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25207,5 +25043,5 @@
 uid 9247,0
 )
-*889 (LeafLogPort
+*884 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25223,5 +25059,5 @@
 uid 9249,0
 )
-*890 (LeafLogPort
+*885 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25238,5 +25074,5 @@
 uid 10024,0
 )
-*891 (LeafLogPort
+*886 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25251,5 +25087,5 @@
 uid 10026,0
 )
-*892 (LeafLogPort
+*887 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25264,5 +25100,5 @@
 uid 10028,0
 )
-*893 (LeafLogPort
+*888 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25280,5 +25116,5 @@
 uid 10208,0
 )
-*894 (LeafLogPort
+*889 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25296,5 +25132,5 @@
 uid 10210,0
 )
-*895 (LeafLogPort
+*890 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25308,5 +25144,5 @@
 uid 10294,0
 )
-*896 (LeafLogPort
+*891 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25320,5 +25156,5 @@
 uid 10334,0
 )
-*897 (LeafLogPort
+*892 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25333,5 +25169,5 @@
 uid 10336,0
 )
-*898 (LeafLogPort
+*893 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25346,5 +25182,5 @@
 uid 10338,0
 )
-*899 (LeafLogPort
+*894 (LeafLogPort
 port (LogicalPort
 m 4
@@ -25360,5 +25196,5 @@
 uid 10340,0
 )
-*900 (LeafLogPort
+*895 (LeafLogPort
 port (LogicalPort
 m 1
@@ -25373,19 +25209,5 @@
 uid 10342,0
 )
-*901 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
-n "trigger_out"
-t "std_logic"
-preAdd 0
-posAdd 0
-o 120
-suid 240,0
-)
-)
-uid 10473,0
-)
-*902 (LeafLogPort
+*896 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -25404,80 +25226,80 @@
 uid 10475,0
 )
+*897 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "socks_connected"
+t "std_logic"
+o 111
+suid 243,0
+)
+)
+uid 10763,0
+)
+*898 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "socks_waiting"
+t "std_logic"
+o 112
+suid 244,0
+)
+)
+uid 10765,0
+)
+*899 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "green"
+t "std_logic"
+o 34
+suid 248,0
+)
+)
+uid 10767,0
+)
+*900 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "amber"
+t "std_logic"
+o 29
+suid 249,0
+)
+)
+uid 10769,0
+)
+*901 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "red"
+t "std_logic"
+o 39
+suid 250,0
+)
+)
+uid 10771,0
+)
+*902 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "drs_readout_started"
+t "std_logic"
+o 87
+suid 252,0
+)
+)
+uid 11411,0
+)
 *903 (LeafLogPort
 port (LogicalPort
 m 4
 decl (Decl
-n "socks_connected"
-t "std_logic"
-o 111
-suid 243,0
-)
-)
-uid 10763,0
-)
-*904 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
-n "socks_waiting"
-t "std_logic"
-o 112
-suid 244,0
-)
-)
-uid 10765,0
-)
-*905 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "green"
-t "std_logic"
-o 34
-suid 248,0
-)
-)
-uid 10767,0
-)
-*906 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "amber"
-t "std_logic"
-o 29
-suid 249,0
-)
-)
-uid 10769,0
-)
-*907 (LeafLogPort
-port (LogicalPort
-m 1
-decl (Decl
-n "red"
-t "std_logic"
-o 39
-suid 250,0
-)
-)
-uid 10771,0
-)
-*908 (LeafLogPort
-port (LogicalPort
-m 4
-decl (Decl
-n "drs_readout_started"
-t "std_logic"
-o 87
-suid 252,0
-)
-)
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-*1062 (MRCItem
-litem &803
+*1055 (MRCItem
+litem &798
 pos 6
 dimension 50
 uid 80,0
 )
-*1063 (MRCItem
-litem &804
+*1056 (MRCItem
+litem &799
 pos 7
 dimension 290
@@ -26601,39 +26417,39 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *1064 (LEmptyRow
+emptyRow *1057 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*1065 (RefLabelRowHdr
-)
-*1066 (TitleRowHdr
-)
-*1067 (FilterRowHdr
-)
-*1068 (RefLabelColHdr
+*1058 (RefLabelRowHdr
+)
+*1059 (TitleRowHdr
+)
+*1060 (FilterRowHdr
+)
+*1061 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*1069 (RowExpandColHdr
+*1062 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*1070 (GroupColHdr
+*1063 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*1071 (NameColHdr
+*1064 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*1072 (TypeColHdr
+*1065 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*1073 (InitColHdr
+*1066 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*1074 (PragmaColHdr
+*1067 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*1075 (EolColHdr
+*1068 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
-*1076 (LogGeneric
+*1069 (LogGeneric
 generic (GiElement
 name "RAMADDRWIDTH64b"
@@ -26650,5 +26466,5 @@
 uid 95,0
 optionalChildren [
-*1077 (Sheet
+*1070 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -26667,6 +26483,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *1078 (MRCItem
-litem &1064
+emptyMRCItem *1071 (MRCItem
+litem &1057
 pos 1
 dimension 20
@@ -26674,18 +26490,18 @@
 uid 97,0
 optionalChildren [
-*1079 (MRCItem
-litem &1065
+*1072 (MRCItem
+litem &1058
 pos 0
 dimension 20
 uid 98,0
 )
-*1080 (MRCItem
-litem &1066
+*1073 (MRCItem
+litem &1059
 pos 1
 dimension 23
 uid 99,0
 )
-*1081 (MRCItem
-litem &1067
+*1074 (MRCItem
+litem &1060
 pos 2
 hidden 1
@@ -26693,6 +26509,6 @@
 uid 100,0
 )
-*1082 (MRCItem
-litem &1076
+*1075 (MRCItem
+litem &1069
 pos 0
 dimension 20
@@ -26710,42 +26526,42 @@
 uid 101,0
 optionalChildren [
-*1083 (MRCItem
-litem &1068
+*1076 (MRCItem
+litem &1061
 pos 0
 dimension 20
 uid 102,0
 )
-*1084 (MRCItem
-litem &1070
+*1077 (MRCItem
+litem &1063
 pos 1
 dimension 50
 uid 103,0
 )
-*1085 (MRCItem
-litem &1071
+*1078 (MRCItem
+litem &1064
 pos 2
 dimension 186
 uid 104,0
 )
-*1086 (MRCItem
-litem &1072
+*1079 (MRCItem
+litem &1065
 pos 3
 dimension 96
 uid 105,0
 )
-*1087 (MRCItem
-litem &1073
+*1080 (MRCItem
+litem &1066
 pos 4
 dimension 50
 uid 106,0
 )
-*1088 (MRCItem
-litem &1074
+*1081 (MRCItem
+litem &1067
 pos 5
 dimension 50
 uid 107,0
 )
-*1089 (MRCItem
-litem &1075
+*1082 (MRCItem
+litem &1068
 pos 6
 dimension 80
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb	(revision 10138)
@@ -1199,17 +1199,17 @@
 (vvPair
 variable "date"
-value "04.02.2011"
+value "08.02.2011"
 )
 (vvPair
 variable "day"
-value "Fr"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Freitag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "04"
+value "08"
 )
 (vvPair
@@ -1351,5 +1351,5 @@
 (vvPair
 variable "time"
-value "12:56:44"
+value "11:06:22"
 )
 (vvPair
@@ -4000,5 +4000,5 @@
 )
 )
-lastUid 5873,0
+lastUid 5942,0
 okToSyncOnLoad 1
 OkToSyncGenericsOnLoad 1
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb	(revision 10137)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb	(revision 10138)
@@ -347,4 +347,6 @@
 t "std_logic_vector"
 b "(7 downto 0)"
+prec "-- read/write configRAM"
+preAdd 0
 o 25
 suid 24,0
@@ -358,6 +360,6 @@
 n "config_busy"
 t "std_logic"
-prec "-- --"
-preAdd 0
+preAdd 0
+posAdd 0
 o 31
 suid 25,0
@@ -385,4 +387,5 @@
 n "config_started"
 t "std_logic"
+posAdd 0
 o 24
 suid 27,0
@@ -410,5 +413,7 @@
 n "new_config"
 t "std_logic"
-prec "--"
+prec "-- FAD configuration signals:
+------------------------------------------------------------------------------
+-- start entire configuration chain"
 preAdd 0
 o 23
@@ -441,5 +446,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 35
+o 36
 suid 31,0
 i "'0'"
@@ -457,5 +462,5 @@
 preAdd 0
 posAdd 0
-o 36
+o 37
 suid 32,0
 i "'0'"
@@ -485,5 +490,5 @@
 eolc "-- default DWRITE HIGH."
 posAdd 0
-o 37
+o 38
 suid 35,0
 i "'1'"
@@ -498,7 +503,13 @@
 n "ps_direction"
 t "std_logic"
+prec "------------------------------------------------------------------------------
+
+-- ADC CLK generator, is able to shift phase with respect to X_50M
+-- these signals control the behavior of the digital clock manager (DCM)
+------------------------------------------------------------------------------"
 eolc "-- default phase shift upwards"
-posAdd 0
-o 38
+preAdd 0
+posAdd 0
+o 40
 suid 36,0
 i "'1'"
@@ -516,5 +527,5 @@
 preAdd 0
 posAdd 0
-o 39
+o 41
 suid 37,0
 i "'0'"
@@ -531,5 +542,5 @@
 eolc "-- pulse this to reset the variable phase shift"
 posAdd 0
-o 40
+o 42
 suid 38,0
 i "'0'"
@@ -546,5 +557,5 @@
 eolc "-- default SRCLK on."
 posAdd 0
-o 41
+o 39
 suid 39,0
 i "'1'"
@@ -558,5 +569,4 @@
 n "config_rw_ack"
 t "std_logic"
-prec "-- --"
 preAdd 0
 posAdd 0
@@ -572,5 +582,4 @@
 n "config_rw_ready"
 t "std_logic"
-prec "-- --"
 preAdd 0
 posAdd 0
@@ -587,4 +596,6 @@
 n "socks_connected"
 t "std_logic"
+posc "------------------------------------------------------------------------------"
+posAdd 0
 o 44
 suid 42,0
@@ -599,4 +610,9 @@
 n "socks_waiting"
 t "std_logic"
+prec "------------------------------------------------------------------------------
+
+-- signals used to control FAD LED bahavior:
+-- one of the three LEDs is used for com-status info
+------------------------------------------------------------------------------"
 preAdd 0
 o 43
@@ -612,7 +628,12 @@
 n "trigger_enable"
 t "std_logic"
+prec "------------------------------------------------------------------------------
+
+-- user controllable enable signals
+------------------------------------------------------------------------------"
 eolc "-- default triggers are NOT accepted"
-posAdd 0
-o 42
+preAdd 0
+posAdd 0
+o 35
 suid 44,0
 i "'0'"
@@ -656,4 +677,9 @@
 t "std_logic_vector"
 b "(1 downto 0)"
+prec "------------------------------------------------------------------------------
+
+-- MAC/IP calculation signals:
+------------------------------------------------------------------------------"
+preAdd 0
 o 32
 suid 48,0
@@ -680,4 +706,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
+posAdd 0
 o 34
 suid 50,0
@@ -1114,5 +1141,5 @@
 value "14"
 )
-uid 1329,0
+uid 1354,0
 )
 ]
@@ -1170,5 +1197,5 @@
 pos 0
 dimension 20
-uid 1330,0
+uid 1355,0
 )
 ]
@@ -1283,17 +1310,17 @@
 (vvPair
 variable "date"
-value "27.01.2011"
+value "08.02.2011"
 )
 (vvPair
 variable "day"
-value "Do"
+value "Di"
 )
 (vvPair
 variable "day_long"
-value "Donnerstag"
+value "Dienstag"
 )
 (vvPair
 variable "dd"
-value "27"
+value "08"
 )
 (vvPair
@@ -1359,5 +1386,5 @@
 (vvPair
 variable "mm"
-value "01"
+value "02"
 )
 (vvPair
@@ -1367,9 +1394,9 @@
 (vvPair
 variable "month"
-value "Jan"
+value "Feb"
 )
 (vvPair
 variable "month_long"
-value "Januar"
+value "Februar"
 )
 (vvPair
@@ -1403,5 +1430,5 @@
 (vvPair
 variable "task_ModelSimPath"
-value "<TBD>"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -1435,5 +1462,5 @@
 (vvPair
 variable "time"
-value "15:14:14"
+value "10:18:42"
 )
 (vvPair
@@ -2161,8 +2188,5 @@
 xt "200,31000,13900,35000"
 st "
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
+
 "
 tm "CommentText"
@@ -2439,6 +2463,7 @@
 font "Courier New,8,0"
 )
-xt "2000,36800,33000,37600"
-st "config_addr       : OUT    std_logic_vector (7 downto 0) ;
+xt "2000,38400,33000,40000"
+st "-- read/write configRAM
+config_addr       : OUT    std_logic_vector (7 downto 0) ;
 "
 )
@@ -2449,4 +2474,6 @@
 t "std_logic_vector"
 b "(7 downto 0)"
+prec "-- read/write configRAM"
+preAdd 0
 o 25
 suid 24,0
@@ -2485,7 +2512,6 @@
 font "Courier New,8,0"
 )
-xt "2000,43200,23000,44800"
-st "-- --
-config_busy       : IN     std_logic  ;
+xt "2000,44000,23000,44800"
+st "config_busy       : IN     std_logic  ;
 "
 )
@@ -2494,6 +2520,6 @@
 n "config_busy"
 t "std_logic"
-prec "-- --"
-preAdd 0
+preAdd 0
+posAdd 0
 o 31
 suid 25,0
@@ -2533,5 +2559,5 @@
 font "Courier New,8,0"
 )
-xt "2000,37600,43000,38400"
+xt "2000,40000,43000,40800"
 st "config_data       : INOUT  std_logic_vector (15 downto 0) := (others => 'Z') ;
 "
@@ -2580,5 +2606,5 @@
 font "Courier New,8,0"
 )
-xt "2000,36000,23000,36800"
+xt "2000,37600,23000,38400"
 st "config_started    : IN     std_logic  ;
 "
@@ -2588,4 +2614,5 @@
 n "config_started"
 t "std_logic"
+posAdd 0
 o 24
 suid 27,0
@@ -2625,5 +2652,5 @@
 font "Courier New,8,0"
 )
-xt "2000,38400,37000,39200"
+xt "2000,40800,37000,41600"
 st "config_wr_en      : OUT    std_logic                      := '0' ;
 "
@@ -2672,6 +2699,8 @@
 font "Courier New,8,0"
 )
-xt "2000,34400,37000,36000"
-st "--
+xt "2000,34400,43000,37600"
+st "-- FAD configuration signals:
+------------------------------------------------------------------------------
+-- start entire configuration chain
 new_config        : OUT    std_logic                      := '0' ;
 "
@@ -2682,5 +2711,7 @@
 n "new_config"
 t "std_logic"
-prec "--"
+prec "-- FAD configuration signals:
+------------------------------------------------------------------------------
+-- start entire configuration chain"
 preAdd 0
 o 23
@@ -2722,5 +2753,5 @@
 font "Courier New,8,0"
 )
-xt "2000,39200,37000,40000"
+xt "2000,41600,37000,42400"
 st "config_rd_en      : OUT    std_logic                      := '0' ;
 "
@@ -2770,5 +2801,5 @@
 font "Courier New,8,0"
 )
-xt "2000,47200,50500,48000"
+xt "2000,54400,50500,55200"
 st "denable           : OUT    std_logic                      := '0' ; -- default domino wave off
 "
@@ -2781,5 +2812,5 @@
 eolc "-- default domino wave off"
 posAdd 0
-o 35
+o 36
 suid 31,0
 i "'0'"
@@ -2819,5 +2850,5 @@
 font "Courier New,8,0"
 )
-xt "2000,48000,48500,48800"
+xt "2000,55200,48500,56000"
 st "dwrite_enable     : OUT    std_logic                      := '0' ; -- default DWRITE low.
 "
@@ -2831,5 +2862,5 @@
 preAdd 0
 posAdd 0
-o 36
+o 37
 suid 32,0
 i "'0'"
@@ -2916,5 +2947,5 @@
 font "Courier New,8,0"
 )
-xt "2000,48800,49000,49600"
+xt "2000,56000,49000,56800"
 st "sclk_enable       : OUT    std_logic                      := '1' ; -- default DWRITE HIGH.
 "
@@ -2927,5 +2958,5 @@
 eolc "-- default DWRITE HIGH."
 posAdd 0
-o 37
+o 38
 suid 35,0
 i "'1'"
@@ -2965,6 +2996,11 @@
 font "Courier New,8,0"
 )
-xt "2000,49600,52500,50400"
-st "ps_direction      : OUT    std_logic                      := '1' ; -- default phase shift upwards
+xt "2000,57600,52500,62400"
+st "------------------------------------------------------------------------------
+
+-- ADC CLK generator, is able to shift phase with respect to X_50M
+-- these signals control the behavior of the digital clock manager (DCM)
+------------------------------------------------------------------------------
+ps_direction      : OUT    std_logic                      := '1' ; -- default phase shift upwards
 "
 )
@@ -2974,7 +3010,13 @@
 n "ps_direction"
 t "std_logic"
+prec "------------------------------------------------------------------------------
+
+-- ADC CLK generator, is able to shift phase with respect to X_50M
+-- these signals control the behavior of the digital clock manager (DCM)
+------------------------------------------------------------------------------"
 eolc "-- default phase shift upwards"
-posAdd 0
-o 38
+preAdd 0
+posAdd 0
+o 40
 suid 36,0
 i "'1'"
@@ -3014,5 +3056,5 @@
 font "Courier New,8,0"
 )
-xt "2000,50400,53500,51200"
+xt "2000,62400,53500,63200"
 st "ps_do_phase_shift : OUT    std_logic                      := '0' ; --pulse this to phase shift once
 "
@@ -3026,5 +3068,5 @@
 preAdd 0
 posAdd 0
-o 39
+o 41
 suid 37,0
 i "'0'"
@@ -3064,5 +3106,5 @@
 font "Courier New,8,0"
 )
-xt "2000,51200,61000,52000"
+xt "2000,63200,61000,64000"
 st "ps_reset          : OUT    std_logic                      := '0' ; -- pulse this to reset the variable phase shift
 "
@@ -3075,5 +3117,5 @@
 eolc "-- pulse this to reset the variable phase shift"
 posAdd 0
-o 40
+o 42
 suid 38,0
 i "'0'"
@@ -3113,5 +3155,5 @@
 font "Courier New,8,0"
 )
-xt "2000,52000,47500,52800"
+xt "2000,56800,47500,57600"
 st "srclk_enable      : OUT    std_logic                      := '1' ; -- default SRCLK on.
 "
@@ -3124,5 +3166,5 @@
 eolc "-- default SRCLK on."
 posAdd 0
-o 41
+o 39
 suid 39,0
 i "'1'"
@@ -3161,7 +3203,6 @@
 font "Courier New,8,0"
 )
-xt "2000,40000,23000,41600"
-st "-- --
-config_rw_ack     : IN     std_logic  ;
+xt "2000,42400,23000,43200"
+st "config_rw_ack     : IN     std_logic  ;
 "
 )
@@ -3170,5 +3211,4 @@
 n "config_rw_ack"
 t "std_logic"
-prec "-- --"
 preAdd 0
 posAdd 0
@@ -3209,7 +3249,6 @@
 font "Courier New,8,0"
 )
-xt "2000,41600,23000,43200"
-st "-- --
-config_rw_ready   : IN     std_logic  ;
+xt "2000,43200,23000,44000"
+st "config_rw_ready   : IN     std_logic  ;
 "
 )
@@ -3218,5 +3257,4 @@
 n "config_rw_ready"
 t "std_logic"
-prec "-- --"
 preAdd 0
 posAdd 0
@@ -3258,6 +3296,7 @@
 font "Courier New,8,0"
 )
-xt "2000,54400,22000,55200"
+xt "2000,68800,43000,70400"
 st "socks_connected   : OUT    std_logic 
+------------------------------------------------------------------------------
 "
 )
@@ -3267,4 +3306,6 @@
 n "socks_connected"
 t "std_logic"
+posc "------------------------------------------------------------------------------"
+posAdd 0
 o 44
 suid 42,0
@@ -3304,6 +3345,11 @@
 font "Courier New,8,0"
 )
-xt "2000,53600,23000,54400"
-st "socks_waiting     : OUT    std_logic  ;
+xt "2000,64000,43000,68800"
+st "------------------------------------------------------------------------------
+
+-- signals used to control FAD LED bahavior:
+-- one of the three LEDs is used for com-status info
+------------------------------------------------------------------------------
+socks_waiting     : OUT    std_logic  ;
 "
 )
@@ -3313,4 +3359,9 @@
 n "socks_waiting"
 t "std_logic"
+prec "------------------------------------------------------------------------------
+
+-- signals used to control FAD LED bahavior:
+-- one of the three LEDs is used for com-status info
+------------------------------------------------------------------------------"
 preAdd 0
 o 43
@@ -3351,6 +3402,10 @@
 font "Courier New,8,0"
 )
-xt "2000,52800,55500,53600"
-st "trigger_enable    : OUT    std_logic                      := '0' ; -- default triggers are NOT accepted
+xt "2000,50400,55500,54400"
+st "------------------------------------------------------------------------------
+
+-- user controllable enable signals
+------------------------------------------------------------------------------
+trigger_enable    : OUT    std_logic                      := '0' ; -- default triggers are NOT accepted
 "
 )
@@ -3360,7 +3415,12 @@
 n "trigger_enable"
 t "std_logic"
+prec "------------------------------------------------------------------------------
+
+-- user controllable enable signals
+------------------------------------------------------------------------------"
 eolc "-- default triggers are NOT accepted"
-posAdd 0
-o 42
+preAdd 0
+posAdd 0
+o 35
 suid 44,0
 i "'0'"
@@ -3496,6 +3556,10 @@
 font "Courier New,8,0"
 )
-xt "2000,44800,33000,45600"
-st "MAC_jumper        : IN     std_logic_vector (1 downto 0) ;
+xt "2000,44800,43000,48800"
+st "------------------------------------------------------------------------------
+
+-- MAC/IP calculation signals:
+------------------------------------------------------------------------------
+MAC_jumper        : IN     std_logic_vector (1 downto 0) ;
 "
 )
@@ -3505,4 +3569,9 @@
 t "std_logic_vector"
 b "(1 downto 0)"
+prec "------------------------------------------------------------------------------
+
+-- MAC/IP calculation signals:
+------------------------------------------------------------------------------"
+preAdd 0
 o 32
 suid 48,0
@@ -3541,5 +3610,5 @@
 font "Courier New,8,0"
 )
-xt "2000,45600,33000,46400"
+xt "2000,48800,33000,49600"
 st "BoardID           : IN     std_logic_vector (3 downto 0) ;
 "
@@ -3586,5 +3655,5 @@
 font "Courier New,8,0"
 )
-xt "2000,46400,33000,47200"
+xt "2000,49600,33000,50400"
 st "CrateID           : IN     std_logic_vector (1 downto 0) ;
 "
@@ -3595,4 +3664,5 @@
 t "std_logic_vector"
 b "(1 downto 0)"
+posAdd 0
 o 34
 suid 50,0
@@ -4276,7 +4346,7 @@
 font "Arial,8,1"
 )
-xt "0,55200,2400,56200"
+xt "0,70400,2400,71400"
 st "User:"
-blo "0,56000"
+blo "0,71200"
 )
 internalLabel (Text
@@ -4295,5 +4365,5 @@
 font "Courier New,8,0"
 )
-xt "2000,56200,2000,56200"
+xt "2000,71400,2000,71400"
 tm "SyDeclarativeTextMgr"
 )
@@ -4308,5 +4378,5 @@
 )
 )
-lastUid 1330,0
+lastUid 1355,0
 activeModelName "Symbol:CDM"
 )
