Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/REFCLK_counter_behavior.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/REFCLK_counter_behavior.vhd (revision 10148) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/REFCLK_counter_behavior.vhd (revision 10149) @@ -26,6 +26,6 @@ counter_result : out std_logic_vector(11 downto 0) := (others => '0'); - alarm_refclk_too_high : out std_logic := '0'; - alarm_refclk_too_low : out std_logic := '0' + alarm_refclk_too_high : out std_logic := '1'; + alarm_refclk_too_low : out std_logic := '1' ); END ENTITY REFCLK_counter; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd (revision 10148) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd (revision 10149) @@ -5,6 +5,4 @@ -- and clock_generator_variable_PS_struct.vhd -- --- --- library ieee; use ieee.std_logic_1164.all; @@ -19,5 +17,5 @@ PORT( CLK : IN std_logic; - rst : in std_logic; --asynch in of DCM + rst : out std_logic := '0'; --asynch in of DCM -- interface to: clock_generator_variable_PS_struct.vhd @@ -26,5 +24,5 @@ PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' PSDONE : IN std_logic; -- will pulse once, if phase shifting was done. - LOCKED : IN std_logic; + LOCKED : IN std_logic; -- when is this going high? @@ -32,5 +30,6 @@ shift_phase : IN std_logic; direction : IN std_logic; -- corresponds to 'PSINCDEC' - + reset_DCM : in std_logic; -- asynch in: orders us, to reset the DCM + -- status: shifting : OUT std_logic := '0'; @@ -72,28 +71,32 @@ architecture first_behave of phase_shifter is - constant OFFS_MIN : integer := -128; - constant OFFS_MAX : integer := 127; + constant OFFS_MIN : integer := -51; + constant OFFS_MAX : integer := 51; - type states is (INIT, READY_STATE, SHIFTING_STATE, WAITINGFORDONE); + type states is (INIT, READY_STATE, PRE_SHIFTING_STATE, SHIFTING_STATE, WAITINGFORDONE, RESET_STATE); signal state,next_state : states := INIT; signal local_direction : std_logic; signal offset_int : integer range OFFS_MIN to OFFS_MAX := 0; - - - + signal lower_limit_reached : std_logic := '0'; + signal upper_limit_reached : std_logic := '0'; + + signal reset_dcm_sr : std_logic_vector(1 downto 0) := "00"; + signal shift_phase_sr : std_logic_vector(1 downto 0) := "00"; + signal ready_int : std_logic := '0'; begin -- concurrent statements: DCM_locked <= LOCKED; +ready <= ready_int; PSCLK <= CLK; -offset <= std_logic_vector(to_signed(offset_int,8)); +offset <= LOCKED & ready_int & std_logic_vector(to_signed(offset_int,6)); -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high. + -- is this really coorect? + FSM_Registers: process(CLK, LOCKED, rst) begin - if rst = '1' then - state <= INIT; - elsif LOCKED = '0' then + if LOCKED = '0' then state <= INIT; elsif Rising_edge(CLK) then @@ -106,62 +109,94 @@ begin next_state <= state; + reset_dcm_sr <= reset_dcm_sr(1) & reset_DCM; --synch in + shift_phase_sr <= shift_phase_sr(1) & shift_phase; --synch in case state is - - -- INIT state: here the FSM is idling, when LOCKED is not HIGH. - when INIT => - ready <= '0'; - offset_int <= 0; - shifting <= '0'; - PSEN <= '0'; - if (LOCKED = '1') then - next_state <= READY_STATE; - else + -- INIT state: here the FSM is idling, when LOCKED is not HIGH. + when INIT => + rst <= '0'; + ready_int <= '0'; + shifting <= '0'; + PSEN <= '0'; + offset_int <= 0; + if (LOCKED = '1') then + next_state <= READY_STATE; + else + next_state <= INIT; + end if; + -- RESET state: when ordered to do so: DCM is reseted and FSM send back to INIT. + when RESET_STATE => + rst <= '1'; + ready_int <= '0'; + shifting <= '0'; + PSEN <= '0'; next_state <= INIT; - end if; - - -- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high - when READY_STATE => - ready <= '1'; - shifting <= '0'; - PSEN <= '0'; - if (shift_phase = '1') then - next_state <= SHIFTING_STATE; - local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high - else - next_state <= READY_STATE; - end if; - - -- SHIFTING_STATE state: PSENC is set HIGH here and set low in the next state. - when SHIFTING_STATE => - ready <= '1'; - shifting <= '1'; - PSEN <= '1'; - PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up. - next_state <= WAITINGFORDONE; - - -- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle. - when WAITINGFORDONE => - ready <= '1'; - shifting <= '1'; - PSEN <= '0'; - if (PSDONE = '1') then - next_state <= READY_STATE; - if (local_direction = '1') then - if (offset_int < OFFS_MAX) then - offset_int <= offset_int + 1; - end if; - else - if (offset_int > OFFS_MIN) then - offset_int <= offset_int - 1; - end if; - end if; - else - next_state <= WAITINGFORDONE; - end if; - + + -- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high, or + -- if reset_DCM goes high, we will reset the DCM and go back to init. + when READY_STATE => + ready_int <= '1'; + shifting <= '0'; + PSEN <= '0'; + + lower_limit_reached <='0'; + upper_limit_reached <='0'; + if (offset_int = OFFS_MIN) then + lower_limit_reached <= '1'; + elsif (offset_int = OFFS_MAX) then + upper_limit_reached <= '1'; + end if; + + if (shift_phase_sr = "01") then + local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high + next_state <= PRE_SHIFTING_STATE; + else + next_state <= READY_STATE; + end if; + + if (reset_dcm_sr = "01") then + next_state <= RESET_STATE; + end if; + + -- checks if possible to shift in asked direction. If not ... back to READY. + when PRE_SHIFTING_STATE => + ready_int <= '0'; + if (local_direction = '1' and upper_limit_reached = '1') or + (local_direction = '0' and lower_limit_reached = '1') then + next_state <= READY_STATE; + else + next_state <= SHIFTING_STATE; + end if; + + + -- SHIFTING_STATE state: PSENC is set HIGH here and set low in the next state. + when SHIFTING_STATE => + ready_int <= '0'; + shifting <= '1'; + PSEN <= '1'; + PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up. + next_state <= WAITINGFORDONE; + + -- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle. + when WAITINGFORDONE => + ready_int <= '0'; + shifting <= '1'; + PSEN <= '0'; + if (PSDONE = '1') then + next_state <= READY_STATE; + if (local_direction = '1') then + offset_int <= offset_int + 1; + else + offset_int <= offset_int - 1; + end if; + else + next_state <= WAITINGFORDONE; + end if; + + -- does this work???? + when others => + next_state <= RESET_STATE; + end case; end process; - - end first_behave;