Index: /firmware/FAD/doc/memory_manager.tex =================================================================== --- /firmware/FAD/doc/memory_manager.tex (revision 10149) +++ /firmware/FAD/doc/memory_manager.tex (revision 10150) @@ -185,33 +185,35 @@ 0x2002 & REFCLK cntr 10 & REFCLK cntr 32 & EVT cntr 10 & EVT cntr 32 \\ 0x2003 & TRG-GEN-DIV & TRG-GEN-No & DCM-PS-STATUS & 0x0(cid)8(bid) \\ -0x2004 & more status & more status & time10 & time32 \\ -0x2005 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ -0x2006 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ -0x2007 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ -\hline -0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ -0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ -0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ -0x200A & data adc3 & data adc2 & data adc1 & data adc0 \\ +0x2004 & DNA10 & DNA32 & DNA54 & 0x00DNA6 \\ +0x2005 & more status & more status & time10 & time32 \\ +0x2006 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ +0x2007 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ +0x2008 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ +\hline +0x2009 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ +0x200A & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ +0x200B & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ +0x200C & data adc3 & data adc2 & data adc1 & data adc0 \\ 0x20.. &&&& ... \\ -0x206D & data adc3 & data adc2 & data adc1 & data adc0 \\ +0x206F & data adc3 & data adc2 & data adc1 & data adc0 \\ \hline 0x20.. &&&& ... \\ \hline -0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 \\ -0x2340 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ -0x2341 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ -0x2342 & data adc3 & data adc2 & data adc1 & data adc0 \\ +0x23?? & 0x0039 & 0x0029 & 0x0019 & 0x0009 \\ +0x23?? & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ +0x23?? & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ +0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ 0x23.. &&&& ... \\ -0x23A5 & data adc3 & data adc2 & data adc1 & data adc0 \\ -\hline -0x23A6 & 0x0000 & 0x0000 & 0x04FE & 0x4242\\ +0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ +\hline +0x23?? & 0x0000 & 0x0000 & 0x04FE & 0x4242\\ \hline \end {tabular} - \caption{NEW word order of event in Data RAM. 64bit addressing. As of > 08.02.2011} \label{new64bitRAM} \end{table} +A detailed description is given after, next table.\\ + \newpage Which in turn changes the the word order in the 16bit address space like this @@ -221,36 +223,48 @@ address & 16bit word & description \\ \hline -0x8000 & 0xFB01 & Start Flag - fix value \\ +0x8000 & 0xFB01 & Start Flag - fix value: "FB01" \\ 0x8001 & 0xllll & package length in 16bit words \\ 0x8002 & 0xvvvv & version - deduced from SVN revision number \\ -0x8003 & 0xsssP & 12 bits for status - TBD - 4 bit showing PLLLCK status \\ \hdashline +0x8003 & 0xsssP & 12 bits for status - TBD - 4 bit showing PLLLCK status \\ +\hdashline 0x8004 & 0x00T6 & FTM trigger ID byte 6 : CRC \\ 0x8005 & 0xT5T4 & ... bytes 5 and 4 : Type 2 and Type 1\\ 0x8006 & 0xT3T2 & ... bytes 3 and 2 : TRG number high word \\ -0x8007 & 0xT1T0 & ... bytes 1 and 0 : TRG number low word \\ \hdashline +0x8007 & 0xT1T0 & ... bytes 1 and 0 : TRG number low word \\ +\hdashline 0x8008 & 0xev32 & FAD event counter high word \\ 0x8009 & 0xev10 & FAD event counter low word -- should be equal to T3T2T1T0\\ 0x800A & 0xRC32 & REFCLK counter high word \\ -0x800B & 0xRC10 & REFCLK counter low word \\ \hdashline +0x800B & 0xRC10 & REFCLK counter low word \\ +\hdashline 0x800C & 0x0(cid)8(bid) & Board ID \\ 0x800D & DCM-PS & status of ADC clock phase shifter , value and locked-bit\\ 0x800E & TRG-GEN-No& Number of Triggers to generare, when 'trigger continous' issued \\ -0x800F & TRG-GEN-DIV& continous trigger generator clock prescaler \\ \hdashline -0x8010 & timer32 & timer high word \\ -0x8011 & timer10 & timer low word \\ -0x8012 & more status1 & reserved for status info; high word \\ -0x8013 & more status0 & reserved for status info; low word \\ \hdashline -0x8014 & 0xttt0 & temperature sensor next to DRS 0 \\ -0x8015 & 0xttt1 & temperature sensor next to DRS 1 \\ -0x8016 & 0xttt2 & temperature sensor next to DRS 2 \\ -0x8017 & 0xttt3 & temperature sensor next to DRS 3 \\ \hdashline -0x8018 & 0xdac0 & setting of DAC channel A \\ -0x8019 & 0xdac1 & setting of DAC channel B \\ -0x801A & 0xdac2 & setting of DAC channel C \\ -0x801B & 0xdac3 & setting of DAC channel D \\ \hdashline -0x801C & 0xdac4 & setting of DAC channel E \\ -0x801D & 0xdac5 & setting of DAC channel F \\ -0x801E & 0xdac6 & setting of DAC channel G \\ -0x801F & 0xdac7 & setting of DAC channel H \\ +0x800F & TRG-GEN-DIV& continous trigger generator clock prescaler \\ +\hdashline +0x8010 & 0x00 DNA6 & MSB of DNA \\ +0x8011 & DNA54 & ... DNA ... \\ +0x8012 & DNA32 & ... DNA ... \\ +0x8013 & DNA10 & LSB of DNA \\ +\hdashline +0x8014 & timer32 & timer high word \\ +0x8015 & timer10 & timer low word \\ +0x8016 & more status1 & reserved for status info; high word \\ +0x8017 & more status0 & reserved for status info; low word \\ +\hdashline +0x8018 & 0xttt0 & temperature sensor next to DRS 0 \\ +0x8019 & 0xttt1 & temperature sensor next to DRS 1 \\ +0x801A & 0xttt2 & temperature sensor next to DRS 2 \\ +0x801B & 0xttt3 & temperature sensor next to DRS 3 \\ +\hdashline +0x801C & 0xdac0 & setting of DAC channel A \\ +0x801D & 0xdac1 & setting of DAC channel B \\ +0x801E & 0xdac2 & setting of DAC channel C \\ +0x801F & 0xdac3 & setting of DAC channel D \\ +\hdashline +0x8020 & 0xdac4 & setting of DAC channel E \\ +0x8021 & 0xdac5 & setting of DAC channel F \\ +0x8022 & 0xdac6 & setting of DAC channel G \\ +0x8023 & 0xdac7 & setting of DAC channel H \\ \hline 0x8... & ... & ...data ... \\ @@ -261,7 +275,7 @@ \label{16bitRAM} \end{table} - This new order has several advantages apart from the additional information included. -All data may be treated as 64bit aligned. And the data readout process does not have to jump over word during data sending. +All data may be treated as 64bit aligned. And the data readout process does not need jump over words during data sending. + \newpage @@ -287,4 +301,7 @@ unsgined short number_of_triggers_to_generate; unsigned short trigger_generator_prescaler; + // ------------------------------ + unsigned char reserved; + unsigned char DNA[7]; // '1' & 55 unique bits of Xilinx DNA // ------------------------------ unsigned long time;